\t (00:00:59) allegro 16.6 P004 (v16-6-112G) Windows 32
\t (00:00:59)     Journal start - Sun Jun 28 23:24:25 2015
\t (00:00:59)         Host=WIN-6CEF9ULMP6T User=Administrator Pid=5628 CPUs=20
\t (00:00:59) 
\d (00:00:59) Database opened: E:/_doc/ALTERA/SMB2/pcb_design_files/100-0310112-01_reva.brd
\i (00:00:59) signalintegrity 
\i (00:01:01) setwindow form.vf_vis
\i (00:01:01) FORM vf_vis 1 all_colorvisible YES 
\i (00:01:01) FORM vf_vis 2 all_colorvisible YES 
\i (00:01:02) FORM vf_vis 3 all_colorvisible YES 
\i (00:01:03) FORM vf_vis 2 all_colorvisible NO 
\i (00:01:04) FORM vf_vis 5 all_colorvisible YES 
\i (00:01:04) FORM vf_vis 5 all_colorvisible NO 
\i (00:01:05) FORM vf_vis 4 all_colorvisible YES 
\i (00:01:07) FORM vf_vis 6 all_colorvisible YES 
\i (00:01:10) FORM vf_vis 1 etch_colorvisible color 8 
\i (00:01:14) FORM vf_vis 4 etch_colorvisible color 57 
\i (00:01:15) setwindow pcb
\i (00:01:15) zoom in 1 
\i (00:01:15) setwindow pcb
\i (00:01:15) zoom in 3441.790 3152.859
\i (00:01:15) trapsize 13376
\i (00:01:15) zoom in 1 
\i (00:01:15) setwindow pcb
\i (00:01:15) zoom in 3441.791 3152.859
\i (00:01:15) trapsize 6688
\i (00:01:15) zoom in 1 
\i (00:01:15) setwindow pcb
\i (00:01:15) zoom in 3441.791 3152.860
\i (00:01:15) trapsize 3344
\i (00:01:16) zoom out 1 
\i (00:01:16) setwindow pcb
\i (00:01:16) zoom out 3441.791 3152.860
\i (00:01:16) trapsize 6688
\i (00:01:18) prmed 
\i (00:01:20) setwindow form.prmedit
\i (00:01:20) FORM prmedit display_padless_holes YES 
\i (00:01:21) FORM prmedit display_non_plated_holes YES 
\i (00:01:22) FORM prmedit display_plated_holes YES 
\i (00:01:23) FORM prmedit display_enhance YES 
\i (00:01:24) FORM prmedit done  
\i (00:01:24) setwindow pcb
\i (00:01:24) signalintegrity 
\i (00:01:25) zoom in 1 
\i (00:01:25) setwindow pcb
\i (00:01:25) zoom in 3629.061 3140.822
\i (00:01:25) trapsize 3344
\i (00:01:25) zoom out 1 
\i (00:01:25) setwindow pcb
\i (00:01:25) zoom out 3629.061 3140.822
\i (00:01:25) trapsize 6688
\i (00:01:28) roam y -96 
\i (00:01:28) roam y -96
\i (00:01:29) roam y -96 
\i (00:01:29) roam y -96
\i (00:01:29) roam y -96 
\i (00:01:29) roam y -96
\i (00:01:32) setwindow form.mini
\i (00:01:32) FORM mini class PACKAGE KEEPIN 
\i (00:01:34) FORM mini class PACKAGE GEOMETRY 
\i (00:01:36) FORM mini subcolor 1 
\i (00:01:38) FORM mini subclass PLACE_BOUND_TOP 
\i (00:01:39) FORM mini subcolor 1 
\i (00:01:41) FORM mini subclass SAMSUNG 
\i (00:01:42) FORM mini subcolor 1 
\i (00:01:42) setwindow pcb
\i (00:01:42) zoom out 1 
\i (00:01:42) setwindow pcb
\i (00:01:42) zoom out 3666.516 3743.693
\i (00:01:42) trapsize 13376
\i (00:01:42) zoom out 1 
\i (00:01:42) setwindow pcb
\i (00:01:42) zoom out 3658.489 3730.318
\i (00:01:42) trapsize 26753
\i (00:01:43) roam y 96 
\i (00:01:43) roam y 96
\i (00:01:45) zoom in 1 
\i (00:01:45) setwindow pcb
\i (00:01:45) zoom in 3893.915 3329.023
\i (00:01:45) trapsize 13376
\i (00:01:45) zoom in 1 
\i (00:01:45) setwindow pcb
\i (00:01:45) zoom in 3883.214 3342.399
\i (00:01:45) trapsize 6688
\i (00:01:46) roam y -96 
\i (00:01:46) roam y -96
\i (00:01:46) roam y -96 
\i (00:01:46) roam y -96
\i (00:01:46) roam y -96 
\i (00:01:46) roam y -96
\i (00:01:46) roam y -96 
\i (00:01:46) roam y -96
\i (00:01:46) roam y -96 
\i (00:01:46) roam y -96
\i (00:01:47) roam y -96 
\i (00:01:47) roam y -96
\i (00:01:47) roam y -96 
\i (00:01:47) roam y -96
\i (00:01:47) roam x -96 
\i (00:01:47) roam x -96
\i (00:01:48) zoom in 1 
\i (00:01:48) setwindow pcb
\i (00:01:48) zoom in 3744.913 4249.325
\i (00:01:48) trapsize 3344
\i (00:01:48) roam y -96 
\i (00:01:48) roam y -96
\i (00:01:49) roam y 96 
\i (00:01:49) roam y 96
\i (00:01:49) zoom out 1 
\i (00:01:49) setwindow pcb
\i (00:01:49) zoom out 3744.244 4249.324
\i (00:01:49) trapsize 6688
\i (00:01:49) roam x -96 
\i (00:01:49) roam x -96
\i (00:01:49) roam x -96 
\i (00:01:49) roam x -96
\i (00:01:50) roam x -96 
\i (00:01:50) roam x -96
\i (00:07:35) iangle 90 
\e (00:07:35) angle command is not allowed in this mode.
\i (00:07:37) zoom out 1 
\i (00:07:37) setwindow pcb
\i (00: