README -------------------------------------------------------------------------------------------------------------- The files contained in this directory can be used to run pre-compiled projects for the Stratix Memory Board 1, as well as run the TCL Based Board Test System for testing User IO. Also included is a script to download the initial factory configuration to the board. Minimum Requirements -------------------------------------------------------------------------------------------------------------- 1) Quartus 4.0 SP1 2) USB-Blaster or ByteBlaster II. (USB Blaster is prefered). Description of Contents -------------------------------------------------------------------------------------------------------------- Configuration Files -- smb1_max_top.pof -- Design that implements Max and Flash configuratio scheme. Downloads configuration data from the Flash to the FPGA. -- smb1_top.sof -- Basic NIOS design that uses RS232 communication for board test functionality. This is loaded into the Safe Page by default. -- bts_dimm_200.sof -- DDR Test design for the DDR I Dimm. This generates LFSR Data that is then written to the DDR Memory, read back, and then verified. This is done across the entire device. -- bts_sb_133.sof -- DDR Test design for the DDR I Devices. This generates LFSR Data that is then written to the DDR Memory, read back, and then verified. This is done across the entire device. -- bts_rldram_cio_200.sof -- RLDRAM CIO test design that generates LFSR data that is written to the devices, and then verified. This is done across the devices entire addressable space. -- bts_rldram_sio_200.sof -- RLDRAM SIO test design that generates LFSR data that is written to the devices, and then verified. This is done across the devices entire addressable space. All of the batch files in this directory are used to load the tests. Select the test you wish to run. The last few characters of the filename give the configuration cable type the file uses. Factory Image ---------------------------------------------------------------------------------------------------------------- During the production tests, a set of configuration files (all of the above listed sofs) are organized and programmed into the flash. This allows the FPGA to be configured with any of the test designs on power up. If the flash image is corrupted for some reason, run smb1_factory_image_xxx.bat where xxx is either b2 or usb depending on the configuration cable being used. All of these scripts assume that the board is setup to have both the Max device and the Stratix device in the JTAG Chain.