module a2gx125_fpga_bup
(
	input			clkin_100,
   input       	reset_n,
    
   output           lcd_wen,
   inout   [7:  0]  lcd_data,
   output           lcd_en,
   output           lcd_d_cn,    

    output			  enet_mdc,
	 inout			  enet_mdio,
	 output			  enet_reset_n,
    input           enet_rx_clk,
    input           enet_rx_dv,
    input   [3:0]   enet_rx_d,
    output          enet_gtx_clk,
    output          enet_tx_en,
    output  [3:0]   enet_tx_d,	

	input [1:0]		button_pio,
	output [3:0]	led_pio,

    output [12:0]	mem_addr,
    output [2:0]	mem_ba,
    output			mem_cas_n,
    output			mem_cke,
    inout			mem_clk_n,
    inout			mem_clk,
    output			mem_cs_n,
    output [1:0]	mem_dm,
    inout  [15:0]	mem_dq,
    inout  [1:0]	mem_dqs,
    inout  [1:0]	mem_dqsn,
    output			mem_odt,
	output			mem_ras_n,
	output			mem_reset_n,
	output			mem_we_n,

	output [25:0]	flash_a,
	inout  [31:0]	flash_d,
	output			flash_oe_n,
	output			flash_ce_n,
	output			flash_we_n,
	output			flash_reset_n,
	output			flash_clk,
	output			flash_adv_n
);

	assign flash_adv_n = 1'b0;
	assign flash_clk = 1'b0;
   assign flash_reset_n = reset_n;
//
// Ethernet interface assignments
//
wire        mdio_in;
wire        mdio_oen;
wire        mdio_out;

wire			eth_mode;
wire			ena_10;

wire 			tx_clk;
wire        enet_tx_125;
wire        enet_tx_25;
wire        enet_tx_2p5;

assign mdio_in = enet_mdio;
assign enet_mdio = mdio_oen == 0 ? mdio_out : 1'bz;

 // PHY interface: need minimum 10ms delay for POR

parameter MSB = 21; // was 20 in 9.1sp2 but doesn't seem to improve reset success or avert crash

reg [MSB:0] epcount; // 21 bits (2 exp 21) * 20ns = ~42ms
 
always @(posedge clkin_100)
begin 
	if (reset_n == 1'b0)
		epcount <= MSB+1'b0;
	else
	if (epcount[MSB] == 1'b0)
		epcount <= epcount +1;
	else
		epcount <= epcount;
	end
 
assign enet_reset_n = !epcount[MSB-1]; // phy held low for ~21 msec after cpu_reset

//assign enet_reset_n = reset_n;

altddio_out     altddio_out_component (
                    .outclock ( tx_clk ),
                    .dataout ( enet_gtx_clk ),
                    .aclr (!reset_n),
                    .datain_h (1'b1),
                    .datain_l (1'b0),
                    .outclocken (1'b1),
                    .aset (1'b0),
                    .sclr (1'b0),
                    .sset (1'b0),
                    .oe_out (),
                    .oe (1'b1)
                    );
        defparam
                altddio_out_component.extend_oe_disable = "UNUSED",
                altddio_out_component.intended_device_family = "Arria II GX",
                altddio_out_component.invert_output = "OFF",
                altddio_out_component.lpm_type = "altddio_out",
                altddio_out_component.oe_reg = "UNUSED",
                altddio_out_component.width = 1;


assign tx_clk    =   (eth_mode) ? (enet_tx_125) :       // GbE Mode = 125MHz clock
                     (ena_10) ? (enet_tx_2p5) :         // 10Mb Mode = 2.5MHz clock
                     (enet_tx_25);                      // 100Mb Mode = 25MHz clock

// TX PLL 100 => 125, 25, 2.5
tx_clk_pll tx_clk_inst
(
	.areset (!reset_n),
	.inclk0 (clkin_100),
	.c0     (enet_tx_125),
	.c1     (enet_tx_25),
	.c2     (enet_tx_2p5),
	.locked ()
);

sopc_system sopc_system_inst
(
      .clkin_100                               (clkin_100),
      .reset_n                                 (reset_n),
		.LCD_E_from_the_lcd				           (lcd_en),
		.LCD_RS_from_the_lcd			              (lcd_d_cn),
		.LCD_RW_from_the_lcd			              (lcd_wen),
		.LCD_data_to_and_from_the_lcd            (lcd_data),     
     
      .sdram_aux_full_rate_clk_out             (),
      .sdram_aux_half_rate_clk_out             (),
      .sdram_phy_clk_out                       (), 
 //   .global_reset_n_to_the_sdram             (reset_n),  //qsys conversion
      .sdram_reset_n					              (reset_n),  //qsys conversion      
      .mem_addr_from_the_sdram                 (mem_addr),
      .mem_ba_from_the_sdram                   (mem_ba),
      .mem_cas_n_from_the_sdram                (mem_cas_n),
      .mem_cke_from_the_sdram                  (mem_cke),
      .mem_clk_n_to_and_from_the_sdram         (mem_clk_n),
      .mem_clk_to_and_from_the_sdram           (mem_clk),
      .mem_cs_n_from_the_sdram                 (mem_cs_n),
      .mem_dm_from_the_sdram                   (mem_dm),
      .mem_dq_to_and_from_the_sdram            (mem_dq),
      .mem_dqs_to_and_from_the_sdram           (mem_dqs),
      .mem_dqsn_to_and_from_the_sdram          (mem_dqsn),
      .mem_odt_from_the_sdram                  (mem_odt),
      .mem_ras_n_from_the_sdram                (mem_ras_n),
      .mem_reset_n_from_the_sdram              (mem_reset_n),
      .mem_we_n_from_the_sdram                 (mem_we_n), 
      .reset_phy_clk_n_from_the_sdram          (),

      .in_port_to_the_button_pio               (button_pio),
      .out_port_from_the_led_pio               (led_pio),

      .ena_10_from_the_tse_mac                 (ena_10),
      .eth_mode_from_the_tse_mac               (eth_mode),
      .mdc_from_the_tse_mac                    (enet_mdc),
      .mdio_in_to_the_tse_mac                  (mdio_in),
      .mdio_oen_from_the_tse_mac               (mdio_oen),
      .mdio_out_from_the_tse_mac               (mdio_out),
      .rgmii_in_to_the_tse_mac                 (enet_rx_d),
      .rgmii_out_from_the_tse_mac              (enet_tx_d),      
      .rx_clk_to_the_tse_mac                   (enet_rx_clk),
      .rx_control_to_the_tse_mac               (enet_rx_dv),
      .set_1000_to_the_tse_mac                 (),
      .set_10_to_the_tse_mac                   (),
      .tx_clk_to_the_tse_mac                   (tx_clk),
      .tx_control_from_the_tse_mac             (enet_tx_en),
      
      .flash_tristate_bridge_address           (flash_a),
      .flash_tristate_bridge_data              (flash_d),
      .read_n_to_the_ext_flash                 (flash_oe_n),
      .write_n_to_the_ext_flash                (flash_we_n),     
      .select_n_to_the_ext_flash               (flash_ce_n)    
      
);

endmodule