## Generated SDC file "a2gx125_fpga_bup.out.sdc"

## Copyright (C) 1991-2011 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions 
## and other software and tools, and its AMPP partner logic 
## functions, and any output files from any of the foregoing 
## (including device programming or simulation files), and any 
## associated documentation or information are expressly subject 
## to the terms and conditions of the Altera Program License 
## Subscription Agreement, Altera MegaCore Function License 
## Agreement, or other applicable license agreement, including, 
## without limitation, that your use is for the sole purpose of 
## programming logic devices manufactured by Altera and sold by 
## Altera or its authorized distributors.  Please refer to the 
## applicable agreement for further details.


## VENDOR  "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 11.1 Build 173 11/01/2011 SJ Full Version"

## DATE    "Mon Nov 14 12:29:53 2011"

##
## DEVICE  "EP2AGX125EF35C4"
##


#**************************************************************
# Time Information
#**************************************************************

set_time_format -unit ns -decimal_places 3



#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
create_clock -name {clkin_100} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clkin_100}]
create_clock -name {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]} -period 3.333 -waveform { 0.000 1.666 } [get_ports {mem_dqs[0]}] -add
create_clock -name {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]} -period 3.333 -waveform { 0.000 1.666 } [get_ports {mem_dqs[1]}] -add
create_clock -name {enet_rx_clk} -period 8.000 -waveform { 0.000 4.000 } [get_ports {enet_rx_clk}]


#**************************************************************
# Create Generated Clock
#**************************************************************

create_generated_clock -name {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 3 -divide_by 2 -phase 28.125 -master_clock {clkin_100} [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 
create_generated_clock -name {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 3 -master_clock {clkin_100} [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] 
create_generated_clock -name {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]} -source [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 3 -phase -90.000 -master_clock {clkin_100} [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] 
create_generated_clock -name {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]} -source [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 3 -master_clock {clkin_100} [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] 
create_generated_clock -name {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]} -source [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 3 -master_clock {clkin_100} [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] 
create_generated_clock -name {tx_clk_inst|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {tx_clk_inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 5 -divide_by 4 -master_clock {clkin_100} [get_pins {tx_clk_inst|altpll_component|auto_generated|pll1|clk[0]}] 
create_generated_clock -name {tx_clk_inst|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {tx_clk_inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 4 -master_clock {clkin_100} [get_pins {tx_clk_inst|altpll_component|auto_generated|pll1|clk[1]}] 
create_generated_clock -name {tx_clk_inst|altpll_component|auto_generated|pll1|clk[2]} -source [get_pins {tx_clk_inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 40 -master_clock {clkin_100} [get_pins {tx_clk_inst|altpll_component|auto_generated|pll1|clk[2]}] 
create_generated_clock -name {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_rise} -source [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {mem_clk}] -add
create_generated_clock -name {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall} -source [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {mem_clk}] -add
create_generated_clock -name {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_rise} -source [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} -invert [get_ports {mem_clk_n}] -add
create_generated_clock -name {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall} -source [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} -invert [get_ports {mem_clk_n}] -add
create_generated_clock -name {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock} -source [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -divide_by 2 -master_clock {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]} [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q}] 
create_generated_clock -name {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]} -source [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {mem_dqs[0]}] -add
create_generated_clock -name {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]} -source [get_pins {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {mem_dqs[1]}] -add
create_generated_clock -name {tx_clk_125} -source [get_pins {tx_clk_inst|altpll_component|auto_generated|pll1|clk[0]}] -master_clock {tx_clk_inst|altpll_component|auto_generated|pll1|clk[0]} [get_nets {tx_clk}] -add
create_generated_clock -name {enet_gtx_clk_125} -source [get_nets {tx_clk}] -master_clock {tx_clk_125} [get_ports {enet_gtx_clk}] -add
create_generated_clock -name {tx_clk_25} -source [get_pins {tx_clk_inst|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {tx_clk_inst|altpll_component|auto_generated|pll1|clk[1]} [get_nets {tx_clk}] -add
create_generated_clock -name {enet_gtx_clk_25} -source [get_nets {tx_clk}] -master_clock {tx_clk_25} [get_ports {enet_gtx_clk}] -add
create_generated_clock -name {tx_clk_2p5} -source [get_pins {tx_clk_inst|altpll_component|auto_generated|pll1|clk[2]}] -master_clock {tx_clk_inst|altpll_component|auto_generated|pll1|clk[2]} [get_nets {tx_clk}] -add
create_generated_clock -name {enet_gtx_clk_2p5} -source [get_nets {tx_clk}] -master_clock {tx_clk_2p5} [get_ports {enet_gtx_clk}] -add


#**************************************************************
# Set Clock Latency
#**************************************************************



#**************************************************************
# Set Clock Uncertainty
#**************************************************************

set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {enet_rx_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {enet_rx_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {tx_clk_125}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {tx_clk_125}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {tx_clk_25}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {tx_clk_25}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {tx_clk_2p5}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {tx_clk_2p5}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {enet_rx_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {enet_rx_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {tx_clk_125}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {tx_clk_125}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {tx_clk_25}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {tx_clk_25}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {tx_clk_2p5}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {tx_clk_2p5}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {clkin_100}] -rise_to [get_clocks {clkin_100}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {clkin_100}] -fall_to [get_clocks {clkin_100}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {clkin_100}] -rise_to [get_clocks {clkin_100}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {clkin_100}] -fall_to [get_clocks {clkin_100}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {enet_rx_clk}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {enet_rx_clk}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {enet_rx_clk}] -rise_to [get_clocks {enet_rx_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {enet_rx_clk}] -fall_to [get_clocks {enet_rx_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {enet_rx_clk}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {enet_rx_clk}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {enet_rx_clk}] -rise_to [get_clocks {enet_rx_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {enet_rx_clk}] -fall_to [get_clocks {enet_rx_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}]  0.030 
set_clock_uncertainty -rise_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}]  0.030 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}]  0.030 
set_clock_uncertainty -fall_from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}]  0.030 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {tx_clk_125}]  0.030 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {tx_clk_125}]  0.030 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {enet_gtx_clk_125}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {enet_gtx_clk_125}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {tx_clk_125}]  0.030 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {tx_clk_125}]  0.030 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {enet_gtx_clk_125}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {enet_gtx_clk_125}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {tx_clk_25}]  0.030 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {tx_clk_25}]  0.030 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {enet_gtx_clk_25}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {enet_gtx_clk_25}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {tx_clk_25}]  0.030 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {tx_clk_25}]  0.030 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {enet_gtx_clk_25}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {enet_gtx_clk_25}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {tx_clk_2p5}]  0.030 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {tx_clk_2p5}]  0.030 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {enet_gtx_clk_2p5}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {enet_gtx_clk_2p5}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {tx_clk_2p5}]  0.030 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {tx_clk_2p5}]  0.030 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {enet_gtx_clk_2p5}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {enet_gtx_clk_2p5}]  0.050 


#**************************************************************
# Set Input Delay
#**************************************************************

set_input_delay -add_delay -max -clock [get_clocks {enet_rx_clk}]  -1.125 [get_ports {enet_rx_d[0]}]
set_input_delay -add_delay -min -clock [get_clocks {enet_rx_clk}]  -2.875 [get_ports {enet_rx_d[0]}]
set_input_delay -add_delay -max -clock_fall -clock [get_clocks {enet_rx_clk}]  -1.125 [get_ports {enet_rx_d[0]}]
set_input_delay -add_delay -min -clock_fall -clock [get_clocks {enet_rx_clk}]  -2.875 [get_ports {enet_rx_d[0]}]
set_input_delay -add_delay -max -clock [get_clocks {enet_rx_clk}]  -1.125 [get_ports {enet_rx_d[1]}]
set_input_delay -add_delay -min -clock [get_clocks {enet_rx_clk}]  -2.875 [get_ports {enet_rx_d[1]}]
set_input_delay -add_delay -max -clock_fall -clock [get_clocks {enet_rx_clk}]  -1.125 [get_ports {enet_rx_d[1]}]
set_input_delay -add_delay -min -clock_fall -clock [get_clocks {enet_rx_clk}]  -2.875 [get_ports {enet_rx_d[1]}]
set_input_delay -add_delay -max -clock [get_clocks {enet_rx_clk}]  -1.125 [get_ports {enet_rx_d[2]}]
set_input_delay -add_delay -min -clock [get_clocks {enet_rx_clk}]  -2.875 [get_ports {enet_rx_d[2]}]
set_input_delay -add_delay -max -clock_fall -clock [get_clocks {enet_rx_clk}]  -1.125 [get_ports {enet_rx_d[2]}]
set_input_delay -add_delay -min -clock_fall -clock [get_clocks {enet_rx_clk}]  -2.875 [get_ports {enet_rx_d[2]}]
set_input_delay -add_delay -max -clock [get_clocks {enet_rx_clk}]  -1.125 [get_ports {enet_rx_d[3]}]
set_input_delay -add_delay -min -clock [get_clocks {enet_rx_clk}]  -2.875 [get_ports {enet_rx_d[3]}]
set_input_delay -add_delay -max -clock_fall -clock [get_clocks {enet_rx_clk}]  -1.125 [get_ports {enet_rx_d[3]}]
set_input_delay -add_delay -min -clock_fall -clock [get_clocks {enet_rx_clk}]  -2.875 [get_ports {enet_rx_d[3]}]
set_input_delay -add_delay -max -clock [get_clocks {enet_rx_clk}]  -1.125 [get_ports {enet_rx_dv}]
set_input_delay -add_delay -min -clock [get_clocks {enet_rx_clk}]  -2.875 [get_ports {enet_rx_dv}]
set_input_delay -add_delay -max -clock_fall -clock [get_clocks {enet_rx_clk}]  -1.125 [get_ports {enet_rx_dv}]
set_input_delay -add_delay -min -clock_fall -clock [get_clocks {enet_rx_clk}]  -2.875 [get_ports {enet_rx_dv}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  0.175 [get_ports {mem_dq[0]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  -0.047 [get_ports {mem_dq[0]}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  0.175 [get_ports {mem_dq[1]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  -0.047 [get_ports {mem_dq[1]}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  0.175 [get_ports {mem_dq[2]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  -0.047 [get_ports {mem_dq[2]}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  0.175 [get_ports {mem_dq[3]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  -0.047 [get_ports {mem_dq[3]}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  0.175 [get_ports {mem_dq[4]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  -0.047 [get_ports {mem_dq[4]}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  0.175 [get_ports {mem_dq[5]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  -0.047 [get_ports {mem_dq[5]}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  0.175 [get_ports {mem_dq[6]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  -0.047 [get_ports {mem_dq[6]}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  0.175 [get_ports {mem_dq[7]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  -0.047 [get_ports {mem_dq[7]}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  0.175 [get_ports {mem_dq[8]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  -0.047 [get_ports {mem_dq[8]}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  0.175 [get_ports {mem_dq[9]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  -0.047 [get_ports {mem_dq[9]}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  0.175 [get_ports {mem_dq[10]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  -0.047 [get_ports {mem_dq[10]}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  0.175 [get_ports {mem_dq[11]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  -0.047 [get_ports {mem_dq[11]}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  0.175 [get_ports {mem_dq[12]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  -0.047 [get_ports {mem_dq[12]}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  0.175 [get_ports {mem_dq[13]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  -0.047 [get_ports {mem_dq[13]}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  0.175 [get_ports {mem_dq[14]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  -0.047 [get_ports {mem_dq[14]}]
set_input_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  0.175 [get_ports {mem_dq[15]}]
set_input_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  -0.047 [get_ports {mem_dq[15]}]


#**************************************************************
# Set Output Delay
#**************************************************************

set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_125}]  -0.825 [get_ports {enet_tx_d[0]}]
set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_125}]  -2.775 [get_ports {enet_tx_d[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  -0.825 [get_ports {enet_tx_d[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  -2.775 [get_ports {enet_tx_d[0]}]
set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_25}]  -0.825 [get_ports {enet_tx_d[0]}]
set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_25}]  -2.775 [get_ports {enet_tx_d[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  -0.825 [get_ports {enet_tx_d[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  -2.775 [get_ports {enet_tx_d[0]}]
set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_2p5}]  -0.825 [get_ports {enet_tx_d[0]}]
set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_2p5}]  -2.775 [get_ports {enet_tx_d[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  -0.825 [get_ports {enet_tx_d[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  -2.775 [get_ports {enet_tx_d[0]}]
set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_125}]  -0.825 [get_ports {enet_tx_d[1]}]
set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_125}]  -2.775 [get_ports {enet_tx_d[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  -0.825 [get_ports {enet_tx_d[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  -2.775 [get_ports {enet_tx_d[1]}]
set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_25}]  -0.825 [get_ports {enet_tx_d[1]}]
set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_25}]  -2.775 [get_ports {enet_tx_d[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  -0.825 [get_ports {enet_tx_d[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  -2.775 [get_ports {enet_tx_d[1]}]
set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_2p5}]  -0.825 [get_ports {enet_tx_d[1]}]
set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_2p5}]  -2.775 [get_ports {enet_tx_d[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  -0.825 [get_ports {enet_tx_d[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  -2.775 [get_ports {enet_tx_d[1]}]
set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_125}]  -0.825 [get_ports {enet_tx_d[2]}]
set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_125}]  -2.775 [get_ports {enet_tx_d[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  -0.825 [get_ports {enet_tx_d[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  -2.775 [get_ports {enet_tx_d[2]}]
set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_25}]  -0.825 [get_ports {enet_tx_d[2]}]
set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_25}]  -2.775 [get_ports {enet_tx_d[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  -0.825 [get_ports {enet_tx_d[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  -2.775 [get_ports {enet_tx_d[2]}]
set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_2p5}]  -0.825 [get_ports {enet_tx_d[2]}]
set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_2p5}]  -2.775 [get_ports {enet_tx_d[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  -0.825 [get_ports {enet_tx_d[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  -2.775 [get_ports {enet_tx_d[2]}]
set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_125}]  -0.825 [get_ports {enet_tx_d[3]}]
set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_125}]  -2.775 [get_ports {enet_tx_d[3]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  -0.825 [get_ports {enet_tx_d[3]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  -2.775 [get_ports {enet_tx_d[3]}]
set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_25}]  -0.825 [get_ports {enet_tx_d[3]}]
set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_25}]  -2.775 [get_ports {enet_tx_d[3]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  -0.825 [get_ports {enet_tx_d[3]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  -2.775 [get_ports {enet_tx_d[3]}]
set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_2p5}]  -0.825 [get_ports {enet_tx_d[3]}]
set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_2p5}]  -2.775 [get_ports {enet_tx_d[3]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  -0.825 [get_ports {enet_tx_d[3]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  -2.775 [get_ports {enet_tx_d[3]}]
set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_125}]  -0.825 [get_ports {enet_tx_en}]
set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_125}]  -2.775 [get_ports {enet_tx_en}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  -0.825 [get_ports {enet_tx_en}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  -2.775 [get_ports {enet_tx_en}]
set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_25}]  -0.825 [get_ports {enet_tx_en}]
set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_25}]  -2.775 [get_ports {enet_tx_en}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  -0.825 [get_ports {enet_tx_en}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  -2.775 [get_ports {enet_tx_en}]
set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_2p5}]  -0.825 [get_ports {enet_tx_en}]
set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_2p5}]  -2.775 [get_ports {enet_tx_en}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  -0.825 [get_ports {enet_tx_en}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  -2.775 [get_ports {enet_tx_en}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_addr[0]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_addr[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_addr[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_addr[0]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_addr[1]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_addr[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_addr[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_addr[1]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_addr[2]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_addr[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_addr[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_addr[2]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_addr[3]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_addr[3]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_addr[3]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_addr[3]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_addr[4]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_addr[4]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_addr[4]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_addr[4]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_addr[5]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_addr[5]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_addr[5]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_addr[5]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_addr[6]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_addr[6]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_addr[6]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_addr[6]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_addr[7]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_addr[7]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_addr[7]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_addr[7]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_addr[8]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_addr[8]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_addr[8]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_addr[8]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_addr[9]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_addr[9]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_addr[9]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_addr[9]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_addr[10]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_addr[10]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_addr[10]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_addr[10]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_addr[11]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_addr[11]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_addr[11]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_addr[11]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_addr[12]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_addr[12]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_addr[12]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_addr[12]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_ba[0]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_ba[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_ba[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_ba[0]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_ba[1]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_ba[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_ba[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_ba[1]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_ba[2]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_ba[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_ba[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_ba[2]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_cas_n}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_cas_n}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_cas_n}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_cas_n}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_cke}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_cke}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_cke}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_cke}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_cs_n}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_cs_n}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_cs_n}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_cs_n}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dm[0]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dm[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dm[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dm[0]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dm[1]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dm[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dm[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dm[1]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[0]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[0]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[1]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[1]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[2]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[2]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[3]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[3]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[3]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[3]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[4]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[4]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[4]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[4]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[5]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[5]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[5]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[5]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[6]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[6]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[6]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[6]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[7]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[7]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  0.315 [get_ports {mem_dq[7]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -0.350 [get_ports {mem_dq[7]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[8]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[8]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[8]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[8]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[9]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[9]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[9]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[9]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[10]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[10]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[10]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[10]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[11]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[11]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[11]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[11]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[12]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[12]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[12]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[12]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[13]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[13]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[13]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[13]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[14]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[14]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[14]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[14]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[15]}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[15]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  0.315 [get_ports {mem_dq[15]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -0.350 [get_ports {mem_dq[15]}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_odt}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_odt}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_odt}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_odt}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_ras_n}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_ras_n}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_ras_n}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_ras_n}]
set_output_delay -add_delay -max -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  0.223 [get_ports {mem_we_n}]
set_output_delay -add_delay -min -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -0.239 [get_ports {mem_we_n}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  0.223 [get_ports {mem_we_n}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]  -0.239 [get_ports {mem_we_n}]


#**************************************************************
# Set Clock Groups
#**************************************************************

set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
set_clock_groups -exclusive -group [get_clocks {sopc_system_inst|the_sdram|sdram_controller_phy_inst|sdram_phy_inst|sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -group [get_clocks {tx_clk_125 enet_gtx_clk_125}] -group [get_clocks {tx_clk_25  enet_gtx_clk_25 }] -group [get_clocks {tx_clk_2p5 enet_gtx_clk_2p5}] -group [get_clocks {enet_rx_clk}] 


#**************************************************************
# Set False Path
#**************************************************************

set_false_path  -from  [get_clocks {clkin_100}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {clkin_100}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]
set_false_path -setup -rise_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -fall_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]
set_false_path -setup -fall_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -rise_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]
set_false_path -hold -rise_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -rise_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]
set_false_path -hold -fall_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -fall_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]
set_false_path -setup -rise_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -fall_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]
set_false_path -setup -fall_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -rise_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]
set_false_path -hold -rise_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -rise_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]
set_false_path -hold -fall_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -fall_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]
set_false_path  -rise_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]
set_false_path  -rise_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_rise}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]
set_false_path  -from  [get_clocks {clkin_100}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {clkin_100}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[0]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]
set_false_path -setup -rise_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -fall_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]
set_false_path -setup -fall_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -rise_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]
set_false_path -hold -rise_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -rise_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]
set_false_path -hold -fall_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -fall_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsin_mem_dqs[1]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]
set_false_path -setup -rise_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -fall_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]
set_false_path -setup -fall_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -rise_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]
set_false_path -hold -rise_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -rise_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]
set_false_path -hold -fall_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -fall_to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]
set_false_path  -rise_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]
set_false_path  -rise_from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_n_mem_clk_n_ac_fall}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_fall}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ck_p_mem_clk_ac_rise}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]
set_false_path -setup -rise_from  [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}]  -fall_to  [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25 enet_gtx_clk_2p5}]
set_false_path -setup -fall_from  [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}]  -rise_to  [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25 enet_gtx_clk_2p5}]
set_false_path -hold -rise_from  [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}]  -rise_to  [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25 enet_gtx_clk_2p5}]
set_false_path -hold -fall_from  [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}]  -fall_to  [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25 enet_gtx_clk_2p5}]
set_false_path -setup -rise_from  [get_clocks {enet_rx_clk}]  -fall_to  [get_clocks {enet_rx_clk}]
set_false_path -setup -fall_from  [get_clocks {enet_rx_clk}]  -rise_to  [get_clocks {enet_rx_clk}]
set_false_path -hold -rise_from  [get_clocks {enet_rx_clk}]  -rise_to  [get_clocks {enet_rx_clk}]
set_false_path -hold -fall_from  [get_clocks {enet_rx_clk}]  -fall_to  [get_clocks {enet_rx_clk}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {enet_rx_clk}]
set_false_path  -from  [get_clocks {tx_clk_25}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path  -from  [get_clocks {tx_clk_2p5}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path  -from  [get_clocks {enet_rx_clk}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path  -from  [get_clocks {tx_clk_125}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path  -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {tx_clk_125}]
set_false_path -from [get_ports {mem_clk}] -to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]
set_false_path -from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -through [get_nets {*ams_pipe*}] -to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]
set_false_path -from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -through [get_nets {*ams_pipe*}] -to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}] 
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [all_registers]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}] 
set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
set_false_path -to [get_pins -nocase -compatibility_mode {*altera_tse_reset_synchronizer_chain*|clrn}]
set_false_path -to [get_pins -nocase -compatibility_mode {*|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn}]
set_false_path -from [get_keepers {*sopc_system_cpu:*|sopc_system_cpu_nios2_oci:the_sopc_system_cpu_nios2_oci|sopc_system_cpu_nios2_oci_break:the_sopc_system_cpu_nios2_oci_break|break_readreg*}] -to [get_keepers {*sopc_system_cpu:*|sopc_system_cpu_nios2_oci:the_sopc_system_cpu_nios2_oci|sopc_system_cpu_jtag_debug_module_wrapper:the_sopc_system_cpu_jtag_debug_module_wrapper|sopc_system_cpu_jtag_debug_module_tck:the_sopc_system_cpu_jtag_debug_module_tck|*sr*}]
set_false_path -from [get_keepers {*sopc_system_cpu:*|sopc_system_cpu_nios2_oci:the_sopc_system_cpu_nios2_oci|sopc_system_cpu_nios2_oci_debug:the_sopc_system_cpu_nios2_oci_debug|*resetlatch}] -to [get_keepers {*sopc_system_cpu:*|sopc_system_cpu_nios2_oci:the_sopc_system_cpu_nios2_oci|sopc_system_cpu_jtag_debug_module_wrapper:the_sopc_system_cpu_jtag_debug_module_wrapper|sopc_system_cpu_jtag_debug_module_tck:the_sopc_system_cpu_jtag_debug_module_tck|*sr[33]}]
set_false_path -from [get_keepers {*sopc_system_cpu:*|sopc_system_cpu_nios2_oci:the_sopc_system_cpu_nios2_oci|sopc_system_cpu_nios2_oci_debug:the_sopc_system_cpu_nios2_oci_debug|monitor_ready}] -to [get_keepers {*sopc_system_cpu:*|sopc_system_cpu_nios2_oci:the_sopc_system_cpu_nios2_oci|sopc_system_cpu_jtag_debug_module_wrapper:the_sopc_system_cpu_jtag_debug_module_wrapper|sopc_system_cpu_jtag_debug_module_tck:the_sopc_system_cpu_jtag_debug_module_tck|*sr[0]}]
set_false_path -from [get_keepers {*sopc_system_cpu:*|sopc_system_cpu_nios2_oci:the_sopc_system_cpu_nios2_oci|sopc_system_cpu_nios2_oci_debug:the_sopc_system_cpu_nios2_oci_debug|monitor_error}] -to [get_keepers {*sopc_system_cpu:*|sopc_system_cpu_nios2_oci:the_sopc_system_cpu_nios2_oci|sopc_system_cpu_jtag_debug_module_wrapper:the_sopc_system_cpu_jtag_debug_module_wrapper|sopc_system_cpu_jtag_debug_module_tck:the_sopc_system_cpu_jtag_debug_module_tck|*sr[34]}]
set_false_path -from [get_keepers {*sopc_system_cpu:*|sopc_system_cpu_nios2_oci:the_sopc_system_cpu_nios2_oci|sopc_system_cpu_nios2_ocimem:the_sopc_system_cpu_nios2_ocimem|*MonDReg*}] -to [get_keepers {*sopc_system_cpu:*|sopc_system_cpu_nios2_oci:the_sopc_system_cpu_nios2_oci|sopc_system_cpu_jtag_debug_module_wrapper:the_sopc_system_cpu_jtag_debug_module_wrapper|sopc_system_cpu_jtag_debug_module_tck:the_sopc_system_cpu_jtag_debug_module_tck|*sr*}]
set_false_path -from [get_keepers {*sopc_system_cpu:*|sopc_system_cpu_nios2_oci:the_sopc_system_cpu_nios2_oci|sopc_system_cpu_jtag_debug_module_wrapper:the_sopc_system_cpu_jtag_debug_module_wrapper|sopc_system_cpu_jtag_debug_module_tck:the_sopc_system_cpu_jtag_debug_module_tck|*sr*}] -to [get_keepers {*sopc_system_cpu:*|sopc_system_cpu_nios2_oci:the_sopc_system_cpu_nios2_oci|sopc_system_cpu_jtag_debug_module_wrapper:the_sopc_system_cpu_jtag_debug_module_wrapper|sopc_system_cpu_jtag_debug_module_sysclk:the_sopc_system_cpu_jtag_debug_module_sysclk|*jdo*}]
set_false_path -from [get_keepers {sld_hub:*|irf_reg*}] -to [get_keepers {*sopc_system_cpu:*|sopc_system_cpu_nios2_oci:the_sopc_system_cpu_nios2_oci|sopc_system_cpu_jtag_debug_module_wrapper:the_sopc_system_cpu_jtag_debug_module_wrapper|sopc_system_cpu_jtag_debug_module_sysclk:the_sopc_system_cpu_jtag_debug_module_sysclk|ir*}]
set_false_path -from [get_keepers {sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1]}] -to [get_keepers {*sopc_system_cpu:*|sopc_system_cpu_nios2_oci:the_sopc_system_cpu_nios2_oci|sopc_system_cpu_nios2_oci_debug:the_sopc_system_cpu_nios2_oci_debug|monitor_go}]
set_false_path -to [get_ports {mem_reset_n}]
set_false_path -from [get_ports {mem_clk}] -to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]
set_false_path -to [get_ports {mem_clk}]
set_false_path -to [get_ports {mem_clk_n}]
set_false_path -from [all_registers] -to [get_ports {mem_dqs[0]}]
set_false_path -from [all_registers] -to [get_ports {mem_dqsn[0]}]
set_false_path -from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -through [get_nets {*ams_pipe*}] -to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[0]}]
set_false_path -from [all_registers] -to [get_ports {mem_dqs[1]}]
set_false_path -from [all_registers] -to [get_ports {mem_dqsn[1]}]
set_false_path -from [get_keepers {*bidir_dq_*_oe_ff_inst}] 
set_false_path -from [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -through [get_nets {*ams_pipe*}] -to [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_ddr_dqsout_mem_dqs[1]}]
set_false_path -from [get_keepers {{mem_dq[0]} {mem_dq[1]} {mem_dq[2]} {mem_dq[3]} {mem_dq[4]} {mem_dq[5]} {mem_dq[6]} {mem_dq[7]} {mem_dq[10]} {mem_dq[11]} {mem_dq[12]} {mem_dq[13]} {mem_dq[14]} {mem_dq[15]} {mem_dq[8]} {mem_dq[9]}}] -to [get_keepers {*datain_reg*}]
set_false_path -from [get_pins -compatibility_mode {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|*seq_wrapper|*seq_inst|*dgrb|?d_lat*|clk}] 
set_false_path -from [get_pins -compatibility_mode {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|*seq_wrapper|*seq_inst|seq_mem_clk_disable*}] 
set_false_path -through [get_pins -compatibility_mode {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy*_inst|clk|*pll|altpll_component|auto_generated|pll_lock_sync|clrn}] 
set_false_path -through [get_pins -compatibility_mode {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy*_inst|clk|global_pre_clear|clrn}] 
set_false_path -through [get_pins -compatibility_mode {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy*_inst|clk|reset_master_ams|clrn}] 
set_false_path -through [get_pins -compatibility_mode {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy*_inst|clk|mem_clk_pipe|ams_pipe[*]|clrn}] 
set_false_path -through [get_pins -compatibility_mode {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy*_inst|clk|write_clk_pipe|ams_pipe[*]|clrn}] 
set_false_path -through [get_pins -compatibility_mode {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy*_inst|clk|measure_clk_pipe|ams_pipe[*]|clrn}] 
set_false_path -through [get_pins -compatibility_mode {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy*_inst|clk|clk_div_reset_ams_n_r|clrn}] 
set_false_path -through [get_pins -compatibility_mode {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy*_inst|clk|clk_div_reset_ams_n|clrn}] 
set_false_path -through [get_pins -compatibility_mode {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy*_inst|clk|pll_reconfig_reset_ams_n_r|clrn}] 
set_false_path -through [get_pins -compatibility_mode {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy*_inst|clk|pll_reconfig_reset_ams_n|clrn}] 
set_false_path -through [get_pins -compatibility_mode {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy*_inst|clk|phs_shft_busy_siii|d}] 
set_false_path -through [get_pins -compatibility_mode {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy*_inst|clk|poa_clk_pipe|ams_pipe[*]|clrn}] 
set_false_path -to [get_keepers {mem_reset_n}]
set_false_path -from [get_pins -compatibility_mode {*_alt_mem_phy_inst|*seq_wrapper|*seq_inst|*|seq_mmc_start*|*}] -to [get_keepers {*alt_mem_phy_mimic:mmc|seq_mmc_start_metastable*}]
set_false_path -from [get_keepers {*_alt_mem_phy_inst|*seq_wrapper|*seq_inst|seq_ac_add_1t_ac_lat_internal*}] 
set_false_path -from [get_pins -compatibility_mode {*_alt_mem_phy_inst|*mmc|mimic_done_out*}] -to [get_keepers {*_alt_mem_phy_inst|*seq_wrapper|*seq_inst|*dgrb|*v_mmc_seq_done_1r*}]
set_false_path -from [all_registers] -to [get_keepers {mem_cke mem_odt mem_cs_n {mem_addr[0]} {mem_addr[10]} {mem_addr[11]} {mem_addr[12]} {mem_addr[1]} {mem_addr[2]} {mem_addr[3]} {mem_addr[4]} {mem_addr[5]} {mem_addr[6]} {mem_addr[7]} {mem_addr[8]} {mem_addr[9]} {mem_ba[0]} {mem_ba[1]} {mem_ba[2]} mem_cas_n mem_ras_n mem_we_n}]
set_false_path -from [get_ports {reset_n}] 
set_false_path -from [get_ports {button_pio[*]}] 
set_false_path -to [get_ports {led_pio[*]}]
set_false_path -to [get_ports {enet_gtx_clk}]


#**************************************************************
# Set Multicycle Path
#**************************************************************

set_multicycle_path -setup -end -from [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*}] -to [all_registers] 5
set_multicycle_path -setup -end -from [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*}] -to [all_registers] 5
set_multicycle_path -setup -end -from [all_registers] -to [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*}] 5
set_multicycle_path -hold -end -from [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*}] -to [all_registers] 5
set_multicycle_path -hold -end -from [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*}] -to [all_registers] 5
set_multicycle_path -hold -end -from [all_registers] -to [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*}] 5
set_multicycle_path -setup -end -to [get_keepers {{mem_addr[0]} {mem_addr[10]} {mem_addr[11]} {mem_addr[12]} {mem_addr[1]} {mem_addr[2]} {mem_addr[3]} {mem_addr[4]} {mem_addr[5]} {mem_addr[6]} {mem_addr[7]} {mem_addr[8]} {mem_addr[9]} {mem_ba[0]} {mem_ba[1]} {mem_ba[2]} mem_cas_n mem_ras_n mem_we_n}] 2
set_multicycle_path -hold -end -to [get_keepers {{mem_addr[0]} {mem_addr[10]} {mem_addr[11]} {mem_addr[12]} {mem_addr[1]} {mem_addr[2]} {mem_addr[3]} {mem_addr[4]} {mem_addr[5]} {mem_addr[6]} {mem_addr[7]} {mem_addr[8]} {mem_addr[9]} {mem_ba[0]} {mem_ba[1]} {mem_ba[2]} mem_cas_n mem_ras_n mem_we_n}] 1


#**************************************************************
# Set Maximum Delay
#**************************************************************

set_max_delay -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 9.000
set_max_delay -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] 9.000
set_max_delay -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 3.333
set_max_delay -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 9.000
set_max_delay -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] 9.000
set_max_delay -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 3.333
set_max_delay -from [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|dout_reg_sft*}] -to [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*}] 7.000
set_max_delay -from [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|eop_sft*}] -to [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*}] 7.000
set_max_delay -from [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|sop_reg*}] -to [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*}] 7.000
set_max_delay -from [get_keepers {{mem_dq[0]} {mem_dq[1]} {mem_dq[2]} {mem_dq[3]} {mem_dq[4]} {mem_dq[5]} {mem_dq[6]} {mem_dq[7]}}] -0.036
set_max_delay -from [get_keepers {{mem_dq[10]} {mem_dq[11]} {mem_dq[12]} {mem_dq[13]} {mem_dq[14]} {mem_dq[15]} {mem_dq[8]} {mem_dq[9]}}] -0.036
set_max_delay -to [get_ports {flash_a[*] flash_d[*] flash_oe_n flash_ce_n flash_we_n flash_adv_n flash_olk}] 10.000
set_max_delay -from [get_ports {flash_d[*]}] 6.000
set_max_delay -to [get_ports {enet_mdc enet_mdio enet_reset_n}] 10.000
set_max_delay -from [get_ports {enet_mdio}] 6.000
set_max_delay -to [get_ports {altera_reserved_tdo}] 20.000
set_max_delay -from [get_ports {altera_reserved_tdi altera_reserved_tms}] 20.000


#**************************************************************
# Set Minimum Delay
#**************************************************************

set_min_delay -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -9.000
set_min_delay -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -9.000
set_min_delay -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -3.333
set_min_delay -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -9.000
set_min_delay -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -9.000
set_min_delay -from  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]  -to  [get_clocks {sopc_system_inst|sdram|sopc_system_sdram_controller_phy_inst|sopc_system_sdram_phy_inst|sopc_system_sdram_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -3.333
set_min_delay -from [get_keepers {{mem_dq[0]} {mem_dq[1]} {mem_dq[2]} {mem_dq[3]} {mem_dq[4]} {mem_dq[5]} {mem_dq[6]} {mem_dq[7]}}] -1.217
set_min_delay -from [get_keepers {{mem_dq[10]} {mem_dq[11]} {mem_dq[12]} {mem_dq[13]} {mem_dq[14]} {mem_dq[15]} {mem_dq[8]} {mem_dq[9]}}] -1.217
set_min_delay -to [get_ports {flash_a[*] flash_d[*] flash_oe_n flash_ce_n flash_we_n flash_adv_n flash_olk}] 2.000
set_min_delay -from [get_ports {flash_d[*]}] -2.000
set_min_delay -to [get_ports {enet_mdc enet_mdio enet_reset_n}] 2.000
set_min_delay -from [get_ports {enet_mdio}] 0.000
set_min_delay -to [get_ports {altera_reserved_tdo}] 0.000
set_min_delay -from [get_ports {altera_reserved_tdi altera_reserved_tms}] 0.000


#**************************************************************
# Set Input Transition
#**************************************************************