ep_g3x8_avmm256_integrated

2016.05.16.23:04:47 Datasheet
Overview
  clk_0  ep_g3x8_avmm256_integrated

All Components
   DUT altera_pcie_a10_hip 15.1
   onchip_memory2_0 altera_avalon_onchip_memory2 15.1
   pio_button altera_avalon_pio 15.1
   pio_led altera_avalon_pio 15.1
Memory Map
DUT
 rxm_bar4  dma_rd_master  dma_wr_master  rd_dcm_master  wr_dcm_master
  DUT
txs  0x00000000 0x00000000
rd_dts_slave  0x80000000
wr_dts_slave  0x80002000
  onchip_memory2_0
s1  0x00000000 0x00000000
s2  0x00000000
  pio_button
s1  0x04000020
  pio_led
s1  0x04000010

DUT

altera_pcie_a10_hip v15.1
DUT dma_rd_master   onchip_memory2_0
  s1
dma_wr_master  
  s2
rxm_bar4  
  s1
coreclkout_hip  
  clk1
coreclkout_hip  
  clk2
app_nreset_status  
  reset1
app_nreset_status  
  reset2
rxm_bar4   pio_led
  s1
coreclkout_hip  
  clk
app_nreset_status  
  reset
rxm_bar4   pio_button
  s1
coreclkout_hip  
  clk
app_nreset_status  
  reset


Parameters

interface_type_hwtcl Avalon-MM with DMA
app_interface_width_hwtcl 256-bit
wrala_hwtcl 0
device_family ARRIA10
base_device NIGHTFURY5
part_trait_device 10AX115N3F45I2SG
bar0_address_width_mux_hwtcl 9
bar1_address_width_mux_hwtcl 0
bar2_address_width_mux_hwtcl 0
bar3_address_width_mux_hwtcl 0
bar4_address_width_mux_hwtcl 27
bar5_address_width_mux_hwtcl 0
st_signal_width_integer_hwtcl 1
data_width_integer_hwtcl 256
data_width_integer_rxm_txs_hwtcl 32
data_byte_width_integer_hwtcl 32
reconfig_address_width_integer_hwtcl 13
data_byte_width_integer_rxm_txs_hwtcl 4
burst_count_integer_hwtcl 5
empty_integer_hwtcl 2
port_type_integer_hwtcl 0
link_width_integer_hwtcl 8
lane_rate_integer_hwtcl 3
pld_clk_mhz_integer_hwtcl 2500
bar0_type_integer_hwtcl 1
bar1_type_integer_hwtcl 0
bar2_type_integer_hwtcl 0
bar3_type_integer_hwtcl 0
bar4_type_integer_hwtcl 1
bar5_type_integer_hwtcl 0
include_dma_hwtcl 1
txs_addr_width_integer_hwtcl 64
interface_type_integer_hwtcl 1
dma_width_hwtcl 256
dma_be_width_hwtcl 32
dma_brst_cnt_w_hwtcl 5
set_embedded_debug_enable_hwtcl 0
set_capability_reg_enable_hwtcl 0
set_csr_soft_logic_enable_hwtcl 0
set_prbs_soft_logic_enable_hwtcl 0
rcfg_jtag_enable_hwtcl 0
cpl_spc_header_hwtcl 195
cpl_spc_data_hwtcl 773
avmm_addr_width_hwtcl 64
cb_pcie_mode_hwtcl 0
cb_pcie_rx_lite_hwtcl 0
cg_impl_cra_av_slave_port_hwtcl 0
cg_enable_advanced_interrupt_hwtcl 0
cg_enable_a2p_interrupt_hwtcl 0
enable_hip_status_for_avmm_hwtcl 0
internal_controller_hwtcl 1
enable_rxm_burst_hwtcl 0
extended_tag_support_hwtcl 0
user_txs_addr_width_hwtcl 64
cg_a2p_addr_map_num_entries_hwtcl 2
cg_a2p_addr_map_pass_thru_bits_hwtcl 20
link_width_hwtcl x8
lane_rate_hwtcl Gen3 (8.0 Gbps)
port_type_hwtcl Native endpoint
pcie_spec_version_hwtcl 3.0
rx_buffer_credit_alloc_hwtcl Low
rx_buffer_post_credit_alloc_display Header:n/a Data:n/a
rx_buffer_nonpost_credit_alloc_display Header:n/a Data:n/a
rx_buffer_credit_alloc_display Header:195 Data:773
rx_cred_ctl_param_hwtcl 0
pll_refclk_freq_hwtcl 100 MHz
set_pld_clk_x1_625MHz_hwtcl 0
enable_avst_reset_hwtcl 0
use_rx_st_be_hwtcl 0
use_ast_parity_hwtcl 0
multiple_packets_per_cycle_hwtcl 0
cvp_enable_hwtcl 0
use_tx_cons_cred_sel_hwtcl 0
cseb_config_bypass_hwtcl 0
cseb_autonomous_hwtcl 0
speed_change_hwtcl 0
hip_reconfig_hwtcl 0
xcvr_reconfig_hwtcl 0
export_fpll_output_to_top_level_hwtcl 0
export_phy_input_to_top_level_hwtcl 0
enable_lmi_hwtcl 0
adme_enable_hwtcl 0
enable_devkit_conduit_hwtcl 0
enable_skp_det 0
select_design_example_hwtcl PIO
enable_example_design_qii_hwtcl 1
enable_example_design_sim_hwtcl 1
enable_example_design_synth_hwtcl 1
enable_example_design_tb_hwtcl 1
apps_type_hwtcl 0
select_design_example_rtl_lang_hwtcl Verilog
targeted_devkit_hwtcl Arria 10 FPGA Development Kit
bar0_type_hwtcl 64-bit prefetchable memory
bar0_address_width_hwtcl 28
bar1_type_hwtcl Disabled
bar1_address_width_hwtcl 0
bar2_type_hwtcl Disabled
bar2_address_width_hwtcl 0
bar3_type_hwtcl Disabled
bar3_address_width_hwtcl 0
bar4_type_hwtcl 64-bit prefetchable memory
bar4_address_width_hwtcl 0
bar5_type_hwtcl Disabled
bar5_address_width_hwtcl 0
expansion_base_address_register_hwtcl 0
bar0_address_width_avmm_hwtcl 0
bar1_address_width_avmm_hwtcl 0
bar2_address_width_avmm_hwtcl 0
bar3_address_width_avmm_hwtcl 0
bar4_address_width_avmm_hwtcl 27
bar5_address_width_avmm_hwtcl 0
io_window_addr_width_hwtcl 0
prefetchable_mem_window_addr_width_hwtcl 0
vendor_id_hwtcl 4466
device_id_hwtcl 57347
pf0_vf_device_id_hwtcl 0
revision_id_hwtcl 0
class_code_hwtcl 0
pf0_subclass_code_hwtcl 0
subsystem_vendor_id_hwtcl 0
subsystem_device_id_hwtcl 0
maximum_payload_size_hwtcl 256
extended_tag_field_hwtcl 32
completion_timeout_hwtcl NONE
completion_timeout_disable_hwtcl 1
enable_completion_timeout_disable_hwtcl 1
advance_error_reporting_hwtcl 0
ecrc_check_capable_hwtcl 0
ecrc_gen_capable_hwtcl 0
use_crc_forwarding_hwtcl 0
track_rxfc_cplbuf_ovf_hwtcl 0
port_link_number_hwtcl 1
dll_active_report_support_hwtcl 0
surprise_down_error_support_hwtcl 0
slot_clock_cfg_hwtcl 1
msi_multi_message_capable_hwtcl 4
user_id_hwtcl 0
enable_function_msix_support_hwtcl 0
msix_table_size_hwtcl 0
msix_table_offset_hwtcl 0
msix_table_bir_hwtcl 0
msix_pba_offset_hwtcl 0
msix_pba_bir_hwtcl 0
enable_slot_register_hwtcl 0
slot_power_scale_hwtcl 0
slot_power_limit_hwtcl 0
slot_number_hwtcl 0
endpoint_l0_latency_hwtcl 0
endpoint_l1_latency_hwtcl 0
deemphasis_enable_hwtcl 0
gen3_coeff_1_hwtcl 9
bfm_drive_interface_clk_hwtcl 1
bfm_drive_interface_npor_hwtcl 1
bfm_drive_interface_pipe_hwtcl 1
bfm_drive_interface_control_hwtcl 1
serial_sim_hwtcl 1
enable_pipe32_phyip_ser_driver_hwtcl 0
cseb_extend_pci_hwtcl 0
cseb_extend_pcie_hwtcl 0
reserved_debug_hwtcl 0
include_sriov_hwtcl 0
app_msi_req_fn_hwtcl 8
cfg_num_vf_width_hwtcl 8
flr_completed_vf_width_hwtcl 4
sriov2_en 0
total_pf_count_hwtcl 1
pf0_vf_count_user_hwtcl 0
pf1_vf_count_user_hwtcl 0
pf2_vf_count_user_hwtcl 0
pf3_vf_count_user_hwtcl 0
pf0_vf_count_hwtcl 0
pf1_vf_count_hwtcl 0
pf2_vf_count_hwtcl 0
pf3_vf_count_hwtcl 0
total_vf_count_hwtcl 4
total_pf_count_width_hwtcl 1
total_vf_count_width_hwtcl 1
system_page_sizes_supported_hwtcl 1363
sr_iov_support_hwtcl 0
ari_support_hwtcl 0
flr_capability_hwtcl 0
pf_tph_support_hwtcl 0
pf0_tph_int_mode_support_hwtcl 0
pf0_tph_dev_specific_mode_support_hwtcl 0
pf0_tph_st_table_location_hwtcl 0
pf0_tph_st_table_size_hwtcl 63
pf1_tph_int_mode_support_hwtcl 0
pf1_tph_dev_specific_mode_support_hwtcl 0
pf1_tph_st_table_location_hwtcl 0
pf1_tph_st_table_size_hwtcl 63
pf2_tph_int_mode_support_hwtcl 0
pf2_tph_dev_specific_mode_support_hwtcl 0
pf2_tph_st_table_location_hwtcl 0
pf2_tph_st_table_size_hwtcl 63
pf3_tph_int_mode_support_hwtcl 0
pf3_tph_dev_specific_mode_support_hwtcl 0
pf3_tph_st_table_location_hwtcl 0
pf3_tph_st_table_size_hwtcl 63
vf_tph_support_hwtcl 0
pf0_vf_tph_int_mode_support_hwtcl 0
pf0_vf_tph_dev_specific_mode_support_hwtcl 0
pf0_vf_tph_st_table_location_hwtcl 0
pf0_vf_tph_st_table_size_hwtcl 63
pf1_vf_tph_int_mode_support_hwtcl 0
pf1_vf_tph_dev_specific_mode_support_hwtcl 0
pf1_vf_tph_st_table_location_hwtcl 0
pf1_vf_tph_st_table_size_hwtcl 63
pf2_vf_tph_int_mode_support_hwtcl 0
pf2_vf_tph_dev_specific_mode_support_hwtcl 0
pf2_vf_tph_st_table_location_hwtcl 0
pf2_vf_tph_st_table_size_hwtcl 63
pf3_vf_tph_int_mode_support_hwtcl 0
pf3_vf_tph_dev_specific_mode_support_hwtcl 0
pf3_vf_tph_st_table_location_hwtcl 0
pf3_vf_tph_st_table_size_hwtcl 63
pf_ats_support_hwtcl 0
pf0_ats_invalidate_queue_depth_hwtcl 0
pf1_ats_invalidate_queue_depth_hwtcl 0
pf2_ats_invalidate_queue_depth_hwtcl 0
pf3_ats_invalidate_queue_depth_hwtcl 0
vf_ats_support_hwtcl 0
pf0_bar0_present_hwtcl 1
pf0_bar1_present_hwtcl 0
pf0_bar2_present_hwtcl 0
pf0_bar3_present_hwtcl 0
pf0_bar4_present_hwtcl 0
pf0_bar5_present_hwtcl 0
pf0_bar0_type_hwtcl 1
pf0_bar2_type_hwtcl 1
pf0_bar4_type_hwtcl 1
pf0_bar0_prefetchable_hwtcl 1
pf0_bar1_prefetchable_hwtcl 1
pf0_bar2_prefetchable_hwtcl 1
pf0_bar3_prefetchable_hwtcl 1
pf0_bar4_prefetchable_hwtcl 1
pf0_bar5_prefetchable_hwtcl 1
pf0_bar0_size_hwtcl 12
pf0_bar1_size_hwtcl 12
pf0_bar2_size_hwtcl 12
pf0_bar3_size_hwtcl 12
pf0_bar4_size_hwtcl 12
pf0_bar5_size_hwtcl 12
pf0_vf_bar0_present_hwtcl 0
pf0_vf_bar1_present_hwtcl 0
pf0_vf_bar2_present_hwtcl 0
pf0_vf_bar3_present_hwtcl 0
pf0_vf_bar4_present_hwtcl 0
pf0_vf_bar5_present_hwtcl 0
pf0_vf_bar0_type_hwtcl 1
pf0_vf_bar2_type_hwtcl 1
pf0_vf_bar4_type_hwtcl 1
pf0_vf_bar0_prefetchable_hwtcl 1
pf0_vf_bar1_prefetchable_hwtcl 1
pf0_vf_bar2_prefetchable_hwtcl 1
pf0_vf_bar3_prefetchable_hwtcl 1
pf0_vf_bar4_prefetchable_hwtcl 1
pf0_vf_bar5_prefetchable_hwtcl 1
pf0_vf_bar0_size_hwtcl 12
pf0_vf_bar1_size_hwtcl 12
pf0_vf_bar2_size_hwtcl 12
pf0_vf_bar3_size_hwtcl 12
pf0_vf_bar4_size_hwtcl 12
pf0_vf_bar5_size_hwtcl 12
pf1_bar0_present_hwtcl 0
pf1_bar1_present_hwtcl 0
pf1_bar2_present_hwtcl 0
pf1_bar3_present_hwtcl 0
pf1_bar4_present_hwtcl 0
pf1_bar5_present_hwtcl 0
pf1_bar0_type_hwtcl 1
pf1_bar2_type_hwtcl 1
pf1_bar4_type_hwtcl 1
pf1_bar0_prefetchable_hwtcl 1
pf1_bar1_prefetchable_hwtcl 1
pf1_bar2_prefetchable_hwtcl 1
pf1_bar3_prefetchable_hwtcl 1
pf1_bar4_prefetchable_hwtcl 1
pf1_bar5_prefetchable_hwtcl 1
pf1_bar0_size_hwtcl 12
pf1_bar1_size_hwtcl 12
pf1_bar2_size_hwtcl 12
pf1_bar3_size_hwtcl 12
pf1_bar4_size_hwtcl 12
pf1_bar5_size_hwtcl 12
pf1_vf_bar0_present_hwtcl 0
pf1_vf_bar1_present_hwtcl 0
pf1_vf_bar2_present_hwtcl 0
pf1_vf_bar3_present_hwtcl 0
pf1_vf_bar4_present_hwtcl 0
pf1_vf_bar5_present_hwtcl 0
pf1_vf_bar0_type_hwtcl 1
pf1_vf_bar2_type_hwtcl 1
pf1_vf_bar4_type_hwtcl 1
pf1_vf_bar0_prefetchable_hwtcl 1
pf1_vf_bar1_prefetchable_hwtcl 1
pf1_vf_bar2_prefetchable_hwtcl 1
pf1_vf_bar3_prefetchable_hwtcl 1
pf1_vf_bar4_prefetchable_hwtcl 1
pf1_vf_bar5_prefetchable_hwtcl 1
pf1_vf_bar0_size_hwtcl 12
pf1_vf_bar1_size_hwtcl 12
pf1_vf_bar2_size_hwtcl 12
pf1_vf_bar3_size_hwtcl 12
pf1_vf_bar4_size_hwtcl 12
pf1_vf_bar5_size_hwtcl 12
pf2_bar0_present_hwtcl 0
pf2_bar1_present_hwtcl 0
pf2_bar2_present_hwtcl 0
pf2_bar3_present_hwtcl 0
pf2_bar4_present_hwtcl 0
pf2_bar5_present_hwtcl 0
pf2_bar0_type_hwtcl 1
pf2_bar2_type_hwtcl 1
pf2_bar4_type_hwtcl 1
pf2_bar0_prefetchable_hwtcl 1
pf2_bar1_prefetchable_hwtcl 1
pf2_bar2_prefetchable_hwtcl 1
pf2_bar3_prefetchable_hwtcl 1
pf2_bar4_prefetchable_hwtcl 1
pf2_bar5_prefetchable_hwtcl 1
pf2_bar0_size_hwtcl 12
pf2_bar1_size_hwtcl 12
pf2_bar2_size_hwtcl 12
pf2_bar3_size_hwtcl 12
pf2_bar4_size_hwtcl 12
pf2_bar5_size_hwtcl 12
pf2_vf_bar0_present_hwtcl 0
pf2_vf_bar1_present_hwtcl 0
pf2_vf_bar2_present_hwtcl 0
pf2_vf_bar3_present_hwtcl 0
pf2_vf_bar4_present_hwtcl 0
pf2_vf_bar5_present_hwtcl 0
pf2_vf_bar0_type_hwtcl 1
pf2_vf_bar2_type_hwtcl 1
pf2_vf_bar4_type_hwtcl 1
pf2_vf_bar0_prefetchable_hwtcl 1
pf2_vf_bar1_prefetchable_hwtcl 1
pf2_vf_bar2_prefetchable_hwtcl 1
pf2_vf_bar3_prefetchable_hwtcl 1
pf2_vf_bar4_prefetchable_hwtcl 1
pf2_vf_bar5_prefetchable_hwtcl 1
pf2_vf_bar0_size_hwtcl 12
pf2_vf_bar1_size_hwtcl 12
pf2_vf_bar2_size_hwtcl 12
pf2_vf_bar3_size_hwtcl 12
pf2_vf_bar4_size_hwtcl 12
pf2_vf_bar5_size_hwtcl 12
pf3_bar0_present_hwtcl 0
pf3_bar1_present_hwtcl 0
pf3_bar2_present_hwtcl 0
pf3_bar3_present_hwtcl 0
pf3_bar4_present_hwtcl 0
pf3_bar5_present_hwtcl 0
pf3_bar0_type_hwtcl 1
pf3_bar2_type_hwtcl 1
pf3_bar4_type_hwtcl 1
pf3_bar0_prefetchable_hwtcl 1
pf3_bar1_prefetchable_hwtcl 1
pf3_bar2_prefetchable_hwtcl 1
pf3_bar3_prefetchable_hwtcl 1
pf3_bar4_prefetchable_hwtcl 1
pf3_bar5_prefetchable_hwtcl 1
pf3_bar0_size_hwtcl 12
pf3_bar1_size_hwtcl 12
pf3_bar2_size_hwtcl 12
pf3_bar3_size_hwtcl 12
pf3_bar4_size_hwtcl 12
pf3_bar5_size_hwtcl 12
pf3_vf_bar0_present_hwtcl 0
pf3_vf_bar1_present_hwtcl 0
pf3_vf_bar2_present_hwtcl 0
pf3_vf_bar3_present_hwtcl 0
pf3_vf_bar4_present_hwtcl 0
pf3_vf_bar5_present_hwtcl 0
pf3_vf_bar0_type_hwtcl 1
pf3_vf_bar2_type_hwtcl 1
pf3_vf_bar4_type_hwtcl 1
pf3_vf_bar0_prefetchable_hwtcl 1
pf3_vf_bar1_prefetchable_hwtcl 1
pf3_vf_bar2_prefetchable_hwtcl 1
pf3_vf_bar3_prefetchable_hwtcl 1
pf3_vf_bar4_prefetchable_hwtcl 1
pf3_vf_bar5_prefetchable_hwtcl 1
pf3_vf_bar0_size_hwtcl 12
pf3_vf_bar1_size_hwtcl 12
pf3_vf_bar2_size_hwtcl 12
pf3_vf_bar3_size_hwtcl 12
pf3_vf_bar4_size_hwtcl 12
pf3_vf_bar5_size_hwtcl 12
pf1_vendor_id_hwtcl 0
pf1_device_id_hwtcl 0
pf1_vf_device_id_hwtcl 0
pf1_revision_id_hwtcl 0
pf1_class_code_hwtcl 0
pf1_subclass_code_hwtcl 0
pf1_subsystem_vendor_id_hwtcl 0
pf1_subsystem_device_id_hwtcl 0
pf2_vendor_id_hwtcl 0
pf2_device_id_hwtcl 0
pf2_vf_device_id_hwtcl 0
pf2_revision_id_hwtcl 0
pf2_class_code_hwtcl 0
pf2_subclass_code_hwtcl 0
pf2_subsystem_vendor_id_hwtcl 0
pf2_subsystem_device_id_hwtcl 0
pf3_vendor_id_hwtcl 0
pf3_device_id_hwtcl 0
pf3_vf_device_id_hwtcl 0
pf3_revision_id_hwtcl 0
pf3_class_code_hwtcl 0
pf3_subclass_code_hwtcl 0
pf3_subsystem_vendor_id_hwtcl 0
pf3_subsystem_device_id_hwtcl 0
pf_msi_support_hwtcl 0
pf0_msi_multi_message_capable_hwtcl 4
pf1_msi_multi_message_capable_hwtcl 4
pf_enable_function_msix_support_hwtcl 0
vf_msix_cap_present_hwtcl 0
pf0_msix_table_size_hwtcl 0
pf0_msix_table_offset_hwtcl 0
pf0_msix_table_bir_hwtcl 0
pf0_msix_pba_offset_hwtcl 0
pf0_msix_pba_bir_hwtcl 0
pf1_msix_table_size_hwtcl 0
pf1_msix_table_offset_hwtcl 0
pf1_msix_table_bir_hwtcl 0
pf1_msix_pba_offset_hwtcl 0
pf1_msix_pba_bir_hwtcl 0
pf2_msix_table_size_hwtcl 0
pf2_msix_table_offset_hwtcl 0
pf2_msix_table_bir_hwtcl 0
pf2_msix_pba_offset_hwtcl 0
pf2_msix_pba_bir_hwtcl 0
pf3_msix_table_size_hwtcl 0
pf3_msix_table_offset_hwtcl 0
pf3_msix_table_bir_hwtcl 0
pf3_msix_pba_offset_hwtcl 0
pf3_msix_pba_bir_hwtcl 0
pf0_vf_msix_tbl_size_hwtcl 0
pf0_vf_msix_tbl_offset_hwtcl 0
pf0_vf_msix_tbl_bir_hwtcl 0
pf0_vf_msix_pba_offset_hwtcl 0
pf0_vf_msix_pba_bir_hwtcl 0
pf1_vf_msix_tbl_size_hwtcl 0
pf1_vf_msix_tbl_offset_hwtcl 0
pf1_vf_msix_tbl_bir_hwtcl 0
pf1_vf_msix_pba_offset_hwtcl 0
pf1_vf_msix_pba_bir_hwtcl 0
pf2_vf_msix_tbl_size_hwtcl 0
pf2_vf_msix_tbl_offset_hwtcl 0
pf2_vf_msix_tbl_bir_hwtcl 0
pf2_vf_msix_pba_offset_hwtcl 0
pf2_vf_msix_pba_bir_hwtcl 0
pf3_vf_msix_tbl_size_hwtcl 0
pf3_vf_msix_tbl_offset_hwtcl 0
pf3_vf_msix_tbl_bir_hwtcl 0
pf3_vf_msix_pba_offset_hwtcl 0
pf3_vf_msix_pba_bir_hwtcl 0
pf0_interrupt_pin_hwtcl inta
pf1_interrupt_pin_hwtcl inta
pf2_interrupt_pin_hwtcl inta
pf3_interrupt_pin_hwtcl inta
pf0_intr_line_hwtcl 0
pf1_intr_line_hwtcl 0
pf2_intr_line_hwtcl 0
pf3_intr_line_hwtcl 0
app_msi_addr_pf_hwtcl 64
app_msi_data_pf_hwtcl 16
app_msi_mask_pf_hwtcl 32
app_msi_msg_en_pf_hwtcl 3
sim_sriov_dma_hwtcl 0
link2csr_width_hwtcl 16
lmi_width_hwtcl 8
cseb_route_to_avl_rx_st_hwtcl 0
test_cseb_switch_hwtcl 0
cseb_temp_busy_crs_hwtcl 0
message_level error
rx_polinv_soft_logic_enable 0
slave_address_map_0_hwtcl 0
slave_address_map_1_hwtcl 0
slave_address_map_2_hwtcl 0
slave_address_map_2_hprxm_hwtcl 0
slave_address_map_3_hwtcl 0
slave_address_map_4_hwtcl 27
slave_address_map_5_hwtcl 0
design_environment_hwtcl QSYS
tlp_inspector_hwtcl 0
tlp_inspector_use_signal_probe_hwtcl 0
tlp_inspector_use_thin_rx_master 0
tlp_insp_trg_dw0_hwtcl 2049
tlp_insp_trg_dw1_hwtcl 0
tlp_insp_trg_dw2_hwtcl 0
enable_ast_trs_hwtcl 0
ast_trs_num_desc_hwtcl 16
ast_trs_txdata_width_hwtcl 256
ast_trs_txdesc_width_hwtcl 256
ast_trs_txstatus_width_hwtcl 256
ast_trs_rxdata_width_hwtcl 256
ast_trs_rxdesc_width_hwtcl 256
ast_trs_txmty_width_hwtcl 32
ast_trs_rxmty_width_hwtcl 32
dma_use_scfifo_ext_hwtcl 0
use_dynamic_design_example_hwtcl 0
silicon_rev 20nm5es
hip_ac_pwr_clk_freq_in_hz 250000000
ko_compl_data 773
ko_compl_header 195
acknack_base 0
acknack_set false
advance_error_reporting disable
app_interface_width avst_256bit
arb_upfc_30us_counter 0
arb_upfc_30us_en enable
aspm_config_management true
aspm_patch_disable enable_both
ast_width_rx rx_256
ast_width_tx tx_256
atomic_malformed false
atomic_op_completer_32bit false
atomic_op_completer_64bit false
atomic_op_routing false
auto_msg_drop_enable false
bar0_size_mask 0
bar0_type bar0_64bit_prefetch_mem
bar1_size_mask 0
bar1_type bar1_disable
bar2_size_mask 0
bar2_type bar2_disable
bar3_size_mask 0
bar3_type bar3_disable
bar4_size_mask 0
bar4_type bar4_64bit_prefetch_mem
bar5_size_mask 0
bar5_type bar5_disable
base_counter_sel count_clk_62p5
bist_memory_settings 2417851639246850506078208
bridge_port_ssid_support false
bridge_port_vga_enable false
bypass_cdc false
bypass_clk_switch false
bypass_tl false
cas_completer_128bit false
cdc_clk_relation mesochronous
cdc_dummy_insert_limit 11
cfg_parchk_ena disable
cfgbp_req_recov_disable false
class_code 0
clock_pwr_management false
completion_timeout none_compl_timeout
core_clk_divider div_2
core_clk_freq_mhz core_clk_250mhz
core_clk_out_sel core_clk_out_div_1
core_clk_sel pld_clk
core_clk_source pll_fixed_clk
cseb_bar_match_checking enable
cseb_config_bypass disable
cseb_cpl_status_during_cvp config_retry_status
cseb_cpl_tag_checking enable
cseb_disable_auto_crs false
cseb_extend_pci false
cseb_extend_pcie false
cseb_min_error_checking false
cseb_route_to_avl_rx_st cseb
cseb_temp_busy_crs completer_abort_tmp_busy
cvp_clk_reset false
cvp_data_compressed false
cvp_data_encrypted false
cvp_enable cvp_dis
cvp_mode_reset false
cvp_rate_sel full_rate
d0_pme false
d1_pme false
d1_support false
d2_pme false
d2_support false
d3_cold_pme false
d3_hot_pme false
data_pack_rx disable
deemphasis_enable false
deskew_comma skp_eieos_deskw
device_id 57347
device_number 0
device_specific_init false
dft_clock_obsrv_en disable
dft_clock_obsrv_sel dft_pclk
diffclock_nfts_count 128
dis_cplovf disable
dis_paritychk disable
disable_link_x2_support false
disable_snoop_packet false
dl_tx_check_parity_edb disable
dll_active_report_support false
early_dl_up false
ecrc_check_capable false
ecrc_gen_capable false
egress_block_err_report_ena false
ei_delay_powerdown_count 10
eie_before_nfts_count 4
electromech_interlock false
en_ieiupdatefc false
en_lane_errchk false
en_phystatus_dly false
ena_ido_cpl false
ena_ido_req false
enable_adapter_half_rate_mode false
enable_ch0_pclk_out pclk_central
enable_ch01_pclk_out pclk_ch0
enable_completion_timeout_disable true
enable_directed_spd_chng false
enable_function_msix_support false
enable_l0s_aspm false
enable_l1_aspm false
enable_rx_buffer_checking false
enable_rx_reordering true
enable_slot_register false
endpoint_l0_latency 0
endpoint_l1_latency 0
eql_rq_int_en_number 0
errmgt_fcpe_patch_dis enable
errmgt_fep_patch_dis enable
expansion_base_address_register 0
extend_tag_field false
extended_format_field true
extended_tag_reset false
fc_init_timer 1024
flow_control_timeout_count 200
flow_control_update_count 30
flr_capability false
force_dis_to_det false
force_gen1_dis false
force_tx_coeff_preset_lpbk false
frame_err_patch_dis enable
func_mode enable
g3_bypass_equlz false
g3_coeff_done_tmout enable
g3_deskew_char default_sdsos
g3_dis_be_frm_err false
g3_dn_rx_hint_eqlz_0 0
g3_dn_rx_hint_eqlz_1 0
g3_dn_rx_hint_eqlz_2 0
g3_dn_rx_hint_eqlz_3 0
g3_dn_rx_hint_eqlz_4 0
g3_dn_rx_hint_eqlz_5 0
g3_dn_rx_hint_eqlz_6 0
g3_dn_rx_hint_eqlz_7 0
g3_dn_tx_preset_eqlz_0 0
g3_dn_tx_preset_eqlz_1 0
g3_dn_tx_preset_eqlz_2 0
g3_dn_tx_preset_eqlz_3 0
g3_dn_tx_preset_eqlz_4 0
g3_dn_tx_preset_eqlz_5 0
g3_dn_tx_preset_eqlz_6 0
g3_dn_tx_preset_eqlz_7 0
g3_force_ber_max false
g3_force_ber_min true
g3_lnk_trn_rx_ts false
g3_ltssm_eq_dbg false
g3_ltssm_rec_dbg false
g3_pause_ltssm_rec_en disable
g3_quiesce_guarant false
g3_redo_equlz_dis false
g3_redo_equlz_en false
g3_up_rx_hint_eqlz_0 0
g3_up_rx_hint_eqlz_1 0
g3_up_rx_hint_eqlz_2 0
g3_up_rx_hint_eqlz_3 0
g3_up_rx_hint_eqlz_4 0
g3_up_rx_hint_eqlz_5 0
g3_up_rx_hint_eqlz_6 0
g3_up_rx_hint_eqlz_7 0
g3_up_tx_preset_eqlz_0 0
g3_up_tx_preset_eqlz_1 0
g3_up_tx_preset_eqlz_2 0
g3_up_tx_preset_eqlz_3 0
g3_up_tx_preset_eqlz_4 0
g3_up_tx_preset_eqlz_5 0
g3_up_tx_preset_eqlz_6 0
g3_up_tx_preset_eqlz_7 0
gen123_lane_rate_mode gen1_gen2_gen3
gen2_diffclock_nfts_count 255
gen2_pma_pll_usage not_applicaple
gen2_sameclock_nfts_count 255
gen3_coeff_1 9
gen3_coeff_1_ber_meas 4
gen3_coeff_1_nxtber_less 1
gen3_coeff_1_nxtber_more 1
gen3_coeff_1_preset_hint 0
gen3_coeff_1_reqber 0
gen3_coeff_1_sel preset_1
gen3_coeff_10 0
gen3_coeff_10_ber_meas 0
gen3_coeff_10_nxtber_less 0
gen3_coeff_10_nxtber_more 0
gen3_coeff_10_preset_hint 0
gen3_coeff_10_reqber 0
gen3_coeff_10_sel preset_10
gen3_coeff_11 0
gen3_coeff_11_ber_meas 0
gen3_coeff_11_nxtber_less 0
gen3_coeff_11_nxtber_more 0
gen3_coeff_11_preset_hint 0
gen3_coeff_11_reqber 0
gen3_coeff_11_sel preset_11
gen3_coeff_12 0
gen3_coeff_12_ber_meas 0
gen3_coeff_12_nxtber_less 0
gen3_coeff_12_nxtber_more 0
gen3_coeff_12_preset_hint 0
gen3_coeff_12_reqber 0
gen3_coeff_12_sel preset_12
gen3_coeff_13 0
gen3_coeff_13_ber_meas 0
gen3_coeff_13_nxtber_less 0
gen3_coeff_13_nxtber_more 0
gen3_coeff_13_preset_hint 0
gen3_coeff_13_reqber 0
gen3_coeff_13_sel preset_13
gen3_coeff_14 0
gen3_coeff_14_ber_meas 0
gen3_coeff_14_nxtber_less 0
gen3_coeff_14_nxtber_more 0
gen3_coeff_14_preset_hint 0
gen3_coeff_14_reqber 0
gen3_coeff_14_sel preset_14
gen3_coeff_15 0
gen3_coeff_15_ber_meas 0
gen3_coeff_15_nxtber_less 0
gen3_coeff_15_nxtber_more 0
gen3_coeff_15_preset_hint 0
gen3_coeff_15_reqber 0
gen3_coeff_15_sel preset_15
gen3_coeff_16 0
gen3_coeff_16_ber_meas 0
gen3_coeff_16_nxtber_less 0
gen3_coeff_16_nxtber_more 0
gen3_coeff_16_preset_hint 0
gen3_coeff_16_reqber 0
gen3_coeff_16_sel preset_16
gen3_coeff_17 196608
gen3_coeff_17_ber_meas 0
gen3_coeff_17_nxtber_less 0
gen3_coeff_17_nxtber_more 0
gen3_coeff_17_preset_hint 0
gen3_coeff_17_reqber 0
gen3_coeff_17_sel preset_17
gen3_coeff_18 196609
gen3_coeff_18_ber_meas 0
gen3_coeff_18_nxtber_less 0
gen3_coeff_18_nxtber_more 0
gen3_coeff_18_preset_hint 0
gen3_coeff_18_reqber 0
gen3_coeff_18_sel preset_18
gen3_coeff_19 196609
gen3_coeff_19_ber_meas 0
gen3_coeff_19_nxtber_less 0
gen3_coeff_19_nxtber_more 0
gen3_coeff_19_preset_hint 0
gen3_coeff_19_reqber 0
gen3_coeff_19_sel preset_19
gen3_coeff_2 9
gen3_coeff_2_ber_meas 4
gen3_coeff_2_nxtber_less 2
gen3_coeff_2_nxtber_more 2
gen3_coeff_2_preset_hint 7
gen3_coeff_2_reqber 0
gen3_coeff_2_sel preset_2
gen3_coeff_20 196609
gen3_coeff_20_ber_meas 0
gen3_coeff_20_nxtber_less 0
gen3_coeff_20_nxtber_more 0
gen3_coeff_20_preset_hint 0
gen3_coeff_20_reqber 0
gen3_coeff_20_sel preset_20
gen3_coeff_21 196609
gen3_coeff_21_ber_meas 0
gen3_coeff_21_nxtber_less 0
gen3_coeff_21_nxtber_more 0
gen3_coeff_21_preset_hint 0
gen3_coeff_21_reqber 0
gen3_coeff_21_sel preset_21
gen3_coeff_22 196609
gen3_coeff_22_ber_meas 0
gen3_coeff_22_nxtber_less 7
gen3_coeff_22_nxtber_more 0
gen3_coeff_22_preset_hint 0
gen3_coeff_22_reqber 0
gen3_coeff_22_sel preset_22
gen3_coeff_23 196609
gen3_coeff_23_ber_meas 0
gen3_coeff_23_nxtber_less 0
gen3_coeff_23_nxtber_more 0
gen3_coeff_23_preset_hint 0
gen3_coeff_23_reqber 0
gen3_coeff_23_sel preset_23
gen3_coeff_24 196609
gen3_coeff_24_ber_meas 0
gen3_coeff_24_nxtber_less 0
gen3_coeff_24_nxtber_more 0
gen3_coeff_24_preset_hint 7
gen3_coeff_24_reqber 0
gen3_coeff_24_sel preset_24
gen3_coeff_3 9
gen3_coeff_3_ber_meas 8
gen3_coeff_3_nxtber_less 4
gen3_coeff_3_nxtber_more 4
gen3_coeff_3_preset_hint 7
gen3_coeff_3_reqber 31
gen3_coeff_3_sel preset_3
gen3_coeff_4 8
gen3_coeff_4_ber_meas 4
gen3_coeff_4_nxtber_less 4
gen3_coeff_4_nxtber_more 4
gen3_coeff_4_preset_hint 7
gen3_coeff_4_reqber 31
gen3_coeff_4_sel preset_4
gen3_coeff_5 0
gen3_coeff_5_ber_meas 0
gen3_coeff_5_nxtber_less 0
gen3_coeff_5_nxtber_more 0
gen3_coeff_5_preset_hint 7
gen3_coeff_5_reqber 0
gen3_coeff_5_sel preset_5
gen3_coeff_6 0
gen3_coeff_6_ber_meas 0
gen3_coeff_6_nxtber_less 0
gen3_coeff_6_nxtber_more 0
gen3_coeff_6_preset_hint 0
gen3_coeff_6_reqber 0
gen3_coeff_6_sel preset_6
gen3_coeff_7 0
gen3_coeff_7_ber_meas 0
gen3_coeff_7_nxtber_less 0
gen3_coeff_7_nxtber_more 0
gen3_coeff_7_preset_hint 0
gen3_coeff_7_reqber 0
gen3_coeff_7_sel preset_7
gen3_coeff_8 0
gen3_coeff_8_ber_meas 0
gen3_coeff_8_nxtber_less 0
gen3_coeff_8_nxtber_more 0
gen3_coeff_8_preset_hint 0
gen3_coeff_8_reqber 0
gen3_coeff_8_sel preset_8
gen3_coeff_9 0
gen3_coeff_9_ber_meas 0
gen3_coeff_9_nxtber_less 0
gen3_coeff_9_nxtber_more 0
gen3_coeff_9_preset_hint 0
gen3_coeff_9_reqber 0
gen3_coeff_9_sel preset_9
gen3_coeff_delay_count 125
gen3_coeff_errchk enable
gen3_dcbal_en true
gen3_diffclock_nfts_count 128
gen3_force_local_coeff false
gen3_full_swing 60
gen3_half_swing false
gen3_low_freq 20
gen3_paritychk enable
gen3_pl_framing_err_dis enable
gen3_preset_coeff_1 64320
gen3_preset_coeff_10 3210
gen3_preset_coeff_11 84480
gen3_preset_coeff_2 44160
gen3_preset_coeff_3 52224
gen3_preset_coeff_4 36096
gen3_preset_coeff_5 3840
gen3_preset_coeff_6 3462
gen3_preset_coeff_7 3336
gen3_preset_coeff_8 51846
gen3_preset_coeff_9 35592
gen3_reset_eieos_cnt_bit false
gen3_rxfreqlock_counter 0
gen3_sameclock_nfts_count 128
gen3_scrdscr_bypass false
gen3_skip_ph2_ph3 false
hard_reset_bypass false
hard_rst_sig_chnl_en enable_hrc_sig_x8
hard_rst_tx_pll_rst_chnl_en enable_hrc_txpll_rst_ch34
hip_base_address 0
hip_clock_dis enable_hip_clk
hip_hard_reset enable
hip_pcs_sig_chnl_en enable_hip_pcs_sig_x8
hot_plug_support 0
hrc_chnl_txpll_master_cgb_rst_select ch3_master_cgb_sel
hrdrstctrl_en hrdrstctrl_en
iei_enable_settings gen3_infei_infsd_gen2_infsd_gen1_infsd_sd
indicator 0
intel_id_access false
interrupt_pin inta
io_window_addr_width none
jtag_id 0
l0_exit_latency_diffclock 6
l0_exit_latency_sameclock 6
l01_entry_latency 31
l0s_adj_rply_timer_dis enable
l1_exit_latency_diffclock 0
l1_exit_latency_sameclock 0
l2_async_logic disable
lane_mask ln_mask_x8
lane_rate gen3
link_width x8
low_priority_vc single_vc_low_pr
ltr_mechanism false
ltssm_1ms_timeout disable
ltssm_freqlocked_check disable
malformed_tlp_truncate_en disable
max_link_width x8_link_width
max_payload_size payload_256
maximum_current 0
millisecond_cycle_count 248496
msi_64bit_addressing_capable true
msi_masking_capable false
msi_multi_message_capable count_4
msi_support true
msix_pba_bir 0
msix_pba_offset 0
msix_table_bir 0
msix_table_offset 0
msix_table_size 0
national_inst_thru_enhance false
no_command_completed false
no_soft_reset false
pcie_base_spec pcie_3p0
pcie_mode ep_native
pcie_spec_1p0_compliance spec_1p1
pcie_spec_version v3
pclk_out_sel pclk
pld_in_use_reg false
pm_latency_patch_dis enable
pm_txdl_patch_dis enable
pme_clock false
port_link_number 1
port_type native_ep
powerdown_mode powerup
prefetchable_mem_window_addr_width prefetch_0
r2c_mask_easy false
r2c_mask_enable false
rec_frqlk_mon_en disable
register_pipe_signals true
retry_buffer_last_active_address 1023
retry_buffer_memory_settings 12885005388
retry_ecc_corr_mask_dis enable
revision_id 0
role_based_error_reporting true
rp_bug_fix_pri_sec_stat_reg 127
rpltim_base 16
rpltim_set true
rstctl_ltssm_dis false
rstctrl_1ms_count_fref_clk 100000
rstctrl_1us_count_fref_clk 100
rstctrl_altpe3_crst_n_inv false
rstctrl_altpe3_rst_n_inv false
rstctrl_altpe3_srst_n_inv false
rstctrl_chnl_cal_done_select ch01234567_out_chnl_cal_done
rstctrl_debug_en false
rstctrl_force_inactive_rst false
rstctrl_fref_clk_select ch0_sel
rstctrl_hard_block_enable hard_rst_ctl
rstctrl_hip_ep hip_ep
rstctrl_mask_tx_pll_lock_select ch3_sel_mask_tx_pll_lock
rstctrl_perst_enable level
rstctrl_perstn_select perstn_pin
rstctrl_pld_clr true
rstctrl_pll_cal_done_select ch34_sel_pll_cal_done
rstctrl_rx_pcs_rst_n_inv false
rstctrl_rx_pcs_rst_n_select ch01234567_out_rx_pcs_rst
rstctrl_rx_pll_freq_lock_select not_active_rx_pll_f_lock
rstctrl_rx_pll_lock_select ch01234567_sel_rx_pll_lock
rstctrl_rx_pma_rstb_inv false
rstctrl_rx_pma_rstb_select ch01234567_out_rx_pma_rstb
rstctrl_timer_a 10
rstctrl_timer_a_type a_timer_fref_cycles
rstctrl_timer_b 10
rstctrl_timer_b_type b_timer_fref_cycles
rstctrl_timer_c 10
rstctrl_timer_c_type c_timer_fref_cycles
rstctrl_timer_d 20
rstctrl_timer_d_type d_timer_fref_cycles
rstctrl_timer_e 1
rstctrl_timer_e_type e_timer_fref_cycles
rstctrl_timer_f 10
rstctrl_timer_f_type f_timer_fref_cycles
rstctrl_timer_g 10
rstctrl_timer_g_type g_timer_fref_cycles
rstctrl_timer_h 4
rstctrl_timer_h_type h_timer_micro_secs
rstctrl_timer_i 20
rstctrl_timer_i_type i_timer_fref_cycles
rstctrl_timer_j 20
rstctrl_timer_j_type j_timer_fref_cycles
rstctrl_tx_lcff_pll_lock_select ch34_sel_lcff_pll_lock
rstctrl_tx_lcff_pll_rstb_select ch34_out_lcff_pll_rstb
rstctrl_tx_pcs_rst_n_inv false
rstctrl_tx_pcs_rst_n_select ch01234567_out_tx_pcs_rst
rstctrl_tx_pma_rstb_inv false
rstctrl_tx_pma_syncp_inv false
rstctrl_tx_pma_syncp_select ch3_out_tx_pma_syncp
rx_ast_parity disable
rx_buffer_credit_alloc low
rx_buffer_fc_protect 68
rx_buffer_protect 68
rx_cdc_almost_empty 3
rx_cdc_almost_full 12
rx_cred_ctl_param disable
rx_ei_l0s disable
rx_l0s_count_idl 0
rx_ptr0_nonposted_dpram_max 2047
rx_ptr0_nonposted_dpram_min 2008
rx_ptr0_posted_dpram_max 2007
rx_ptr0_posted_dpram_min 0
rx_runt_patch_dis enable
rx_sop_ctrl rx_sop_boundary_256
rx_trunc_patch_dis enable
rx_use_prst true
rx_use_prst_ep true
rxbuf_ecc_corr_mask_dis enable
sameclock_nfts_count 128
sel_enable_pcs_rx_fifo_err disable_sel
sim_mode disable
simple_ro_fifo_control_en disable
single_rx_detect detect_all_lanes
skp_os_gen3_count 0
skp_os_schedule_count 0
slot_number 0
slot_power_limit 0
slot_power_scale 0
slotclk_cfg static_slotclkcfgon
ssid 0
ssvid 0
subsystem_device_id 0
subsystem_vendor_id 0
sup_mode user_mode
surprise_down_error_support false
tl_cfg_div cfg_clk_div_7
tl_tx_check_parity_msg disable
tph_completer false
tx_ast_parity disable
tx_cdc_almost_empty 5
tx_cdc_almost_full 11
tx_sop_ctrl boundary_256
tx_swing 0
txdl_fair_arbiter_counter 0
txdl_fair_arbiter_en enable
txrate_adv capability
uc_calibration_en uc_calibration_en
use_aer false
use_crc_forwarding false
user_id 0
vc_arbitration single_vc_arb
vc_enable single_vc
vc0_clk_enable true
vc0_rx_buffer_memory_settings 12885005388
vc0_rx_flow_ctrl_compl_data 0
vc0_rx_flow_ctrl_compl_header 0
vc0_rx_flow_ctrl_nonposted_data 0
vc0_rx_flow_ctrl_nonposted_header 16
vc0_rx_flow_ctrl_posted_data 16
vc0_rx_flow_ctrl_posted_header 16
vc1_clk_enable false
vendor_id 4466
vsec_cap 0
vsec_id 0
wrong_device_id disable
not_use_k_gbl_bits not_used_k_gbl
avmm_force_inter_sel_csr_ctrl disable
operating_voltage standard
rxdl_bad_tlp_patch_dis rxdlbug2_enable_both
avmm_dprio_broadcast_en_csr_ctrl disable
hip_ac_pwr_uw_per_mhz 828
rxdl_bad_sop_eop_filter_dis rxdlbug1_enable_both
rxdl_lcrc_patch_dis rxdlbug3_enable_both
capab_rate_rxcfg_en disable
avmm_cvp_inter_sel_csr_ctrl disable
lmi_hold_off_cfg_timer_en disable
avmm_power_iso_en_csr_ctrl disable
AUTO_RXM_IRQ_INTERRUPTS_USED -1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

clk_0

clock_source v15.1


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

onchip_memory2_0

altera_avalon_onchip_memory2 v15.1
DUT dma_rd_master   onchip_memory2_0
  s1
dma_wr_master  
  s2
rxm_bar4  
  s1
coreclkout_hip  
  clk1
coreclkout_hip  
  clk2
app_nreset_status  
  reset1
app_nreset_status  
  reset2


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 256
dualPort true
initMemContent false
initializationFileName onchip_mem
instanceID NONE
memorySize 524288
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
simMemInitOnlyFilename 0
singleClockOperation false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
copyInitFile false
useShallowMemBlocks false
writable true
ecc_enabled false
resetrequest_enabled true
autoInitializationFileName ep_g3x8_avmm256_integrated_onchip_memory2_0
deviceFamily ARRIA10
deviceFeatures ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0
derived_set_addr_width 14
derived_set_data_width 256
derived_gui_ram_block_type Automatic
derived_is_hardcopy false
derived_init_file_name ep_g3x8_avmm256_integrated_onchip_memory2_0.hex
generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 1
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE ep_g3x8_avmm256_integrated_onchip_memory2_0
INIT_MEM_CONTENT 0
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 524288
WRITABLE 1

pio_button

altera_avalon_pio v15.1
DUT rxm_bar4   pio_button
  s1
coreclkout_hip  
  clk
app_nreset_status  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 4
clockRate 250000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 4
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 250000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_led

altera_avalon_pio v15.1
DUT rxm_bar4   pio_led
  s1
coreclkout_hip  
  clk
app_nreset_status  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 4
clockRate 250000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 4
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 250000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0
generation took 0.03 seconds rendering took 0.18 seconds