device_family |
ARRIA10 |
device |
10AX115N3F45E2SGE3 |
base_device |
NIGHTFURY5 |
design_environment |
NATIVE |
device_revision |
20nm5 |
message_level |
error |
anlg_voltage |
1_1V |
anlg_link |
sr |
support_mode |
user_mode |
protocol_mode |
basic_enh |
pma_mode |
basic |
duplex_mode |
duplex |
channels |
4 |
set_data_rate |
10312.5 |
rcfg_iface_enable |
0 |
enable_simple_interface |
1 |
enable_split_interface |
0 |
set_enable_calibration |
0 |
enable_calibration |
1 |
set_disconnect_analog_resets |
0 |
enable_analog_resets |
1 |
enable_reset_sequence |
1 |
enable_transparent_pcs |
0 |
enable_parallel_loopback |
0 |
bonded_mode |
not_bonded |
set_pcs_bonding_master |
Auto |
pcs_bonding_master |
0 |
tx_pma_clk_div |
1 |
plls |
1 |
pll_select |
0 |
enable_port_tx_analog_reset_ack |
0 |
enable_port_tx_pma_clkout |
0 |
enable_port_tx_pma_div_clkout |
0 |
tx_pma_div_clkout_divider |
0 |
enable_port_tx_pma_iqtxrx_clkout |
0 |
enable_port_tx_pma_elecidle |
0 |
enable_port_tx_pma_qpipullup |
0 |
enable_port_tx_pma_qpipulldn |
0 |
enable_port_tx_pma_txdetectrx |
0 |
enable_port_tx_pma_rxfound |
0 |
enable_port_rx_seriallpbken_tx |
1 |
number_physical_bonding_clocks |
1 |
cdr_refclk_cnt |
1 |
cdr_refclk_select |
0 |
set_cdr_refclk_freq |
644.531250 |
rx_ppm_detect_threshold |
1000 |
rx_pma_ctle_adaptation_mode |
manual |
rx_pma_dfe_adaptation_mode |
disabled |
rx_pma_dfe_fixed_taps |
7 |
enable_ports_adaptation |
0 |
enable_port_rx_analog_reset_ack |
0 |
enable_port_rx_pma_clkout |
0 |
enable_port_rx_pma_div_clkout |
0 |
rx_pma_div_clkout_divider |
0 |
enable_port_rx_pma_iqtxrx_clkout |
0 |
enable_port_rx_pma_clkslip |
0 |
enable_port_rx_pma_qpipulldn |
0 |
enable_port_rx_is_lockedtodata |
1 |
enable_port_rx_is_lockedtoref |
1 |
enable_ports_rx_manual_cdr_mode |
1 |
enable_ports_rx_manual_ppm |
0 |
enable_port_rx_signaldetect |
0 |
enable_port_rx_seriallpbken |
1 |
enable_ports_rx_prbs |
1 |
std_pcs_pma_width |
10 |
display_std_tx_pld_pcs_width |
10 |
display_std_rx_pld_pcs_width |
10 |
std_low_latency_bypass_enable |
0 |
enable_hip |
0 |
enable_skp_ports |
0 |
enable_hard_reset |
0 |
set_hip_cal_en |
0 |
hip_cal_en |
disable |
std_tx_pcfifo_mode |
low_latency |
std_rx_pcfifo_mode |
low_latency |
enable_port_tx_std_pcfifo_full |
0 |
enable_port_tx_std_pcfifo_empty |
0 |
enable_port_rx_std_pcfifo_full |
0 |
enable_port_rx_std_pcfifo_empty |
0 |
std_tx_byte_ser_mode |
Disabled |
std_rx_byte_deser_mode |
Disabled |
std_tx_8b10b_enable |
0 |
std_tx_8b10b_disp_ctrl_enable |
0 |
std_rx_8b10b_enable |
0 |
std_rx_rmfifo_mode |
disabled |
std_rx_rmfifo_pattern_n |
0 |
std_rx_rmfifo_pattern_p |
0 |
enable_port_rx_std_rmfifo_full |
0 |
enable_port_rx_std_rmfifo_empty |
0 |
pcie_rate_match |
Bypass |
std_tx_bitslip_enable |
0 |
enable_port_tx_std_bitslipboundarysel |
0 |
std_rx_word_aligner_mode |
bitslip |
std_rx_word_aligner_pattern_len |
7 |
std_rx_word_aligner_pattern |
0 |
std_rx_word_aligner_rknumber |
3 |
std_rx_word_aligner_renumber |
3 |
std_rx_word_aligner_rgnumber |
3 |
std_rx_word_aligner_rvnumber |
0 |
std_rx_word_aligner_fast_sync_status_enable |
0 |
enable_port_rx_std_wa_patternalign |
0 |
enable_port_rx_std_wa_a1a2size |
0 |
enable_port_rx_std_bitslipboundarysel |
0 |
enable_port_rx_std_bitslip |
0 |
std_tx_bitrev_enable |
0 |
std_tx_byterev_enable |
0 |
std_tx_polinv_enable |
0 |
enable_port_tx_polinv |
0 |
std_rx_bitrev_enable |
0 |
enable_port_rx_std_bitrev_ena |
0 |
std_rx_byterev_enable |
0 |
enable_port_rx_std_byterev_ena |
0 |
std_rx_polinv_enable |
0 |
enable_port_rx_polinv |
0 |
enable_port_rx_std_signaldetect |
0 |
enable_ports_pipe_sw |
0 |
enable_ports_pipe_hclk |
0 |
enable_ports_pipe_g3_analog |
0 |
enable_ports_pipe_rx_elecidle |
0 |
enable_port_pipe_rx_polarity |
0 |
enh_pcs_pma_width |
40 |
enh_pld_pcs_width |
40 |
enh_low_latency_enable |
0 |
enh_rxtxfifo_double_width |
0 |
enh_txfifo_mode |
Phase compensation |
enh_txfifo_pfull |
11 |
enh_txfifo_pempty |
2 |
enable_port_tx_enh_fifo_full |
0 |
enable_port_tx_enh_fifo_pfull |
0 |
enable_port_tx_enh_fifo_empty |
0 |
enable_port_tx_enh_fifo_pempty |
0 |
enable_port_tx_enh_fifo_cnt |
0 |
enh_rxfifo_mode |
Phase compensation |
enh_rxfifo_pfull |
23 |
enh_rxfifo_pempty |
2 |
enh_rxfifo_align_del |
0 |
enh_rxfifo_control_del |
0 |
enable_port_rx_enh_data_valid |
0 |
enable_port_rx_enh_fifo_full |
0 |
enable_port_rx_enh_fifo_pfull |
0 |
enable_port_rx_enh_fifo_empty |
0 |
enable_port_rx_enh_fifo_pempty |
0 |
enable_port_rx_enh_fifo_cnt |
0 |
enable_port_rx_enh_fifo_del |
0 |
enable_port_rx_enh_fifo_insert |
0 |
enable_port_rx_enh_fifo_rd_en |
0 |
enable_port_rx_enh_fifo_align_val |
0 |
enable_port_rx_enh_fifo_align_clr |
0 |
enh_tx_frmgen_enable |
0 |
enh_tx_frmgen_mfrm_length |
2048 |
enh_tx_frmgen_burst_enable |
0 |
enable_port_tx_enh_frame |
0 |
enable_port_tx_enh_frame_diag_status |
0 |
enable_port_tx_enh_frame_burst_en |
0 |
enh_rx_frmsync_enable |
0 |
enh_rx_frmsync_mfrm_length |
2048 |
enable_port_rx_enh_frame |
0 |
enable_port_rx_enh_frame_lock |
0 |
enable_port_rx_enh_frame_diag_status |
0 |
enh_tx_crcgen_enable |
0 |
enh_tx_crcerr_enable |
0 |
enh_rx_crcchk_enable |
0 |
enable_port_rx_enh_crc32_err |
0 |
enable_port_rx_enh_highber |
0 |
enable_port_rx_enh_highber_clr_cnt |
0 |
enable_port_rx_enh_clr_errblk_count |
0 |
enh_tx_64b66b_enable |
0 |
enh_rx_64b66b_enable |
0 |
enh_tx_sh_err |
0 |
enh_tx_scram_enable |
0 |
enh_tx_scram_seed |
0 |
enh_rx_descram_enable |
0 |
enh_tx_dispgen_enable |
0 |
enh_rx_dispchk_enable |
0 |
enh_tx_randomdispbit_enable |
0 |
enh_rx_blksync_enable |
0 |
enable_port_rx_enh_blk_lock |
0 |
enh_tx_bitslip_enable |
0 |
enh_tx_polinv_enable |
0 |
enh_rx_bitslip_enable |
0 |
enh_rx_polinv_enable |
0 |
enable_port_tx_enh_bitslip |
0 |
enable_port_rx_enh_bitslip |
0 |
enh_rx_krfec_err_mark_enable |
0 |
enh_rx_krfec_err_mark_type |
10G |
enh_tx_krfec_burst_err_enable |
0 |
enh_tx_krfec_burst_err_len |
1 |
enable_port_krfec_tx_enh_frame |
0 |
enable_port_krfec_rx_enh_frame |
0 |
enable_port_krfec_rx_enh_frame_diag_status |
0 |
pcs_direct_width |
8 |
generate_docs |
1 |
generate_add_hdl_instance_example |
0 |
validation_rule_select |
|
enable_advanced_options |
0 |
enable_physical_bonding_clocks |
0 |
enable_debug_options |
0 |
enable_advanced_avmm_options |
0 |
l_channels |
4 |
tx_enable |
1 |
datapath_select |
Enhanced |
rx_enable |
1 |
l_split_iface |
0 |
l_pcs_pma_width |
40 |
l_tx_pld_pcs_width |
40 |
l_rx_pld_pcs_width |
40 |
l_pll_settings |
343.750000 {refclk 343.750000 m 15 n 1 lpfd 1 lpd 1 fvco 5156.25} 687.500000 {refclk 687.500000 m 15 n 2 lpfd 1 lpd 1 fvco 5156.25} 322.265625 {refclk 322.265625 m 16 n 1 lpfd 1 lpd 1 fvco 5156.25} 644.531250 {refclk 644.531250 m 16 n 2 lpfd 1 lpd 1 fvco 5156.25} 303.308824 {refclk 303.308824 m 17 n 1 lpfd 1 lpd 1 fvco 5156.25} 606.617647 {refclk 606.617647 m 17 n 2 lpfd 1 lpd 1 fvco 5156.25} 286.458333 {refclk 286.458333 m 18 n 1 lpfd 1 lpd 1 fvco 5156.25} 572.916667 {refclk 572.916667 m 18 n 2 lpfd 1 lpd 1 fvco 5156.25} 271.381579 {refclk 271.381579 m 19 n 1 lpfd 1 lpd 1 fvco 5156.25} 542.763158 {refclk 542.763158 m 19 n 2 lpfd 1 lpd 1 fvco 5156.25} 257.812500 {refclk 257.812500 m 20 n 1 lpfd 1 lpd 1 fvco 5156.25} 515.625000 {refclk 515.625000 m 20 n 2 lpfd 1 lpd 1 fvco 5156.25} 245.535714 {refclk 245.535714 m 21 n 1 lpfd 1 lpd 1 fvco 5156.25} 491.071429 {refclk 491.071429 m 21 n 2 lpfd 1 lpd 1 fvco 5156.25} 234.375000 {refclk 234.375000 m 22 n 1 lpfd 1 lpd 1 fvco 5156.25} 468.750000 {refclk 468.750000 m 22 n 2 lpfd 1 lpd 1 fvco 5156.25} 224.184783 {refclk 224.184783 m 23 n 1 lpfd 1 lpd 1 fvco 5156.25} 448.369565 {refclk 448.369565 m 23 n 2 lpfd 1 lpd 1 fvco 5156.25} 214.843750 {refclk 214.843750 m 24 n 1 lpfd 1 lpd 1 fvco 5156.25} 429.687500 {refclk 429.687500 m 24 n 2 lpfd 1 lpd 1 fvco 5156.25} 206.250000 {refclk 206.250000 m 25 n 1 lpfd 1 lpd 1 fvco 5156.25} 412.500000 {refclk 412.500000 m 25 n 2 lpfd 1 lpd 1 fvco 5156.25} 198.317308 {refclk 198.317308 m 26 n 1 lpfd 1 lpd 1 fvco 5156.25} 396.634615 {refclk 396.634615 m 26 n 2 lpfd 1 lpd 1 fvco 5156.25} 793.269231 {refclk 793.269231 m 26 n 4 lpfd 1 lpd 1 fvco 5156.25} 190.972222 {refclk 190.972222 m 27 n 1 lpfd 1 lpd 1 fvco 5156.25} 381.944444 {refclk 381.944444 m 27 n 2 lpfd 1 lpd 1 fvco 5156.25} 763.888889 {refclk 763.888889 m 27 n 4 lpfd 1 lpd 1 fvco 5156.25} 184.151786 {refclk 184.151786 m 28 n 1 lpfd 1 lpd 1 fvco 5156.25} 368.303571 {refclk 368.303571 m 28 n 2 lpfd 1 lpd 1 fvco 5156.25} 736.607143 {refclk 736.607143 m 28 n 4 lpfd 1 lpd 1 fvco 5156.25} 177.801724 {refclk 177.801724 m 29 n 1 lpfd 1 lpd 1 fvco 5156.25} 355.603448 {refclk 355.603448 m 29 n 2 lpfd 1 lpd 1 fvco 5156.25} 711.206897 {refclk 711.206897 m 29 n 4 lpfd 1 lpd 1 fvco 5156.25} 171.875000 {refclk 171.875000 m 30 n 1 lpfd 1 lpd 1 fvco 5156.25} 166.330645 {refclk 166.330645 m 31 n 1 lpfd 1 lpd 1 fvco 5156.25} 332.661290 {refclk 332.661290 m 31 n 2 lpfd 1 lpd 1 fvco 5156.25} 665.322581 {refclk 665.322581 m 31 n 4 lpfd 1 lpd 1 fvco 5156.25} 161.132813 {refclk 161.132813 m 32 n 1 lpfd 1 lpd 1 fvco 5156.25} 156.250000 {refclk 156.250000 m 33 n 1 lpfd 1 lpd 1 fvco 5156.25} 312.500000 {refclk 312.500000 m 33 n 2 lpfd 1 lpd 1 fvco 5156.25} 625.000000 {refclk 625.000000 m 33 n 4 lpfd 1 lpd 1 fvco 5156.25} 151.654412 {refclk 151.654412 m 34 n 1 lpfd 1 lpd 1 fvco 5156.25} 147.321429 {refclk 147.321429 m 35 n 1 lpfd 1 lpd 1 fvco 5156.25} 294.642857 {refclk 294.642857 m 35 n 2 lpfd 1 lpd 1 fvco 5156.25} 589.285714 {refclk 589.285714 m 35 n 4 lpfd 1 lpd 1 fvco 5156.25} 143.229167 {refclk 143.229167 m 36 n 1 lpfd 1 lpd 1 fvco 5156.25} 139.358108 {refclk 139.358108 m 37 n 1 lpfd 1 lpd 1 fvco 5156.25} 278.716216 {refclk 278.716216 m 37 n 2 lpfd 1 lpd 1 fvco 5156.25} 557.432432 {refclk 557.432432 m 37 n 4 lpfd 1 lpd 1 fvco 5156.25} 135.690789 {refclk 135.690789 m 38 n 1 lpfd 1 lpd 1 fvco 5156.25} 132.211538 {refclk 132.211538 m 39 n 1 lpfd 1 lpd 1 fvco 5156.25} 264.423077 {refclk 264.423077 m 39 n 2 lpfd 1 lpd 1 fvco 5156.25} 528.846154 {refclk 528.846154 m 39 n 4 lpfd 1 lpd 1 fvco 5156.25} 128.906250 {refclk 128.906250 m 40 n 1 lpfd 1 lpd 1 fvco 5156.25} 125.762195 {refclk 125.762195 m 41 n 1 lpfd 1 lpd 1 fvco 5156.25} 251.524390 {refclk 251.524390 m 41 n 2 lpfd 1 lpd 1 fvco 5156.25} 503.048780 {refclk 503.048780 m 41 n 4 lpfd 1 lpd 1 fvco 5156.25} 122.767857 {refclk 122.767857 m 42 n 1 lpfd 1 lpd 1 fvco 5156.25} 119.912791 {refclk 119.912791 m 43 n 1 lpfd 1 lpd 1 fvco 5156.25} 239.825581 {refclk 239.825581 m 43 n 2 lpfd 1 lpd 1 fvco 5156.25} 479.651163 {refclk 479.651163 m 43 n 4 lpfd 1 lpd 1 fvco 5156.25} 117.187500 {refclk 117.187500 m 44 n 1 lpfd 1 lpd 1 fvco 5156.25} 114.583333 {refclk 114.583333 m 45 n 1 lpfd 1 lpd 1 fvco 5156.25} 229.166667 {refclk 229.166667 m 45 n 2 lpfd 1 lpd 1 fvco 5156.25} 458.333333 {refclk 458.333333 m 45 n 4 lpfd 1 lpd 1 fvco 5156.25} 112.092391 {refclk 112.092391 m 46 n 1 lpfd 1 lpd 1 fvco 5156.25} 109.707447 {refclk 109.707447 m 47 n 1 lpfd 1 lpd 1 fvco 5156.25} 219.414894 {refclk 219.414894 m 47 n 2 lpfd 1 lpd 1 fvco 5156.25} 438.829787 {refclk 438.829787 m 47 n 4 lpfd 1 lpd 1 fvco 5156.25} 107.421875 {refclk 107.421875 m 48 n 1 lpfd 1 lpd 1 fvco 5156.25} 105.229592 {refclk 105.229592 m 49 n 1 lpfd 1 lpd 1 fvco 5156.25} 210.459184 {refclk 210.459184 m 49 n 2 lpfd 1 lpd 1 fvco 5156.25} 420.918367 {refclk 420.918367 m 49 n 4 lpfd 1 lpd 1 fvco 5156.25} 103.125000 {refclk 103.125000 m 50 n 1 lpfd 1 lpd 1 fvco 5156.25} 101.102941 {refclk 101.102941 m 51 n 1 lpfd 1 lpd 1 fvco 5156.25} 202.205882 {refclk 202.205882 m 51 n 2 lpfd 1 lpd 1 fvco 5156.25} 404.411765 {refclk 404.411765 m 51 n 4 lpfd 1 lpd 1 fvco 5156.25} 99.158654 {refclk 99.158654 m 52 n 1 lpfd 1 lpd 1 fvco 5156.25} 97.287736 {refclk 97.287736 m 53 n 1 lpfd 1 lpd 1 fvco 5156.25} 194.575472 {refclk 194.575472 m 53 n 2 lpfd 1 lpd 1 fvco 5156.25} 389.150943 {refclk 389.150943 m 53 n 4 lpfd 1 lpd 1 fvco 5156.25} 778.301887 {refclk 778.301887 m 53 n 8 lpfd 1 lpd 1 fvco 5156.25} 95.486111 {refclk 95.486111 m 54 n 1 lpfd 1 lpd 1 fvco 5156.25} 93.750000 {refclk 93.750000 m 55 n 1 lpfd 1 lpd 1 fvco 5156.25} 187.500000 {refclk 187.500000 m 55 n 2 lpfd 1 lpd 1 fvco 5156.25} 375.000000 {refclk 375.000000 m 55 n 4 lpfd 1 lpd 1 fvco 5156.25} 750.000000 {refclk 750.000000 m 55 n 8 lpfd 1 lpd 1 fvco 5156.25} 92.075893 {refclk 92.075893 m 56 n 1 lpfd 1 lpd 1 fvco 5156.25} 90.460526 {refclk 90.460526 m 57 n 1 lpfd 1 lpd 1 fvco 5156.25} 180.921053 {refclk 180.921053 m 57 n 2 lpfd 1 lpd 1 fvco 5156.25} 361.842105 {refclk 361.842105 m 57 n 4 lpfd 1 lpd 1 fvco 5156.25} 723.684211 {refclk 723.684211 m 57 n 8 lpfd 1 lpd 1 fvco 5156.25} 88.900862 {refclk 88.900862 m 58 n 1 lpfd 1 lpd 1 fvco 5156.25} 87.394068 {refclk 87.394068 m 59 n 1 lpfd 1 lpd 1 fvco 5156.25} 174.788136 {refclk 174.788136 m 59 n 2 lpfd 1 lpd 1 fvco 5156.25} 349.576271 {refclk 349.576271 m 59 n 4 lpfd 1 lpd 1 fvco 5156.25} 699.152542 {refclk 699.152542 m 59 n 8 lpfd 1 lpd 1 fvco 5156.25} 85.937500 {refclk 85.937500 m 60 n 1 lpfd 1 lpd 1 fvco 5156.25} 84.528689 {refclk 84.528689 m 61 n 1 lpfd 1 lpd 1 fvco 5156.25} 169.057377 {refclk 169.057377 m 61 n 2 lpfd 1 lpd 1 fvco 5156.25} 338.114754 {refclk 338.114754 m 61 n 4 lpfd 1 lpd 1 fvco 5156.25} 676.229508 {refclk 676.229508 m 61 n 8 lpfd 1 lpd 1 fvco 5156.25} 83.165323 {refclk 83.165323 m 62 n 1 lpfd 1 lpd 1 fvco 5156.25} 81.845238 {refclk 81.845238 m 63 n 1 lpfd 1 lpd 1 fvco 5156.25} 163.690476 {refclk 163.690476 m 63 n 2 lpfd 1 lpd 1 fvco 5156.25} 327.380952 {refclk 327.380952 m 63 n 4 lpfd 1 lpd 1 fvco 5156.25} 654.761905 {refclk 654.761905 m 63 n 8 lpfd 1 lpd 1 fvco 5156.25} 80.566406 {refclk 80.566406 m 64 n 1 lpfd 1 lpd 1 fvco 5156.25} 79.326923 {refclk 79.326923 m 65 n 1 lpfd 1 lpd 1 fvco 5156.25} 158.653846 {refclk 158.653846 m 65 n 2 lpfd 1 lpd 1 fvco 5156.25} 317.307692 {refclk 317.307692 m 65 n 4 lpfd 1 lpd 1 fvco 5156.25} 634.615385 {refclk 634.615385 m 65 n 8 lpfd 1 lpd 1 fvco 5156.25} 78.125000 {refclk 78.125000 m 66 n 1 lpfd 1 lpd 1 fvco 5156.25} 76.958955 {refclk 76.958955 m 67 n 1 lpfd 1 lpd 1 fvco 5156.25} 153.917910 {refclk 153.917910 m 67 n 2 lpfd 1 lpd 1 fvco 5156.25} 307.835821 {refclk 307.835821 m 67 n 4 lpfd 1 lpd 1 fvco 5156.25} 615.671642 {refclk 615.671642 m 67 n 8 lpfd 1 lpd 1 fvco 5156.25} 75.827206 {refclk 75.827206 m 68 n 1 lpfd 1 lpd 1 fvco 5156.25} 74.728261 {refclk 74.728261 m 69 n 1 lpfd 1 lpd 1 fvco 5156.25} 149.456522 {refclk 149.456522 m 69 n 2 lpfd 1 lpd 1 fvco 5156.25} 298.913043 {refclk 298.913043 m 69 n 4 lpfd 1 lpd 1 fvco 5156.25} 597.826087 {refclk 597.826087 m 69 n 8 lpfd 1 lpd 1 fvco 5156.25} 73.660714 {refclk 73.660714 m 70 n 1 lpfd 1 lpd 1 fvco 5156.25} 72.623239 {refclk 72.623239 m 71 n 1 lpfd 1 lpd 1 fvco 5156.25} 145.246479 {refclk 145.246479 m 71 n 2 lpfd 1 lpd 1 fvco 5156.25} 290.492958 {refclk 290.492958 m 71 n 4 lpfd 1 lpd 1 fvco 5156.25} 580.985915 {refclk 580.985915 m 71 n 8 lpfd 1 lpd 1 fvco 5156.25} 71.614583 {refclk 71.614583 m 72 n 1 lpfd 1 lpd 1 fvco 5156.25} 70.633562 {refclk 70.633562 m 73 n 1 lpfd 1 lpd 1 fvco 5156.25} 141.267123 {refclk 141.267123 m 73 n 2 lpfd 1 lpd 1 fvco 5156.25} 282.534247 {refclk 282.534247 m 73 n 4 lpfd 1 lpd 1 fvco 5156.25} 565.068493 {refclk 565.068493 m 73 n 8 lpfd 1 lpd 1 fvco 5156.25} 69.679054 {refclk 69.679054 m 74 n 1 lpfd 1 lpd 1 fvco 5156.25} 68.750000 {refclk 68.750000 m 75 n 1 lpfd 1 lpd 1 fvco 5156.25} 137.500000 {refclk 137.500000 m 75 n 2 lpfd 1 lpd 1 fvco 5156.25} 275.000000 {refclk 275.000000 m 75 n 4 lpfd 1 lpd 1 fvco 5156.25} 550.000000 {refclk 550.000000 m 75 n 8 lpfd 1 lpd 1 fvco 5156.25} 67.845395 {refclk 67.845395 m 76 n 1 lpfd 1 lpd 1 fvco 5156.25} 66.964286 {refclk 66.964286 m 77 n 1 lpfd 1 lpd 1 fvco 5156.25} 133.928571 {refclk 133.928571 m 77 n 2 lpfd 1 lpd 1 fvco 5156.25} 267.857143 {refclk 267.857143 m 77 n 4 lpfd 1 lpd 1 fvco 5156.25} 535.714286 {refclk 535.714286 m 77 n 8 lpfd 1 lpd 1 fvco 5156.25} 66.105769 {refclk 66.105769 m 78 n 1 lpfd 1 lpd 1 fvco 5156.25} 65.268987 {refclk 65.268987 m 79 n 1 lpfd 1 lpd 1 fvco 5156.25} 130.537975 {refclk 130.537975 m 79 n 2 lpfd 1 lpd 1 fvco 5156.25} 261.075949 {refclk 261.075949 m 79 n 4 lpfd 1 lpd 1 fvco 5156.25} 522.151899 {refclk 522.151899 m 79 n 8 lpfd 1 lpd 1 fvco 5156.25} 64.453125 {refclk 64.453125 m 80 n 1 lpfd 1 lpd 1 fvco 5156.25} 63.657407 {refclk 63.657407 m 81 n 1 lpfd 1 lpd 1 fvco 5156.25} 127.314815 {refclk 127.314815 m 81 n 2 lpfd 1 lpd 1 fvco 5156.25} 254.629630 {refclk 254.629630 m 81 n 4 lpfd 1 lpd 1 fvco 5156.25} 509.259259 {refclk 509.259259 m 81 n 8 lpfd 1 lpd 1 fvco 5156.25} 62.881098 {refclk 62.881098 m 82 n 1 lpfd 1 lpd 1 fvco 5156.25} 62.123494 {refclk 62.123494 m 83 n 1 lpfd 1 lpd 1 fvco 5156.25} 124.246988 {refclk 124.246988 m 83 n 2 lpfd 1 lpd 1 fvco 5156.25} 248.493976 {refclk 248.493976 m 83 n 4 lpfd 1 lpd 1 fvco 5156.25} 496.987952 {refclk 496.987952 m 83 n 8 lpfd 1 lpd 1 fvco 5156.25} 61.383929 {refclk 61.383929 m 84 n 1 lpfd 1 lpd 1 fvco 5156.25} 60.661765 {refclk 60.661765 m 85 n 1 lpfd 1 lpd 1 fvco 5156.25} 121.323529 {refclk 121.323529 m 85 n 2 lpfd 1 lpd 1 fvco 5156.25} 242.647059 {refclk 242.647059 m 85 n 4 lpfd 1 lpd 1 fvco 5156.25} 485.294118 {refclk 485.294118 m 85 n 8 lpfd 1 lpd 1 fvco 5156.25} 59.956395 {refclk 59.956395 m 86 n 1 lpfd 1 lpd 1 fvco 5156.25} 59.267241 {refclk 59.267241 m 87 n 1 lpfd 1 lpd 1 fvco 5156.25} 118.534483 {refclk 118.534483 m 87 n 2 lpfd 1 lpd 1 fvco 5156.25} 237.068966 {refclk 237.068966 m 87 n 4 lpfd 1 lpd 1 fvco 5156.25} 474.137931 {refclk 474.137931 m 87 n 8 lpfd 1 lpd 1 fvco 5156.25} 58.593750 {refclk 58.593750 m 88 n 1 lpfd 1 lpd 1 fvco 5156.25} 57.935393 {refclk 57.935393 m 89 n 1 lpfd 1 lpd 1 fvco 5156.25} 115.870787 {refclk 115.870787 m 89 n 2 lpfd 1 lpd 1 fvco 5156.25} 231.741573 {refclk 231.741573 m 89 n 4 lpfd 1 lpd 1 fvco 5156.25} 463.483146 {refclk 463.483146 m 89 n 8 lpfd 1 lpd 1 fvco 5156.25} 57.291667 {refclk 57.291667 m 90 n 1 lpfd 1 lpd 1 fvco 5156.25} 56.662088 {refclk 56.662088 m 91 n 1 lpfd 1 lpd 1 fvco 5156.25} 113.324176 {refclk 113.324176 m 91 n 2 lpfd 1 lpd 1 fvco 5156.25} 226.648352 {refclk 226.648352 m 91 n 4 lpfd 1 lpd 1 fvco 5156.25} 453.296703 {refclk 453.296703 m 91 n 8 lpfd 1 lpd 1 fvco 5156.25} 56.046196 {refclk 56.046196 m 92 n 1 lpfd 1 lpd 1 fvco 5156.25} 55.443548 {refclk 55.443548 m 93 n 1 lpfd 1 lpd 1 fvco 5156.25} 110.887097 {refclk 110.887097 m 93 n 2 lpfd 1 lpd 1 fvco 5156.25} 221.774194 {refclk 221.774194 m 93 n 4 lpfd 1 lpd 1 fvco 5156.25} 443.548387 {refclk 443.548387 m 93 n 8 lpfd 1 lpd 1 fvco 5156.25} 54.853723 {refclk 54.853723 m 94 n 1 lpfd 1 lpd 1 fvco 5156.25} 54.276316 {refclk 54.276316 m 95 n 1 lpfd 1 lpd 1 fvco 5156.25} 108.552632 {refclk 108.552632 m 95 n 2 lpfd 1 lpd 1 fvco 5156.25} 217.105263 {refclk 217.105263 m 95 n 4 lpfd 1 lpd 1 fvco 5156.25} 434.210526 {refclk 434.210526 m 95 n 8 lpfd 1 lpd 1 fvco 5156.25} 53.710938 {refclk 53.710938 m 96 n 1 lpfd 1 lpd 1 fvco 5156.25} 53.157216 {refclk 53.157216 m 97 n 1 lpfd 1 lpd 1 fvco 5156.25} 106.314433 {refclk 106.314433 m 97 n 2 lpfd 1 lpd 1 fvco 5156.25} 212.628866 {refclk 212.628866 m 97 n 4 lpfd 1 lpd 1 fvco 5156.25} 425.257732 {refclk 425.257732 m 97 n 8 lpfd 1 lpd 1 fvco 5156.25} 52.614796 {refclk 52.614796 m 98 n 1 lpfd 1 lpd 1 fvco 5156.25} 52.083333 {refclk 52.083333 m 99 n 1 lpfd 1 lpd 1 fvco 5156.25} 104.166667 {refclk 104.166667 m 99 n 2 lpfd 1 lpd 1 fvco 5156.25} 208.333333 {refclk 208.333333 m 99 n 4 lpfd 1 lpd 1 fvco 5156.25} 416.666667 {refclk 416.666667 m 99 n 8 lpfd 1 lpd 1 fvco 5156.25} 51.562500 {refclk 51.562500 m 100 n 1 lpfd 1 lpd 1 fvco 5156.25} 51.051980 {refclk 51.051980 m 101 n 1 lpfd 1 lpd 1 fvco 5156.25} 102.103960 {refclk 102.103960 m 101 n 2 lpfd 1 lpd 1 fvco 5156.25} 204.207921 {refclk 204.207921 m 101 n 4 lpfd 1 lpd 1 fvco 5156.25} 408.415842 {refclk 408.415842 m 101 n 8 lpfd 1 lpd 1 fvco 5156.25} 50.551471 {refclk 50.551471 m 102 n 1 lpfd 1 lpd 1 fvco 5156.25} 50.060680 {refclk 50.060680 m 103 n 1 lpfd 1 lpd 1 fvco 5156.25} 100.121359 {refclk 100.121359 m 103 n 2 lpfd 1 lpd 1 fvco 5156.25} 200.242718 {refclk 200.242718 m 103 n 4 lpfd 1 lpd 1 fvco 5156.25} 400.485437 {refclk 400.485437 m 103 n 8 lpfd 1 lpd 1 fvco 5156.25} allowed_ranges {50.060680 50.551471 51.051980 51.562500 52.083333 52.614796 53.157216 53.710938 54.276316 54.853723 55.443548 56.046196 56.662088 57.291667 57.935393 58.593750 59.267241 59.956395 60.661765 61.383929 62.123494 62.881098 63.657407 64.453125 65.268987 66.105769 66.964286 67.845395 68.750000 69.679054 70.633562 71.614583 72.623239 73.660714 74.728261 75.827206 76.958955 78.125000 79.326923 80.566406 81.845238 83.165323 84.528689 85.937500 87.394068 88.900862 90.460526 92.075893 93.750000 95.486111 97.287736 99.158654 100.121359 101.102941 102.103960 103.125000 104.166667 105.229592 106.314433 107.421875 108.552632 109.707447 110.887097 112.092391 113.324176 114.583333 115.870787 117.187500 118.534483 119.912791 121.323529 122.767857 124.246988 125.762195 127.314815 128.906250 130.537975 132.211538 133.928571 135.690789 137.500000 139.358108 141.267123 143.229167 145.246479 147.321429 149.456522 151.654412 153.917910 156.250000 158.653846 161.132813 163.690476 166.330645 169.057377 171.875000 174.788136 177.801724 180.921053 184.151786 187.500000 190.972222 194.575472 198.317308 200.242718 202.205882 204.207921 206.250000 208.333333 210.459184 212.628866 214.843750 217.105263 219.414894 221.774194 224.184783 226.648352 229.166667 231.741573 234.375000 237.068966 239.825581 242.647059 245.535714 248.493976 251.524390 254.629630 257.812500 261.075949 264.423077 267.857143 271.381579 275.000000 278.716216 282.534247 286.458333 290.492958 294.642857 298.913043 303.308824 307.835821 312.500000 317.307692 322.265625 327.380952 332.661290 338.114754 343.750000 349.576271 355.603448 361.842105 368.303571 375.000000 381.944444 389.150943 396.634615 400.485437 404.411765 408.415842 412.500000 416.666667 420.918367 425.257732 429.687500 434.210526 438.829787 443.548387 448.369565 453.296703 458.333333 463.483146 468.750000 474.137931 479.651163 485.294118 491.071429 496.987952 503.048780 509.259259 515.625000 522.151899 528.846154 535.714286 542.763158 550.000000 557.432432 565.068493 572.916667 580.985915 589.285714 597.826087 606.617647 615.671642 625.000000 634.615385 644.531250 654.761905 665.322581 676.229508 687.500000 699.152542 711.206897 723.684211 736.607143 750.000000 763.888889 778.301887 793.269231} |
l_pll_settings_key |
644.531250 |
l_enable_pma_bonding |
0 |
enable_std |
0 |
l_enable_std_pipe |
0 |
l_enable_tx_std |
0 |
l_enable_rx_std |
0 |
l_enable_tx_std_iface |
0 |
l_enable_rx_std_iface |
0 |
l_std_tx_word_count |
1 |
l_std_tx_word_width |
10 |
l_std_tx_field_width |
11 |
l_std_rx_word_count |
1 |
l_std_rx_word_width |
10 |
l_std_rx_field_width |
16 |
l_std_tx_pld_pcs_width |
10 |
l_std_rx_pld_pcs_width |
10 |
enable_enh |
1 |
l_enable_tx_enh |
1 |
l_enable_rx_enh |
1 |
l_enable_tx_enh_iface |
1 |
l_enable_rx_enh_iface |
1 |
enable_pcs_dir |
0 |
l_enable_tx_pcs_dir |
0 |
l_enable_rx_pcs_dir |
0 |
l_rcfg_ifaces |
1 |
l_rcfg_addr_bits |
12 |
rcfg_enable |
1 |
rcfg_shared |
1 |
rcfg_jtag_enable |
1 |
rcfg_separate_avmm_busy |
0 |
rcfg_enable_avmm_busy_port |
0 |
adme_prot_mode |
basic_enh |
adme_data_rate |
10312500000 |
set_embedded_debug_enable |
0 |
set_capability_reg_enable |
1 |
set_user_identifier |
0 |
set_csr_soft_logic_enable |
1 |
set_prbs_soft_logic_enable |
1 |
set_odi_soft_logic_enable |
0 |
dbg_embedded_debug_enable |
1 |
dbg_capability_reg_enable |
1 |
dbg_user_identifier |
0 |
dbg_stat_soft_logic_enable |
1 |
dbg_ctrl_soft_logic_enable |
1 |
dbg_prbs_soft_logic_enable |
1 |
dbg_odi_soft_logic_enable |
0 |
rcfg_file_prefix |
altera_xcvr_native_a10 |
rcfg_sv_file_enable |
1 |
rcfg_h_file_enable |
1 |
rcfg_mif_file_enable |
1 |
rcfg_multi_enable |
0 |
set_rcfg_emb_strm_enable |
0 |
rcfg_emb_strm_enable |
0 |
rcfg_reduced_files_enable |
0 |
rcfg_profile_cnt |
2 |
rcfg_profile_select |
1 |
rcfg_profile_data0 |
|
rcfg_profile_data1 |
|
rcfg_profile_data2 |
|
rcfg_profile_data3 |
|
rcfg_profile_data4 |
|
rcfg_profile_data5 |
|
rcfg_profile_data6 |
|
rcfg_profile_data7 |
|
rcfg_params |
anlg_voltage,anlg_link,support_mode,protocol_mode,pma_mode,duplex_mode,channels,set_data_rate,rcfg_iface_enable,enable_simple_interface,enable_split_interface,set_enable_calibration,enable_parallel_loopback,bonded_mode,set_pcs_bonding_master,tx_pma_clk_div,plls,pll_select,enable_port_tx_analog_reset_ack,enable_port_tx_pma_clkout,enable_port_tx_pma_div_clkout,tx_pma_div_clkout_divider,enable_port_tx_pma_iqtxrx_clkout,enable_port_tx_pma_elecidle,enable_port_tx_pma_qpipullup,enable_port_tx_pma_qpipulldn,enable_port_tx_pma_txdetectrx,enable_port_tx_pma_rxfound,enable_port_rx_seriallpbken_tx,number_physical_bonding_clocks,cdr_refclk_cnt,cdr_refclk_select,set_cdr_refclk_freq,rx_ppm_detect_threshold,rx_pma_ctle_adaptation_mode,rx_pma_dfe_adaptation_mode,rx_pma_dfe_fixed_taps,enable_ports_adaptation,enable_port_rx_analog_reset_ack,enable_port_rx_pma_clkout,enable_port_rx_pma_div_clkout,rx_pma_div_clkout_divider,enable_port_rx_pma_iqtxrx_clkout,enable_port_rx_pma_clkslip,enable_port_rx_pma_qpipulldn,enable_port_rx_is_lockedtodata,enable_port_rx_is_lockedtoref,enable_ports_rx_manual_cdr_mode,enable_ports_rx_manual_ppm,enable_port_rx_signaldetect,enable_port_rx_seriallpbken,enable_ports_rx_prbs,std_pcs_pma_width,std_low_latency_bypass_enable,enable_hip,enable_skp_ports,enable_hard_reset,set_hip_cal_en,std_tx_pcfifo_mode,std_rx_pcfifo_mode,enable_port_tx_std_pcfifo_full,enable_port_tx_std_pcfifo_empty,enable_port_rx_std_pcfifo_full,enable_port_rx_std_pcfifo_empty,std_tx_byte_ser_mode,std_rx_byte_deser_mode,std_tx_8b10b_enable,std_tx_8b10b_disp_ctrl_enable,std_rx_8b10b_enable,std_rx_rmfifo_mode,std_rx_rmfifo_pattern_n,std_rx_rmfifo_pattern_p,enable_port_rx_std_rmfifo_full,enable_port_rx_std_rmfifo_empty,pcie_rate_match,std_tx_bitslip_enable,enable_port_tx_std_bitslipboundarysel,std_rx_word_aligner_mode,std_rx_word_aligner_pattern_len,std_rx_word_aligner_pattern,std_rx_word_aligner_rknumber,std_rx_word_aligner_renumber,std_rx_word_aligner_rgnumber,std_rx_word_aligner_fast_sync_status_enable,enable_port_rx_std_wa_patternalign,enable_port_rx_std_wa_a1a2size,enable_port_rx_std_bitslipboundarysel,enable_port_rx_std_bitslip,std_tx_bitrev_enable,std_tx_byterev_enable,std_tx_polinv_enable,enable_port_tx_polinv,std_rx_bitrev_enable,enable_port_rx_std_bitrev_ena,std_rx_byterev_enable,enable_port_rx_std_byterev_ena,std_rx_polinv_enable,enable_port_rx_polinv,enable_port_rx_std_signaldetect,enable_ports_pipe_sw,enable_ports_pipe_hclk,enable_ports_pipe_g3_analog,enable_ports_pipe_rx_elecidle,enable_port_pipe_rx_polarity,enh_pcs_pma_width,enh_pld_pcs_width,enh_low_latency_enable,enh_rxtxfifo_double_width,enh_txfifo_mode,enh_txfifo_pfull,enh_txfifo_pempty,enable_port_tx_enh_fifo_full,enable_port_tx_enh_fifo_pfull,enable_port_tx_enh_fifo_empty,enable_port_tx_enh_fifo_pempty,enable_port_tx_enh_fifo_cnt,enh_rxfifo_mode,enh_rxfifo_pfull,enh_rxfifo_pempty,enh_rxfifo_align_del,enh_rxfifo_control_del,enable_port_rx_enh_data_valid,enable_port_rx_enh_fifo_full,enable_port_rx_enh_fifo_pfull,enable_port_rx_enh_fifo_empty,enable_port_rx_enh_fifo_pempty,enable_port_rx_enh_fifo_cnt,enable_port_rx_enh_fifo_del,enable_port_rx_enh_fifo_insert,enable_port_rx_enh_fifo_rd_en,enable_port_rx_enh_fifo_align_val,enable_port_rx_enh_fifo_align_clr,enh_tx_frmgen_enable,enh_tx_frmgen_mfrm_length,enh_tx_frmgen_burst_enable,enable_port_tx_enh_frame,enable_port_tx_enh_frame_diag_status,enable_port_tx_enh_frame_burst_en,enh_rx_frmsync_enable,enh_rx_frmsync_mfrm_length,enable_port_rx_enh_frame,enable_port_rx_enh_frame_lock,enable_port_rx_enh_frame_diag_status,enh_tx_crcgen_enable,enh_tx_crcerr_enable,enh_rx_crcchk_enable,enable_port_rx_enh_crc32_err,enable_port_rx_enh_highber,enable_port_rx_enh_highber_clr_cnt,enable_port_rx_enh_clr_errblk_count,enh_tx_64b66b_enable,enh_rx_64b66b_enable,enh_tx_sh_err,enh_tx_scram_enable,enh_tx_scram_seed,enh_rx_descram_enable,enh_tx_dispgen_enable,enh_rx_dispchk_enable,enh_tx_randomdispbit_enable,enh_rx_blksync_enable,enable_port_rx_enh_blk_lock,enh_tx_bitslip_enable,enh_tx_polinv_enable,enh_rx_bitslip_enable,enh_rx_polinv_enable,enable_port_tx_enh_bitslip,enable_port_rx_enh_bitslip,enh_rx_krfec_err_mark_enable,enh_rx_krfec_err_mark_type,enh_tx_krfec_burst_err_enable,enh_tx_krfec_burst_err_len,enable_port_krfec_tx_enh_frame,enable_port_krfec_rx_enh_frame,enable_port_krfec_rx_enh_frame_diag_status,pcs_direct_width,enable_analog_settings,anlg_tx_analog_mode,anlg_enable_tx_default_ovr,anlg_tx_vod_output_swing_ctrl,anlg_tx_pre_emp_sign_pre_tap_1t,anlg_tx_pre_emp_switching_ctrl_pre_tap_1t,anlg_tx_pre_emp_sign_pre_tap_2t,anlg_tx_pre_emp_switching_ctrl_pre_tap_2t,anlg_tx_pre_emp_sign_1st_post_tap,anlg_tx_pre_emp_switching_ctrl_1st_post_tap,anlg_tx_pre_emp_sign_2nd_post_tap,anlg_tx_pre_emp_switching_ctrl_2nd_post_tap,anlg_tx_slew_rate_ctrl,anlg_tx_compensation_en,anlg_tx_term_sel,anlg_enable_rx_default_ovr,anlg_rx_one_stage_enable,anlg_rx_eq_dc_gain_trim,anlg_rx_adp_ctle_acgain_4s,anlg_rx_adp_ctle_eqz_1s_sel,anlg_rx_adp_vga_sel,anlg_rx_adp_dfe_fxtap1,anlg_rx_adp_dfe_fxtap2,anlg_rx_adp_dfe_fxtap3,anlg_rx_adp_dfe_fxtap4,anlg_rx_adp_dfe_fxtap5,anlg_rx_adp_dfe_fxtap6,anlg_rx_adp_dfe_fxtap7,anlg_rx_adp_dfe_fxtap8,anlg_rx_adp_dfe_fxtap9,anlg_rx_adp_dfe_fxtap10,anlg_rx_adp_dfe_fxtap11,anlg_rx_term_sel |
rcfg_param_labels |
VCCR_GXB and VCCT_GXB supply voltage for the Transceiver,Tranceiver Link Type,Protocol support mode,Transceiver configuration rules,PMA configuration rules,Transceiver mode,Number of data channels,Data rate,Enable datapath and interface reconfiguration,Enable simplified data interface,Provide separate interface for each channel,Enable calibration,Enable parallel loopback,TX channel bonding mode,PCS TX channel bonding master,TX local clock division factor,Number of TX PLL clock inputs per channel,Initial TX PLL clock input selection,Enable tx_analog_reset_ack port,Enable tx_pma_clkout port,Enable tx_pma_div_clkout port,tx_pma_div_clkout division factor,Enable tx_pma_iqtxrx_clkout port,Enable tx_pma_elecidle port,Enable tx_pma_qpipullup port (QPI),Enable tx_pma_qpipulldn port (QPI),Enable tx_pma_txdetectrx port (QPI),Enable tx_pma_rxfound port (QPI),Enable rx_seriallpbken port,Number of physical bonding clock ports to use.,Number of CDR reference clocks,Selected CDR reference clock,Selected CDR reference clock frequency,PPM detector threshold,CTLE adaptation mode,DFE adaptation mode,Number of fixed dfe taps,Enable adaptation control ports,Enable rx_analog_reset_ack port,Enable rx_pma_clkout port,Enable rx_pma_div_clkout port,rx_pma_div_clkout division factor,Enable rx_pma_iqtxrx_clkout port,Enable rx_pma_clkslip port,Enable rx_pma_qpipulldn port (QPI),Enable rx_is_lockedtodata port,Enable rx_is_lockedtoref port,Enable rx_set_locktodata and rx_set_locktoref ports,Enable rx_fref and rx_clklow ports,Enable rx_signaldetect port,Enable rx_seriallpbken port,Enable PRBS verifier control and status ports,Standard PCS / PMA interface width,Enable 'Standard PCS' low latency mode,Enable PCIe hard IP support,Enable SKP ports for Gen3,Enable hard reset controller (HIP),Enable PCIe hard IP calibration,TX FIFO mode,RX FIFO mode,Enable tx_std_pcfifo_full port,Enable tx_std_pcfifo_empty port,Enable rx_std_pcfifo_full port,Enable rx_std_pcfifo_empty port,TX byte serializer mode,RX byte deserializer mode,Enable TX 8B/10B encoder,Enable TX 8B/10B disparity control,Enable RX 8B/10B decoder,RX rate match FIFO mode,RX rate match insert/delete -ve pattern (hex),RX rate match insert/delete +ve pattern (hex),Enable rx_std_rmfifo_full port,Enable rx_std_rmfifo_empty port,PCI Express Gen 3 rate match FIFO mode,Enable TX bitslip,Enable tx_std_bitslipboundarysel port,RX word aligner mode,RX word aligner pattern length,RX word aligner pattern (hex),Number of word alignment patterns to achieve sync,Number of invalid data words to lose sync,Number of valid data words to decrement error count,Enable fast sync status reporting for deterministic latency SM,Enable rx_std_wa_patternalign port,Enable rx_std_wa_a1a2size port,Enable rx_std_bitslipboundarysel port,Enable rx_bitslip port,Enable TX bit reversal,Enable TX byte reversal,Enable TX polarity inversion,Enable tx_polinv port,Enable RX bit reversal,Enable rx_std_bitrev_ena port,Enable RX byte reversal,Enable rx_std_byterev_ena port,Enable RX polarity inversion,Enable rx_polinv port,Enable rx_std_signaldetect port,Enable PCIe dynamic datarate switch ports,Enable PCIe pipe_hclk_in and pipe_hclk_out ports,Enable PCIe Gen 3 analog control ports,Enable PCIe electrical idle control and status ports,Enable PCIe pipe_rx_polarity port,Enhanced PCS / PMA interface width,FPGA fabric / Enhanced PCS interface width,Enable 'Enhanced PCS' low latency mode,Enable RX/TX FIFO double width mode,TX FIFO mode,TX FIFO partially full threshold,TX FIFO partially empty threshold,Enable tx_enh_fifo_full port,Enable tx_enh_fifo_pfull port,Enable tx_enh_fifo_empty port,Enable tx_enh_fifo_pempty port,Enable tx_enh_fifo_cnt port,RX FIFO mode,RX FIFO partially full threshold,RX FIFO partially empty threshold,Enable RX FIFO alignment word deletion (Interlaken),Enable RX FIFO control word deletion (Interlaken),Enable rx_enh_data_valid port,Enable rx_enh_fifo_full port,Enable rx_enh_fifo_pfull port,Enable rx_enh_fifo_empty port,Enable rx_enh_fifo_pempty port,Enable rx_enh_fifo_cnt port,Enable rx_enh_fifo_del port (10GBASE-R),Enable rx_enh_fifo_insert port (10GBASE-R),Enable rx_enh_fifo_rd_en port,Enable rx_enh_fifo_align_val port (Interlaken),Enable rx_enh_fifo_align_clr port (Interlaken),Enable Interlaken frame generator,Frame generator metaframe length,Enable frame generator burst control,Enable tx_enh_frame port,Enable tx_enh_frame_diag_status port,Enable tx_enh_frame_burst_en port,Enable Interlaken frame synchronizer,Frame synchronizer metaframe length,Enable rx_enh_frame port,Enable rx_enh_frame_lock port,Enable rx_enh_frame_diag_status port,Enable Interlaken TX CRC-32 generator,Enable Interlaken TX CRC-32 generator error insertion,Enable Interlaken RX CRC-32 checker,Enable rx_enh_crc32_err port,Enable rx_enh_highber port (10GBASE-R),Enable rx_enh_highber_clr_cnt port (10GBASE-R),Enable rx_enh_clr_errblk_count port (10GBASE-R & FEC),Enable TX 64b/66b encoder,Enable RX 64b/66b decoder,Enable TX sync header error insertion,Enable TX scrambler (10GBASE-R/Interlaken),TX scrambler seed (10GBASE-R/Interlaken),Enable RX descrambler (10GBASE-R/Interlaken),Enable Interlaken TX disparity generator,Enable Interlaken RX disparity checker,Enable Interlaken TX random disparity bit,Enable RX block synchronizer,Enable rx_enh_blk_lock port,Enable TX data bitslip,Enable TX data polarity inversion,Enable RX data bitslip,Enable RX data polarity inversion,Enable tx_enh_bitslip port,Enable rx_bitslip port,Enable RX KR-FEC error marking,Error marking type,Enable KR-FEC TX error insertion,KR-FEC TX error insertion spacing,Enable tx_enh_frame port,Enable rx_enh_frame port,Enable rx_enh_frame_diag_status port,PCS Direct interface width,Include PMA analog settings in configuration files,Analog Mode (Altera-recommended Default Setting Rules),Override Altera-recommended Analog Mode Default Settings,Output Swing Level (VOD),Pre-Emphasis First Pre-Tap Polarity,Pre-Emphasis First Pre-Tap Magnitude,Pre-Emphasis Second Pre-Tap Polarity,Pre-Emphasis Second Pre-Tap Magnitude,Pre-Emphasis First Post-Tap Polarity,Pre-Emphasis First Post-Tap Magnitude,Pre-Emphasis Second Post-Tap Polarity,Pre-Emphasis Second Post-Tap Magnitude,Slew Rate Control,High-Speed Compensation,On-Chip Termination,Override Altera-recommended Default Settings,CTLE (Continuous Time Linear Equalizer) mode,DC Gain Control of High Gain Mode CTLE,AC Gain Control of High Gain Mode CTLE,AC Gain Control of High Data Rate Mode CTLE,Variable Gain Amplifier (VGA) Voltage Swing Select,Decision Feedback Equalizer (DFE) Fixed Tap 1 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 2 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 3 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 4 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 5 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 6 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 7 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 8 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 9 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 10 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 11 Co-efficient,On-Chip Termination |
rcfg_param_vals0 |
|
rcfg_param_vals1 |
|
rcfg_param_vals2 |
|
rcfg_param_vals3 |
|
rcfg_param_vals4 |
|
rcfg_param_vals5 |
|
rcfg_param_vals6 |
|
rcfg_param_vals7 |
|
l_rcfg_datapath_message |
0 |
enable_analog_settings |
0 |
anlg_tx_analog_mode |
user_custom |
anlg_enable_tx_default_ovr |
0 |
anlg_tx_vod_output_swing_ctrl |
0 |
anlg_tx_pre_emp_sign_pre_tap_1t |
fir_pre_1t_neg |
anlg_tx_pre_emp_switching_ctrl_pre_tap_1t |
0 |
anlg_tx_pre_emp_sign_pre_tap_2t |
fir_pre_2t_neg |
anlg_tx_pre_emp_switching_ctrl_pre_tap_2t |
0 |
anlg_tx_pre_emp_sign_1st_post_tap |
fir_post_1t_neg |
anlg_tx_pre_emp_switching_ctrl_1st_post_tap |
0 |
anlg_tx_pre_emp_sign_2nd_post_tap |
fir_post_2t_neg |
anlg_tx_pre_emp_switching_ctrl_2nd_post_tap |
0 |
anlg_tx_slew_rate_ctrl |
slew_r7 |
anlg_tx_compensation_en |
enable |
anlg_tx_term_sel |
r_r1 |
anlg_enable_rx_default_ovr |
0 |
anlg_rx_one_stage_enable |
s1_mode |
anlg_rx_eq_dc_gain_trim |
stg2_gain7 |
anlg_rx_adp_ctle_acgain_4s |
radp_ctle_acgain_4s_1 |
anlg_rx_adp_ctle_eqz_1s_sel |
radp_ctle_eqz_1s_sel_3 |
anlg_rx_adp_vga_sel |
radp_vga_sel_2 |
anlg_rx_adp_dfe_fxtap1 |
radp_dfe_fxtap1_0 |
anlg_rx_adp_dfe_fxtap2 |
radp_dfe_fxtap2_0 |
anlg_rx_adp_dfe_fxtap3 |
radp_dfe_fxtap3_0 |
anlg_rx_adp_dfe_fxtap4 |
radp_dfe_fxtap4_0 |
anlg_rx_adp_dfe_fxtap5 |
radp_dfe_fxtap5_0 |
anlg_rx_adp_dfe_fxtap6 |
radp_dfe_fxtap6_0 |
anlg_rx_adp_dfe_fxtap7 |
radp_dfe_fxtap7_0 |
anlg_rx_adp_dfe_fxtap8 |
radp_dfe_fxtap8_0 |
anlg_rx_adp_dfe_fxtap9 |
radp_dfe_fxtap9_0 |
anlg_rx_adp_dfe_fxtap10 |
radp_dfe_fxtap10_0 |
anlg_rx_adp_dfe_fxtap11 |
radp_dfe_fxtap11_0 |
anlg_rx_term_sel |
r_r1 |
l_anlg_tx_enable |
0 |
l_anlg_rx_enable |
0 |
hssi_gen3_rx_pcs_block_sync |
bypass_block_sync |
hssi_gen3_rx_pcs_block_sync_sm |
disable_blk_sync_sm |
hssi_gen3_rx_pcs_cdr_ctrl_force_unalgn |
disable |
hssi_gen3_rx_pcs_lpbk_force |
lpbk_frce_dis |
hssi_gen3_rx_pcs_mode |
disable_pcs |
hssi_gen3_rx_pcs_rate_match_fifo |
bypass_rm_fifo |
hssi_gen3_rx_pcs_rate_match_fifo_latency |
low_latency |
hssi_gen3_rx_pcs_reverse_lpbk |
rev_lpbk_dis |
hssi_gen3_rx_pcs_rx_b4gb_par_lpbk |
b4gb_par_lpbk_dis |
hssi_gen3_rx_pcs_rx_force_balign |
dis_force_balign |
hssi_gen3_rx_pcs_rx_ins_del_one_skip |
ins_del_one_skip_dis |
hssi_gen3_rx_pcs_rx_num_fixed_pat |
0 |
hssi_gen3_rx_pcs_rx_test_out_sel |
rx_test_out0 |
hssi_gen3_rx_pcs_sup_mode |
user_mode |
hssi_gen3_rx_pcs_silicon_rev |
20nm5es |
hssi_gen3_rx_pcs_reconfig_settings |
{} |
hssi_gen3_tx_pcs_mode |
disable_pcs |
hssi_gen3_tx_pcs_reverse_lpbk |
rev_lpbk_dis |
hssi_gen3_tx_pcs_sup_mode |
user_mode |
hssi_gen3_tx_pcs_tx_bitslip |
0 |
hssi_gen3_tx_pcs_tx_gbox_byp |
bypass_gbox |
hssi_gen3_tx_pcs_silicon_rev |
20nm5es |
hssi_krfec_rx_pcs_blksync_cor_en |
detect |
hssi_krfec_rx_pcs_bypass_gb |
bypass_dis |
hssi_krfec_rx_pcs_clr_ctrl |
both_enabled |
hssi_krfec_rx_pcs_ctrl_bit_reverse |
ctrl_bit_reverse_en |
hssi_krfec_rx_pcs_data_bit_reverse |
data_bit_reverse_dis |
hssi_krfec_rx_pcs_dv_start |
with_blklock |
hssi_krfec_rx_pcs_err_mark_type |
err_mark_10g |
hssi_krfec_rx_pcs_error_marking_en |
err_mark_dis |
hssi_krfec_rx_pcs_low_latency_en |
disable |
hssi_krfec_rx_pcs_lpbk_mode |
lpbk_dis |
hssi_krfec_rx_pcs_parity_invalid_enum |
8 |
hssi_krfec_rx_pcs_parity_valid_num |
4 |
hssi_krfec_rx_pcs_pipeln_blksync |
enable |
hssi_krfec_rx_pcs_pipeln_descrm |
disable |
hssi_krfec_rx_pcs_pipeln_errcorrect |
disable |
hssi_krfec_rx_pcs_pipeln_errtrap_ind |
enable |
hssi_krfec_rx_pcs_pipeln_errtrap_lfsr |
disable |
hssi_krfec_rx_pcs_pipeln_errtrap_loc |
disable |
hssi_krfec_rx_pcs_pipeln_errtrap_pat |
disable |
hssi_krfec_rx_pcs_pipeln_gearbox |
enable |
hssi_krfec_rx_pcs_pipeln_syndrm |
enable |
hssi_krfec_rx_pcs_pipeln_trans_dec |
disable |
hssi_krfec_rx_pcs_prot_mode |
disable_mode |
hssi_krfec_rx_pcs_receive_order |
receive_lsb |
hssi_krfec_rx_pcs_rx_testbus_sel |
overall |
hssi_krfec_rx_pcs_signal_ok_en |
sig_ok_en |
hssi_krfec_rx_pcs_sup_mode |
user_mode |
hssi_krfec_rx_pcs_silicon_rev |
20nm5es |
hssi_krfec_rx_pcs_reconfig_settings |
{} |
hssi_krfec_tx_pcs_burst_err |
burst_err_dis |
hssi_krfec_tx_pcs_burst_err_len |
burst_err_len1 |
hssi_krfec_tx_pcs_ctrl_bit_reverse |
ctrl_bit_reverse_en |
hssi_krfec_tx_pcs_data_bit_reverse |
data_bit_reverse_dis |
hssi_krfec_tx_pcs_enc_frame_query |
enc_query_dis |
hssi_krfec_tx_pcs_low_latency_en |
disable |
hssi_krfec_tx_pcs_pipeln_encoder |
enable |
hssi_krfec_tx_pcs_pipeln_scrambler |
enable |
hssi_krfec_tx_pcs_prot_mode |
disable_mode |
hssi_krfec_tx_pcs_sup_mode |
user_mode |
hssi_krfec_tx_pcs_transcode_err |
trans_err_dis |
hssi_krfec_tx_pcs_transmit_order |
transmit_lsb |
hssi_krfec_tx_pcs_tx_testbus_sel |
overall |
hssi_krfec_tx_pcs_silicon_rev |
20nm5es |
hssi_10g_rx_pcs_align_del |
align_del_dis |
hssi_10g_rx_pcs_ber_bit_err_total_cnt |
bit_err_total_cnt_10g |
hssi_10g_rx_pcs_ber_clken |
ber_clk_dis |
hssi_10g_rx_pcs_ber_xus_timer_window |
19530 |
hssi_10g_rx_pcs_bitslip_mode |
bitslip_dis |
hssi_10g_rx_pcs_blksync_bitslip_type |
bitslip_comb |
hssi_10g_rx_pcs_blksync_bitslip_wait_cnt |
1 |
hssi_10g_rx_pcs_blksync_bitslip_wait_type |
bitslip_cnt |
hssi_10g_rx_pcs_blksync_bypass |
blksync_bypass_en |
hssi_10g_rx_pcs_blksync_clken |
blksync_clk_dis |
hssi_10g_rx_pcs_blksync_enum_invalid_sh_cnt |
enum_invalid_sh_cnt_10g |
hssi_10g_rx_pcs_blksync_knum_sh_cnt_postlock |
knum_sh_cnt_postlock_10g |
hssi_10g_rx_pcs_blksync_knum_sh_cnt_prelock |
knum_sh_cnt_prelock_10g |
hssi_10g_rx_pcs_blksync_pipeln |
blksync_pipeln_dis |
hssi_10g_rx_pcs_clr_errblk_cnt_en |
disable |
hssi_10g_rx_pcs_control_del |
control_del_none |
hssi_10g_rx_pcs_crcchk_bypass |
crcchk_bypass_en |
hssi_10g_rx_pcs_crcchk_clken |
crcchk_clk_dis |
hssi_10g_rx_pcs_crcchk_inv |
crcchk_inv_en |
hssi_10g_rx_pcs_crcchk_pipeln |
crcchk_pipeln_en |
hssi_10g_rx_pcs_crcflag_pipeln |
crcflag_pipeln_en |
hssi_10g_rx_pcs_ctrl_bit_reverse |
ctrl_bit_reverse_dis |
hssi_10g_rx_pcs_data_bit_reverse |
data_bit_reverse_dis |
hssi_10g_rx_pcs_dec_64b66b_rxsm_bypass |
dec_64b66b_rxsm_bypass_en |
hssi_10g_rx_pcs_dec64b66b_clken |
dec64b66b_clk_dis |
hssi_10g_rx_pcs_descrm_bypass |
descrm_bypass_en |
hssi_10g_rx_pcs_descrm_clken |
descrm_clk_dis |
hssi_10g_rx_pcs_descrm_mode |
async |
hssi_10g_rx_pcs_descrm_pipeln |
enable |
hssi_10g_rx_pcs_dft_clk_out_sel |
rx_master_clk |
hssi_10g_rx_pcs_dis_signal_ok |
dis_signal_ok_en |
hssi_10g_rx_pcs_dispchk_bypass |
dispchk_bypass_en |
hssi_10g_rx_pcs_empty_flag_type |
empty_rd_side |
hssi_10g_rx_pcs_fast_path |
fast_path_en |
hssi_10g_rx_pcs_fec_clken |
fec_clk_dis |
hssi_10g_rx_pcs_fec_enable |
fec_dis |
hssi_10g_rx_pcs_fifo_double_read |
fifo_double_read_dis |
hssi_10g_rx_pcs_fifo_stop_rd |
rd_empty |
hssi_10g_rx_pcs_fifo_stop_wr |
n_wr_full |
hssi_10g_rx_pcs_force_align |
force_align_dis |
hssi_10g_rx_pcs_frmsync_bypass |
frmsync_bypass_en |
hssi_10g_rx_pcs_frmsync_clken |
frmsync_clk_dis |
hssi_10g_rx_pcs_frmsync_enum_scrm |
enum_scrm_default |
hssi_10g_rx_pcs_frmsync_enum_sync |
enum_sync_default |
hssi_10g_rx_pcs_frmsync_flag_type |
location_only |
hssi_10g_rx_pcs_frmsync_knum_sync |
knum_sync_default |
hssi_10g_rx_pcs_frmsync_mfrm_length |
2048 |
hssi_10g_rx_pcs_frmsync_pipeln |
frmsync_pipeln_en |
hssi_10g_rx_pcs_full_flag_type |
full_wr_side |
hssi_10g_rx_pcs_gb_rx_idwidth |
width_40 |
hssi_10g_rx_pcs_gb_rx_odwidth |
width_40 |
hssi_10g_rx_pcs_gbexp_clken |
gbexp_clk_en |
hssi_10g_rx_pcs_low_latency_en |
disable |
hssi_10g_rx_pcs_lpbk_mode |
lpbk_dis |
hssi_10g_rx_pcs_master_clk_sel |
master_rx_pma_clk |
hssi_10g_rx_pcs_pempty_flag_type |
pempty_rd_side |
hssi_10g_rx_pcs_pfull_flag_type |
pfull_wr_side |
hssi_10g_rx_pcs_phcomp_rd_del |
phcomp_rd_del3 |
hssi_10g_rx_pcs_pld_if_type |
fifo |
hssi_10g_rx_pcs_prot_mode |
basic_mode |
hssi_10g_rx_pcs_rand_clken |
rand_clk_dis |
hssi_10g_rx_pcs_rd_clk_sel |
rd_rx_pld_clk |
hssi_10g_rx_pcs_rdfifo_clken |
rdfifo_clk_en |
hssi_10g_rx_pcs_rx_fifo_write_ctrl |
blklock_stops |
hssi_10g_rx_pcs_rx_scrm_width |
bit64 |
hssi_10g_rx_pcs_rx_sh_location |
msb |
hssi_10g_rx_pcs_rx_signal_ok_sel |
synchronized_ver |
hssi_10g_rx_pcs_rx_sm_bypass |
rx_sm_bypass_en |
hssi_10g_rx_pcs_rx_sm_hiber |
rx_sm_hiber_en |
hssi_10g_rx_pcs_rx_sm_pipeln |
rx_sm_pipeln_en |
hssi_10g_rx_pcs_rx_testbus_sel |
rx_fifo_testbus1 |
hssi_10g_rx_pcs_rx_true_b2b |
b2b |
hssi_10g_rx_pcs_rxfifo_empty |
empty_default |
hssi_10g_rx_pcs_rxfifo_full |
full_default |
hssi_10g_rx_pcs_rxfifo_mode |
phase_comp |
hssi_10g_rx_pcs_rxfifo_pempty |
2 |
hssi_10g_rx_pcs_rxfifo_pfull |
23 |
hssi_10g_rx_pcs_stretch_num_stages |
one_stage |
hssi_10g_rx_pcs_sup_mode |
user_mode |
hssi_10g_rx_pcs_test_mode |
test_off |
hssi_10g_rx_pcs_wrfifo_clken |
wrfifo_clk_en |
hssi_10g_rx_pcs_advanced_user_mode |
disable |
hssi_10g_rx_pcs_silicon_rev |
20nm5es |
hssi_10g_rx_pcs_reconfig_settings |
{} |
hssi_10g_tx_pcs_bitslip_en |
bitslip_dis |
hssi_10g_tx_pcs_bonding_dft_en |
dft_dis |
hssi_10g_tx_pcs_bonding_dft_val |
dft_0 |
hssi_10g_tx_pcs_comp_cnt |
0 |
hssi_10g_tx_pcs_compin_sel |
compin_master |
hssi_10g_tx_pcs_crcgen_bypass |
crcgen_bypass_en |
hssi_10g_tx_pcs_crcgen_clken |
crcgen_clk_dis |
hssi_10g_tx_pcs_crcgen_err |
crcgen_err_dis |
hssi_10g_tx_pcs_crcgen_inv |
crcgen_inv_en |
hssi_10g_tx_pcs_ctrl_bit_reverse |
ctrl_bit_reverse_dis |
hssi_10g_tx_pcs_ctrl_plane_bonding |
individual |
hssi_10g_tx_pcs_data_bit_reverse |
data_bit_reverse_dis |
hssi_10g_tx_pcs_dft_clk_out_sel |
tx_master_clk |
hssi_10g_tx_pcs_dispgen_bypass |
dispgen_bypass_en |
hssi_10g_tx_pcs_dispgen_clken |
dispgen_clk_dis |
hssi_10g_tx_pcs_dispgen_err |
dispgen_err_dis |
hssi_10g_tx_pcs_dispgen_pipeln |
dispgen_pipeln_dis |
hssi_10g_tx_pcs_distdwn_bypass_pipeln |
distdwn_bypass_pipeln_dis |
hssi_10g_tx_pcs_distdwn_master |
distdwn_master_en |
hssi_10g_tx_pcs_distup_bypass_pipeln |
distup_bypass_pipeln_dis |
hssi_10g_tx_pcs_distup_master |
distup_master_en |
hssi_10g_tx_pcs_dv_bond |
dv_bond_dis |
hssi_10g_tx_pcs_empty_flag_type |
empty_rd_side |
hssi_10g_tx_pcs_enc_64b66b_txsm_bypass |
enc_64b66b_txsm_bypass_en |
hssi_10g_tx_pcs_enc64b66b_txsm_clken |
enc64b66b_txsm_clk_dis |
hssi_10g_tx_pcs_fastpath |
fastpath_en |
hssi_10g_tx_pcs_fec_clken |
fec_clk_dis |
hssi_10g_tx_pcs_fec_enable |
fec_dis |
hssi_10g_tx_pcs_fifo_double_write |
fifo_double_write_dis |
hssi_10g_tx_pcs_fifo_reg_fast |
fifo_reg_fast_dis |
hssi_10g_tx_pcs_fifo_stop_rd |
rd_empty |
hssi_10g_tx_pcs_fifo_stop_wr |
n_wr_full |
hssi_10g_tx_pcs_frmgen_burst |
frmgen_burst_dis |
hssi_10g_tx_pcs_frmgen_bypass |
frmgen_bypass_en |
hssi_10g_tx_pcs_frmgen_clken |
frmgen_clk_dis |
hssi_10g_tx_pcs_frmgen_mfrm_length |
2048 |
hssi_10g_tx_pcs_frmgen_pipeln |
frmgen_pipeln_en |
hssi_10g_tx_pcs_frmgen_pyld_ins |
frmgen_pyld_ins_dis |
hssi_10g_tx_pcs_frmgen_wordslip |
frmgen_wordslip_dis |
hssi_10g_tx_pcs_full_flag_type |
full_wr_side |
hssi_10g_tx_pcs_gb_pipeln_bypass |
disable |
hssi_10g_tx_pcs_gb_tx_idwidth |
width_40 |
hssi_10g_tx_pcs_gb_tx_odwidth |
width_40 |
hssi_10g_tx_pcs_gbred_clken |
gbred_clk_en |
hssi_10g_tx_pcs_indv |
indv_en |
hssi_10g_tx_pcs_low_latency_en |
disable |
hssi_10g_tx_pcs_master_clk_sel |
master_tx_pma_clk |
hssi_10g_tx_pcs_pempty_flag_type |
pempty_rd_side |
hssi_10g_tx_pcs_pfull_flag_type |
pfull_wr_side |
hssi_10g_tx_pcs_phcomp_rd_del |
phcomp_rd_del4 |
hssi_10g_tx_pcs_pld_if_type |
fifo |
hssi_10g_tx_pcs_prot_mode |
basic_mode |
hssi_10g_tx_pcs_pseudo_random |
all_0 |
hssi_10g_tx_pcs_pseudo_seed_a |
288230376151711743 |
hssi_10g_tx_pcs_pseudo_seed_b |
288230376151711743 |
hssi_10g_tx_pcs_random_disp |
disable |
hssi_10g_tx_pcs_rdfifo_clken |
rdfifo_clk_en |
hssi_10g_tx_pcs_scrm_bypass |
scrm_bypass_en |
hssi_10g_tx_pcs_scrm_clken |
scrm_clk_dis |
hssi_10g_tx_pcs_scrm_mode |
async |
hssi_10g_tx_pcs_scrm_pipeln |
enable |
hssi_10g_tx_pcs_sh_err |
sh_err_dis |
hssi_10g_tx_pcs_sop_mark |
sop_mark_dis |
hssi_10g_tx_pcs_stretch_num_stages |
one_stage |
hssi_10g_tx_pcs_sup_mode |
user_mode |
hssi_10g_tx_pcs_test_mode |
test_off |
hssi_10g_tx_pcs_tx_scrm_err |
scrm_err_dis |
hssi_10g_tx_pcs_tx_scrm_width |
bit64 |
hssi_10g_tx_pcs_tx_sh_location |
msb |
hssi_10g_tx_pcs_tx_sm_bypass |
tx_sm_bypass_en |
hssi_10g_tx_pcs_tx_sm_pipeln |
tx_sm_pipeln_en |
hssi_10g_tx_pcs_tx_testbus_sel |
tx_fifo_testbus1 |
hssi_10g_tx_pcs_txfifo_empty |
empty_default |
hssi_10g_tx_pcs_txfifo_full |
full_default |
hssi_10g_tx_pcs_txfifo_mode |
phase_comp |
hssi_10g_tx_pcs_txfifo_pempty |
2 |
hssi_10g_tx_pcs_txfifo_pfull |
11 |
hssi_10g_tx_pcs_wr_clk_sel |
wr_tx_pld_clk |
hssi_10g_tx_pcs_wrfifo_clken |
wrfifo_clk_en |
hssi_10g_tx_pcs_advanced_user_mode |
disable |
hssi_10g_tx_pcs_silicon_rev |
20nm5es |
hssi_10g_tx_pcs_reconfig_settings |
{} |
hssi_8g_rx_pcs_auto_error_replacement |
dis_err_replace |
hssi_8g_rx_pcs_auto_speed_nego |
dis_asn |
hssi_8g_rx_pcs_bit_reversal |
dis_bit_reversal |
hssi_8g_rx_pcs_bonding_dft_en |
dft_dis |
hssi_8g_rx_pcs_bonding_dft_val |
dft_0 |
hssi_8g_rx_pcs_bypass_pipeline_reg |
dis_bypass_pipeline |
hssi_8g_rx_pcs_byte_deserializer |
dis_bds |
hssi_8g_rx_pcs_cdr_ctrl_rxvalid_mask |
dis_rxvalid_mask |
hssi_8g_rx_pcs_clkcmp_pattern_n |
0 |
hssi_8g_rx_pcs_clkcmp_pattern_p |
0 |
hssi_8g_rx_pcs_clock_gate_bds_dec_asn |
en_bds_dec_asn_clk_gating |
hssi_8g_rx_pcs_clock_gate_cdr_eidle |
en_cdr_eidle_clk_gating |
hssi_8g_rx_pcs_clock_gate_dw_pc_wrclk |
en_dw_pc_wrclk_gating |
hssi_8g_rx_pcs_clock_gate_dw_rm_rd |
en_dw_rm_rdclk_gating |
hssi_8g_rx_pcs_clock_gate_dw_rm_wr |
en_dw_rm_wrclk_gating |
hssi_8g_rx_pcs_clock_gate_dw_wa |
en_dw_wa_clk_gating |
hssi_8g_rx_pcs_clock_gate_pc_rdclk |
en_pc_rdclk_gating |
hssi_8g_rx_pcs_clock_gate_sw_pc_wrclk |
en_sw_pc_wrclk_gating |
hssi_8g_rx_pcs_clock_gate_sw_rm_rd |
en_sw_rm_rdclk_gating |
hssi_8g_rx_pcs_clock_gate_sw_rm_wr |
en_sw_rm_wrclk_gating |
hssi_8g_rx_pcs_clock_gate_sw_wa |
en_sw_wa_clk_gating |
hssi_8g_rx_pcs_clock_observation_in_pld_core |
internal_sw_wa_clk |
hssi_8g_rx_pcs_ctrl_plane_bonding_compensation |
dis_compensation |
hssi_8g_rx_pcs_ctrl_plane_bonding_consumption |
individual |
hssi_8g_rx_pcs_ctrl_plane_bonding_distribution |
not_master_chnl_distr |
hssi_8g_rx_pcs_eidle_entry_eios |
dis_eidle_eios |
hssi_8g_rx_pcs_eidle_entry_iei |
dis_eidle_iei |
hssi_8g_rx_pcs_eidle_entry_sd |
dis_eidle_sd |
hssi_8g_rx_pcs_eightb_tenb_decoder |
en_8b10b_ibm |
hssi_8g_rx_pcs_err_flags_sel |
err_flags_wa |
hssi_8g_rx_pcs_fixed_pat_det |
dis_fixed_patdet |
hssi_8g_rx_pcs_fixed_pat_num |
0 |
hssi_8g_rx_pcs_force_signal_detect |
en_force_signal_detect |
hssi_8g_rx_pcs_gen3_clk_en |
disable_clk |
hssi_8g_rx_pcs_gen3_rx_clk_sel |
rcvd_clk |
hssi_8g_rx_pcs_gen3_tx_clk_sel |
tx_pma_clk |
hssi_8g_rx_pcs_hip_mode |
dis_hip |
hssi_8g_rx_pcs_ibm_invalid_code |
dis_ibm_invalid_code |
hssi_8g_rx_pcs_invalid_code_flag_only |
dis_invalid_code_only |
hssi_8g_rx_pcs_pad_or_edb_error_replace |
replace_edb |
hssi_8g_rx_pcs_pcs_bypass |
dis_pcs_bypass |
hssi_8g_rx_pcs_phase_comp_rdptr |
disable_rdptr |
hssi_8g_rx_pcs_phase_compensation_fifo |
low_latency |
hssi_8g_rx_pcs_pipe_if_enable |
dis_pipe_rx |
hssi_8g_rx_pcs_pma_dw |
ten_bit |
hssi_8g_rx_pcs_polinv_8b10b_dec |
dis_polinv_8b10b_dec |
hssi_8g_rx_pcs_prot_mode |
disabled_prot_mode |
hssi_8g_rx_pcs_rate_match |
dis_rm |
hssi_8g_rx_pcs_rate_match_del_thres |
dis_rm_del_thres |
hssi_8g_rx_pcs_rate_match_empty_thres |
dis_rm_empty_thres |
hssi_8g_rx_pcs_rate_match_full_thres |
dis_rm_full_thres |
hssi_8g_rx_pcs_rate_match_ins_thres |
dis_rm_ins_thres |
hssi_8g_rx_pcs_rate_match_start_thres |
dis_rm_start_thres |
hssi_8g_rx_pcs_rx_clk_free_running |
en_rx_clk_free_run |
hssi_8g_rx_pcs_rx_clk2 |
rcvd_clk_clk2 |
hssi_8g_rx_pcs_rx_pcs_urst |
en_rx_pcs_urst |
hssi_8g_rx_pcs_rx_rcvd_clk |
rcvd_clk_rcvd_clk |
hssi_8g_rx_pcs_rx_rd_clk |
pld_rx_clk |
hssi_8g_rx_pcs_rx_refclk |
dis_refclk_sel |
hssi_8g_rx_pcs_rx_wr_clk |
rx_clk2_div_1_2_4 |
hssi_8g_rx_pcs_sup_mode |
user_mode |
hssi_8g_rx_pcs_symbol_swap |
dis_symbol_swap |
hssi_8g_rx_pcs_sync_sm_idle_eios |
dis_syncsm_idle |
hssi_8g_rx_pcs_test_bus_sel |
tx_testbus |
hssi_8g_rx_pcs_tx_rx_parallel_loopback |
dis_plpbk |
hssi_8g_rx_pcs_wa_boundary_lock_ctrl |
sync_sm |
hssi_8g_rx_pcs_wa_clk_slip_spacing |
16 |
hssi_8g_rx_pcs_wa_det_latency_sync_status_beh |
dont_care_assert_sync |
hssi_8g_rx_pcs_wa_disp_err_flag |
en_disp_err_flag |
hssi_8g_rx_pcs_wa_kchar |
dis_kchar |
hssi_8g_rx_pcs_wa_pd |
wa_pd_10 |
hssi_8g_rx_pcs_wa_pd_data |
0 |
hssi_8g_rx_pcs_wa_pd_polarity |
dont_care_both_pol |
hssi_8g_rx_pcs_wa_pld_controlled |
dis_pld_ctrl |
hssi_8g_rx_pcs_wa_renumber_data |
3 |
hssi_8g_rx_pcs_wa_rgnumber_data |
3 |
hssi_8g_rx_pcs_wa_rknumber_data |
3 |
hssi_8g_rx_pcs_wa_rosnumber_data |
1 |
hssi_8g_rx_pcs_wa_rvnumber_data |
0 |
hssi_8g_rx_pcs_wa_sync_sm_ctrl |
gige_sync_sm |
hssi_8g_rx_pcs_wait_cnt |
0 |
hssi_8g_rx_pcs_silicon_rev |
20nm5es |
hssi_8g_rx_pcs_reconfig_settings |
{} |
hssi_8g_tx_pcs_auto_speed_nego_gen2 |
dis_asn_g2 |
hssi_8g_tx_pcs_bit_reversal |
dis_bit_reversal |
hssi_8g_tx_pcs_bonding_dft_en |
dft_dis |
hssi_8g_tx_pcs_bonding_dft_val |
dft_0 |
hssi_8g_tx_pcs_bypass_pipeline_reg |
dis_bypass_pipeline |
hssi_8g_tx_pcs_byte_serializer |
dis_bs |
hssi_8g_tx_pcs_clock_gate_bs_enc |
en_bs_enc_clk_gating |
hssi_8g_tx_pcs_clock_gate_dw_fifowr |
en_dw_fifowr_clk_gating |
hssi_8g_tx_pcs_clock_gate_fiford |
en_fiford_clk_gating |
hssi_8g_tx_pcs_clock_gate_sw_fifowr |
en_sw_fifowr_clk_gating |
hssi_8g_tx_pcs_clock_observation_in_pld_core |
internal_refclk_b |
hssi_8g_tx_pcs_ctrl_plane_bonding_compensation |
dis_compensation |
hssi_8g_tx_pcs_ctrl_plane_bonding_consumption |
individual |
hssi_8g_tx_pcs_ctrl_plane_bonding_distribution |
not_master_chnl_distr |
hssi_8g_tx_pcs_data_selection_8b10b_encoder_input |
normal_data_path |
hssi_8g_tx_pcs_dynamic_clk_switch |
dis_dyn_clk_switch |
hssi_8g_tx_pcs_eightb_tenb_disp_ctrl |
dis_disp_ctrl |
hssi_8g_tx_pcs_eightb_tenb_encoder |
en_8b10b_ibm |
hssi_8g_tx_pcs_force_echar |
dis_force_echar |
hssi_8g_tx_pcs_force_kchar |
dis_force_kchar |
hssi_8g_tx_pcs_gen3_tx_clk_sel |
dis_tx_clk |
hssi_8g_tx_pcs_gen3_tx_pipe_clk_sel |
dis_tx_pipe_clk |
hssi_8g_tx_pcs_hip_mode |
dis_hip |
hssi_8g_tx_pcs_pcs_bypass |
dis_pcs_bypass |
hssi_8g_tx_pcs_phase_comp_rdptr |
disable_rdptr |
hssi_8g_tx_pcs_phase_compensation_fifo |
low_latency |
hssi_8g_tx_pcs_phfifo_write_clk_sel |
pld_tx_clk |
hssi_8g_tx_pcs_pma_dw |
ten_bit |
hssi_8g_tx_pcs_prot_mode |
disabled_prot_mode |
hssi_8g_tx_pcs_refclk_b_clk_sel |
tx_pma_clock |
hssi_8g_tx_pcs_revloop_back_rm |
dis_rev_loopback_rx_rm |
hssi_8g_tx_pcs_sup_mode |
user_mode |
hssi_8g_tx_pcs_symbol_swap |
dis_symbol_swap |
hssi_8g_tx_pcs_tx_bitslip |
dis_tx_bitslip |
hssi_8g_tx_pcs_tx_compliance_controlled_disparity |
dis_txcompliance |
hssi_8g_tx_pcs_tx_fast_pld_reg |
dis_tx_fast_pld_reg |
hssi_8g_tx_pcs_txclk_freerun |
en_freerun_tx |
hssi_8g_tx_pcs_txpcs_urst |
en_txpcs_urst |
hssi_8g_tx_pcs_silicon_rev |
20nm5es |
hssi_8g_tx_pcs_reconfig_settings |
{} |
hssi_tx_pld_pcs_interface_hd_chnl_hip_en |
disable |
hssi_tx_pld_pcs_interface_hd_chnl_hrdrstctl_en |
disable |
hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx |
basic_10gpcs_tx |
hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx |
individual_tx |
hssi_tx_pld_pcs_interface_hd_chnl_pma_dw_tx |
pma_40b_tx |
hssi_tx_pld_pcs_interface_hd_chnl_pld_fifo_mode_tx |
fifo_tx |
hssi_tx_pld_pcs_interface_hd_chnl_shared_fifo_width_tx |
single_tx |
hssi_tx_pld_pcs_interface_hd_chnl_low_latency_en_tx |
disable |
hssi_tx_pld_pcs_interface_hd_chnl_func_mode |
enable |
hssi_tx_pld_pcs_interface_hd_chnl_sup_mode |
user_mode |
hssi_tx_pld_pcs_interface_hd_chnl_channel_operation_mode |
tx_rx_pair_enabled |
hssi_tx_pld_pcs_interface_hd_chnl_lpbk_en |
disable |
hssi_tx_pld_pcs_interface_hd_chnl_frequency_rules_en |
enable |
hssi_tx_pld_pcs_interface_hd_chnl_speed_grade |
e3 |
hssi_tx_pld_pcs_interface_hd_chnl_pma_tx_clk_hz |
257812500 |
hssi_tx_pld_pcs_interface_hd_chnl_pld_tx_clk_hz |
257812500 |
hssi_tx_pld_pcs_interface_hd_chnl_pld_uhsif_tx_clk_hz |
0 |
hssi_tx_pld_pcs_interface_hd_chnl_hclk_clk_hz |
0 |
hssi_tx_pld_pcs_interface_hd_chnl_pld_pcs_refclk_dig_nonatpg_mode_clk_hz |
0 |
hssi_tx_pld_pcs_interface_hd_chnl_pld_8g_refclk_dig_nonatpg_mode_clk_hz |
0 |
hssi_tx_pld_pcs_interface_hd_chnl_pcs_tx_ac_pwr_uw_per_mhz |
0 |
hssi_tx_pld_pcs_interface_hd_chnl_pcs_tx_pwr_scaling_clk |
pma_tx_clk |
hssi_tx_pld_pcs_interface_hd_fifo_sup_mode |
user_mode |
hssi_tx_pld_pcs_interface_hd_fifo_channel_operation_mode |
tx_rx_pair_enabled |
hssi_tx_pld_pcs_interface_hd_fifo_prot_mode_tx |
teng_mode_tx |
hssi_tx_pld_pcs_interface_hd_fifo_shared_fifo_width_tx |
single_tx |
hssi_tx_pld_pcs_interface_hd_10g_sup_mode |
user_mode |
hssi_tx_pld_pcs_interface_hd_10g_channel_operation_mode |
tx_rx_pair_enabled |
hssi_tx_pld_pcs_interface_hd_10g_lpbk_en |
disable |
hssi_tx_pld_pcs_interface_hd_10g_advanced_user_mode_tx |
disable |
hssi_tx_pld_pcs_interface_hd_10g_pma_dw_tx |
pma_40b_tx |
hssi_tx_pld_pcs_interface_hd_10g_fifo_mode_tx |
fifo_tx |
hssi_tx_pld_pcs_interface_hd_10g_prot_mode_tx |
basic_mode_tx |
hssi_tx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_tx |
individual_tx |
hssi_tx_pld_pcs_interface_hd_10g_low_latency_en_tx |
disable |
hssi_tx_pld_pcs_interface_hd_10g_shared_fifo_width_tx |
single_tx |
hssi_tx_pld_pcs_interface_hd_8g_sup_mode |
user_mode |
hssi_tx_pld_pcs_interface_hd_8g_channel_operation_mode |
tx_rx_pair_enabled |
hssi_tx_pld_pcs_interface_hd_8g_lpbk_en |
disable |
hssi_tx_pld_pcs_interface_hd_8g_prot_mode_tx |
disabled_prot_mode_tx |
hssi_tx_pld_pcs_interface_hd_8g_hip_mode |
disable |
hssi_tx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_tx |
ctrl_master_tx |
hssi_tx_pld_pcs_interface_hd_8g_pma_dw_tx |
pma_10b_tx |
hssi_tx_pld_pcs_interface_hd_8g_fifo_mode_tx |
fifo_tx |
hssi_tx_pld_pcs_interface_hd_g3_sup_mode |
user_mode |
hssi_tx_pld_pcs_interface_hd_g3_prot_mode |
disabled_prot_mode |
hssi_tx_pld_pcs_interface_hd_krfec_sup_mode |
user_mode |
hssi_tx_pld_pcs_interface_hd_krfec_channel_operation_mode |
tx_rx_pair_enabled |
hssi_tx_pld_pcs_interface_hd_krfec_lpbk_en |
disable |
hssi_tx_pld_pcs_interface_hd_krfec_prot_mode_tx |
disabled_prot_mode_tx |
hssi_tx_pld_pcs_interface_hd_krfec_low_latency_en_tx |
disable |
hssi_tx_pld_pcs_interface_hd_pmaif_sup_mode |
user_mode |
hssi_tx_pld_pcs_interface_hd_pmaif_lpbk_en |
disable |
hssi_tx_pld_pcs_interface_hd_pmaif_channel_operation_mode |
tx_rx_pair_enabled |
hssi_tx_pld_pcs_interface_hd_pmaif_sim_mode |
disable |
hssi_tx_pld_pcs_interface_hd_pmaif_prot_mode_tx |
teng_basic_mode_tx |
hssi_tx_pld_pcs_interface_hd_pmaif_ctrl_plane_bonding |
individual |
hssi_tx_pld_pcs_interface_hd_pmaif_pma_dw_tx |
pma_40b_tx |
hssi_tx_pld_pcs_interface_hd_pldif_prot_mode_tx |
teng_pld_fifo_mode_tx |
hssi_tx_pld_pcs_interface_hd_pldif_hrdrstctl_en |
disable |
hssi_tx_pld_pcs_interface_hd_pldif_sup_mode |
user_mode |
hssi_tx_pld_pcs_interface_pcs_tx_clk_source |
teng |
hssi_tx_pld_pcs_interface_pcs_tx_data_source |
hip_disable |
hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_en |
delay1_clk_disable |
hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_sel |
pcs_tx_clk |
hssi_tx_pld_pcs_interface_pcs_tx_delay1_ctrl |
delay1_path0 |
hssi_tx_pld_pcs_interface_pcs_tx_delay1_data_sel |
one_ff_delay |
hssi_tx_pld_pcs_interface_pcs_tx_delay2_clk_en |
delay2_clk_disable |
hssi_tx_pld_pcs_interface_pcs_tx_delay2_ctrl |
delay2_path0 |
hssi_tx_pld_pcs_interface_pcs_tx_output_sel |
teng_output |
hssi_tx_pld_pcs_interface_silicon_rev |
20nm5es |
hssi_tx_pld_pcs_interface_pcs_tx_clk_out_sel |
teng_clk_out |
hssi_tx_pld_pcs_interface_reconfig_settings |
{} |
hssi_rx_pld_pcs_interface_hd_chnl_hip_en |
disable |
hssi_rx_pld_pcs_interface_hd_chnl_transparent_pcs_rx |
disable |
hssi_rx_pld_pcs_interface_hd_chnl_hrdrstctl_en |
disable |
hssi_rx_pld_pcs_interface_hd_chnl_prot_mode_rx |
basic_10gpcs_rx |
hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx |
individual_rx |
hssi_rx_pld_pcs_interface_hd_chnl_pma_dw_rx |
pma_40b_rx |
hssi_rx_pld_pcs_interface_hd_chnl_pld_fifo_mode_rx |
fifo_rx |
hssi_rx_pld_pcs_interface_hd_chnl_shared_fifo_width_rx |
single_rx |
hssi_rx_pld_pcs_interface_hd_chnl_low_latency_en_rx |
disable |
hssi_rx_pld_pcs_interface_hd_chnl_func_mode |
enable |
hssi_rx_pld_pcs_interface_hd_chnl_sup_mode |
user_mode |
hssi_rx_pld_pcs_interface_hd_chnl_channel_operation_mode |
tx_rx_pair_enabled |
hssi_rx_pld_pcs_interface_hd_chnl_lpbk_en |
disable |
hssi_rx_pld_pcs_interface_hd_10g_advanced_user_mode_rx |
disable |
hssi_rx_pld_pcs_interface_hd_chnl_frequency_rules_en |
enable |
hssi_rx_pld_pcs_interface_hd_chnl_speed_grade |
e3 |
hssi_rx_pld_pcs_interface_hd_chnl_pma_rx_clk_hz |
257812500 |
hssi_rx_pld_pcs_interface_hd_chnl_pld_rx_clk_hz |
257812500 |
hssi_rx_pld_pcs_interface_hd_chnl_fref_clk_hz |
322265625 |
hssi_rx_pld_pcs_interface_hd_chnl_clklow_clk_hz |
322265625 |
hssi_rx_pld_pcs_interface_hd_chnl_hclk_clk_hz |
0 |
hssi_rx_pld_pcs_interface_hd_chnl_pld_pcs_refclk_dig_nonatpg_mode_clk_hz |
0 |
hssi_rx_pld_pcs_interface_hd_chnl_pld_8g_refclk_dig_nonatpg_mode_clk_hz |
0 |
hssi_rx_pld_pcs_interface_hd_chnl_pcs_rx_ac_pwr_uw_per_mhz |
0 |
hssi_rx_pld_pcs_interface_hd_chnl_operating_voltage |
standard |
hssi_rx_pld_pcs_interface_hd_chnl_pcs_ac_pwr_rules_en |
disable |
hssi_rx_pld_pcs_interface_hd_chnl_pcs_rx_pwr_scaling_clk |
pma_rx_clk |
hssi_rx_pld_pcs_interface_hd_chnl_pcs_pair_ac_pwr_uw_per_mhz |
0 |
hssi_rx_pld_pcs_interface_hd_fifo_sup_mode |
user_mode |
hssi_rx_pld_pcs_interface_hd_fifo_channel_operation_mode |
tx_rx_pair_enabled |
hssi_rx_pld_pcs_interface_hd_fifo_prot_mode_rx |
teng_mode_rx |
hssi_rx_pld_pcs_interface_hd_fifo_shared_fifo_width_rx |
single_rx |
hssi_rx_pld_pcs_interface_hd_10g_sup_mode |
user_mode |
hssi_rx_pld_pcs_interface_hd_10g_channel_operation_mode |
tx_rx_pair_enabled |
hssi_rx_pld_pcs_interface_hd_10g_lpbk_en |
disable |
hssi_rx_pld_pcs_interface_hd_10g_pma_dw_rx |
pma_40b_rx |
hssi_rx_pld_pcs_interface_hd_10g_fifo_mode_rx |
fifo_rx |
hssi_rx_pld_pcs_interface_hd_10g_prot_mode_rx |
basic_mode_rx |
hssi_rx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_rx |
individual_rx |
hssi_rx_pld_pcs_interface_hd_10g_low_latency_en_rx |
disable |
hssi_rx_pld_pcs_interface_hd_10g_shared_fifo_width_rx |
single_rx |
hssi_rx_pld_pcs_interface_hd_10g_test_bus_mode |
rx |
hssi_rx_pld_pcs_interface_hd_8g_sup_mode |
user_mode |
hssi_rx_pld_pcs_interface_hd_8g_channel_operation_mode |
tx_rx_pair_enabled |
hssi_rx_pld_pcs_interface_hd_8g_lpbk_en |
disable |
hssi_rx_pld_pcs_interface_hd_8g_prot_mode_rx |
disabled_prot_mode_rx |
hssi_rx_pld_pcs_interface_hd_8g_hip_mode |
disable |
hssi_rx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_rx |
individual_rx |
hssi_rx_pld_pcs_interface_hd_8g_pma_dw_rx |
pma_10b_rx |
hssi_rx_pld_pcs_interface_hd_8g_fifo_mode_rx |
fifo_rx |
hssi_rx_pld_pcs_interface_hd_g3_sup_mode |
user_mode |
hssi_rx_pld_pcs_interface_hd_g3_prot_mode |
disabled_prot_mode |
hssi_rx_pld_pcs_interface_hd_krfec_sup_mode |
user_mode |
hssi_rx_pld_pcs_interface_hd_krfec_channel_operation_mode |
tx_rx_pair_enabled |
hssi_rx_pld_pcs_interface_hd_krfec_lpbk_en |
disable |
hssi_rx_pld_pcs_interface_hd_krfec_prot_mode_rx |
disabled_prot_mode_rx |
hssi_rx_pld_pcs_interface_hd_krfec_low_latency_en_rx |
disable |
hssi_rx_pld_pcs_interface_hd_krfec_test_bus_mode |
tx |
hssi_rx_pld_pcs_interface_hd_pmaif_sup_mode |
user_mode |
hssi_rx_pld_pcs_interface_hd_pmaif_lpbk_en |
disable |
hssi_rx_pld_pcs_interface_hd_pmaif_channel_operation_mode |
tx_rx_pair_enabled |
hssi_rx_pld_pcs_interface_hd_pmaif_sim_mode |
disable |
hssi_rx_pld_pcs_interface_hd_pmaif_prot_mode_rx |
teng_basic_mode_rx |
hssi_rx_pld_pcs_interface_hd_pmaif_pma_dw_rx |
pma_40b_rx |
hssi_rx_pld_pcs_interface_hd_pldif_prot_mode_rx |
teng_pld_fifo_mode_rx |
hssi_rx_pld_pcs_interface_hd_pldif_hrdrstctl_en |
disable |
hssi_rx_pld_pcs_interface_hd_pldif_sup_mode |
user_mode |
hssi_rx_pld_pcs_interface_pcs_rx_block_sel |
teng |
hssi_rx_pld_pcs_interface_pcs_rx_clk_sel |
pld_rx_clk |
hssi_rx_pld_pcs_interface_pcs_rx_hip_clk_en |
hip_rx_disable |
hssi_rx_pld_pcs_interface_pcs_rx_output_sel |
teng_output |
hssi_rx_pld_pcs_interface_silicon_rev |
20nm5es |
hssi_rx_pld_pcs_interface_pcs_rx_clk_out_sel |
teng_clk_out |
hssi_rx_pld_pcs_interface_reconfig_settings |
{} |
hssi_common_pld_pcs_interface_dft_clk_out_en |
dft_clk_out_disable |
hssi_common_pld_pcs_interface_dft_clk_out_sel |
teng_rx_dft_clk |
hssi_common_pld_pcs_interface_hrdrstctrl_en |
hrst_dis |
hssi_common_pld_pcs_interface_pcs_testbus_block_sel |
pma_if |
hssi_common_pld_pcs_interface_silicon_rev |
20nm5es |
hssi_common_pld_pcs_interface_reconfig_settings |
{} |
hssi_rx_pcs_pma_interface_block_sel |
ten_g_pcs |
hssi_rx_pcs_pma_interface_channel_operation_mode |
tx_rx_pair_enabled |
hssi_rx_pcs_pma_interface_clkslip_sel |
pld |
hssi_rx_pcs_pma_interface_lpbk_en |
disable |
hssi_rx_pcs_pma_interface_master_clk_sel |
master_rx_pma_clk |
hssi_rx_pcs_pma_interface_pldif_datawidth_mode |
pldif_data_10bit |
hssi_rx_pcs_pma_interface_pma_dw_rx |
pma_40b_rx |
hssi_rx_pcs_pma_interface_pma_if_dft_en |
dft_dis |
hssi_rx_pcs_pma_interface_pma_if_dft_val |
dft_0 |
hssi_rx_pcs_pma_interface_prbs_clken |
prbs_clk_dis |
hssi_rx_pcs_pma_interface_prbs_ver |
prbs_off |
hssi_rx_pcs_pma_interface_prbs9_dwidth |
prbs9_64b |
hssi_rx_pcs_pma_interface_prot_mode_rx |
teng_basic_mode_rx |
hssi_rx_pcs_pma_interface_rx_dyn_polarity_inversion |
rx_dyn_polinv_dis |
hssi_rx_pcs_pma_interface_rx_lpbk_en |
lpbk_dis |
hssi_rx_pcs_pma_interface_rx_prbs_force_signal_ok |
force_sig_ok |
hssi_rx_pcs_pma_interface_rx_prbs_mask |
prbsmask128 |
hssi_rx_pcs_pma_interface_rx_prbs_mode |
teng_mode |
hssi_rx_pcs_pma_interface_rx_signalok_signaldet_sel |
sel_sig_det |
hssi_rx_pcs_pma_interface_rx_static_polarity_inversion |
rx_stat_polinv_dis |
hssi_rx_pcs_pma_interface_rx_uhsif_lpbk_en |
uhsif_lpbk_dis |
hssi_rx_pcs_pma_interface_sup_mode |
user_mode |
hssi_rx_pcs_pma_interface_silicon_rev |
20nm5es |
hssi_rx_pcs_pma_interface_reconfig_settings |
{} |
hssi_tx_pcs_pma_interface_bypass_pma_txelecidle |
true |
hssi_tx_pcs_pma_interface_channel_operation_mode |
tx_rx_pair_enabled |
hssi_tx_pcs_pma_interface_lpbk_en |
disable |
hssi_tx_pcs_pma_interface_master_clk_sel |
master_tx_pma_clk |
hssi_tx_pcs_pma_interface_pcie_sub_prot_mode_tx |
other_prot_mode |
hssi_tx_pcs_pma_interface_pldif_datawidth_mode |
pldif_data_10bit |
hssi_tx_pcs_pma_interface_pma_dw_tx |
pma_40b_tx |
hssi_tx_pcs_pma_interface_pma_if_dft_en |
dft_dis |
hssi_tx_pcs_pma_interface_pmagate_en |
pmagate_dis |
hssi_tx_pcs_pma_interface_prbs_clken |
prbs_clk_dis |
hssi_tx_pcs_pma_interface_prbs_gen_pat |
prbs_gen_dis |
hssi_tx_pcs_pma_interface_prbs9_dwidth |
prbs9_64b |
hssi_tx_pcs_pma_interface_prot_mode_tx |
teng_basic_mode_tx |
hssi_tx_pcs_pma_interface_sq_wave_num |
sq_wave_default |
hssi_tx_pcs_pma_interface_sqwgen_clken |
sqwgen_clk_dis |
hssi_tx_pcs_pma_interface_sup_mode |
user_mode |
hssi_tx_pcs_pma_interface_tx_dyn_polarity_inversion |
tx_dyn_polinv_dis |
hssi_tx_pcs_pma_interface_tx_pma_data_sel |
ten_g_pcs |
hssi_tx_pcs_pma_interface_tx_static_polarity_inversion |
tx_stat_polinv_dis |
hssi_tx_pcs_pma_interface_uhsif_cnt_step_filt_before_lock |
uhsif_filt_stepsz_b4lock_2 |
hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_after_lock_value |
0 |
hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_before_lock |
uhsif_filt_cntthr_b4lock_8 |
hssi_tx_pcs_pma_interface_uhsif_dcn_test_update_period |
uhsif_dcn_test_period_4 |
hssi_tx_pcs_pma_interface_uhsif_dcn_testmode_enable |
uhsif_dcn_test_mode_disable |
hssi_tx_pcs_pma_interface_uhsif_dead_zone_count_thresh |
uhsif_dzt_cnt_thr_2 |
hssi_tx_pcs_pma_interface_uhsif_dead_zone_detection_enable |
uhsif_dzt_disable |
hssi_tx_pcs_pma_interface_uhsif_dead_zone_obser_window |
uhsif_dzt_obr_win_16 |
hssi_tx_pcs_pma_interface_uhsif_dead_zone_skip_size |
uhsif_dzt_skipsz_4 |
hssi_tx_pcs_pma_interface_uhsif_delay_cell_index_sel |
uhsif_index_cram |
hssi_tx_pcs_pma_interface_uhsif_delay_cell_margin |
uhsif_dcn_margin_2 |
hssi_tx_pcs_pma_interface_uhsif_delay_cell_static_index_value |
0 |
hssi_tx_pcs_pma_interface_uhsif_dft_dead_zone_control |
uhsif_dft_dz_det_val_0 |
hssi_tx_pcs_pma_interface_uhsif_dft_up_filt_control |
uhsif_dft_up_val_0 |
hssi_tx_pcs_pma_interface_uhsif_enable |
uhsif_disable |
hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_after_lock |
uhsif_lkd_segsz_aflock_512 |
hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_before_lock |
uhsif_lkd_segsz_b4lock_16 |
hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_after_lock_value |
0 |
hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_before_lock_value |
0 |
hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_after_lock_value |
0 |
hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_before_lock_value |
0 |
hssi_tx_pcs_pma_interface_silicon_rev |
20nm5es |
hssi_tx_pcs_pma_interface_reconfig_settings |
{} |
hssi_common_pcs_pma_interface_asn_clk_enable |
false |
hssi_common_pcs_pma_interface_asn_enable |
dis_asn |
hssi_common_pcs_pma_interface_block_sel |
eight_g_pcs |
hssi_common_pcs_pma_interface_bypass_early_eios |
true |
hssi_common_pcs_pma_interface_bypass_pcie_switch |
true |
hssi_common_pcs_pma_interface_bypass_pma_ltr |
true |
hssi_common_pcs_pma_interface_bypass_pma_sw_done |
false |
hssi_common_pcs_pma_interface_bypass_ppm_lock |
false |
hssi_common_pcs_pma_interface_bypass_send_syncp_fbkp |
true |
hssi_common_pcs_pma_interface_bypass_txdetectrx |
true |
hssi_common_pcs_pma_interface_cdr_control |
dis_cdr_ctrl |
hssi_common_pcs_pma_interface_cid_enable |
dis_cid_mode |
hssi_common_pcs_pma_interface_cp_cons_sel |
cp_cons_master |
hssi_common_pcs_pma_interface_cp_dwn_mstr |
true |
hssi_common_pcs_pma_interface_cp_up_mstr |
true |
hssi_common_pcs_pma_interface_ctrl_plane_bonding |
individual |
hssi_common_pcs_pma_interface_data_mask_count |
0 |
hssi_common_pcs_pma_interface_data_mask_count_multi |
0 |
hssi_common_pcs_pma_interface_dft_observation_clock_selection |
dft_clk_obsrv_tx0 |
hssi_common_pcs_pma_interface_early_eios_counter |
0 |
hssi_common_pcs_pma_interface_force_freqdet |
force_freqdet_dis |
hssi_common_pcs_pma_interface_free_run_clk_enable |
false |
hssi_common_pcs_pma_interface_ignore_sigdet_g23 |
false |
hssi_common_pcs_pma_interface_pc_en_counter |
0 |
hssi_common_pcs_pma_interface_pc_rst_counter |
0 |
hssi_common_pcs_pma_interface_pcie_hip_mode |
hip_disable |
hssi_common_pcs_pma_interface_ph_fifo_reg_mode |
phfifo_reg_mode_dis |
hssi_common_pcs_pma_interface_phfifo_flush_wait |
0 |
hssi_common_pcs_pma_interface_pipe_if_g3pcs |
pipe_if_8gpcs |
hssi_common_pcs_pma_interface_pma_done_counter |
0 |
hssi_common_pcs_pma_interface_pma_if_dft_en |
dft_dis |
hssi_common_pcs_pma_interface_pma_if_dft_val |
dft_0 |
hssi_common_pcs_pma_interface_ppm_cnt_rst |
ppm_cnt_rst_dis |
hssi_common_pcs_pma_interface_ppm_deassert_early |
deassert_early_dis |
hssi_common_pcs_pma_interface_ppm_gen1_2_cnt |
cnt_32k |
hssi_common_pcs_pma_interface_ppm_post_eidle_delay |
cnt_200_cycles |
hssi_common_pcs_pma_interface_ppmsel |
ppmsel_1000 |
hssi_common_pcs_pma_interface_prot_mode |
other_protocols |
hssi_common_pcs_pma_interface_rxvalid_mask |
rxvalid_mask_dis |
hssi_common_pcs_pma_interface_sigdet_wait_counter |
0 |
hssi_common_pcs_pma_interface_sigdet_wait_counter_multi |
0 |
hssi_common_pcs_pma_interface_sim_mode |
disable |
hssi_common_pcs_pma_interface_spd_chg_rst_wait_cnt_en |
false |
hssi_common_pcs_pma_interface_sup_mode |
user_mode |
hssi_common_pcs_pma_interface_testout_sel |
asn_test |
hssi_common_pcs_pma_interface_wait_clk_on_off_timer |
0 |
hssi_common_pcs_pma_interface_wait_pipe_synchronizing |
0 |
hssi_common_pcs_pma_interface_wait_send_syncp_fbkp |
0 |
hssi_common_pcs_pma_interface_silicon_rev |
20nm5es |
hssi_common_pcs_pma_interface_ppm_det_buckets |
ppm_300_100_bucket |
hssi_common_pcs_pma_interface_reconfig_settings |
{} |
hssi_fifo_rx_pcs_double_read_mode |
double_read_dis |
hssi_fifo_rx_pcs_prot_mode |
teng_mode |
hssi_fifo_rx_pcs_silicon_rev |
20nm5es |
hssi_fifo_tx_pcs_double_write_mode |
double_write_dis |
hssi_fifo_tx_pcs_prot_mode |
teng_mode |
hssi_fifo_tx_pcs_silicon_rev |
20nm5es |
hssi_pipe_gen3_bypass_rx_detection_enable |
false |
hssi_pipe_gen3_bypass_rx_preset |
0 |
hssi_pipe_gen3_bypass_rx_preset_enable |
false |
hssi_pipe_gen3_bypass_tx_coefficent |
0 |
hssi_pipe_gen3_bypass_tx_coefficent_enable |
false |
hssi_pipe_gen3_elecidle_delay_g3 |
0 |
hssi_pipe_gen3_ind_error_reporting |
dis_ind_error_reporting |
hssi_pipe_gen3_mode |
disable_pcs |
hssi_pipe_gen3_phy_status_delay_g12 |
0 |
hssi_pipe_gen3_phy_status_delay_g3 |
0 |
hssi_pipe_gen3_phystatus_rst_toggle_g12 |
dis_phystatus_rst_toggle |
hssi_pipe_gen3_phystatus_rst_toggle_g3 |
dis_phystatus_rst_toggle_g3 |
hssi_pipe_gen3_rate_match_pad_insertion |
dis_rm_fifo_pad_ins |
hssi_pipe_gen3_sup_mode |
user_mode |
hssi_pipe_gen3_test_out_sel |
disable_test_out |
hssi_pipe_gen3_silicon_rev |
20nm5es |
hssi_pipe_gen1_2_elec_idle_delay_val |
0 |
hssi_pipe_gen1_2_error_replace_pad |
replace_edb |
hssi_pipe_gen1_2_hip_mode |
dis_hip |
hssi_pipe_gen1_2_ind_error_reporting |
dis_ind_error_reporting |
hssi_pipe_gen1_2_phystatus_delay_val |
0 |
hssi_pipe_gen1_2_phystatus_rst_toggle |
dis_phystatus_rst_toggle |
hssi_pipe_gen1_2_pipe_byte_de_serializer_en |
dont_care_bds |
hssi_pipe_gen1_2_prot_mode |
disabled_prot_mode |
hssi_pipe_gen1_2_rpre_emph_a_val |
0 |
hssi_pipe_gen1_2_rpre_emph_b_val |
0 |
hssi_pipe_gen1_2_rpre_emph_c_val |
0 |
hssi_pipe_gen1_2_rpre_emph_d_val |
0 |
hssi_pipe_gen1_2_rpre_emph_e_val |
0 |
hssi_pipe_gen1_2_rvod_sel_a_val |
0 |
hssi_pipe_gen1_2_rvod_sel_b_val |
0 |
hssi_pipe_gen1_2_rvod_sel_c_val |
0 |
hssi_pipe_gen1_2_rvod_sel_d_val |
0 |
hssi_pipe_gen1_2_rvod_sel_e_val |
0 |
hssi_pipe_gen1_2_rx_pipe_enable |
dis_pipe_rx |
hssi_pipe_gen1_2_rxdetect_bypass |
dis_rxdetect_bypass |
hssi_pipe_gen1_2_sup_mode |
user_mode |
hssi_pipe_gen1_2_tx_pipe_enable |
dis_pipe_tx |
hssi_pipe_gen1_2_txswing |
dis_txswing |
hssi_pipe_gen1_2_silicon_rev |
20nm5es |
hssi_pipe_gen1_2_reconfig_settings |
{} |
pma_adapt_silicon_rev |
20nm5es |
pma_adapt_adp_1s_ctle_bypass |
radp_1s_ctle_bypass_1 |
pma_adapt_adp_4s_ctle_bypass |
radp_4s_ctle_bypass_1 |
pma_adapt_adp_ctle_acgain_4s |
radp_ctle_acgain_4s_1 |
pma_adapt_adp_ctle_en |
radp_ctle_disable |
pma_adapt_adp_ctle_hold_en |
radp_ctle_not_held |
pma_adapt_adp_ctle_scale |
radp_ctle_scale_0 |
pma_adapt_adp_dfe_bw |
radp_dfe_bw_3 |
pma_adapt_adp_dfe_cycle |
radp_dfe_cycle_6 |
pma_adapt_adp_dfe_fltap_bypass |
radp_dfe_fltap_bypass_1 |
pma_adapt_adp_dfe_fltap_en |
radp_dfe_fltap_disable |
pma_adapt_adp_dfe_fltap_hold_en |
radp_dfe_fltap_not_held |
pma_adapt_adp_dfe_fltap_load |
radp_dfe_fltap_load_0 |
pma_adapt_adp_dfe_fltap_position |
radp_dfe_fltap_position_0 |
pma_adapt_adp_dfe_fxtap8 |
radp_dfe_fxtap8_0 |
pma_adapt_adp_dfe_fxtap8_sgn |
radp_dfe_fxtap8_sgn_0 |
pma_adapt_adp_dfe_fxtap9 |
radp_dfe_fxtap9_0 |
pma_adapt_adp_dfe_fxtap9_sgn |
radp_dfe_fxtap9_sgn_0 |
pma_adapt_adp_dfe_fxtap10 |
radp_dfe_fxtap10_0 |
pma_adapt_adp_dfe_fxtap10_sgn |
radp_dfe_fxtap10_sgn_0 |
pma_adapt_adp_dfe_fxtap11 |
radp_dfe_fxtap11_0 |
pma_adapt_adp_dfe_fxtap11_sgn |
radp_dfe_fxtap11_sgn_0 |
pma_adapt_adp_dfe_fxtap_bypass |
radp_dfe_fxtap_bypass_1 |
pma_adapt_adp_dfe_fxtap_en |
radp_dfe_fxtap_disable |
pma_adapt_adp_dfe_fxtap_hold_en |
radp_dfe_fxtap_not_held |
pma_adapt_adp_dfe_fxtap_load |
radp_dfe_fxtap_load_0 |
pma_adapt_adp_dfe_fxtap1 |
radp_dfe_fxtap1_0 |
pma_adapt_adp_dfe_fxtap2 |
radp_dfe_fxtap2_0 |
pma_adapt_adp_dfe_fxtap2_sgn |
radp_dfe_fxtap2_sgn_0 |
pma_adapt_adp_dfe_fxtap3 |
radp_dfe_fxtap3_0 |
pma_adapt_adp_dfe_fxtap3_sgn |
radp_dfe_fxtap3_sgn_0 |
pma_adapt_adp_dfe_fxtap4 |
radp_dfe_fxtap4_0 |
pma_adapt_adp_dfe_fxtap4_sgn |
radp_dfe_fxtap4_sgn_0 |
pma_adapt_adp_dfe_fxtap5 |
radp_dfe_fxtap5_0 |
pma_adapt_adp_dfe_fxtap5_sgn |
radp_dfe_fxtap5_sgn_0 |
pma_adapt_adp_dfe_fxtap6 |
radp_dfe_fxtap6_0 |
pma_adapt_adp_dfe_fxtap6_sgn |
radp_dfe_fxtap6_sgn_0 |
pma_adapt_adp_dfe_fxtap7 |
radp_dfe_fxtap7_0 |
pma_adapt_adp_dfe_fxtap7_sgn |
radp_dfe_fxtap7_sgn_0 |
pma_adapt_adp_dfe_mode |
radp_dfe_mode_4 |
pma_adapt_adp_dfe_vref_polarity |
radp_dfe_vref_polarity_0 |
pma_adapt_adp_force_freqlock |
radp_force_freqlock_off |
pma_adapt_adp_lfeq_fb_sel |
radp_lfeq_fb_sel_0 |
pma_adapt_adp_status_sel |
radp_status_sel_0 |
pma_adapt_adp_vga_bypass |
radp_vga_bypass_1 |
pma_adapt_adp_vga_en |
radp_vga_disable |
pma_adapt_adp_vga_polarity |
radp_vga_polarity_0 |
pma_adapt_adp_vga_sel |
radp_vga_sel_2 |
pma_adapt_adp_vga_sweep_direction |
radp_vga_sweep_direction_1 |
pma_adapt_adp_vga_threshold |
radp_vga_threshold_4 |
pma_adapt_adp_vref_bw |
radp_vref_bw_1 |
pma_adapt_adp_vref_bypass |
radp_vref_bypass_1 |
pma_adapt_adp_vref_cycle |
radp_vref_cycle_6 |
pma_adapt_adp_vref_en |
radp_vref_disable |
pma_adapt_adp_vref_hold_en |
radp_vref_not_held |
pma_adapt_adp_vref_polarity |
radp_vref_polarity_0 |
pma_adapt_adp_vref_sel |
radp_vref_sel_21 |
pma_adapt_adp_vref_vga_level |
radp_vref_vga_level_13 |
pma_adapt_datarate |
10312500000 bps |
pma_adapt_odi_en |
rodi_en_0 |
pma_adapt_odi_rstn |
rodi_rstn_0 |
pma_adapt_odi_spec_sel |
rodi_spec_sel_0 |
pma_adapt_odi_vref_sel |
rodi_vref_sel_0 |
pma_adapt_optimal |
true |
pma_adapt_initial_settings |
true |
pma_adapt_prot_mode |
basic_rx |
pma_adapt_sup_mode |
user_mode |
pma_adapt_adapt_dfe_control_sel |
r_adapt_dfe_control_sel_0 |
pma_adapt_adp_ctle_adapt_bw |
radp_ctle_adapt_bw_3 |
pma_adapt_adp_dfe_spec_sign |
radp_dfe_spec_sign_0 |
pma_adapt_adp_ctle_force_spec_sign |
radp_ctle_force_spec_sign_0 |
pma_adapt_odi_mode |
rodi_mode_0 |
pma_adapt_adp_ctle_threshold |
radp_ctle_threshold_0 |
pma_adapt_adp_ctle_window |
radp_ctle_window_0 |
pma_adapt_adp_ctle_threshold_en |
radp_ctle_threshold_en_0 |
pma_adapt_adp_ctle_spec_sign |
radp_ctle_spec_sign_0 |
pma_adapt_adp_odi_control_sel |
radp_odi_control_sel_0 |
pma_adapt_adp_spec_avg_window |
radp_spec_avg_window_4 |
pma_adapt_adp_ctle_adapt_cycle_window |
radp_ctle_adapt_cycle_window_7 |
pma_adapt_odi_dfe_spec_en |
rodi_dfe_spec_en_0 |
pma_adapt_adp_dfe_clkout_div_sel |
radp_dfe_clkout_div_sel_0 |
pma_adapt_adp_ctle_load_value |
radp_ctle_load_value_0 |
pma_adapt_rrx_pcie_eqz |
rrx_pcie_eqz_0 |
pma_adapt_adp_bist_mode |
radp_bist_mode_0 |
pma_adapt_adapt_dfe_sel |
r_adapt_dfe_sel_0 |
pma_adapt_adp_spec_trans_filter |
radp_spec_trans_filter_2 |
pma_adapt_adp_frame_en |
radp_frame_en_0 |
pma_adapt_odi_count_threshold |
rodi_count_threshold_0 |
pma_adapt_adp_bist_spec_en |
radp_bist_spec_en_0 |
pma_adapt_adapt_mode |
manual |
pma_adapt_adp_ctle_adapt_oneshot |
radp_ctle_adapt_oneshot_1 |
pma_adapt_adp_bist_auxpath_en |
radp_bist_auxpath_disable |
pma_adapt_adp_frame_out_sel |
radp_frame_out_sel_0 |
pma_adapt_adapt_vga_sel |
r_adapt_vga_sel_0 |
pma_adapt_adp_vref_load |
radp_vref_load_0 |
pma_adapt_adp_ctle_scale_en |
radp_ctle_scale_en_0 |
pma_adapt_adp_onetime_dfe |
radp_onetime_dfe_0 |
pma_adapt_adp_dfe_force_spec_sign |
radp_dfe_force_spec_sign_0 |
pma_adapt_adp_frame_odi_sel |
radp_frame_odi_sel_0 |
pma_adapt_adp_bist_datapath_en |
radp_bist_datapath_disable |
pma_adapt_adp_control_mux_bypass |
radp_control_mux_bypass_0 |
pma_adapt_adp_ctle_vref_polarity |
radp_ctle_vref_polarity_0 |
pma_adapt_adp_bist_count_rstn |
radp_bist_count_rstn_0 |
pma_adapt_adp_ctle_eqz_1s_sel |
radp_ctle_eqz_1s_sel_3 |
pma_adapt_adp_vref_dfe_spec_en |
radp_vref_dfe_spec_en_0 |
pma_adapt_adp_adapt_rstn |
radp_adapt_rstn_1 |
pma_adapt_adp_adapt_start |
radp_adapt_start_0 |
pma_adapt_odi_start |
rodi_start_0 |
pma_adapt_adp_ctle_sweep_direction |
radp_ctle_sweep_direction_1 |
pma_adapt_adp_vga_load |
radp_vga_load_0 |
pma_adapt_adp_frame_capture |
radp_frame_capture_0 |
pma_adapt_adp_adapt_control_sel |
radp_adapt_control_sel_0 |
pma_adapt_adp_bist_odi_dfe_sel |
radp_bist_odi_dfe_sel_0 |
pma_adapt_adapt_vref_sel |
r_adapt_vref_sel_0 |
pma_adapt_adp_mode |
radp_mode_8 |
pma_adapt_adp_ctle_load |
radp_ctle_load_0 |
pma_cdr_refclk_cdr_clkin_scratch0_src |
cdr_clkin_scratch0_src_refclk_iqclk |
pma_cdr_refclk_cdr_clkin_scratch1_src |
cdr_clkin_scratch1_src_refclk_iqclk |
pma_cdr_refclk_cdr_clkin_scratch2_src |
cdr_clkin_scratch2_src_refclk_iqclk |
pma_cdr_refclk_cdr_clkin_scratch3_src |
cdr_clkin_scratch3_src_refclk_iqclk |
pma_cdr_refclk_cdr_clkin_scratch4_src |
cdr_clkin_scratch4_src_refclk_iqclk |
pma_cdr_refclk_powerdown_mode |
powerup |
pma_cdr_refclk_receiver_detect_src |
iqclk_src |
pma_cdr_refclk_xmux_refclk_src |
refclk_iqclk |
pma_cdr_refclk_xpm_iqref_mux_iqclk_sel |
power_down |
pma_cdr_refclk_xpm_iqref_mux_scratch0_src |
scratch0_power_down |
pma_cdr_refclk_xpm_iqref_mux_scratch1_src |
scratch1_power_down |
pma_cdr_refclk_xpm_iqref_mux_scratch2_src |
scratch2_power_down |
pma_cdr_refclk_xpm_iqref_mux_scratch3_src |
scratch3_power_down |
pma_cdr_refclk_xpm_iqref_mux_scratch4_src |
scratch4_power_down |
pma_cdr_refclk_refclk_select |
ref_iqclk0 |
pma_cdr_refclk_silicon_rev |
20nm5es |
pma_cdr_refclk_inclk0_logical_to_physical_mapping |
ref_iqclk0 |
pma_cdr_refclk_inclk1_logical_to_physical_mapping |
ref_iqclk0 |
pma_cdr_refclk_inclk2_logical_to_physical_mapping |
ref_iqclk0 |
pma_cdr_refclk_inclk3_logical_to_physical_mapping |
ref_iqclk0 |
pma_cdr_refclk_inclk4_logical_to_physical_mapping |
ref_iqclk0 |
pma_cgb_silicon_rev |
20nm5es |
pma_cgb_observe_cgb_clocks |
observe_nothing |
pma_cgb_bitslip_enable |
disable_bitslip |
pma_cgb_bonding_mode |
x1_non_bonded |
pma_cgb_bonding_reset_enable |
disallow_bonding_reset |
pma_cgb_cgb_power_down |
normal_cgb |
pma_cgb_datarate |
10312500000 bps |
pma_cgb_pcie_gen3_bitwidth |
pciegen3_wide |
pma_cgb_prot_mode |
basic_tx |
pma_cgb_scratch0_x1_clock_src |
unused |
pma_cgb_scratch1_x1_clock_src |
unused |
pma_cgb_scratch2_x1_clock_src |
unused |
pma_cgb_scratch3_x1_clock_src |
unused |
pma_cgb_select_done_master_or_slave |
choose_master_pcie_sw_done |
pma_cgb_ser_mode |
forty_bit |
pma_cgb_ser_powerdown |
normal_poweron_ser |
pma_cgb_sup_mode |
user_mode |
pma_cgb_vccdreg_output |
vccdreg_nominal |
pma_cgb_x1_clock_source_sel |
cdr_txpll_t |
pma_cgb_x1_div_m_sel |
divbypass |
pma_cgb_xn_clock_source_sel |
sel_xn_up |
pma_cgb_input_select_x1 |
fpll_bot |
pma_cgb_input_select_gen3 |
unused |
pma_cgb_input_select_xn |
unused |
pma_cgb_tx_ucontrol_reset |
disable |
pma_cgb_tx_ucontrol_en |
disable |
pma_cgb_initial_settings |
true |
pma_cgb_tx_ucontrol_pcie |
gen1 |
pma_cgb_dprio_cgb_vreg_boost |
no_voltage_boost |
pma_rx_dfe_silicon_rev |
20nm5es |
pma_rx_dfe_atb_select |
atb_disable |
pma_rx_dfe_datarate |
10312500000 bps |
pma_rx_dfe_dft_en |
dft_disable |
pma_rx_dfe_oc_sa_c270 |
0 |
pma_rx_dfe_oc_sa_c90 |
0 |
pma_rx_dfe_oc_sa_d0c0 |
0 |
pma_rx_dfe_oc_sa_d0c180 |
0 |
pma_rx_dfe_oc_sa_d1c0 |
0 |
pma_rx_dfe_oc_sa_d1c180 |
0 |
pma_rx_dfe_optimal |
true |
pma_rx_dfe_pdb |
dfe_enable |
pma_rx_dfe_pdb_fixedtap |
fixtap_dfe_powerdown |
pma_rx_dfe_pdb_floattap |
floattap_dfe_powerdown |
pma_rx_dfe_pdb_fxtap4t7 |
fxtap4t7_powerdown |
pma_rx_dfe_power_mode |
high_perf |
pma_rx_dfe_sel_fltapstep_dec |
fltap_step_no_dec |
pma_rx_dfe_sel_fltapstep_inc |
fltap_step_no_inc |
pma_rx_dfe_sel_fxtapstep_dec |
fxtap_step_no_dec |
pma_rx_dfe_sel_fxtapstep_inc |
fxtap_step_no_inc |
pma_rx_dfe_sel_oc_en |
off_canc_disable |
pma_rx_dfe_sel_probe_tstmx |
probe_tstmx_none |
pma_rx_dfe_sup_mode |
user_mode |
pma_rx_dfe_uc_rx_dfe_cal |
uc_rx_dfe_cal_off |
pma_rx_dfe_uc_rx_dfe_cal_status |
uc_rx_dfe_cal_notdone |
pma_rx_dfe_oc_sa_adp1 |
0 |
pma_rx_dfe_oc_sa_adp2 |
0 |
pma_rx_dfe_initial_settings |
true |
pma_rx_dfe_prot_mode |
basic_rx |
pma_rx_odi_silicon_rev |
20nm5es |
pma_rx_odi_datarate |
10312500000 bps |
pma_rx_odi_enable_odi |
power_down_eye |
pma_rx_odi_monitor_bw_sel |
bw_1 |
pma_rx_odi_optimal |
true |
pma_rx_odi_phase_steps_64_vs_128 |
phase_steps_64 |
pma_rx_odi_phase_steps_sel |
step40 |
pma_rx_odi_power_mode |
high_perf |
pma_rx_odi_sup_mode |
user_mode |
pma_rx_odi_v_vert_threshold_scaling |
scale_3 |
pma_rx_odi_vert_threshold |
vert_0 |
pma_rx_odi_oc_sa_c0 |
0 |
pma_rx_odi_initial_settings |
true |
pma_rx_odi_v_vert_sel |
plus |
pma_rx_odi_sel_oc_en |
off_canc_disable |
pma_rx_odi_clk_dcd_bypass |
no_bypass |
pma_rx_odi_invert_dfe_vref |
no_inversion |
pma_rx_odi_step_ctrl_sel |
dprio_mode |
pma_rx_odi_prot_mode |
basic_rx |
pma_rx_odi_oc_sa_c180 |
0 |
pma_rx_buf_silicon_rev |
20nm5es |
pma_rx_buf_bypass_eqz_stages_234 |
bypass_off |
pma_rx_buf_cdrclk_to_cgb |
cdrclk_2cgb_dis |
pma_rx_buf_datarate |
10312500000 bps |
pma_rx_buf_diag_lp_en |
dlp_off |
pma_rx_buf_eq_bw_sel |
eq_bw_3 |
pma_rx_buf_input_vcm_sel |
high_vcm |
pma_rx_buf_link_rx |
sr |
pma_rx_buf_offset_cal_pd |
eqz1_en |
pma_rx_buf_offset_cancellation_ctrl |
volt_0mv |
pma_rx_buf_offset_pd |
oc_en |
pma_rx_buf_optimal |
true |
pma_rx_buf_pdb_rx |
normal_rx_on |
pma_rx_buf_power_mode_rx |
high_perf |
pma_rx_buf_prot_mode |
basic_rx |
pma_rx_buf_qpi_enable |
non_qpi_mode |
pma_rx_buf_rx_atb_select |
atb_disable |
pma_rx_buf_rx_refclk_divider |
bypass_divider |
pma_rx_buf_rx_sel_bias_source |
bias_vcmdrv |
pma_rx_buf_sup_mode |
user_mode |
pma_rx_buf_term_sel |
r_r1 |
pma_rx_buf_vccela_supply_voltage |
vccela_1p1v |
pma_rx_buf_vcm_current_add |
vcm_current_default |
pma_rx_buf_vcm_sel |
vcm_setting_02 |
pma_rx_buf_eq_dc_gain_trim |
stg2_gain7 |
pma_rx_buf_offset_cancellation_coarse |
coarse_setting_00 |
pma_rx_buf_bodybias_select |
bodybias_sel1 |
pma_rx_buf_bodybias_enable |
bodybias_en |
pma_rx_buf_offset_cancellation_fine |
fine_setting_00 |
pma_rx_buf_act_isource_disable |
isrc_en |
pma_rx_buf_one_stage_enable |
s1_mode |
pma_rx_buf_loopback_modes |
lpbk_disable |
pma_rx_buf_lfeq_zero_control |
lfeq_setting_2 |
pma_rx_buf_initial_settings |
true |
pma_rx_buf_lfeq_enable |
non_lfeq_mode |
pma_rx_buf_term_tri_enable |
disable_tri |
pma_rx_buf_vga_bandwidth_select |
vga_bw_1 |
pma_rx_buf_refclk_en |
disable |
pma_rx_buf_cgm_bias_disable |
cgmbias_en |
pma_rx_buf_pm_tx_rx_pcie_gen |
non_pcie |
pma_rx_buf_pm_tx_rx_pcie_gen_bitwidth |
pcie_gen3_32b |
pma_rx_buf_pm_tx_rx_cvp_mode |
cvp_off |
pma_rx_buf_pm_tx_rx_testmux_select |
setting0 |
pma_rx_buf_xrx_path_jtag_hys |
hys_increase_disable |
pma_rx_buf_xrx_path_jtag_lp |
lp_off |
pma_rx_buf_xrx_path_uc_rx_rstb |
rx_reset_on |
pma_rx_buf_xrx_path_uc_pcie_sw |
uc_pcie_gen1 |
pma_rx_buf_xrx_path_uc_cal_enable |
rx_cal_off |
pma_rx_buf_xrx_path_uc_cru_rstb |
cdr_lf_reset_off |
pma_rx_buf_xrx_path_sup_mode |
user_mode |
pma_rx_buf_power_rail_er |
1120 |
pma_rx_buf_power_rail_eht |
0 |
pma_rx_buf_xrx_path_gt_enabled |
disable |
pma_rx_buf_xrx_path_analog_mode |
user_custom |
pma_rx_buf_xrx_path_prot_mode |
basic_rx |
pma_rx_buf_pm_speed_grade |
e3 |
pma_rx_buf_power_mode |
high_perf |
pma_rx_buf_iostandard |
hssi_diffio |
pma_rx_buf_xrx_path_datarate |
10312500000 bps |
pma_rx_buf_xrx_path_datawidth |
40 |
pma_rx_buf_xrx_path_pma_rx_divclk_hz |
257812500 |
pma_rx_buf_xrx_path_optimal |
true |
pma_rx_buf_link |
sr |
pma_rx_buf_xrx_path_initial_settings |
true |
pma_rx_buf_rx_vga_oc_en |
vga_cal_off |
pma_rx_sd_silicon_rev |
20nm5es |
pma_rx_sd_link |
sr |
pma_rx_sd_optimal |
true |
pma_rx_sd_power_mode |
high_perf |
pma_rx_sd_prot_mode |
basic_rx |
pma_rx_sd_sd_output_off |
1 |
pma_rx_sd_sd_output_on |
15 |
pma_rx_sd_sd_pdb |
sd_off |
pma_rx_sd_sd_threshold |
sdlv_3 |
pma_rx_sd_sup_mode |
user_mode |
pma_tx_ser_silicon_rev |
20nm5es |
pma_tx_ser_clk_divtx_deskew |
deskew_delay8 |
pma_tx_ser_control_clk_divtx |
no_dft_control_clkdivtx |
pma_tx_ser_duty_cycle_correction_mode_ctrl |
dcc_disable |
pma_tx_ser_ser_clk_divtx_user_sel |
divtx_user_off |
pma_tx_ser_ser_clk_mon |
disable_clk_mon |
pma_tx_ser_ser_powerdown |
normal_poweron_ser |
pma_tx_ser_sup_mode |
user_mode |
pma_tx_ser_initial_settings |
true |
pma_tx_ser_prot_mode |
basic_tx |
pma_tx_ser_bonding_mode |
x1_non_bonded |
pma_tx_buf_silicon_rev |
20nm5es |
pma_tx_buf_datarate |
10312500000 bps |
pma_tx_buf_dft_sel |
dft_disabled |
pma_tx_buf_duty_cycle_correction_bandwidth |
dcc_bw_12 |
pma_tx_buf_duty_cycle_correction_mode_ctrl |
dcc_disable |
pma_tx_buf_duty_cycle_input_polarity |
dcc_input_pos |
pma_tx_buf_duty_cycle_setting |
dcc_t32 |
pma_tx_buf_duty_cycle_setting_aux |
dcc2_t32 |
pma_tx_buf_jtag_drv_sel |
drv1 |
pma_tx_buf_jtag_lp |
lp_off |
pma_tx_buf_link_tx |
sr |
pma_tx_buf_lst |
atb_disabled |
pma_tx_buf_optimal |
true |
pma_tx_buf_pre_emp_sign_1st_post_tap |
fir_post_1t_neg |
pma_tx_buf_pre_emp_sign_2nd_post_tap |
fir_post_2t_neg |
pma_tx_buf_pre_emp_sign_pre_tap_1t |
fir_pre_1t_neg |
pma_tx_buf_pre_emp_sign_pre_tap_2t |
fir_pre_2t_neg |
pma_tx_buf_pre_emp_switching_ctrl_1st_post_tap |
0 |
pma_tx_buf_pre_emp_switching_ctrl_2nd_post_tap |
0 |
pma_tx_buf_pre_emp_switching_ctrl_pre_tap_1t |
0 |
pma_tx_buf_pre_emp_switching_ctrl_pre_tap_2t |
0 |
pma_tx_buf_prot_mode |
basic_tx |
pma_tx_buf_rx_det |
mode_0 |
pma_tx_buf_rx_det_output_sel |
rx_det_pcie_out |
pma_tx_buf_rx_det_pdb |
rx_det_off |
pma_tx_buf_slew_rate_ctrl |
slew_r5 |
pma_tx_buf_sup_mode |
user_mode |
pma_tx_buf_term_code |
rterm_code7 |
pma_tx_buf_term_sel |
r_r1 |
pma_tx_buf_tx_powerdown |
normal_tx_on |
pma_tx_buf_user_fir_coeff_ctrl_sel |
ram_ctl |
pma_tx_buf_vod_output_swing_ctrl |
31 |
pma_tx_buf_initial_settings |
true |
pma_tx_buf_duty_cycle_correction_reference2 |
dcc_ref2_3 |
pma_tx_buf_ser_powerdown |
normal_ser_on |
pma_tx_buf_swing_level |
lv |
pma_tx_buf_vreg_output |
vccdreg_nominal |
pma_tx_buf_duty_cycle_correction_reference1 |
dcc_ref1_3 |
pma_tx_buf_duty_cycle_correction_reset_n |
reset_n |
pma_tx_buf_res_cal_local |
non_local |
pma_tx_buf_term_n_tune |
rterm_n0 |
pma_tx_buf_cpen_ctrl |
cp_l0 |
pma_tx_buf_term_p_tune |
rterm_p0 |
pma_tx_buf_calibration_en |
false |
pma_tx_buf_low_power_en |
disable |
pma_tx_buf_compensation_en |
enable |
pma_tx_buf_dcd_detection_en |
enable |
pma_tx_buf_uc_txvod_cal |
uc_tx_vod_cal_off |
pma_tx_buf_uc_txvod_cal_cont |
uc_tx_vod_cal_cont_off |
pma_tx_buf_uc_skew_cal |
uc_skew_cal_off |
pma_tx_buf_uc_dcd_cal |
uc_dcd_cal_off |
pma_tx_buf_uc_txvod_cal_status |
uc_tx_vod_cal_notdone |
pma_tx_buf_uc_skew_cal_status |
uc_skew_cal_notdone |
pma_tx_buf_uc_dcd_cal_status |
uc_dcd_cal_notdone |
pma_tx_buf_uc_gen3 |
gen3_off |
pma_tx_buf_uc_gen4 |
gen4_off |
pma_tx_buf_uc_vcc_setting |
vcc_setting2 |
pma_tx_buf_mcgb_location_for_pcie |
0 |
pma_tx_buf_xtx_path_prot_mode |
basic_tx |
pma_tx_buf_xtx_path_optimal |
true |
pma_tx_buf_xtx_path_datarate |
10312500000 bps |
pma_tx_buf_xtx_path_datawidth |
40 |
pma_tx_buf_xtx_path_clock_divider_ratio |
1 |
pma_tx_buf_xtx_path_pma_tx_divclk_hz |
257812500 |
pma_tx_buf_xtx_path_tx_pll_clk_hz |
5156250000 |
pma_tx_buf_link |
sr |
pma_tx_buf_xtx_path_swing_level |
lv |
pma_tx_buf_xtx_path_sup_mode |
user_mode |
pma_tx_buf_xtx_path_initial_settings |
true |
pma_tx_buf_xtx_path_calibration_en |
false |
pma_tx_buf_xtx_path_bonding_mode |
x1_non_bonded |
pma_tx_buf_pm_speed_grade |
e3 |
pma_tx_buf_power_mode |
high_perf |
pma_tx_buf_power_rail_et |
1120 |
pma_tx_buf_power_rail_eht |
0 |
pma_tx_buf_xtx_path_gt_enabled |
disable |
pma_tx_buf_xtx_path_analog_mode |
user_custom |
pma_tx_buf_compensation_driver_en |
disable |
pma_tx_buf_sense_amp_offset_cal_curr_p |
0 |
pma_tx_buf_chgpmp_current_dn_trim |
cp_current_trimming_dn_setting0 |
pma_tx_buf_duty_cycle_correction_bandwidth_dn |
dcd_bw_dn_0 |
pma_tx_buf_sense_amp_offset_cal_curr_n |
sa_os_cal_in_0 |
pma_tx_buf_chgpmp_current_up_trim |
cp_current_trimming_up_setting0 |
pma_tx_buf_chgpmp_up_trim_double |
normal_up_trim_current |
pma_tx_buf_duty_cycle_cp_comp_en |
cp_comp_off |
pma_tx_buf_dcd_clk_div_ctrl |
dcd_ck_div128 |
pma_tx_buf_duty_cycle_detector_sa_cal |
dcd_sa_cal_disable |
pma_tx_buf_duty_cycle_detector_cp_cal |
dcd_cp_cal_disable |
pma_tx_buf_tri_driver |
tri_driver_disable |
pma_tx_buf_cdr_cp_calibration_en |
cdr_cp_cal_disable |
pma_tx_buf_chgpmp_dn_trim_double |
normal_dn_trim_current |
pma_tx_buf_calibration_resistor_value |
res_setting0 |
cdr_pll_silicon_rev |
20nm5es |
cdr_pll_pma_width |
40 |
cdr_pll_cgb_div |
1 |
cdr_pll_is_cascaded_pll |
false |
cdr_pll_bandwidth_range_high |
0 hz |
cdr_pll_bandwidth_range_low |
0 hz |
cdr_pll_datarate |
10312500000 bps |
cdr_pll_f_max_pfd |
350000000 Hz |
cdr_pll_f_max_ref |
800000000 Hz |
cdr_pll_f_max_vco |
9800000000 Hz |
cdr_pll_f_min_gt_channel |
8700000000 Hz |
cdr_pll_f_min_pfd |
50000000 Hz |
cdr_pll_f_min_ref |
50000000 Hz |
cdr_pll_f_min_vco |
4900000000 Hz |
cdr_pll_lpd_counter |
1 |
cdr_pll_lpfd_counter |
1 |
cdr_pll_n_counter_scratch |
2 |
cdr_pll_output_clock_frequency |
5156250000 Hz |
cdr_pll_reference_clock_frequency |
644531250 hz |
cdr_pll_set_cdr_vco_speed |
3 |
cdr_pll_set_cdr_vco_speed_fix |
60 |
cdr_pll_vco_freq |
5156250000 Hz |
cdr_pll_atb_select_control |
atb_off |
cdr_pll_auto_reset_on |
auto_reset_off |
cdr_pll_bbpd_data_pattern_filter_select |
bbpd_data_pat_off |
cdr_pll_bw_sel |
medium |
cdr_pll_cdr_odi_select |
sel_cdr |
cdr_pll_cdr_phaselock_mode |
no_ignore_lock |
cdr_pll_cdr_powerdown_mode |
power_up |
cdr_pll_chgpmp_current_pd |
cp_current_pd_setting0 |
cdr_pll_chgpmp_current_pfd |
cp_current_pfd_setting2 |
cdr_pll_chgpmp_replicate |
false |
cdr_pll_chgpmp_testmode |
cp_test_disable |
cdr_pll_clklow_mux_select |
clklow_mux_cdr_fbclk |
cdr_pll_diag_loopback_enable |
false |
cdr_pll_disable_up_dn |
true |
cdr_pll_fref_clklow_div |
2 |
cdr_pll_fref_mux_select |
fref_mux_cdr_refclk |
cdr_pll_gpon_lck2ref_control |
gpon_lck2ref_off |
cdr_pll_initial_settings |
true |
cdr_pll_lck2ref_delay_control |
lck2ref_delay_2 |
cdr_pll_lf_resistor_pd |
lf_pd_setting2 |
cdr_pll_lf_resistor_pfd |
lf_pfd_setting2 |
cdr_pll_lf_ripple_cap |
lf_no_ripple |
cdr_pll_loop_filter_bias_select |
lpflt_bias_7 |
cdr_pll_loopback_mode |
loopback_disabled |
cdr_pll_ltd_ltr_micro_controller_select |
ltd_ltr_pcs |
cdr_pll_m_counter |
16 |
cdr_pll_n_counter |
2 |
cdr_pll_optimal |
true |
cdr_pll_pd_fastlock_mode |
false |
cdr_pll_pd_l_counter |
1 |
cdr_pll_pfd_l_counter |
1 |
cdr_pll_position |
position_unknown |
cdr_pll_power_mode |
high_perf |
cdr_pll_primary_use |
cdr |
cdr_pll_prot_mode |
basic_rx |
cdr_pll_requires_gt_capable_channel |
false |
cdr_pll_reverse_serial_loopback |
no_loopback |
cdr_pll_set_cdr_v2i_enable |
true |
cdr_pll_set_cdr_vco_reset |
false |
cdr_pll_set_cdr_vco_speed_pciegen3 |
cdr_vco_max_speedbin_pciegen3 |
cdr_pll_side |
side_unknown |
cdr_pll_pm_speed_grade |
e3 |
cdr_pll_sup_mode |
user_mode |
cdr_pll_top_or_bottom |
tb_unknown |
cdr_pll_tx_pll_prot_mode |
txpll_unused |
cdr_pll_txpll_hclk_driver_enable |
false |
cdr_pll_vco_overrange_voltage |
vco_overrange_off |
cdr_pll_vco_underrange_voltage |
vco_underange_off |
cdr_pll_fb_select |
direct_fb |
cdr_pll_uc_ro_cal |
uc_ro_cal_on |
cdr_pll_uc_ro_cal_status |
uc_ro_cal_notdone |
cdr_pll_iqclk_mux_sel |
power_down |
cdr_pll_uc_cru_rstb |
cdr_lf_reset_off |
cdr_pll_pcie_gen |
non_pcie |
cdr_pll_analog_mode |
user_custom |
cdr_pll_f_max_m_counter |
1 |
cdr_pll_chgpmp_vccreg |
vreg_fw0 |
cdr_pll_set_cdr_input_freq_range |
0 |
cdr_pll_chgpmp_current_dn_trim |
cp_current_trimming_dn_setting0 |
cdr_pll_chgpmp_up_pd_trim_double |
normal_up_trim_current |
cdr_pll_chgpmp_current_up_pd |
cp_current_pd_up_setting3 |
cdr_pll_f_max_cmu_out_freq |
1 |
cdr_pll_chgpmp_current_up_trim |
cp_current_trimming_up_setting0 |
cdr_pll_chgpmp_dn_pd_trim_double |
normal_dn_trim_current |
cdr_pll_cal_vco_count_length |
sel_8b_count |
cdr_pll_chgpmp_current_dn_pd |
cp_current_pd_dn_setting3 |
cdr_pll_enable_idle_rx_channel_support |
false |
pma_rx_deser_silicon_rev |
20nm5es |
pma_rx_deser_clkdiv_source |
vco_bypass_normal |
pma_rx_deser_clkdivrx_user_mode |
clkdivrx_user_disabled |
pma_rx_deser_datarate |
10312500000 bps |
pma_rx_deser_deser_factor |
40 |
pma_rx_deser_deser_powerdown |
deser_power_up |
pma_rx_deser_force_adaptation_outputs |
normal_outputs |
pma_rx_deser_force_clkdiv_for_testing |
normal_clkdiv |
pma_rx_deser_optimal |
true |
pma_rx_deser_sdclk_enable |
false |
pma_rx_deser_sup_mode |
user_mode |
pma_rx_deser_rst_n_adapt_odi |
no_rst_adapt_odi |
pma_rx_deser_bitslip_bypass |
bs_bypass_yes |
pma_rx_deser_prot_mode |
basic_rx |
pma_rx_deser_pcie_gen |
non_pcie |
pma_rx_deser_pcie_gen_bitwidth |
pcie_gen3_32b |
pma_rx_deser_tdr_mode |
select_bbpd_data |
data_rate_bps |
10312500000 bps |
l_protocol_mode |
basic_enh |
pcs_speedgrade |
e3 |
pma_speedgrade |
e3 |
rapid_validate |
0 |
rapid_invalid_parameters_cache |
|
rapid_non_derived_parameters_cache |
device_family,value {Arria 10} allowed_ranges {} full_validation 1,device,value 10AX115N3F45E2SGE3 allowed_ranges {} full_validation 1,base_device,value NIGHTFURY5 allowed_ranges {} full_validation 1,design_environment,value NATIVE allowed_ranges {} full_validation 1,message_level,value error allowed_ranges {error warning} full_validation 0,anlg_voltage,value 1_1V allowed_ranges {1_1V 1_0V 0_9V} full_validation 0,anlg_link,value sr allowed_ranges {sr lr} full_validation 0,support_mode,value user_mode allowed_ranges {user_mode engineering_mode} full_validation 0,protocol_mode,value basic_enh allowed_ranges {{basic_std:Basic/Custom (Standard PCS)} {basic_std_rm:Basic/Custom w/Rate Match (Standard PCS)} {cpri:CPRI (Auto)} {cpri_rx_tx:CPRI (Manual)} gige:GbE {gige_1588:GbE 1588} {pipe_g1:Gen 1 PIPE} {pipe_g2:Gen 2 PIPE} {pipe_g3:Gen 3 PIPE} {basic_enh:Basic (Enhanced PCS)} interlaken_mode:Interlaken teng_baser_mode:10GBASE-R {teng_1588_mode:10GBASE-R 1588} {teng_baser_krfec_mode:10GBASE-R w/KR FEC} {fortyg_basekr_krfec_mode:40GBASE-R w/KR FEC} {basic_krfec_mode:Basic w/KR FEC} {pcs_direct:PCS Direct}} full_validation 0,pma_mode,value basic allowed_ranges {basic SATA:SATA/SAS QPI GPON} full_validation 0,duplex_mode,value duplex allowed_ranges {{duplex:TX/RX Duplex} {tx:TX Simplex} {rx:RX Simplex}} full_validation 0,channels,value 4 allowed_ranges 1:96 full_validation 0,set_data_rate,value 10312.5 allowed_ranges {} full_validation 0,rcfg_iface_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_simple_interface,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,enable_split_interface,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,set_enable_calibration,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,set_disconnect_analog_resets,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_transparent_pcs,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_parallel_loopback,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,bonded_mode,value not_bonded allowed_ranges {{not_bonded:Not bonded} {pma_only:PMA only bonding} {pma_pcs:PMA and PCS bonding}} full_validation 0,set_pcs_bonding_master,value Auto allowed_ranges {Auto 0 1 2 3} full_validation 0,tx_pma_clk_div,value 1 allowed_ranges {1 2 4 8} full_validation 0,plls,value 1 allowed_ranges {1 2 3 4} full_validation 0,pll_select,value 0 allowed_ranges 0 full_validation 0,enable_port_tx_analog_reset_ack,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_pma_clkout,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_pma_div_clkout,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,tx_pma_div_clkout_divider,value 0 allowed_ranges {0:Disabled 1 2 33 40 66} full_validation 0,enable_port_tx_pma_iqtxrx_clkout,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_pma_elecidle,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_pma_qpipullup,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_pma_qpipulldn,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_pma_txdetectrx,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_pma_rxfound,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_seriallpbken_tx,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,number_physical_bonding_clocks,value 1 allowed_ranges {1 2 3 4} full_validation 0,cdr_refclk_cnt,value 1 allowed_ranges {1 2 3 4 5} full_validation 0,cdr_refclk_select,value 0 allowed_ranges 0 full_validation 0,set_cdr_refclk_freq,value 644.531250 allowed_ranges {50.060680 50.551471 51.051980 51.562500 52.083333 52.614796 53.157216 53.710938 54.276316 54.853723 55.443548 56.046196 56.662088 57.291667 57.935393 58.593750 59.267241 59.956395 60.661765 61.383929 62.123494 62.881098 63.657407 64.453125 65.268987 66.105769 66.964286 67.845395 68.750000 69.679054 70.633562 71.614583 72.623239 73.660714 74.728261 75.827206 76.958955 78.125000 79.326923 80.566406 81.845238 83.165323 84.528689 85.937500 87.394068 88.900862 90.460526 92.075893 93.750000 95.486111 97.287736 99.158654 100.121359 101.102941 102.103960 103.125000 104.166667 105.229592 106.314433 107.421875 108.552632 109.707447 110.887097 112.092391 113.324176 114.583333 115.870787 117.187500 118.534483 119.912791 121.323529 122.767857 124.246988 125.762195 127.314815 128.906250 130.537975 132.211538 133.928571 135.690789 137.500000 139.358108 141.267123 143.229167 145.246479 147.321429 149.456522 151.654412 153.917910 156.250000 158.653846 161.132813 163.690476 166.330645 169.057377 171.875000 174.788136 177.801724 180.921053 184.151786 187.500000 190.972222 194.575472 198.317308 200.242718 202.205882 204.207921 206.250000 208.333333 210.459184 212.628866 214.843750 217.105263 219.414894 221.774194 224.184783 226.648352 229.166667 231.741573 234.375000 237.068966 239.825581 242.647059 245.535714 248.493976 251.524390 254.629630 257.812500 261.075949 264.423077 267.857143 271.381579 275.000000 278.716216 282.534247 286.458333 290.492958 294.642857 298.913043 303.308824 307.835821 312.500000 317.307692 322.265625 327.380952 332.661290 338.114754 343.750000 349.576271 355.603448 361.842105 368.303571 375.000000 381.944444 389.150943 396.634615 400.485437 404.411765 408.415842 412.500000 416.666667 420.918367 425.257732 429.687500 434.210526 438.829787 443.548387 448.369565 453.296703 458.333333 463.483146 468.750000 474.137931 479.651163 485.294118 491.071429 496.987952 503.048780 509.259259 515.625000 522.151899 528.846154 535.714286 542.763158 550.000000 557.432432 565.068493 572.916667 580.985915 589.285714 597.826087 606.617647 615.671642 625.000000 634.615385 644.531250 654.761905 665.322581 676.229508 687.500000 699.152542 711.206897 723.684211 736.607143 750.000000 763.888889 778.301887 793.269231} full_validation 0,rx_ppm_detect_threshold,value 1000 allowed_ranges {100 300 500 1000} full_validation 0,rx_pma_ctle_adaptation_mode,value manual allowed_ranges {manual one-time:triggered} full_validation 0,rx_pma_dfe_adaptation_mode,value disabled allowed_ranges {continuous manual disabled} full_validation 0,rx_pma_dfe_fixed_taps,value 7 allowed_ranges {3 7 11} full_validation 0,enable_ports_adaptation,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_analog_reset_ack,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_pma_clkout,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_pma_div_clkout,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,rx_pma_div_clkout_divider,value 0 allowed_ranges {0:Disabled 1 2 33 40 66} full_validation 0,enable_port_rx_pma_iqtxrx_clkout,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_pma_clkslip,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_pma_qpipulldn,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_is_lockedtodata,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_is_lockedtoref,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,enable_ports_rx_manual_cdr_mode,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,enable_ports_rx_manual_ppm,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_signaldetect,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_seriallpbken,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,enable_ports_rx_prbs,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,std_pcs_pma_width,value 10 allowed_ranges {8 10 16 20} full_validation 0,std_low_latency_bypass_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_hip,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_skp_ports,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_hard_reset,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,set_hip_cal_en,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,std_tx_pcfifo_mode,value low_latency allowed_ranges {low_latency register_fifo fast_register} full_validation 0,std_rx_pcfifo_mode,value low_latency allowed_ranges {low_latency register_fifo} full_validation 0,enable_port_tx_std_pcfifo_full,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_std_pcfifo_empty,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_std_pcfifo_full,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_std_pcfifo_empty,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,std_tx_byte_ser_mode,value Disabled allowed_ranges {Disabled {Serialize x2} {Serialize x4}} full_validation 0,std_rx_byte_deser_mode,value Disabled allowed_ranges {Disabled {Deserialize x2} {Deserialize x4}} full_validation 0,std_tx_8b10b_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,std_tx_8b10b_disp_ctrl_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,std_rx_8b10b_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,std_rx_rmfifo_mode,value disabled allowed_ranges {disabled:Disabled {basic (single width):Basic 10-bit PMA} {basic (double width):Basic 20-bit PMA} gige:GbE pipe:PIPE {pipe 0ppm:PIPE 0ppm}} full_validation 0,std_rx_rmfifo_pattern_n,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,std_rx_rmfifo_pattern_p,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_std_rmfifo_full,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_std_rmfifo_empty,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,pcie_rate_match,value Bypass allowed_ranges {Bypass {0 ppm} {600 ppm}} full_validation 0,std_tx_bitslip_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_std_bitslipboundarysel,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,std_rx_word_aligner_mode,value bitslip allowed_ranges {bitslip {manual (PLD controlled):manual (FPGA Fabric controlled)} {synchronous state machine} {deterministic latency}} full_validation 0,std_rx_word_aligner_pattern_len,value 7 allowed_ranges {7 8 10 16 20 32 40} full_validation 0,std_rx_word_aligner_pattern,value 0 allowed_ranges {} full_validation 0,std_rx_word_aligner_rknumber,value 3 allowed_ranges 0:255 full_validation 0,std_rx_word_aligner_renumber,value 3 allowed_ranges 0:63 full_validation 0,std_rx_word_aligner_rgnumber,value 3 allowed_ranges 0:255 full_validation 0,std_rx_word_aligner_rvnumber,value 0 allowed_ranges 0:8191 full_validation 0,std_rx_word_aligner_fast_sync_status_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_std_wa_patternalign,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_std_wa_a1a2size,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_std_bitslipboundarysel,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_std_bitslip,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,std_tx_bitrev_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,std_tx_byterev_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,std_tx_polinv_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_polinv,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,std_rx_bitrev_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_std_bitrev_ena,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,std_rx_byterev_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_std_byterev_ena,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,std_rx_polinv_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_polinv,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_std_signaldetect,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_ports_pipe_sw,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_ports_pipe_hclk,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_ports_pipe_g3_analog,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_ports_pipe_rx_elecidle,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_pipe_rx_polarity,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_pcs_pma_width,value 40 allowed_ranges {32 40 64} full_validation 0,enh_pld_pcs_width,value 40 allowed_ranges {32 40 50 64 66 67} full_validation 0,enh_low_latency_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_rxtxfifo_double_width,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_txfifo_mode,value {Phase compensation} allowed_ranges {{Phase compensation} Register Interlaken Basic {Fast register}} full_validation 0,enh_txfifo_pfull,value 11 allowed_ranges 0:15 full_validation 0,enh_txfifo_pempty,value 2 allowed_ranges 0:15 full_validation 0,enable_port_tx_enh_fifo_full,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_enh_fifo_pfull,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_enh_fifo_empty,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_enh_fifo_pempty,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_enh_fifo_cnt,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_rxfifo_mode,value {Phase compensation} allowed_ranges {{Phase compensation} Register Interlaken 10GBase-R Basic} full_validation 0,enh_rxfifo_pfull,value 23 allowed_ranges 0:31 full_validation 0,enh_rxfifo_pempty,value 2 allowed_ranges 0:31 full_validation 0,enh_rxfifo_align_del,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_rxfifo_control_del,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_data_valid,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_fifo_full,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_fifo_pfull,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_fifo_empty,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_fifo_pempty,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_fifo_cnt,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_fifo_del,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_fifo_insert,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_fifo_rd_en,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_fifo_align_val,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_fifo_align_clr,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_tx_frmgen_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_tx_frmgen_mfrm_length,value 2048 allowed_ranges 0:8192 full_validation 0,enh_tx_frmgen_burst_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_enh_frame,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_enh_frame_diag_status,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_enh_frame_burst_en,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_rx_frmsync_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_rx_frmsync_mfrm_length,value 2048 allowed_ranges 0:8192 full_validation 0,enable_port_rx_enh_frame,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_frame_lock,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_frame_diag_status,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_tx_crcgen_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_tx_crcerr_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_rx_crcchk_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_crc32_err,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_highber,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_highber_clr_cnt,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_clr_errblk_count,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_tx_64b66b_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_rx_64b66b_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_tx_sh_err,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_tx_scram_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_tx_scram_seed,value 0 allowed_ranges {} full_validation 0,enh_rx_descram_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_tx_dispgen_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_rx_dispchk_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_tx_randomdispbit_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_rx_blksync_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_blk_lock,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_tx_bitslip_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_tx_polinv_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_rx_bitslip_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_rx_polinv_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_tx_enh_bitslip,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_rx_enh_bitslip,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_rx_krfec_err_mark_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_rx_krfec_err_mark_type,value 10G allowed_ranges {10G 40G} full_validation 0,enh_tx_krfec_burst_err_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enh_tx_krfec_burst_err_len,value 1 allowed_ranges 1:15 full_validation 0,enable_port_krfec_tx_enh_frame,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_krfec_rx_enh_frame,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,enable_port_krfec_rx_enh_frame_diag_status,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,pcs_direct_width,value 8 allowed_ranges {8 10 16 20 32 40 64} full_validation 0,generate_docs,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,generate_add_hdl_instance_example,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,validation_rule_select,value {} allowed_ranges {} full_validation 0,rcfg_enable,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,rcfg_shared,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,rcfg_jtag_enable,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,rcfg_separate_avmm_busy,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,rcfg_enable_avmm_busy_port,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,set_embedded_debug_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,set_capability_reg_enable,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,set_user_identifier,value 0 allowed_ranges 0:255 full_validation 0,set_csr_soft_logic_enable,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,set_prbs_soft_logic_enable,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,set_odi_soft_logic_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,rcfg_file_prefix,value altera_xcvr_native_a10 allowed_ranges {} full_validation 0,rcfg_sv_file_enable,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,rcfg_h_file_enable,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,rcfg_mif_file_enable,value 1 allowed_ranges -2147483648:2147483647 full_validation 0,rcfg_multi_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,set_rcfg_emb_strm_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,rcfg_reduced_files_enable,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,rcfg_profile_cnt,value 2 allowed_ranges {1 2 3 4 5 6 7 8} full_validation 0,rcfg_profile_select,value 1 allowed_ranges {0 1} full_validation 0,rcfg_profile_data0,value {} allowed_ranges {} full_validation 0,rcfg_profile_data1,value {} allowed_ranges {} full_validation 0,rcfg_profile_data2,value {} allowed_ranges {} full_validation 0,rcfg_profile_data3,value {} allowed_ranges {} full_validation 0,rcfg_profile_data4,value {} allowed_ranges {} full_validation 0,rcfg_profile_data5,value {} allowed_ranges {} full_validation 0,rcfg_profile_data6,value {} allowed_ranges {} full_validation 0,rcfg_profile_data7,value {} allowed_ranges {} full_validation 0,enable_analog_settings,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,anlg_tx_analog_mode,value user_custom allowed_ranges {cei_11100_lr cei_11100_sr cei_12500_lr cei_12500_sr cei_19000_vsr cei_28000_vsr cei_4976_lr cei_4976_sr cei_6375_lr cei_6375_sr cei_9950_lr cei_9950_sr cpri_12500 cpri_e12hv cpri_e12lv cpri_e12lvii cpri_e12lviii cpri_e24lv cpri_e24lvii cpri_e24lviii cpri_e30lv cpri_e30lvii cpri_e30lviii cpri_e48lvii cpri_e48lviii cpri_e60lvii cpri_e60lviii cpri_e6hv cpri_e6lv cpri_e6lvii cpri_e6lviii cpri_e96lviii cpri_e99lviii dp_1620 dp_2700 dp_5400 fc_1600_df_ea_s fc_1600_df_el_s fc_400_df_ea_s fc_400_df_el_s fc_800_df_ea_s fc_800_df_el_s gige_1250 gpon_1244 gpon_155 gpon_2488 gpon_622 hdmi_3400 hdmi_6000 higig_3125 higig_3750 higig_4062 higig_5000 higig_6250 higig_6562 hmc_10000 hmc_12500 hmc_15000 ieee_1000_base_cx ieee_1000_base_kx ieee_100g_base_cr10_10312 ieee_10g_base_cr_10312 ieee_10g_base_cx4 ieee_10g_base_kx4 ieee_10g_kr_10312 ieee_40g_base_cr4_10312 ieee_40g_base_kr_10312 ieee_itut_10g_gpon_epon infiniband_ddr_5000 infiniband_fdr_14000 infiniband_qdr_10000 infiniband_sdr_2500 interlaken_11100 interlaken_12500 interlaken_25781 interlaken_3125 interlaken_6375 jesd204_a_b_12500 jesd204_a_b_312 jesd204_a_b_3125 jesd204_a_b_6375 nppi_10312 otu2_10709 pcie_cable qsgmii_5000 sas_12000 sas_1500 sas_3000 sas_6000 sata_1500 sata_3000 sata_6000 sdi_12000 sdi_1485_hd sdi_270_sd sdi_2970_3g sdi_6000 serial_lite_iii_16400 serial_lite_iii_17400 sff_8431 sfi_2488 sfi_3125 sfi_s_11200 sfi_s_6250 sonet_oc12_622 sonet_oc192_9953 sonet_oc48_2488 srio_10312_lr srio_10312_sr srio_1250_lr srio_1250_sr srio_2500_lr srio_2500_sr srio_3125_lr srio_3125_sr srio_5000_lr srio_5000_mr srio_5000_sr srio_6250_lr srio_6250_mr srio_6250_sr user_custom xaui_3125 xfp_10310 xfp_10520 xfp_10700 xfp_11320 xfp_12500 xfp_9950} full_validation 0,anlg_enable_tx_default_ovr,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,anlg_tx_vod_output_swing_ctrl,value 0 allowed_ranges 0:31 full_validation 0,anlg_tx_pre_emp_sign_pre_tap_1t,value fir_pre_1t_neg allowed_ranges {fir_pre_1t_neg fir_pre_1t_pos} full_validation 0,anlg_tx_pre_emp_switching_ctrl_pre_tap_1t,value 0 allowed_ranges 0:31 full_validation 0,anlg_tx_pre_emp_sign_pre_tap_2t,value fir_pre_2t_neg allowed_ranges {fir_pre_2t_neg fir_pre_2t_pos} full_validation 0,anlg_tx_pre_emp_switching_ctrl_pre_tap_2t,value 0 allowed_ranges 0:7 full_validation 0,anlg_tx_pre_emp_sign_1st_post_tap,value fir_post_1t_neg allowed_ranges {fir_post_1t_neg fir_post_1t_pos} full_validation 0,anlg_tx_pre_emp_switching_ctrl_1st_post_tap,value 0 allowed_ranges 0:63 full_validation 0,anlg_tx_pre_emp_sign_2nd_post_tap,value fir_post_2t_neg allowed_ranges {fir_post_2t_neg fir_post_2t_pos} full_validation 0,anlg_tx_pre_emp_switching_ctrl_2nd_post_tap,value 0 allowed_ranges 0:15 full_validation 0,anlg_tx_slew_rate_ctrl,value slew_r7 allowed_ranges {slew_r0 slew_r1 slew_r2 slew_r3 slew_r4 slew_r5 slew_r6 slew_r7} full_validation 0,anlg_tx_compensation_en,value enable allowed_ranges {disable enable} full_validation 0,anlg_tx_term_sel,value r_r1 allowed_ranges {r_r1 r_r2} full_validation 0,anlg_enable_rx_default_ovr,value 0 allowed_ranges -2147483648:2147483647 full_validation 0,anlg_rx_one_stage_enable,value s1_mode allowed_ranges {non_s1_mode s1_mode} full_validation 0,anlg_rx_eq_dc_gain_trim,value stg2_gain7 allowed_ranges {no_dc_gain stg1_gain1 stg1_gain2 stg1_gain3 stg1_gain4 stg1_gain5 stg1_gain6 stg1_gain7 stg2_gain1 stg2_gain2 stg2_gain3 stg2_gain4 stg2_gain5 stg2_gain6 stg2_gain7 stg3_gain1 stg3_gain2 stg3_gain3 stg3_gain4 stg3_gain5 stg3_gain6 stg3_gain7 stg4_gain1 stg4_gain2 stg4_gain3 stg4_gain4 stg4_gain5 stg4_gain6 stg4_gain7} full_validation 0,anlg_rx_adp_ctle_acgain_4s,value radp_ctle_acgain_4s_1 allowed_ranges {radp_ctle_acgain_4s_0 radp_ctle_acgain_4s_1 radp_ctle_acgain_4s_10 radp_ctle_acgain_4s_11 radp_ctle_acgain_4s_12 radp_ctle_acgain_4s_13 radp_ctle_acgain_4s_14 radp_ctle_acgain_4s_15 radp_ctle_acgain_4s_16 radp_ctle_acgain_4s_17 radp_ctle_acgain_4s_18 radp_ctle_acgain_4s_19 radp_ctle_acgain_4s_2 radp_ctle_acgain_4s_20 radp_ctle_acgain_4s_21 radp_ctle_acgain_4s_22 radp_ctle_acgain_4s_23 radp_ctle_acgain_4s_24 radp_ctle_acgain_4s_25 radp_ctle_acgain_4s_26 radp_ctle_acgain_4s_27 radp_ctle_acgain_4s_28 radp_ctle_acgain_4s_29 radp_ctle_acgain_4s_3 radp_ctle_acgain_4s_30 radp_ctle_acgain_4s_31 radp_ctle_acgain_4s_4 radp_ctle_acgain_4s_5 radp_ctle_acgain_4s_6 radp_ctle_acgain_4s_7 radp_ctle_acgain_4s_8 radp_ctle_acgain_4s_9} full_validation 0,anlg_rx_adp_ctle_eqz_1s_sel,value radp_ctle_eqz_1s_sel_3 allowed_ranges {radp_ctle_eqz_1s_sel_0 radp_ctle_eqz_1s_sel_1 radp_ctle_eqz_1s_sel_10 radp_ctle_eqz_1s_sel_11 radp_ctle_eqz_1s_sel_12 radp_ctle_eqz_1s_sel_13 radp_ctle_eqz_1s_sel_14 radp_ctle_eqz_1s_sel_15 radp_ctle_eqz_1s_sel_2 radp_ctle_eqz_1s_sel_3 radp_ctle_eqz_1s_sel_4 radp_ctle_eqz_1s_sel_5 radp_ctle_eqz_1s_sel_6 radp_ctle_eqz_1s_sel_7 radp_ctle_eqz_1s_sel_8 radp_ctle_eqz_1s_sel_9} full_validation 0,anlg_rx_adp_vga_sel,value radp_vga_sel_2 allowed_ranges {radp_vga_sel_0 radp_vga_sel_1 radp_vga_sel_2 radp_vga_sel_3 radp_vga_sel_4 radp_vga_sel_5 radp_vga_sel_6 radp_vga_sel_7} full_validation 0,anlg_rx_adp_dfe_fxtap1,value radp_dfe_fxtap1_0 allowed_ranges {radp_dfe_fxtap1_0 radp_dfe_fxtap1_1 radp_dfe_fxtap1_10 radp_dfe_fxtap1_100 radp_dfe_fxtap1_101 radp_dfe_fxtap1_102 radp_dfe_fxtap1_103 radp_dfe_fxtap1_104 radp_dfe_fxtap1_105 radp_dfe_fxtap1_106 radp_dfe_fxtap1_107 radp_dfe_fxtap1_108 radp_dfe_fxtap1_109 radp_dfe_fxtap1_11 radp_dfe_fxtap1_110 radp_dfe_fxtap1_111 radp_dfe_fxtap1_112 radp_dfe_fxtap1_113 radp_dfe_fxtap1_114 radp_dfe_fxtap1_115 radp_dfe_fxtap1_116 radp_dfe_fxtap1_117 radp_dfe_fxtap1_118 radp_dfe_fxtap1_119 radp_dfe_fxtap1_12 radp_dfe_fxtap1_120 radp_dfe_fxtap1_121 radp_dfe_fxtap1_122 radp_dfe_fxtap1_123 radp_dfe_fxtap1_124 radp_dfe_fxtap1_125 radp_dfe_fxtap1_126 radp_dfe_fxtap1_127 radp_dfe_fxtap1_13 radp_dfe_fxtap1_14 radp_dfe_fxtap1_15 radp_dfe_fxtap1_16 radp_dfe_fxtap1_17 radp_dfe_fxtap1_18 radp_dfe_fxtap1_19 radp_dfe_fxtap1_2 radp_dfe_fxtap1_20 radp_dfe_fxtap1_21 radp_dfe_fxtap1_22 radp_dfe_fxtap1_23 radp_dfe_fxtap1_24 radp_dfe_fxtap1_25 radp_dfe_fxtap1_26 radp_dfe_fxtap1_27 radp_dfe_fxtap1_28 radp_dfe_fxtap1_29 radp_dfe_fxtap1_3 radp_dfe_fxtap1_30 radp_dfe_fxtap1_31 radp_dfe_fxtap1_32 radp_dfe_fxtap1_33 radp_dfe_fxtap1_34 radp_dfe_fxtap1_35 radp_dfe_fxtap1_36 radp_dfe_fxtap1_37 radp_dfe_fxtap1_38 radp_dfe_fxtap1_39 radp_dfe_fxtap1_4 radp_dfe_fxtap1_40 radp_dfe_fxtap1_41 radp_dfe_fxtap1_42 radp_dfe_fxtap1_43 radp_dfe_fxtap1_44 radp_dfe_fxtap1_45 radp_dfe_fxtap1_46 radp_dfe_fxtap1_47 radp_dfe_fxtap1_48 radp_dfe_fxtap1_49 radp_dfe_fxtap1_5 radp_dfe_fxtap1_50 radp_dfe_fxtap1_51 radp_dfe_fxtap1_52 radp_dfe_fxtap1_53 radp_dfe_fxtap1_54 radp_dfe_fxtap1_55 radp_dfe_fxtap1_56 radp_dfe_fxtap1_57 radp_dfe_fxtap1_58 radp_dfe_fxtap1_59 radp_dfe_fxtap1_6 radp_dfe_fxtap1_60 radp_dfe_fxtap1_61 radp_dfe_fxtap1_62 radp_dfe_fxtap1_63 radp_dfe_fxtap1_64 radp_dfe_fxtap1_65 radp_dfe_fxtap1_66 radp_dfe_fxtap1_67 radp_dfe_fxtap1_68 radp_dfe_fxtap1_69 radp_dfe_fxtap1_7 radp_dfe_fxtap1_70 radp_dfe_fxtap1_71 radp_dfe_fxtap1_72 radp_dfe_fxtap1_73 radp_dfe_fxtap1_74 radp_dfe_fxtap1_75 radp_dfe_fxtap1_76 radp_dfe_fxtap1_77 radp_dfe_fxtap1_78 radp_dfe_fxtap1_79 radp_dfe_fxtap1_8 radp_dfe_fxtap1_80 radp_dfe_fxtap1_81 radp_dfe_fxtap1_82 radp_dfe_fxtap1_83 radp_dfe_fxtap1_84 radp_dfe_fxtap1_85 radp_dfe_fxtap1_86 radp_dfe_fxtap1_87 radp_dfe_fxtap1_88 radp_dfe_fxtap1_89 radp_dfe_fxtap1_9 radp_dfe_fxtap1_90 radp_dfe_fxtap1_91 radp_dfe_fxtap1_92 radp_dfe_fxtap1_93 radp_dfe_fxtap1_94 radp_dfe_fxtap1_95 radp_dfe_fxtap1_96 radp_dfe_fxtap1_97 radp_dfe_fxtap1_98 radp_dfe_fxtap1_99} full_validation 0,anlg_rx_adp_dfe_fxtap2,value radp_dfe_fxtap2_0 allowed_ranges {radp_dfe_fxtap2_0 radp_dfe_fxtap2_1 radp_dfe_fxtap2_10 radp_dfe_fxtap2_100 radp_dfe_fxtap2_101 radp_dfe_fxtap2_102 radp_dfe_fxtap2_103 radp_dfe_fxtap2_104 radp_dfe_fxtap2_105 radp_dfe_fxtap2_106 radp_dfe_fxtap2_107 radp_dfe_fxtap2_108 radp_dfe_fxtap2_109 radp_dfe_fxtap2_11 radp_dfe_fxtap2_110 radp_dfe_fxtap2_111 radp_dfe_fxtap2_112 radp_dfe_fxtap2_113 radp_dfe_fxtap2_114 radp_dfe_fxtap2_115 radp_dfe_fxtap2_116 radp_dfe_fxtap2_117 radp_dfe_fxtap2_118 radp_dfe_fxtap2_119 radp_dfe_fxtap2_12 radp_dfe_fxtap2_120 radp_dfe_fxtap2_121 radp_dfe_fxtap2_122 radp_dfe_fxtap2_123 radp_dfe_fxtap2_124 radp_dfe_fxtap2_125 radp_dfe_fxtap2_126 radp_dfe_fxtap2_127 radp_dfe_fxtap2_13 radp_dfe_fxtap2_14 radp_dfe_fxtap2_15 radp_dfe_fxtap2_16 radp_dfe_fxtap2_17 radp_dfe_fxtap2_18 radp_dfe_fxtap2_19 radp_dfe_fxtap2_2 radp_dfe_fxtap2_20 radp_dfe_fxtap2_21 radp_dfe_fxtap2_22 radp_dfe_fxtap2_23 radp_dfe_fxtap2_24 radp_dfe_fxtap2_25 radp_dfe_fxtap2_26 radp_dfe_fxtap2_27 radp_dfe_fxtap2_28 radp_dfe_fxtap2_29 radp_dfe_fxtap2_3 radp_dfe_fxtap2_30 radp_dfe_fxtap2_31 radp_dfe_fxtap2_32 radp_dfe_fxtap2_33 radp_dfe_fxtap2_34 radp_dfe_fxtap2_35 radp_dfe_fxtap2_36 radp_dfe_fxtap2_37 radp_dfe_fxtap2_38 radp_dfe_fxtap2_39 radp_dfe_fxtap2_4 radp_dfe_fxtap2_40 radp_dfe_fxtap2_41 radp_dfe_fxtap2_42 radp_dfe_fxtap2_43 radp_dfe_fxtap2_44 radp_dfe_fxtap2_45 radp_dfe_fxtap2_46 radp_dfe_fxtap2_47 radp_dfe_fxtap2_48 radp_dfe_fxtap2_49 radp_dfe_fxtap2_5 radp_dfe_fxtap2_50 radp_dfe_fxtap2_51 radp_dfe_fxtap2_52 radp_dfe_fxtap2_53 radp_dfe_fxtap2_54 radp_dfe_fxtap2_55 radp_dfe_fxtap2_56 radp_dfe_fxtap2_57 radp_dfe_fxtap2_58 radp_dfe_fxtap2_59 radp_dfe_fxtap2_6 radp_dfe_fxtap2_60 radp_dfe_fxtap2_61 radp_dfe_fxtap2_62 radp_dfe_fxtap2_63 radp_dfe_fxtap2_64 radp_dfe_fxtap2_65 radp_dfe_fxtap2_66 radp_dfe_fxtap2_67 radp_dfe_fxtap2_68 radp_dfe_fxtap2_69 radp_dfe_fxtap2_7 radp_dfe_fxtap2_70 radp_dfe_fxtap2_71 radp_dfe_fxtap2_72 radp_dfe_fxtap2_73 radp_dfe_fxtap2_74 radp_dfe_fxtap2_75 radp_dfe_fxtap2_76 radp_dfe_fxtap2_77 radp_dfe_fxtap2_78 radp_dfe_fxtap2_79 radp_dfe_fxtap2_8 radp_dfe_fxtap2_80 radp_dfe_fxtap2_81 radp_dfe_fxtap2_82 radp_dfe_fxtap2_83 radp_dfe_fxtap2_84 radp_dfe_fxtap2_85 radp_dfe_fxtap2_86 radp_dfe_fxtap2_87 radp_dfe_fxtap2_88 radp_dfe_fxtap2_89 radp_dfe_fxtap2_9 radp_dfe_fxtap2_90 radp_dfe_fxtap2_91 radp_dfe_fxtap2_92 radp_dfe_fxtap2_93 radp_dfe_fxtap2_94 radp_dfe_fxtap2_95 radp_dfe_fxtap2_96 radp_dfe_fxtap2_97 radp_dfe_fxtap2_98 radp_dfe_fxtap2_99} full_validation 0,anlg_rx_adp_dfe_fxtap3,value radp_dfe_fxtap3_0 allowed_ranges {radp_dfe_fxtap3_0 radp_dfe_fxtap3_1 radp_dfe_fxtap3_10 radp_dfe_fxtap3_100 radp_dfe_fxtap3_101 radp_dfe_fxtap3_102 radp_dfe_fxtap3_103 radp_dfe_fxtap3_104 radp_dfe_fxtap3_105 radp_dfe_fxtap3_106 radp_dfe_fxtap3_107 radp_dfe_fxtap3_108 radp_dfe_fxtap3_109 radp_dfe_fxtap3_11 radp_dfe_fxtap3_110 radp_dfe_fxtap3_111 radp_dfe_fxtap3_112 radp_dfe_fxtap3_113 radp_dfe_fxtap3_114 radp_dfe_fxtap3_115 radp_dfe_fxtap3_116 radp_dfe_fxtap3_117 radp_dfe_fxtap3_118 radp_dfe_fxtap3_119 radp_dfe_fxtap3_12 radp_dfe_fxtap3_120 radp_dfe_fxtap3_121 radp_dfe_fxtap3_122 radp_dfe_fxtap3_123 radp_dfe_fxtap3_124 radp_dfe_fxtap3_125 radp_dfe_fxtap3_126 radp_dfe_fxtap3_127 radp_dfe_fxtap3_13 radp_dfe_fxtap3_14 radp_dfe_fxtap3_15 radp_dfe_fxtap3_16 radp_dfe_fxtap3_17 radp_dfe_fxtap3_18 radp_dfe_fxtap3_19 radp_dfe_fxtap3_2 radp_dfe_fxtap3_20 radp_dfe_fxtap3_21 radp_dfe_fxtap3_22 radp_dfe_fxtap3_23 radp_dfe_fxtap3_24 radp_dfe_fxtap3_25 radp_dfe_fxtap3_26 radp_dfe_fxtap3_27 radp_dfe_fxtap3_28 radp_dfe_fxtap3_29 radp_dfe_fxtap3_3 radp_dfe_fxtap3_30 radp_dfe_fxtap3_31 radp_dfe_fxtap3_32 radp_dfe_fxtap3_33 radp_dfe_fxtap3_34 radp_dfe_fxtap3_35 radp_dfe_fxtap3_36 radp_dfe_fxtap3_37 radp_dfe_fxtap3_38 radp_dfe_fxtap3_39 radp_dfe_fxtap3_4 radp_dfe_fxtap3_40 radp_dfe_fxtap3_41 radp_dfe_fxtap3_42 radp_dfe_fxtap3_43 radp_dfe_fxtap3_44 radp_dfe_fxtap3_45 radp_dfe_fxtap3_46 radp_dfe_fxtap3_47 radp_dfe_fxtap3_48 radp_dfe_fxtap3_49 radp_dfe_fxtap3_5 radp_dfe_fxtap3_50 radp_dfe_fxtap3_51 radp_dfe_fxtap3_52 radp_dfe_fxtap3_53 radp_dfe_fxtap3_54 radp_dfe_fxtap3_55 radp_dfe_fxtap3_56 radp_dfe_fxtap3_57 radp_dfe_fxtap3_58 radp_dfe_fxtap3_59 radp_dfe_fxtap3_6 radp_dfe_fxtap3_60 radp_dfe_fxtap3_61 radp_dfe_fxtap3_62 radp_dfe_fxtap3_63 radp_dfe_fxtap3_64 radp_dfe_fxtap3_65 radp_dfe_fxtap3_66 radp_dfe_fxtap3_67 radp_dfe_fxtap3_68 radp_dfe_fxtap3_69 radp_dfe_fxtap3_7 radp_dfe_fxtap3_70 radp_dfe_fxtap3_71 radp_dfe_fxtap3_72 radp_dfe_fxtap3_73 radp_dfe_fxtap3_74 radp_dfe_fxtap3_75 radp_dfe_fxtap3_76 radp_dfe_fxtap3_77 radp_dfe_fxtap3_78 radp_dfe_fxtap3_79 radp_dfe_fxtap3_8 radp_dfe_fxtap3_80 radp_dfe_fxtap3_81 radp_dfe_fxtap3_82 radp_dfe_fxtap3_83 radp_dfe_fxtap3_84 radp_dfe_fxtap3_85 radp_dfe_fxtap3_86 radp_dfe_fxtap3_87 radp_dfe_fxtap3_88 radp_dfe_fxtap3_89 radp_dfe_fxtap3_9 radp_dfe_fxtap3_90 radp_dfe_fxtap3_91 radp_dfe_fxtap3_92 radp_dfe_fxtap3_93 radp_dfe_fxtap3_94 radp_dfe_fxtap3_95 radp_dfe_fxtap3_96 radp_dfe_fxtap3_97 radp_dfe_fxtap3_98 radp_dfe_fxtap3_99} full_validation 0,anlg_rx_adp_dfe_fxtap4,value radp_dfe_fxtap4_0 allowed_ranges {radp_dfe_fxtap4_0 radp_dfe_fxtap4_1 radp_dfe_fxtap4_10 radp_dfe_fxtap4_11 radp_dfe_fxtap4_12 radp_dfe_fxtap4_13 radp_dfe_fxtap4_14 radp_dfe_fxtap4_15 radp_dfe_fxtap4_16 radp_dfe_fxtap4_17 radp_dfe_fxtap4_18 radp_dfe_fxtap4_19 radp_dfe_fxtap4_2 radp_dfe_fxtap4_20 radp_dfe_fxtap4_21 radp_dfe_fxtap4_22 radp_dfe_fxtap4_23 radp_dfe_fxtap4_24 radp_dfe_fxtap4_25 radp_dfe_fxtap4_26 radp_dfe_fxtap4_27 radp_dfe_fxtap4_28 radp_dfe_fxtap4_29 radp_dfe_fxtap4_3 radp_dfe_fxtap4_30 radp_dfe_fxtap4_31 radp_dfe_fxtap4_32 radp_dfe_fxtap4_33 radp_dfe_fxtap4_34 radp_dfe_fxtap4_35 radp_dfe_fxtap4_36 radp_dfe_fxtap4_37 radp_dfe_fxtap4_38 radp_dfe_fxtap4_39 radp_dfe_fxtap4_4 radp_dfe_fxtap4_40 radp_dfe_fxtap4_41 radp_dfe_fxtap4_42 radp_dfe_fxtap4_43 radp_dfe_fxtap4_44 radp_dfe_fxtap4_45 radp_dfe_fxtap4_46 radp_dfe_fxtap4_47 radp_dfe_fxtap4_48 radp_dfe_fxtap4_49 radp_dfe_fxtap4_5 radp_dfe_fxtap4_50 radp_dfe_fxtap4_51 radp_dfe_fxtap4_52 radp_dfe_fxtap4_53 radp_dfe_fxtap4_54 radp_dfe_fxtap4_55 radp_dfe_fxtap4_56 radp_dfe_fxtap4_57 radp_dfe_fxtap4_58 radp_dfe_fxtap4_59 radp_dfe_fxtap4_6 radp_dfe_fxtap4_60 radp_dfe_fxtap4_61 radp_dfe_fxtap4_62 radp_dfe_fxtap4_63 radp_dfe_fxtap4_7 radp_dfe_fxtap4_8 radp_dfe_fxtap4_9} full_validation 0,anlg_rx_adp_dfe_fxtap5,value radp_dfe_fxtap5_0 allowed_ranges {radp_dfe_fxtap5_0 radp_dfe_fxtap5_1 radp_dfe_fxtap5_10 radp_dfe_fxtap5_11 radp_dfe_fxtap5_12 radp_dfe_fxtap5_13 radp_dfe_fxtap5_14 radp_dfe_fxtap5_15 radp_dfe_fxtap5_16 radp_dfe_fxtap5_17 radp_dfe_fxtap5_18 radp_dfe_fxtap5_19 radp_dfe_fxtap5_2 radp_dfe_fxtap5_20 radp_dfe_fxtap5_21 radp_dfe_fxtap5_22 radp_dfe_fxtap5_23 radp_dfe_fxtap5_24 radp_dfe_fxtap5_25 radp_dfe_fxtap5_26 radp_dfe_fxtap5_27 radp_dfe_fxtap5_28 radp_dfe_fxtap5_29 radp_dfe_fxtap5_3 radp_dfe_fxtap5_30 radp_dfe_fxtap5_31 radp_dfe_fxtap5_32 radp_dfe_fxtap5_33 radp_dfe_fxtap5_34 radp_dfe_fxtap5_35 radp_dfe_fxtap5_36 radp_dfe_fxtap5_37 radp_dfe_fxtap5_38 radp_dfe_fxtap5_39 radp_dfe_fxtap5_4 radp_dfe_fxtap5_40 radp_dfe_fxtap5_41 radp_dfe_fxtap5_42 radp_dfe_fxtap5_43 radp_dfe_fxtap5_44 radp_dfe_fxtap5_45 radp_dfe_fxtap5_46 radp_dfe_fxtap5_47 radp_dfe_fxtap5_48 radp_dfe_fxtap5_49 radp_dfe_fxtap5_5 radp_dfe_fxtap5_50 radp_dfe_fxtap5_51 radp_dfe_fxtap5_52 radp_dfe_fxtap5_53 radp_dfe_fxtap5_54 radp_dfe_fxtap5_55 radp_dfe_fxtap5_56 radp_dfe_fxtap5_57 radp_dfe_fxtap5_58 radp_dfe_fxtap5_59 radp_dfe_fxtap5_6 radp_dfe_fxtap5_60 radp_dfe_fxtap5_61 radp_dfe_fxtap5_62 radp_dfe_fxtap5_63 radp_dfe_fxtap5_7 radp_dfe_fxtap5_8 radp_dfe_fxtap5_9} full_validation 0,anlg_rx_adp_dfe_fxtap6,value radp_dfe_fxtap6_0 allowed_ranges {radp_dfe_fxtap6_0 radp_dfe_fxtap6_1 radp_dfe_fxtap6_10 radp_dfe_fxtap6_11 radp_dfe_fxtap6_12 radp_dfe_fxtap6_13 radp_dfe_fxtap6_14 radp_dfe_fxtap6_15 radp_dfe_fxtap6_16 radp_dfe_fxtap6_17 radp_dfe_fxtap6_18 radp_dfe_fxtap6_19 radp_dfe_fxtap6_2 radp_dfe_fxtap6_20 radp_dfe_fxtap6_21 radp_dfe_fxtap6_22 radp_dfe_fxtap6_23 radp_dfe_fxtap6_24 radp_dfe_fxtap6_25 radp_dfe_fxtap6_26 radp_dfe_fxtap6_27 radp_dfe_fxtap6_28 radp_dfe_fxtap6_29 radp_dfe_fxtap6_3 radp_dfe_fxtap6_30 radp_dfe_fxtap6_31 radp_dfe_fxtap6_4 radp_dfe_fxtap6_5 radp_dfe_fxtap6_6 radp_dfe_fxtap6_7 radp_dfe_fxtap6_8 radp_dfe_fxtap6_9} full_validation 0,anlg_rx_adp_dfe_fxtap7,value radp_dfe_fxtap7_0 allowed_ranges {radp_dfe_fxtap7_0 radp_dfe_fxtap7_1 radp_dfe_fxtap7_10 radp_dfe_fxtap7_11 radp_dfe_fxtap7_12 radp_dfe_fxtap7_13 radp_dfe_fxtap7_14 radp_dfe_fxtap7_15 radp_dfe_fxtap7_16 radp_dfe_fxtap7_17 radp_dfe_fxtap7_18 radp_dfe_fxtap7_19 radp_dfe_fxtap7_2 radp_dfe_fxtap7_20 radp_dfe_fxtap7_21 radp_dfe_fxtap7_22 radp_dfe_fxtap7_23 radp_dfe_fxtap7_24 radp_dfe_fxtap7_25 radp_dfe_fxtap7_26 radp_dfe_fxtap7_27 radp_dfe_fxtap7_28 radp_dfe_fxtap7_29 radp_dfe_fxtap7_3 radp_dfe_fxtap7_30 radp_dfe_fxtap7_31 radp_dfe_fxtap7_4 radp_dfe_fxtap7_5 radp_dfe_fxtap7_6 radp_dfe_fxtap7_7 radp_dfe_fxtap7_8 radp_dfe_fxtap7_9} full_validation 0,anlg_rx_adp_dfe_fxtap8,value radp_dfe_fxtap8_0 allowed_ranges {radp_dfe_fxtap8_0 radp_dfe_fxtap8_1 radp_dfe_fxtap8_10 radp_dfe_fxtap8_11 radp_dfe_fxtap8_12 radp_dfe_fxtap8_13 radp_dfe_fxtap8_14 radp_dfe_fxtap8_15 radp_dfe_fxtap8_16 radp_dfe_fxtap8_17 radp_dfe_fxtap8_18 radp_dfe_fxtap8_19 radp_dfe_fxtap8_2 radp_dfe_fxtap8_20 radp_dfe_fxtap8_21 radp_dfe_fxtap8_22 radp_dfe_fxtap8_23 radp_dfe_fxtap8_24 radp_dfe_fxtap8_25 radp_dfe_fxtap8_26 radp_dfe_fxtap8_27 radp_dfe_fxtap8_28 radp_dfe_fxtap8_29 radp_dfe_fxtap8_3 radp_dfe_fxtap8_30 radp_dfe_fxtap8_31 radp_dfe_fxtap8_32 radp_dfe_fxtap8_33 radp_dfe_fxtap8_34 radp_dfe_fxtap8_35 radp_dfe_fxtap8_36 radp_dfe_fxtap8_37 radp_dfe_fxtap8_38 radp_dfe_fxtap8_39 radp_dfe_fxtap8_4 radp_dfe_fxtap8_40 radp_dfe_fxtap8_41 radp_dfe_fxtap8_42 radp_dfe_fxtap8_43 radp_dfe_fxtap8_44 radp_dfe_fxtap8_45 radp_dfe_fxtap8_46 radp_dfe_fxtap8_47 radp_dfe_fxtap8_48 radp_dfe_fxtap8_49 radp_dfe_fxtap8_5 radp_dfe_fxtap8_50 radp_dfe_fxtap8_51 radp_dfe_fxtap8_52 radp_dfe_fxtap8_53 radp_dfe_fxtap8_54 radp_dfe_fxtap8_55 radp_dfe_fxtap8_56 radp_dfe_fxtap8_57 radp_dfe_fxtap8_58 radp_dfe_fxtap8_59 radp_dfe_fxtap8_6 radp_dfe_fxtap8_60 radp_dfe_fxtap8_61 radp_dfe_fxtap8_62 radp_dfe_fxtap8_63 radp_dfe_fxtap8_7 radp_dfe_fxtap8_8 radp_dfe_fxtap8_9} full_validation 0,anlg_rx_adp_dfe_fxtap9,value radp_dfe_fxtap9_0 allowed_ranges {radp_dfe_fxtap9_0 radp_dfe_fxtap9_1 radp_dfe_fxtap9_10 radp_dfe_fxtap9_11 radp_dfe_fxtap9_12 radp_dfe_fxtap9_13 radp_dfe_fxtap9_14 radp_dfe_fxtap9_15 radp_dfe_fxtap9_16 radp_dfe_fxtap9_17 radp_dfe_fxtap9_18 radp_dfe_fxtap9_19 radp_dfe_fxtap9_2 radp_dfe_fxtap9_20 radp_dfe_fxtap9_21 radp_dfe_fxtap9_22 radp_dfe_fxtap9_23 radp_dfe_fxtap9_24 radp_dfe_fxtap9_25 radp_dfe_fxtap9_26 radp_dfe_fxtap9_27 radp_dfe_fxtap9_28 radp_dfe_fxtap9_29 radp_dfe_fxtap9_3 radp_dfe_fxtap9_30 radp_dfe_fxtap9_31 radp_dfe_fxtap9_32 radp_dfe_fxtap9_33 radp_dfe_fxtap9_34 radp_dfe_fxtap9_35 radp_dfe_fxtap9_36 radp_dfe_fxtap9_37 radp_dfe_fxtap9_38 radp_dfe_fxtap9_39 radp_dfe_fxtap9_4 radp_dfe_fxtap9_40 radp_dfe_fxtap9_41 radp_dfe_fxtap9_42 radp_dfe_fxtap9_43 radp_dfe_fxtap9_44 radp_dfe_fxtap9_45 radp_dfe_fxtap9_46 radp_dfe_fxtap9_47 radp_dfe_fxtap9_48 radp_dfe_fxtap9_49 radp_dfe_fxtap9_5 radp_dfe_fxtap9_50 radp_dfe_fxtap9_51 radp_dfe_fxtap9_52 radp_dfe_fxtap9_53 radp_dfe_fxtap9_54 radp_dfe_fxtap9_55 radp_dfe_fxtap9_56 radp_dfe_fxtap9_57 radp_dfe_fxtap9_58 radp_dfe_fxtap9_59 radp_dfe_fxtap9_6 radp_dfe_fxtap9_60 radp_dfe_fxtap9_61 radp_dfe_fxtap9_62 radp_dfe_fxtap9_63 radp_dfe_fxtap9_7 radp_dfe_fxtap9_8 radp_dfe_fxtap9_9} full_validation 0,anlg_rx_adp_dfe_fxtap10,value radp_dfe_fxtap10_0 allowed_ranges {radp_dfe_fxtap10_0 radp_dfe_fxtap10_1 radp_dfe_fxtap10_10 radp_dfe_fxtap10_11 radp_dfe_fxtap10_12 radp_dfe_fxtap10_13 radp_dfe_fxtap10_14 radp_dfe_fxtap10_15 radp_dfe_fxtap10_16 radp_dfe_fxtap10_17 radp_dfe_fxtap10_18 radp_dfe_fxtap10_19 radp_dfe_fxtap10_2 radp_dfe_fxtap10_20 radp_dfe_fxtap10_21 radp_dfe_fxtap10_22 radp_dfe_fxtap10_23 radp_dfe_fxtap10_24 radp_dfe_fxtap10_25 radp_dfe_fxtap10_26 radp_dfe_fxtap10_27 radp_dfe_fxtap10_28 radp_dfe_fxtap10_29 radp_dfe_fxtap10_3 radp_dfe_fxtap10_30 radp_dfe_fxtap10_31 radp_dfe_fxtap10_32 radp_dfe_fxtap10_33 radp_dfe_fxtap10_34 radp_dfe_fxtap10_35 radp_dfe_fxtap10_36 radp_dfe_fxtap10_37 radp_dfe_fxtap10_38 radp_dfe_fxtap10_39 radp_dfe_fxtap10_4 radp_dfe_fxtap10_40 radp_dfe_fxtap10_41 radp_dfe_fxtap10_42 radp_dfe_fxtap10_43 radp_dfe_fxtap10_44 radp_dfe_fxtap10_45 radp_dfe_fxtap10_46 radp_dfe_fxtap10_47 radp_dfe_fxtap10_48 radp_dfe_fxtap10_49 radp_dfe_fxtap10_5 radp_dfe_fxtap10_50 radp_dfe_fxtap10_51 radp_dfe_fxtap10_52 radp_dfe_fxtap10_53 radp_dfe_fxtap10_54 radp_dfe_fxtap10_55 radp_dfe_fxtap10_56 radp_dfe_fxtap10_57 radp_dfe_fxtap10_58 radp_dfe_fxtap10_59 radp_dfe_fxtap10_6 radp_dfe_fxtap10_60 radp_dfe_fxtap10_61 radp_dfe_fxtap10_62 radp_dfe_fxtap10_63 radp_dfe_fxtap10_7 radp_dfe_fxtap10_8 radp_dfe_fxtap10_9} full_validation 0,anlg_rx_adp_dfe_fxtap11,value radp_dfe_fxtap11_0 allowed_ranges {radp_dfe_fxtap11_0 radp_dfe_fxtap11_1 radp_dfe_fxtap11_10 radp_dfe_fxtap11_11 radp_dfe_fxtap11_12 radp_dfe_fxtap11_13 radp_dfe_fxtap11_14 radp_dfe_fxtap11_15 radp_dfe_fxtap11_16 radp_dfe_fxtap11_17 radp_dfe_fxtap11_18 radp_dfe_fxtap11_19 radp_dfe_fxtap11_2 radp_dfe_fxtap11_20 radp_dfe_fxtap11_21 radp_dfe_fxtap11_22 radp_dfe_fxtap11_23 radp_dfe_fxtap11_24 radp_dfe_fxtap11_25 radp_dfe_fxtap11_26 radp_dfe_fxtap11_27 radp_dfe_fxtap11_28 radp_dfe_fxtap11_29 radp_dfe_fxtap11_3 radp_dfe_fxtap11_30 radp_dfe_fxtap11_31 radp_dfe_fxtap11_32 radp_dfe_fxtap11_33 radp_dfe_fxtap11_34 radp_dfe_fxtap11_35 radp_dfe_fxtap11_36 radp_dfe_fxtap11_37 radp_dfe_fxtap11_38 radp_dfe_fxtap11_39 radp_dfe_fxtap11_4 radp_dfe_fxtap11_40 radp_dfe_fxtap11_41 radp_dfe_fxtap11_42 radp_dfe_fxtap11_43 radp_dfe_fxtap11_44 radp_dfe_fxtap11_45 radp_dfe_fxtap11_46 radp_dfe_fxtap11_47 radp_dfe_fxtap11_48 radp_dfe_fxtap11_49 radp_dfe_fxtap11_5 radp_dfe_fxtap11_50 radp_dfe_fxtap11_51 radp_dfe_fxtap11_52 radp_dfe_fxtap11_53 radp_dfe_fxtap11_54 radp_dfe_fxtap11_55 radp_dfe_fxtap11_56 radp_dfe_fxtap11_57 radp_dfe_fxtap11_58 radp_dfe_fxtap11_59 radp_dfe_fxtap11_6 radp_dfe_fxtap11_60 radp_dfe_fxtap11_61 radp_dfe_fxtap11_62 radp_dfe_fxtap11_63 radp_dfe_fxtap11_7 radp_dfe_fxtap11_8 radp_dfe_fxtap11_9} full_validation 0,anlg_rx_term_sel,value r_r1 allowed_ranges {r_ext0 r_r1 r_r2} full_validation 0,rapid_validate,value 0 allowed_ranges -2147483648:2147483647 full_validation 0 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |