DE2-115 FPGA Board Configuration



Pin Assignments:




Pin Assignment Table:



CLOCK
Name Location Direction Standard
OSC_50[0] A1 input 3.3-V LVTTL
OSC_50[1] A1 input 3.3-V LVTTL
OSC_50[2] A1 input 3.3-V LVTTL
OSC_50[3] A1 input 3.3-V LVTTL



Sma
Name Location Direction Standard
SMA_CLKIN R29 input 3.3-V LVTTL
SMA_CLKOUT R29 output 3.3-V LVTTL



LED
Name Location Direction Standard
LEDR[0] AJ6 output 3.3-V LVTTL
LEDR[1] AK5 output 3.3-V LVTTL
LEDR[2] AJ5 output 3.3-V LVTTL
LEDR[3] AJ4 output 3.3-V LVTTL
LEDR[4] AK3 output 3.3-V LVTTL
LEDR[5] AH4 output 3.3-V LVTTL
LEDR[6] AJ3 output 3.3-V LVTTL
LEDR[7] AJ2 output 3.3-V LVTTL
LEDR[8] AH3 output 3.3-V LVTTL
LEDR[9] AD14 output 3.3-V LVTTL
LEDR[10] AC13 output 3.3-V LVTTL
LEDR[11] AB13 output 3.3-V LVTTL
LEDR[12] AC12 output 3.3-V LVTTL
LEDR[13] AB12 output 3.3-V LVTTL
LEDR[14] AC11 output 3.3-V LVTTL
LEDR[15] AD9 output 3.3-V LVTTL
LEDR[16] AD8 output 3.3-V LVTTL
LEDR[17] AJ7 output 3.3-V LVTTL
LEDG[0] W27 output 3.3-V LVTTL
LEDG[1] W25 output 3.3-V LVTTL
LEDG[2] W23 output 3.3-V LVTTL
LEDG[3] Y27 output 3.3-V LVTTL
LEDG[4] Y24 output 3.3-V LVTTL
LEDG[5] Y23 output 3.3-V LVTTL
LEDG[6] AA27 output 3.3-V LVTTL
LEDG[7] AA24 output 3.3-V LVTTL
LEDG[8] AC14 output 3.3-V LVTTL



KEY
Name Location Direction Standard
KEY[0] T29 input 3.3-V LVTTL
KEY[1] T28 input 3.3-V LVTTL
KEY[2] U30 input 3.3-V LVTTL
KEY[3] U29 input 3.3-V LVTTL



SW
Name Location Direction Standard
SW[0] AA23 input 3.3-V LVTTL
SW[1] AB26 input 3.3-V LVTTL
SW[2] AB25 input 3.3-V LVTTL
SW[3] AC27 input 3.3-V LVTTL
SW[4] AC26 input 3.3-V LVTTL
SW[5] AC24 input 3.3-V LVTTL
SW[6] AC23 input 3.3-V LVTTL
SW[7] AD25 input 3.3-V LVTTL
SW[8] AD24 input 3.3-V LVTTL
SW[9] AE27 input 3.3-V LVTTL
SW[10] W5 input 3.3-V LVTTL
SW[11] V10 input 3.3-V LVTTL
SW[12] U9 input 3.3-V LVTTL
SW[13] T9 input 3.3-V LVTTL
SW[14] L5 input 3.3-V LVTTL
SW[15] L4 input 3.3-V LVTTL
SW[16] L7 input 3.3-V LVTTL
SW[17] L8 input 3.3-V LVTTL



SEG7
Name Location Direction Standard
HEX0_D[0] AE8 output 3.3-V LVTTL
HEX0_D[1] AF9 output 3.3-V LVTTL
HEX0_D[2] AH9 output 3.3-V LVTTL
HEX0_D[3] AD10 output 3.3-V LVTTL
HEX0_D[4] AF10 output 3.3-V LVTTL
HEX0_D[5] AD11 output 3.3-V LVTTL
HEX0_D[6] AD12 output 3.3-V LVTTL
HEX1_D[0] AG13 output 3.3-V LVTTL
HEX1_D[1] AE16 output 3.3-V LVTTL
HEX1_D[2] AF16 output 3.3-V LVTTL
HEX1_D[3] AG16 output 3.3-V LVTTL
HEX1_D[4] AE17 output 3.3-V LVTTL
HEX1_D[5] AF17 output 3.3-V LVTTL
HEX1_D[6] AD17 output 3.3-V LVTTL
HEX2_D[0] AE7 output 3.3-V LVTTL
HEX2_D[1] AF7 output 3.3-V LVTTL
HEX2_D[2] AH5 output 3.3-V LVTTL
HEX2_D[3] AG4 output 3.3-V LVTTL
HEX2_D[4] AB18 output 3.3-V LVTTL
HEX2_D[5] AB19 output 3.3-V LVTTL
HEX2_D[6] AE19 output 3.3-V LVTTL
HEX3_D[0] P6 output 3.3-V LVTTL
HEX3_D[1] P4 output 3.3-V LVTTL
HEX3_D[2] N10 output 3.3-V LVTTL
HEX3_D[3] N7 output 3.3-V LVTTL
HEX3_D[4] M8 output 3.3-V LVTTL
HEX3_D[5] M7 output 3.3-V LVTTL
HEX3_D[6] M6 output 3.3-V LVTTL
HEX4_D[0] P1 output 3.3-V LVTTL
HEX4_D[1] P2 output 3.3-V LVTTL
HEX4_D[2] P3 output 3.3-V LVTTL
HEX4_D[3] N2 output 3.3-V LVTTL
HEX4_D[4] N3 output 3.3-V LVTTL
HEX4_D[5] M1 output 3.3-V LVTTL
HEX4_D[6] M2 output 3.3-V LVTTL
HEX5_D[0] M3 output 3.3-V LVTTL
HEX5_D[1] L1 output 3.3-V LVTTL
HEX5_D[2] L2 output 3.3-V LVTTL
HEX5_D[3] L3 output 3.3-V LVTTL
HEX5_D[4] K1 output 3.3-V LVTTL
HEX5_D[5] K4 output 3.3-V LVTTL
HEX5_D[6] K5 output 3.3-V LVTTL
HEX6_D[0] H6 output 3.3-V LVTTL
HEX6_D[1] H4 output 3.3-V LVTTL
HEX6_D[2] H7 output 3.3-V LVTTL
HEX6_D[3] H8 output 3.3-V LVTTL
HEX6_D[4] G4 output 3.3-V LVTTL
HEX6_D[5] F4 output 3.3-V LVTTL
HEX6_D[6] E4 output 3.3-V LVTTL
HEX7_D[0] K3 output 3.3-V LVTTL
HEX7_D[1] J1 output 3.3-V LVTTL
HEX7_D[2] J2 output 3.3-V LVTTL
HEX7_D[3] H1 output 3.3-V LVTTL
HEX7_D[4] H2 output 3.3-V LVTTL
HEX7_D[5] H3 output 3.3-V LVTTL
HEX7_D[6] G1 output 3.3-V LVTTL



LCD
Name Location Direction Standard
LCD_DATA[0] E1 inout 3.3-V LVTTL
LCD_DATA[1] E3 inout 3.3-V LVTTL
LCD_DATA[2] D2 inout 3.3-V LVTTL
LCD_DATA[3] D3 inout 3.3-V LVTTL
LCD_DATA[4] C1 inout 3.3-V LVTTL
LCD_DATA[5] C2 inout 3.3-V LVTTL
LCD_DATA[6] C3 inout 3.3-V LVTTL
LCD_DATA[7] B2 inout 3.3-V LVTTL
LCD_BLON G3 output 3.3-V LVTTL
LCD_RW F3 output 3.3-V LVTTL
LCD_EN E2 output 3.3-V LVTTL
LCD_RS F2 output 3.3-V LVTTL
LCD_ON F1 output 3.3-V LVTTL



RS232
Name Location Direction Standard
UART_TXD E21 output 3.3-V LVTTL
UART_RXD D21 input 3.3-V LVTTL
UART_CTS G22 output 3.3-V LVTTL
UART_RTS F23 input 3.3-V LVTTL



PS2
Name Location Direction Standard
PS2_KBCLK F24 inout 3.3-V LVTTL
PS2_KBDAT E24 inout 3.3-V LVTTL
PS2_MSCLK D26 inout 3.3-V LVTTL
PS2_MSDAT D25 inout 3.3-V LVTTL



SDCARD
Name Location Direction Standard
SD_CMD W28 inout 3.3-V LVTTL
SD_CLK T26 output 3.3-V LVTTL
SD_WP_n W20 input 3.3-V LVTTL
SD_DAT[0] Y30 inout 3.3-V LVTTL
SD_DAT[1] N6 inout 3.3-V LVTTL
SD_DAT[2] T11 inout 3.3-V LVTTL
SD_DAT[3] R9 inout 3.3-V LVTTL



VGA
Name Location Direction Standard
VGA_HS J19 output 3.3-V LVTTL
VGA_VS H19 output 3.3-V LVTTL
VGA_SYNC_n B15 output 3.3-V LVTTL
VGA_CLK D24 output 3.3-V LVTTL
VGA_BLANK_n C15 output 3.3-V LVTTL
VGA_R[0] D23 output 3.3-V LVTTL
VGA_R[1] E23 output 3.3-V LVTTL
VGA_R[2] E22 output 3.3-V LVTTL
VGA_R[3] D22 output 3.3-V LVTTL
VGA_R[4] H21 output 3.3-V LVTTL
VGA_R[5] G21 output 3.3-V LVTTL
VGA_R[6] H20 output 3.3-V LVTTL
VGA_R[7] F20 output 3.3-V LVTTL
VGA_R[8] E20 output 3.3-V LVTTL
VGA_R[9] G20 output 3.3-V LVTTL
VGA_G[0] A10 output 3.3-V LVTTL
VGA_G[1] B11 output 3.3-V LVTTL
VGA_G[2] A11 output 3.3-V LVTTL
VGA_G[3] C12 output 3.3-V LVTTL
VGA_G[4] B12 output 3.3-V LVTTL
VGA_G[5] A12 output 3.3-V LVTTL
VGA_G[6] C13 output 3.3-V LVTTL
VGA_G[7] B13 output 3.3-V LVTTL
VGA_G[8] B14 output 3.3-V LVTTL
VGA_G[9] A14 output 3.3-V LVTTL
VGA_B[0] B16 output 3.3-V LVTTL
VGA_B[1] C16 output 3.3-V LVTTL
VGA_B[2] A17 output 3.3-V LVTTL
VGA_B[3] B17 output 3.3-V LVTTL
VGA_B[4] C18 output 3.3-V LVTTL
VGA_B[5] B18 output 3.3-V LVTTL
VGA_B[6] B19 output 3.3-V LVTTL
VGA_B[7] A19 output 3.3-V LVTTL
VGA_B[8] C19 output 3.3-V LVTTL
VGA_B[9] D19 output 3.3-V LVTTL



Audio
Name Location Direction Standard
AUD_ADCLRCK F19 inout 3.3-V LVTTL
AUD_ADCDAT E19 input 3.3-V LVTTL
AUD_DACLRCK G18 inout 3.3-V LVTTL
AUD_DACDAT F18 output 3.3-V LVTTL
AUD_XCK D17 output 3.3-V LVTTL
AUD_BCLK E17 inout 3.3-V LVTTL



I2C for EEPROM
Name Location Direction Standard
EEP_I2C_SCL J18 output 3.3-V LVTTL
EEP_I2C_SDA H18 inout 3.3-V LVTTL



I2C for Audioand Tv-Decode 1 and 2
Name Location Direction Standard
I2C_SCL J18 output 3.3-V LVTTL
I2C_SDA H18 inout 3.3-V LVTTL



TV Decoder 1
Name Location Direction Standard
TD0_HS E13 input 3.3-V LVTTL
TD0_VS E14 input 3.3-V LVTTL
TD0_CLK27 G15 input 3.3-V LVTTL
TD0_RESET_n D14 output 3.3-V LVTTL
TD0_DATA[0] A6 input 3.3-V LVTTL
TD0_DATA[1] B6 input 3.3-V LVTTL
TD0_DATA[2] A5 input 3.3-V LVTTL
TD0_DATA[3] B5 input 3.3-V LVTTL
TD0_DATA[4] B4 input 3.3-V LVTTL
TD0_DATA[5] C4 input 3.3-V LVTTL
TD0_DATA[6] A3 input 3.3-V LVTTL
TD0_DATA[7] B3 input 3.3-V LVTTL



TV Decoder 2
Name Location Direction Standard
TD1_HS E15 input 3.3-V LVTTL
TD1_VS D15 input 3.3-V LVTTL
TD1_CLK27 H15 input 3.3-V LVTTL
TD1_RESET_n B10 output 3.3-V LVTTL
TD1_DATA[0] C10 inout 3.3-V LVTTL
TD1_DATA[1] A9 inout 3.3-V LVTTL
TD1_DATA[2] B9 inout 3.3-V LVTTL
TD1_DATA[3] C9 inout 3.3-V LVTTL
TD1_DATA[4] A8 inout 3.3-V LVTTL
TD1_DATA[5] B8 inout 3.3-V LVTTL
TD1_DATA[6] A7 inout 3.3-V LVTTL
TD1_DATA[7] B7 inout 3.3-V LVTTL



USB FIFO
Name Location Direction Standard
USB_RXF_n E9 input 3.3-V LVTTL
USB_TXE_n D8 input 3.3-V LVTTL
USB_RD_n E10 output 3.3-V LVTTL
USB_WR_n D10 output 3.3-V LVTTL
USB_SIMU_n E11 output 3.3-V LVTTL
USB_CLKOUT H14 input 3.3-V LVTTL
USB_OE_n F13 output 3.3-V LVTTL
USB_PWREN_n J13 output 3.3-V LVTTL
USB_SUSPEND_n D12 input 3.3-V LVTTL
USB_RESET_n E12 output 3.3-V LVTTL
USB_DATA[0] H10 inout 3.3-V LVTTL
USB_DATA[1] G9 inout 3.3-V LVTTL
USB_DATA[2] G11 inout 3.3-V LVTTL
USB_DATA[3] F11 inout 3.3-V LVTTL
USB_DATA[4] J12 inout 3.3-V LVTTL
USB_DATA[5] H12 inout 3.3-V LVTTL
USB_DATA[6] H13 inout 3.3-V LVTTL
USB_DATA[7] G13 inout 3.3-V LVTTL



IR Receiver
Name Location Direction Standard
IRDA_RXD W22 input 3.3-V LVTTL



SDRAM
Name Location Direction Standard
DRAM_BA[0] AA9 output 3.3-V LVTTL
DRAM_BA[1] AA10 output 3.3-V LVTTL
DRAM_QDM[0] V9 output 3.3-V LVTTL
DRAM_QDM[1] V9 output 3.3-V LVTTL
DRAM_QDM[2] V9 output 3.3-V LVTTL
DRAM_QDM[3] V9 output 3.3-V LVTTL
DRAM_RAS_n Y9 output 3.3-V LVTTL
DRAM_CAS_n W10 output 3.3-V LVTTL
DRAM_CKE AA8 output 3.3-V LVTTL
DRAM_CLK AD6 output 3.3-V LVTTL
DRAM_WE_n W9 output 3.3-V LVTTL
DRAM_CS_n Y10 output 3.3-V LVTTL
DRAM_DQ[0] AC1 inout 3.3-V LVTTL
DRAM_DQ[1] AC2 inout 3.3-V LVTTL
DRAM_DQ[2] AC3 inout 3.3-V LVTTL
DRAM_DQ[3] AD1 inout 3.3-V LVTTL
DRAM_DQ[4] AD2 inout 3.3-V LVTTL
DRAM_DQ[5] AD3 inout 3.3-V LVTTL
DRAM_DQ[6] AE1 inout 3.3-V LVTTL
DRAM_DQ[7] AE2 inout 3.3-V LVTTL
DRAM_DQ[8] AE3 inout 3.3-V LVTTL
DRAM_DQ[9] AF1 inout 3.3-V LVTTL
DRAM_DQ[10] AC1 inout 3.3-V LVTTL
DRAM_DQ[11] AC2 inout 3.3-V LVTTL
DRAM_DQ[12] AC3 inout 3.3-V LVTTL
DRAM_DQ[13] AD1 inout 3.3-V LVTTL
DRAM_DQ[14] AD2 inout 3.3-V LVTTL
DRAM_DQ[15] AD3 inout 3.3-V LVTTL
DRAM_DQ[16] AE1 inout 3.3-V LVTTL
DRAM_DQ[17] AE2 inout 3.3-V LVTTL
DRAM_DQ[18] AE3 inout 3.3-V LVTTL
DRAM_DQ[19] AF1 inout 3.3-V LVTTL
DRAM_DQ[20] AC1 inout 3.3-V LVTTL
DRAM_DQ[21] AC2 inout 3.3-V LVTTL
DRAM_DQ[22] AC3 inout 3.3-V LVTTL
DRAM_DQ[23] AD1 inout 3.3-V LVTTL
DRAM_DQ[24] AD2 inout 3.3-V LVTTL
DRAM_DQ[25] AD3 inout 3.3-V LVTTL
DRAM_DQ[26] AE1 inout 3.3-V LVTTL
DRAM_DQ[27] AE2 inout 3.3-V LVTTL
DRAM_DQ[28] AE3 inout 3.3-V LVTTL
DRAM_DQ[29] AF1 inout 3.3-V LVTTL
DRAM_DQ[30] AF2 inout 3.3-V LVTTL
DRAM_DQ[31] AF3 inout 3.3-V LVTTL
DRAM_ADDR[0] AA4 output 3.3-V LVTTL
DRAM_ADDR[1] AA5 output 3.3-V LVTTL
DRAM_ADDR[2] AA6 output 3.3-V LVTTL
DRAM_ADDR[3] AB5 output 3.3-V LVTTL
DRAM_ADDR[4] AB7 output 3.3-V LVTTL
DRAM_ADDR[5] AC4 output 3.3-V LVTTL
DRAM_ADDR[6] AC5 output 3.3-V LVTTL
DRAM_ADDR[7] AC6 output 3.3-V LVTTL
DRAM_ADDR[8] AD4 output 3.3-V LVTTL
DRAM_ADDR[9] AC7 output 3.3-V LVTTL
DRAM_ADDR[10] Y8 output 3.3-V LVTTL
DRAM_ADDR[11] AE4 output 3.3-V LVTTL
DRAM_ADDR[12] AF4 output 3.3-V LVTTL



SRAM
Name Location Direction Standard
SRAM_ADDR[0] AG8 output 3.3-V LVTTL
SRAM_ADDR[1] AF8 output 3.3-V LVTTL
SRAM_ADDR[2] AH7 output 3.3-V LVTTL
SRAM_ADDR[3] AG7 output 3.3-V LVTTL
SRAM_ADDR[4] AG6 output 3.3-V LVTTL
SRAM_ADDR[5] AG5 output 3.3-V LVTTL
SRAM_ADDR[6] AE12 output 3.3-V LVTTL
SRAM_ADDR[7] AG12 output 3.3-V LVTTL
SRAM_ADDR[8] AD13 output 3.3-V LVTTL
SRAM_ADDR[9] AE13 output 3.3-V LVTTL
SRAM_ADDR[10] AF14 output 3.3-V LVTTL
SRAM_ADDR[11] AG14 output 3.3-V LVTTL
SRAM_ADDR[12] AE15 output 3.3-V LVTTL
SRAM_ADDR[13] AF15 output 3.3-V LVTTL
SRAM_ADDR[14] AC16 output 3.3-V LVTTL
SRAM_ADDR[15] AF20 output 3.3-V LVTTL
SRAM_ADDR[16] AG20 output 3.3-V LVTTL
SRAM_ADDR[17] AE11 output 3.3-V LVTTL
SRAM_ADDR[18] AF11 output 3.3-V LVTTL
SRAM_ADDR[19] output 3.3-V LVTTL
SRAM_DQ[0] AH10 inout 3.3-V LVTTL
SRAM_DQ[1] AJ10 inout 3.3-V LVTTL
SRAM_DQ[2] AK10 inout 3.3-V LVTTL
SRAM_DQ[3] AJ11 inout 3.3-V LVTTL
SRAM_DQ[4] AK11 inout 3.3-V LVTTL
SRAM_DQ[5] AH12 inout 3.3-V LVTTL
SRAM_DQ[6] AJ12 inout 3.3-V LVTTL
SRAM_DQ[7] AH16 inout 3.3-V LVTTL
SRAM_DQ[8] AK17 inout 3.3-V LVTTL
SRAM_DQ[9] AJ17 inout 3.3-V LVTTL
SRAM_DQ[10] AH17 inout 3.3-V LVTTL
SRAM_DQ[11] AJ18 inout 3.3-V LVTTL
SRAM_DQ[12] AH18 inout 3.3-V LVTTL
SRAM_DQ[13] AK19 inout 3.3-V LVTTL
SRAM_DQ[14] AJ19 inout 3.3-V LVTTL
SRAM_DQ[15] AK23 inout 3.3-V LVTTL
SRAM_UB_n AC21 output 3.3-V LVTTL
SRAM_LB_n AC20 output 3.3-V LVTTL
SRAM_CE_n AH19 output 3.3-V LVTTL
SRAM_CLK AD7 output 3.3-V LVTTL
SRAM_OE_n AD18 output 3.3-V LVTTL
SRAM_WE_n AF18 output 3.3-V LVTTL



Flash
Name Location Direction Standard
FLASH_ADDR[0] AF24 output 3.3-V LVTTL
FLASH_ADDR[1] AG24 output 3.3-V LVTTL
FLASH_ADDR[2] AE23 output 3.3-V LVTTL
FLASH_ADDR[3] AG23 output 3.3-V LVTTL
FLASH_ADDR[4] AF23 output 3.3-V LVTTL
FLASH_ADDR[5] AG22 output 3.3-V LVTTL
FLASH_ADDR[6] AH22 output 3.3-V LVTTL
FLASH_ADDR[7] AF22 output 3.3-V LVTTL
FLASH_ADDR[8] AH27 output 3.3-V LVTTL
FLASH_ADDR[9] AJ27 output 3.3-V LVTTL
FLASH_ADDR[10] AH26 output 3.3-V LVTTL
FLASH_ADDR[11] AJ26 output 3.3-V LVTTL
FLASH_ADDR[12] AK26 output 3.3-V LVTTL
FLASH_ADDR[13] AJ25 output 3.3-V LVTTL
FLASH_ADDR[14] AK25 output 3.3-V LVTTL
FLASH_ADDR[15] AH24 output 3.3-V LVTTL
FLASH_ADDR[16] AG25 output 3.3-V LVTTL
FLASH_ADDR[17] AF21 output 3.3-V LVTTL
FLASH_ADDR[18] AD21 output 3.3-V LVTTL
FLASH_ADDR[19] AK28 output 3.3-V LVTTL
FLASH_ADDR[20] AJ28 output 3.3-V LVTTL
FLASH_ADDR[21] AE20 output 3.3-V LVTTL
FLASH_ADDR[22] AE20 output 3.3-V LVTTL
FLASH_DQ[0] AF29 inout 3.3-V LVTTL
FLASH_DQ[1] AE28 inout 3.3-V LVTTL
FLASH_DQ[2] AE30 inout 3.3-V LVTTL
FLASH_DQ[3] AD30 inout 3.3-V LVTTL
FLASH_DQ[4] AC29 inout 3.3-V LVTTL
FLASH_DQ[5] AB29 inout 3.3-V LVTTL
FLASH_DQ[6] AA29 inout 3.3-V LVTTL
FLASH_DQ[7] Y28 inout 3.3-V LVTTL
FLASH_CE_n AG28 output 3.3-V LVTTL
FLASH_OE_n AG29 output 3.3-V LVTTL
FLASH_RESET_n AH28 output 3.3-V LVTTL
FLASH_RY AH30 input 3.3-V LVTTL
FLASH_WE_n AJ29 output 3.3-V LVTTL
FLASH_WP_n AH29 output 3.3-V LVTTL



GPIO connect to GPIO Default
Name Location Direction Standard GPIO Pin Index
GPIO0_GPIO_D[0] T25 inout 3.3-V LVTTL 1
GPIO0_GPIO_D[1] C30 inout 3.3-V LVTTL 2
GPIO0_GPIO_D[2] T24 inout 3.3-V LVTTL 3
GPIO0_GPIO_D[3] C29 inout 3.3-V LVTTL 4
GPIO0_GPIO_D[4] E28 inout 3.3-V LVTTL 5
GPIO0_GPIO_D[5] D29 inout 3.3-V LVTTL 6
GPIO0_GPIO_D[6] E27 inout 3.3-V LVTTL 7
GPIO0_GPIO_D[7] D28 inout 3.3-V LVTTL 8
GPIO0_GPIO_D[8] E29 inout 3.3-V LVTTL 9
GPIO0_GPIO_D[9] G25 inout 3.3-V LVTTL 10
GPIO0_GPIO_D[10] E30 inout 3.3-V LVTTL 13
GPIO0_GPIO_D[11] G26 inout 3.3-V LVTTL 14
GPIO0_GPIO_D[12] F29 inout 3.3-V LVTTL 15
GPIO0_GPIO_D[13] G29 inout 3.3-V LVTTL 16
GPIO0_GPIO_D[14] F30 inout 3.3-V LVTTL 17
GPIO0_GPIO_D[15] G30 inout 3.3-V LVTTL 18
GPIO0_GPIO_D[16] H23 inout 3.3-V LVTTL 19
GPIO0_GPIO_D[17] H29 inout 3.3-V LVTTL 20
GPIO0_GPIO_D[18] G24 inout 3.3-V LVTTL 21
GPIO0_GPIO_D[19] H30 inout 3.3-V LVTTL 22
GPIO0_GPIO_D[20] J29 inout 3.3-V LVTTL 23
GPIO0_GPIO_D[21] H25 inout 3.3-V LVTTL 24
GPIO0_GPIO_D[22] J30 inout 3.3-V LVTTL 25
GPIO0_GPIO_D[23] H24 inout 3.3-V LVTTL 26
GPIO0_GPIO_D[24] J25 inout 3.3-V LVTTL 27
GPIO0_GPIO_D[25] K24 inout 3.3-V LVTTL 28
GPIO0_GPIO_D[26] J24 inout 3.3-V LVTTL 31
GPIO0_GPIO_D[27] K25 inout 3.3-V LVTTL 32
GPIO0_GPIO_D[28] L22 inout 3.3-V LVTTL 33
GPIO0_GPIO_D[29] M21 inout 3.3-V LVTTL 34
GPIO0_GPIO_D[30] L21 inout 3.3-V LVTTL 35
GPIO0_GPIO_D[31] M22 inout 3.3-V LVTTL 36
GPIO0_GPIO_D[32] N22 inout 3.3-V LVTTL 37
GPIO0_GPIO_D[33] N25 inout 3.3-V LVTTL 38
GPIO0_GPIO_D[34] N21 inout 3.3-V LVTTL 39
GPIO0_GPIO_D[35] N24 inout 3.3-V LVTTL 40



HSMC connect to HSMC Default
Name Location Direction Standard HSMC Pin Index
GPIO1_TX_P[3] B36 output 2.5 V 17
GPIO1_RX_P[3] C38 input 2.5 V 18
GPIO1_TX_N[3] B37 output 2.5 V 19
GPIO1_RX_N[3] C39 input 2.5 V 20
GPIO1_TX_P[2] D36 output 2.5 V 21
GPIO1_RX_P[2] E38 input 2.5 V 22
GPIO1_TX_N[2] D37 output 2.5 V 23
GPIO1_RX_N[2] E39 input 2.5 V 24
GPIO1_TX_P[1] K36 output 2.5 V 25
GPIO1_RX_P[1] L38 input 2.5 V 26
GPIO1_TX_N[1] K37 output 2.5 V 27
GPIO1_RX_N[1] L39 input 2.5 V 28
GPIO1_TX_P[0] M36 output 2.5 V 29
GPIO1_RX_P[0] N38 input 2.5 V 30
GPIO1_TX_N[0] M37 output 2.5 V 31
GPIO1_RX_N[0] N39 input 2.5 V 32
GPIO1_CLK_OUT[0] AF29 output 2.5 V 39
GPIO1_CLK_IN[0] AC34 input 2.5 V 40
GPIO1_D[0] AC26 inout 2.5 V 41
GPIO1_D[1] AC31 inout 2.5 V 42
GPIO1_D[2] AD26 inout 2.5 V 43
GPIO1_D[3] AC32 inout 2.5 V 44
GPIO1_TX_D_P[0] AB27 output 2.5 V 47
GPIO1_RX_D_P[0] AJ32 input 2.5 V 48
GPIO1_TX_D_N[0] AB28 output 2.5 V 49
GPIO1_RX_D_N[0] AK33 input 2.5 V 50
GPIO1_TX_D_P[1] AB30 output 2.5 V 53
GPIO1_RX_D_P[1] AH34 input 2.5 V 54
GPIO1_TX_D_N[1] AB31 output 2.5 V 55
GPIO1_RX_D_N[1] AH35 input 2.5 V 56
GPIO1_TX_D_P[2] AD27 output 2.5 V 59
GPIO1_RX_D_P[2] AJ34 input 2.5 V 60
GPIO1_TX_D_N[2] AE27 output 2.5 V 61
GPIO1_RX_D_N[2] AJ35 input 2.5 V 62
GPIO1_TX_D_P[3] AD28 output 2.5 V 65
GPIO1_RX_D_P[3] AK34 input 2.5 V 66
GPIO1_TX_D_N[3] AD29 output 2.5 V 67
GPIO1_RX_D_N[3] AK35 input 2.5 V 68
GPIO1_TX_D_P[4] AE28 output 2.5 V 71
GPIO1_RX_D_P[4] AN30 input 2.5 V 72
GPIO1_TX_D_N[4] AE29 output 2.5 V 73
GPIO1_RX_D_N[4] AP30 input 2.5 V 74
GPIO1_TX_D_P[5] AE26 output 2.5 V 77
GPIO1_RX_D_P[5] AM34 input 2.5 V 78
GPIO1_TX_D_N[5] AF26 output 2.5 V 79
GPIO1_RX_D_N[5] AM35 input 2.5 V 80
GPIO1_TX_D_P[6] AG31 output 2.5 V 83
GPIO1_RX_D_P[6] AM31 input 2.5 V 84
GPIO1_TX_D_N[6] AG32 output 2.5 V 85
GPIO1_RX_D_N[6] AN31 input 2.5 V 86
GPIO1_TX_D_P[7] AG29 output 2.5 V 89
GPIO1_RX_D_P[7] AN33 input 2.5 V 90
GPIO1_TX_D_N[7] AH29 output 2.5 V 91
GPIO1_RX_D_N[7] AP34 input 2.5 V 92
GPIO1_CLK_OUT_P[1] AG28 output 2.5 V 95
GPIO1_CLK_IN_P[1] AB34 input 2.5 V 96
GPIO1_CLK_OUT_N[1] AH28 output 2.5 V 97
GPIO1_CLK_IN_N[1] AA35 input 2.5 V 98
GPIO1_TX_D_P[8] AC28 output 2.5 V 101
GPIO1_RX_D_P[8] AP32 input 2.5 V 102
GPIO1_TX_D_N[8] AC29 output 2.5 V 103
GPIO1_RX_D_N[8] AR32 input 2.5 V 104
GPIO1_TX_D_P[9] AJ29 output 2.5 V 107
GPIO1_RX_D_P[9] AR31 input 2.5 V 108
GPIO1_TX_D_N[9] AK29 output 2.5 V 109
GPIO1_RX_D_N[9] AT30 input 2.5 V 110
GPIO1_TX_D_P[10] AD30 output 2.5 V 113
GPIO1_RX_D_P[10] AT33 input 2.5 V 114
GPIO1_TX_D_N[10] AD31 output 2.5 V 115
GPIO1_RX_D_N[10] AU33 input 2.5 V 116
GPIO1_TX_D_P[11] AK32 output 2.5 V 119
GPIO1_RX_D_P[11] AU34 input 2.5 V 120
GPIO1_TX_D_N[11] AL32 output 2.5 V 121
GPIO1_RX_D_N[11] AV34 input 2.5 V 122
GPIO1_TX_D_P[12] AG27 output 2.5 V 125
GPIO1_RX_D_P[12] AT32 input 2.5 V 126
GPIO1_TX_D_N[12] AH27 output 2.5 V 127
GPIO1_RX_D_N[12] AU32 input 2.5 V 128
GPIO1_TX_D_P[13] AK31 output 2.5 V 131
GPIO1_RX_D_P[13] AT31 input 2.5 V 132
GPIO1_TX_D_N[13] AL31 output 2.5 V 133
GPIO1_RX_D_N[13] AU31 input 2.5 V 134
GPIO1_TX_D_P[14] AJ31 output 2.5 V 137
GPIO1_RX_D_P[14] AP35 input 2.5 V 138
GPIO1_TX_D_N[14] AH30 output 2.5 V 139
GPIO1_RX_D_N[14] AR35 input 2.5 V 140
GPIO1_TX_D_P[15] AL29 output 2.5 V 143
GPIO1_RX_D_P[15] AN32 input 2.5 V 144
GPIO1_TX_D_N[15] AM29 output 2.5 V 145
GPIO1_RX_D_N[15] AP33 input 2.5 V 146
GPIO1_TX_D_P[16] AK30 output 2.5 V 149
GPIO1_RX_D_P[16] AT34 input 2.5 V 150
GPIO1_TX_D_N[16] AL30 output 2.5 V 151
GPIO1_RX_D_N[16] AR34 input 2.5 V 152
GPIO1_CLK_OUT_P[2] AG34 output 2.5 V 155
GPIO1_CLK_IN_P[2] AF34 input 2.5 V 156
GPIO1_CLK_OUT_N[2] AG35 output 2.5 V 157
GPIO1_CLK_IN_N[2] AE35 input 2.5 V 158