DE2_115_SOPC

2012.06.14.19:52:52 Datasheet
Overview
  clk_50  DE2_115_SOPC
   sdram
 zs_addr  
 zs_ba  
 zs_cas_n  
 zs_cke  
 zs_cs_n  
 zs_dq  
 zs_dqm  
 zs_ras_n  
 zs_we_n  
   key
 in_port  
 in_port  
 out_port  
 in_port  
 out_port  
 out_port  
   lcd
 LCD_data  
 LCD_E  
 LCD_RS  
 LCD_RW  
Processor
   cpu Nios II 10.0
All Components
   cpu altera_nios2 10.0
   sysid altera_avalon_sysid 10.0
   timer altera_avalon_timer 10.0
   clock_crossing_io altera_avalon_clock_crossing 10.0
   sdram altera_avalon_new_sdram_controller 10.0
   key altera_avalon_pio 10.0
   sma_in altera_avalon_pio 10.0
   sma_out altera_avalon_pio 10.0
   sw altera_avalon_pio 10.0
   ledg altera_avalon_pio 10.0
   ledr altera_avalon_pio 10.0
   lcd altera_avalon_lcd_16207 10.0
   sram TERASIC_SRAM 1.0
   seg7 SEG7_IF 1.0
   jtag_uart altera_avalon_jtag_uart 10.0
   pll altpll 10.0
   usb ISP1362_IF 1.0
   timer_stamp altera_avalon_timer 10.0
   vpg VGA_NIOS_CTRL 1.0
   tri_state_bridge_0 altera_avalon_tri_state_bridge 10.0
Memory Map
cpu
 instruction_master  data_master
  cpu
jtag_debug_module  0x08000800 0x08000800
  sysid
control_slave  0x09200070
  timer
s1  0x08001020
  sdram
s1  0x00000000 0x00000000
  key
s1  0x09200020
  sma_in
s1  0x08001040
  sma_out
s1  0x08001050
  sw
s1  0x09200030
  ledg
s1  0x09200040
  ledr
s1  0x09200050
  lcd
control_slave  0x09200060
  sram
avalon_slave  0x08200000 0x08200000
  seg7
avalon_slave  0x09200000
  jtag_uart
avalon_jtag_slave  0x08001070
  pll
pll_slave  0x08001060
  usb
hc  0x08001078
dc  0x08001080
  timer_stamp
s1  0x08001000
  vpg
s1  0x09000000
  cfi_flash
s1  0x0a000000 0x0a000000

clk_50

clock_source v10.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cpu

altera_nios2 v10.0
pll c0   cpu
  clk
d_irq   timer
  irq
data_master  
  s1
data_master   clock_crossing_io
  s1
instruction_master   sdram
  s1
data_master  
  s1
d_irq   key
  irq
data_master   sma_in
  s1
data_master   sma_out
  s1
d_irq   sw
  irq
instruction_master   sram
  avalon_slave
data_master  
  avalon_slave
data_master   jtag_uart
  avalon_jtag_slave
d_irq  
  irq
data_master   pll
  pll_slave
data_master   usb
  hc
d_irq  
  hc_irq
data_master  
  dc
d_irq  
  dc_irq
data_master   timer_stamp
  s1
d_irq  
  irq
instruction_master   tri_state_bridge_0
  avalon_slave
data_master  
  avalon_slave


Parameters

userDefinedSettings
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSets 0
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_interruptControllerType Internal
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bigEndian false
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave cfi_flash.s1
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _8
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
internalIrqMaskSystemInfo 127
instSlaveMapParam <address-map><slave name='sdram.s1' start='0x0' end='0x8000000' /><slave name='cpu.jtag_debug_module' start='0x8000800' end='0x8001000' /><slave name='sram.avalon_slave' start='0x8200000' end='0x8400000' /><slave name='cfi_flash.s1' start='0xA000000' end='0xA800000' /></address-map>
instAddrWidth 28
impl Fast
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave sdram.s1
exceptionOffset 32
deviceFeaturesSystemInfo M512_MEMORY 0 M4K_MEMORY 0 M9K_MEMORY 1 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 1 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0
deviceFamilyName Cyclone IV E
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _2048
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
dataSlaveMapParam <address-map><slave name='sdram.s1' start='0x0' end='0x8000000' /><slave name='cpu.jtag_debug_module' start='0x8000800' end='0x8001000' /><slave name='timer_stamp.s1' start='0x8001000' end='0x8001020' /><slave name='timer.s1' start='0x8001020' end='0x8001040' /><slave name='sma_in.s1' start='0x8001040' end='0x8001050' /><slave name='sma_out.s1' start='0x8001050' end='0x8001060' /><slave name='pll.pll_slave' start='0x8001060' end='0x8001070' /><slave name='jtag_uart.avalon_jtag_slave' start='0x8001070' end='0x8001078' /><slave name='usb.hc' start='0x8001078' end='0x8001080' /><slave name='usb.dc' start='0x8001080' end='0x8001088' /><slave name='sram.avalon_slave' start='0x8200000' end='0x8400000' /><slave name='clock_crossing_io.s1' start='0x9000000' end='0x9400000' /><slave name='cfi_flash.s1' start='0xA000000' end='0xA800000' /></address-map>
dataAddrWidth 28
cpuReset false
cpuID 0
clockFrequency 100000000
breakSlave cpu.jtag_debug_module
breakOffset 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CPU_IMPLEMENTATION "fast"
BIG_ENDIAN 0
CPU_FREQ 100000000u
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
INITDA_SUPPORTED
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x20
RESET_ADDR 0xa000000
BREAK_ADDR 0x8000820
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
INST_ADDR_WIDTH 28
DATA_ADDR_WIDTH 28
NUM_OF_SHADOW_REG_SETS 0

sysid

altera_avalon_sysid v10.0
clock_crossing_io m1   sysid
  control_slave
pll c2  
  clk


Parameters

id 1457883068
timestamp 1339674710
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ID 1457883068u
TIMESTAMP 1339674710u

timer

altera_avalon_timer v10.0
cpu d_irq   timer
  irq
data_master  
  s1
pll c2  
  clk


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 10000000
timeoutPulseOutput false
timerPreset CUSTOM
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 1
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 10000000u
LOAD_VALUE 9999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 1000u

clock_crossing_io

altera_avalon_clock_crossing v10.0
cpu data_master   clock_crossing_io
  s1
pll c0  
  clk_s1
c2  
  clk_m1
m1   sysid
  control_slave
m1   key
  s1
m1   sw
  s1
m1   ledg
  s1
m1   ledr
  s1
m1   lcd
  control_slave
m1   seg7
  avalon_slave
m1   vpg
  s1


Parameters

dataWidth 32
downstreamFIFODepth 32
downstreamUseRegister false
masterSyncDepth 3
maxBurstSize 8
slaveAddressWidth 20
slaveSyncDepth 3
upstreamFIFODepth 256
upstreamUseRegister false
useBurstCount false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

sdram

altera_avalon_new_sdram_controller v10.0
cpu instruction_master   sdram
  s1
data_master  
  s1
pll c0  
  clk


Parameters

TAC 5.5
TMRD 3
TRCD 20.0
TRFC 70.0
TRP 20.0
TWR 14.0
casLatency 3
clockRate 100000000
columnWidth 10
dataWidth 32
generateSimulationModel true
initNOPDelay 0.0
initRefreshCommands 2
masteredTristateBridgeSlave
model custom
numberOfBanks 4
numberOfChipSelects 1
pinsSharedViaTriState false
powerUpDelay 100.0
refreshPeriod 15.625
registerDataIn true
rowWidth 13
size 134217728
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

REGISTER_DATA_IN 1
SIM_MODEL_BASE 1
SDRAM_DATA_WIDTH 32
SDRAM_ADDR_WIDTH 25
SDRAM_ROW_WIDTH 13
SDRAM_COL_WIDTH 10
SDRAM_NUM_CHIPSELECTS 1
SDRAM_NUM_BANKS 4
REFRESH_PERIOD 15.625
POWERUP_DELAY 100.0
CAS_LATENCY 3
T_RFC 70.0
T_RP 20.0
T_MRD 3
T_RCD 20.0
T_AC 5.5
T_WR 14.0
INIT_REFRESH_COMMANDS 2
INIT_NOP_DELAY 0.0
SHARED_DATA 0
STARVATION_INDICATOR 0
TRISTATE_BRIDGE_SLAVE ""
IS_INITIALIZED 1
SDRAM_BANK_WIDTH 2
CONTENTS_INFO ""

key

altera_avalon_pio v10.0
cpu d_irq   key
  irq
clock_crossing_io m1  
  s1
pll c2  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 10000000
direction Input
edgeType FALLING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 4
RESET_VALUE 0x0
EDGE_TYPE "FALLING"
IRQ_TYPE "EDGE"
FREQ 10000000u

sma_in

altera_avalon_pio v10.0
cpu data_master   sma_in
  s1
pll c0  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

sma_out

altera_avalon_pio v10.0
cpu data_master   sma_out
  s1
pll c0  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

sw

altera_avalon_pio v10.0
cpu d_irq   sw
  irq
clock_crossing_io m1  
  s1
pll c2  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 10000000
direction Input
edgeType FALLING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 18
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 18
RESET_VALUE 0x0
EDGE_TYPE "FALLING"
IRQ_TYPE "EDGE"
FREQ 10000000u

ledg

altera_avalon_pio v10.0
clock_crossing_io m1   ledg
  s1
pll c2  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 10000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 9
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 9
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 10000000u

ledr

altera_avalon_pio v10.0
clock_crossing_io m1   ledr
  s1
pll c2  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 10000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 18
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 18
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 10000000u

lcd

altera_avalon_lcd_16207 v10.0
clock_crossing_io m1   lcd
  control_slave
pll c2  
  clk


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

sram

TERASIC_SRAM v1.0
cpu instruction_master   sram
  avalon_slave
data_master  
  avalon_slave
pll c0  
  clock_reset


Parameters

DATA_BITS 16
ADDR_BITS 20
AUTO_CLOCK_RESET_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

seg7

SEG7_IF v1.0
clock_crossing_io m1   seg7
  avalon_slave
pll c2  
  clock_sink


Parameters

SEG7_NUM 8
ADDR_WIDTH 3
DEFAULT_ACTIVE 1
LOW_ACTIVE 1
AUTO_CLOCK_SINK_CLOCK_RATE 10000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

jtag_uart

altera_avalon_jtag_uart v10.0
cpu data_master   jtag_uart
  avalon_jtag_slave
d_irq  
  irq
pll c0  
  clk


Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 64
writeIRQThreshold 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

pll

altpll v10.0
cpu data_master   pll
  pll_slave
clk_50 clk  
  inclk_interface
c0   cpu
  clk
c0   sdram
  clk
c0   sram
  clock_reset
c0   sma_in
  clk
c0   sma_out
  clk
c0   clock_crossing_io
  clk_s1
c2  
  clk_m1
c2   timer
  clk
c2   sysid
  clk
c2   key
  clk
c2   sw
  clk
c2   ledg
  clk
c2   ledr
  clk
c2   lcd
  clk
c2   seg7
  clock_sink
c0   usb
  hc_clock
c0  
  dc_clock
c0   timer_stamp
  clk
c0   jtag_uart
  clk
c0   vpg
  s1_clock
c0   cfi_flash
  clk
c0   tri_state_bridge_0
  clk


Parameters

HIDDEN_CUSTOM_ELABORATION altpll_avalon_elaboration
HIDDEN_CUSTOM_POST_EDIT altpll_avalon_post_edit
INTENDED_DEVICE_FAMILY Cyclone IV E
WIDTH_CLOCK 5
WIDTH_PHASECOUNTERSELECT
PRIMARY_CLOCK
INCLK0_INPUT_FREQUENCY 20000
INCLK1_INPUT_FREQUENCY
OPERATION_MODE NORMAL
PLL_TYPE AUTO
QUALIFY_CONF_DONE
COMPENSATE_CLOCK CLK0
SCAN_CHAIN
GATE_LOCK_SIGNAL
GATE_LOCK_COUNTER
LOCK_HIGH
LOCK_LOW
VALID_LOCK_MULTIPLIER
INVALID_LOCK_MULTIPLIER
SWITCH_OVER_ON_LOSSCLK
SWITCH_OVER_ON_GATED_LOCK
ENABLE_SWITCH_OVER_COUNTER
SKIP_VCO
SWITCH_OVER_COUNTER
SWITCH_OVER_TYPE
FEEDBACK_SOURCE
BANDWIDTH
BANDWIDTH_TYPE AUTO
SPREAD_FREQUENCY
DOWN_SPREAD
SELF_RESET_ON_GATED_LOSS_LOCK
SELF_RESET_ON_LOSS_LOCK
CLK0_MULTIPLY_BY 2
CLK1_MULTIPLY_BY 2
CLK2_MULTIPLY_BY 1
CLK3_MULTIPLY_BY 1
CLK4_MULTIPLY_BY
CLK5_MULTIPLY_BY
CLK6_MULTIPLY_BY
CLK7_MULTIPLY_BY
CLK8_MULTIPLY_BY
CLK9_MULTIPLY_BY
EXTCLK0_MULTIPLY_BY
EXTCLK1_MULTIPLY_BY
EXTCLK2_MULTIPLY_BY
EXTCLK3_MULTIPLY_BY
CLK0_DIVIDE_BY 1
CLK1_DIVIDE_BY 1
CLK2_DIVIDE_BY 5
CLK3_DIVIDE_BY 2
CLK4_DIVIDE_BY
CLK5_DIVIDE_BY
CLK6_DIVIDE_BY
CLK7_DIVIDE_BY
CLK8_DIVIDE_BY
CLK9_DIVIDE_BY
EXTCLK0_DIVIDE_BY
EXTCLK1_DIVIDE_BY
EXTCLK2_DIVIDE_BY
EXTCLK3_DIVIDE_BY
CLK0_PHASE_SHIFT 0
CLK1_PHASE_SHIFT -1806
CLK2_PHASE_SHIFT 0
CLK3_PHASE_SHIFT 0
CLK4_PHASE_SHIFT
CLK5_PHASE_SHIFT
CLK6_PHASE_SHIFT
CLK7_PHASE_SHIFT
CLK8_PHASE_SHIFT
CLK9_PHASE_SHIFT
EXTCLK0_PHASE_SHIFT
EXTCLK1_PHASE_SHIFT
EXTCLK2_PHASE_SHIFT
EXTCLK3_PHASE_SHIFT
CLK0_DUTY_CYCLE 50
CLK1_DUTY_CYCLE 50
CLK2_DUTY_CYCLE 50
CLK3_DUTY_CYCLE 50
CLK4_DUTY_CYCLE
CLK5_DUTY_CYCLE
CLK6_DUTY_CYCLE
CLK7_DUTY_CYCLE
CLK8_DUTY_CYCLE
CLK9_DUTY_CYCLE
EXTCLK0_DUTY_CYCLE
EXTCLK1_DUTY_CYCLE
EXTCLK2_DUTY_CYCLE
EXTCLK3_DUTY_CYCLE
PORT_clkena0 PORT_UNUSED
PORT_clkena1 PORT_UNUSED
PORT_clkena2 PORT_UNUSED
PORT_clkena3 PORT_UNUSED
PORT_clkena4 PORT_UNUSED
PORT_clkena5 PORT_UNUSED
PORT_extclkena0
PORT_extclkena1
PORT_extclkena2
PORT_extclkena3
PORT_extclk0 PORT_UNUSED
PORT_extclk1 PORT_UNUSED
PORT_extclk2 PORT_UNUSED
PORT_extclk3 PORT_UNUSED
PORT_CLKBAD0 PORT_UNUSED
PORT_CLKBAD1 PORT_UNUSED
PORT_clk0 PORT_USED
PORT_clk1 PORT_USED
PORT_clk2 PORT_USED
PORT_clk3 PORT_USED
PORT_clk4 PORT_UNUSED
PORT_clk5 PORT_UNUSED
PORT_clk6
PORT_clk7
PORT_clk8
PORT_clk9
PORT_SCANDATA PORT_UNUSED
PORT_SCANDATAOUT PORT_UNUSED
PORT_SCANDONE PORT_UNUSED
PORT_SCLKOUT1
PORT_SCLKOUT0
PORT_ACTIVECLOCK PORT_UNUSED
PORT_CLKLOSS PORT_UNUSED
PORT_INCLK1 PORT_UNUSED
PORT_INCLK0 PORT_USED
PORT_FBIN PORT_UNUSED
PORT_PLLENA PORT_UNUSED
PORT_CLKSWITCH PORT_UNUSED
PORT_ARESET PORT_USED
PORT_PFDENA PORT_UNUSED
PORT_SCANCLK PORT_UNUSED
PORT_SCANACLR PORT_UNUSED
PORT_SCANREAD PORT_UNUSED
PORT_SCANWRITE PORT_UNUSED
PORT_ENABLE0
PORT_ENABLE1
PORT_LOCKED PORT_USED
PORT_CONFIGUPDATE PORT_UNUSED
PORT_FBOUT
PORT_PHASEDONE PORT_UNUSED
PORT_PHASESTEP PORT_UNUSED
PORT_PHASEUPDOWN PORT_UNUSED
PORT_SCANCLKENA PORT_UNUSED
PORT_PHASECOUNTERSELECT PORT_UNUSED
PORT_VCOOVERRANGE
PORT_VCOUNDERRANGE
DPA_MULTIPLY_BY
DPA_DIVIDE_BY
DPA_DIVIDER
VCO_MULTIPLY_BY
VCO_DIVIDE_BY
SCLKOUT0_PHASE_SHIFT
SCLKOUT1_PHASE_SHIFT
VCO_FREQUENCY_CONTROL
VCO_PHASE_SHIFT_STEP
USING_FBMIMICBIDIR_PORT
SCAN_CHAIN_MIF_FILE
AVALON_USE_SEPARATE_SYSCLK NO
HIDDEN_CONSTANTS CT#CLK2_DIVIDE_BY 5 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 2 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -1806 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#CLK3_MULTIPLY_BY 1 CT#PORT_LOCKED PORT_USED
HIDDEN_PRIVATES PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ3 25.00000000 PT#OUTPUT_FREQ2 10.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK e0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE 300.000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#PHASE_SHIFT1 -65.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE3 25.000000 PT#EFF_OUTPUT_FREQ_VALUE2 10.000000 PT#EFF_OUTPUT_FREQ_VALUE1 100.000000 PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK3 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1267186822954418.mif PT#ACTIVECLK_CHECK 0
HIDDEN_USED_PORTS UP#locked used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used
HIDDEN_IS_NUMERIC IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK2_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1
HIDDEN_MF_PORTS MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1
HIDDEN_IF_PORTS IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0}
HIDDEN_IS_FIRST_EDIT 0
AUTO_INCLK_INTERFACE_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone IV E
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

usb

ISP1362_IF v1.0
pll c0   usb
  hc_clock
c0  
  dc_clock
cpu data_master  
  hc
d_irq  
  hc_irq
data_master  
  dc
d_irq  
  dc_irq


Parameters

AUTO_HC_CLOCK_CLOCK_RATE 100000000
AUTO_DC_CLOCK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

timer_stamp

altera_avalon_timer v10.0
pll c0   timer_stamp
  clk
cpu data_master  
  s1
d_irq  
  irq


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 100000000
timeoutPulseOutput false
timerPreset CUSTOM
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 1
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 100000000u
LOAD_VALUE 99999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 1000u

vpg

VGA_NIOS_CTRL v1.0
pll c0   vpg
  s1_clock
clock_crossing_io m1  
  s1


Parameters

RAM_SIZE 307200
AUTO_S1_CLOCK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cfi_flash

altera_avalon_cfi_flash v10.0
pll c0   cfi_flash
  clk
tri_state_bridge_0 tristate_master  
  s1


Parameters

actualHoldTime 60.0
actualSetupTime 60.0
actualWaitTime 160.0
addressWidth 23
clockRate 100000000
corePreset CUSTOM
dataWidth 8
holdTime 60
setupTime 60
sharedPorts s1/data
timingUnits NS
waitTime 160
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

SETUP_VALUE 60
WAIT_VALUE 160
HOLD_VALUE 60
TIMING_UNITS "ns"
SIZE 8388608u

tri_state_bridge_0

altera_avalon_tri_state_bridge v10.0
pll c0   tri_state_bridge_0
  clk
cpu instruction_master  
  avalon_slave
data_master  
  avalon_slave
tristate_master   cfi_flash
  s1


Parameters

registerIncomingSignals true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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