//--------------------------
// Datum: Nov 11, 2007
// Auteur: fotoopa
// Copyright (c) 2007 http://www.pbase.com/fotoopa
// Deze routines mogen enkel gebruikt worden voor persoonlijke doeleinden en
// mits behoud van deze copyright teksten.
//--------------------------

// Last update: 20071017
// udate TXD en RXD pinnen confor betekenis ( signalen tov FDI chip)
// set_location_assignment PIN_42 -to TXD
// set_location_assignment PIN_49 -to RXD
// set_location_assignment PIN_47 -to CTS
// set_location_assignment PIN_38 -to RTS
// set_location_assignment PIN_48 -to DTR
// set_location_assignment PIN_40 -to DSR

// Last update: 20071010
// set_location_assignment PIN_34 -to MSB_G
// set_location_assignment PIN_35 -to LSB_G
// set_location_assignment PIN_36 -to MSB_R
// set_location_assignment PIN_37 -to LSB_R

// Last update: 20071009
// set_location_assignment PIN_77 -to CS
// set_location_assignment PIN_50 -to CS_FLASH

module vga_data
	(
	input				OSC,
	input				OSCO,
	input				RXD,
	input				RTS,
	input				CTS,
	input				DSR,
	input				DTR,
	input				DCD,
	input				RI,
	input				DS1,
	input				DS2,
	input				DS3,
	input				DS4,
	input				DS5,
	input				DS6,
	input				DS7,
	input				DS8,
	input				MS1,
	input				MS2,
	input				MS3,
	input				MS4,
	input				MS5,
	input				MS6,
	input				PS2_DATA,
	input				PS2_CLK,
	output				CON1,
	output				CON2,
	output				CON3,
	output				CON4,
	output				CON5,
	output				CON6,
	output				CON7,
	output				CON8,
	output				CON9,
	output				CON10,
	output				CON11,
	output				CON12,
	output				CON13,
	output				CON14,
	output				CON15,
	output				CON16,
	output				CON17,
	output				CON18,
	output				CON19,
	output				CON20,
	input				DI,
	input				DO,
	input				TSOP,
	output				TXD,
	output				CS_FLASH,
	output				LD1,
	output				LD2,
	output				LD3,
	output				LD4,
	output				LD5,
	output				LD6,
	output				LD7,
	output				LD8,
	output				LD9,
	output				LD10,
	output				LD11,
	output				LD12,
	output				LD13,
	output				LD14,
	output				LD15,
	output				LD16,
	output				SCK,
	output				LEDA,
	output				LEDB,
	output	reg			SEG_A,
	output	reg			SEG_B,
	output	reg			SEG_C,
	output	reg			SEG_D,
	output				LSB_R,
	output				MSB_R,
	output				LSB_G,
	output				MSB_G,
	output				LSB_B,
	output				MSB_B,
	output	reg			A,
	output	reg			B,
	output	reg			C,
	output	reg			D,
	output	reg			E,
	output	reg			F,
	output	reg			G,
	output	 			DP,
	output				HS,
	output				VS
	);          
	
assign		CS_FLASH	= 1'b1;
assign		SCK			= 1'b0;
assign		TXD			= 1'b1;
// led enables
assign		LEDA		= 1'b1;
assign		LEDB		= 1'b1;
// Led outputs
assign		LD1			= leddisp_reg[0];
assign		LD2			= leddisp_reg[1];
assign		LD3			= leddisp_reg[2];
assign		LD4			= leddisp_reg[3];
assign		LD5			= leddisp_reg[4];
assign		LD6			= leddisp_reg[5];
assign		LD7			= leddisp_reg[6];
assign		LD8			= leddisp_reg[7];
assign		LD9			= leddisp_reg[8];
assign		LD10		= leddisp_reg[9];
assign		LD11		= leddisp_reg[10];
assign		LD12		= leddisp_reg[11];
assign		LD13		= leddisp_reg[12];
assign		LD14		= leddisp_reg[13];
assign		LD15		= leddisp_reg[14];
assign		LD16		= leddisp_reg[15];
// connector outputs    
assign		CON1		= 1'b0;
assign		CON2		= 1'b0;
assign		CON3		= 1'b0;
assign		CON4		= 1'b0;
assign		CON5		= 1'b0;
assign		CON6		= 1'b0;
assign		CON7		= 1'b0;
assign		CON8		= 1'b0;
assign		CON9		= 1'b0;
assign		CON10		= 1'b0;
assign		CON11		= 1'b0;
assign		CON12		= 1'b0;
assign		CON13		= 1'b0;
assign		CON14		= 1'b0;
assign		CON15		= 1'b0;
assign		CON16		= 1'b0;
assign		CON17		= 1'b0;
assign		CON18		= 1'b0;
assign		CON19		= 1'b0;
assign		CON20		= 1'b0;
// VGA output
assign		LSB_R		= R_out[0];
assign		MSB_R		= R_out[1];
assign		LSB_G		= G_out[0];
assign		MSB_G		= G_out[1];
assign		LSB_B		= B_out[0];
assign		MSB_B		= B_out[1];
assign		HS 			= h_sync;
assign		VS 			= v_sync;

assign		DP			= 1'b0;

reg		[6:0]		hex;
reg		[7:0]		ascii;
reg		[7:0]		ascii_reg;
reg		[1:0]		state;
reg		[3:0]		ram_state;
reg		[1:0]		wr_state;
reg					wr_state_ena;
reg					ram_state_ena;
reg		[1:0]		clk_10ms_reg;
reg					flank_10ms_reg;
reg		[11:0]		ram_adr;
reg	 				ram_wr;
reg		[7:0]		ram_data;
reg	 				ascii_ena;
reg		[3:0]		digita;			// sec aanduiding op VGA monitor
reg		[3:0]		digitb;			// sec aanduiding op VGA monitor
reg		[3:0]		digitc;			// min aanduiding op VGA monitor
reg		[3:0]		digitd;			// min aanduiding op VGA monitor
reg		[3:0]		digite;			// uur aanduiding op VGA monitor
reg		[3:0]		digitf;			// uur aanduiding op VGA monitor
reg		[3:0]		blink_cnt;		// dubbelpunt blinking op VGA monitor
reg		[3:0]		bin_in;
reg		[3:0]		bin_lcd;
reg		[15:0]		led_reg;
reg		[15:0]		leddisp_reg;

// wire connectie's tussen de modules
wire	[1:0]		R_out;			// rood
wire	[1:0]		G_out;			// groen
wire	[1:0]		B_out;			// blauw
wire	 			v_sync;			// horizontale sync
wire	 			h_sync;			// vertikale sync
wire	 			disp;			// display enable LCD 4.3"
wire				clk_vga;		// clock  LCD 4.3"
wire	 			resetn;			// algemene powerup reset, actief laag.

parameter	LED_ZONE1_BEG		= 12'h406;
parameter	LED_ZONE2_BEG		= 12'h415;
parameter	LED_ZONE1_END		= LED_ZONE1_BEG+(8*LED_REGEL_OFFSET);
parameter	LED_ZONE2_END		= LED_ZONE2_BEG+(8*LED_REGEL_OFFSET);
parameter	LED_REGEL_OFFSET	= 12'h080;
parameter	RAM_MAX				= 12'hfff;
display_driver vga640x480
	(
	.clk_vga	(clk_vga),
	.resetn		(resetn),
	.dpram_wr	(ram_wr),	
	.dpram_data	(ram_data),	
	.dpram_adr	(ram_adr),	
	.h_sync		(h_sync),	
	.v_sync		(v_sync),
	.disp		(disp),
	.R_color	(R_out),
	.G_color	(G_out),
	.B_color	(B_out)
	);

Reset_Delay rst(
	.iCLK	(clk_vga),
	.oRESET	(resetn)		// algemene reset
	);

pll_lcd vga_pll(
	.inclk0(OSC),
	.c0(clk_vga)			// vga clk
);

clock_module sys_clocks
	(
	.clk_50mhz	(OSC),
	.clk_1us	(clk_1us),
	.clk_10us	(clk_10us),
	.clk_100us	(clk_100us),
	.clk_1ms	(clk_1ms),
	.clk_10ms	(clk_10ms),
	.clk_100ms	(clk_100ms),
	.clk_1s		(clk_1s)
	);
always @(posedge clk_100ms)
leddisp_reg <= leddisp_reg+1;

// seconden teller tot 5 digits (tot 99.999) als bcd waarde.
always @(posedge clk_1s)
begin 
if (!MS2) if(digitb != 5) digitb <= digitb + 1; else digitb <= 0;
if (!MS3) if(digitc != 9) digitc <= digitc + 1; else digitc <= 0;
if (!MS4) if(digitd != 5) digitd <= digitd + 1; else digitd <= 0;
if (!MS5) if(digite == 9) digite <= 0; 
	else 
		if((digite == 3)&(digitf == 2)) digite <= 0;
			else
			digite <= digite+1;
if (!MS6) if(digitf == 2) digitf <= 0;
	else if((digitf == 1) & (digite >= 3))
			begin 
				digitf <= 2;
				digite <= 0;
			end else digitf <= digitf+1;
if (MS2 & MS3 & MS4 & MS5 & MS6)
begin
	if(digita != 9) digita <= digita + 1;
	else  
	begin 
		digita <= 0;
		if(digitb != 5) digitb <= digitb + 1; 
		else  
		begin 
			digitb <= 0;
			if(digitc != 9) digitc <= digitc + 1;
			else 
			begin
				digitc <= 0; 
				if(digitd != 5) digitd <= digitd + 1; 
				else  
				begin 
					digitd <= 0;
					if(digite != 9) digite <= digite + 1;
					if(digite == 9) 
						begin
							digite <= 0;
							digitf <= digitf + 1;
						end
					if((digitf == 2) & (digite == 3))
						begin
							digite <= 0; 
							digitf <= 0; 
						end
				end
			end
		end
	end
end
end

always @ (posedge clk_100ms)
begin
	if (blink_cnt == 9)	
		blink_cnt <= 0;
	else
		blink_cnt <= blink_cnt+1;
end

always @ (posedge clk_vga)
begin
	clk_10ms_reg[1:0]	<= {clk_10ms_reg[0],clk_10ms};			// ander clock domain, hersync!
	flank_10ms_reg 		<= !clk_10ms_reg[1] & clk_10ms_reg[0];
	
	case (ram_state)
	0: 	begin
			if (flank_10ms_reg) // 100 x per seconde refresch schermdata
				begin
					wr_state_ena	<= 1;
					ram_adr			<= 15;
					bin_lcd 		<= digita[3:0];
					ram_state_ena 	<= 0;
					ram_state		<= 1;
				end
		end
	1: 	begin
			if (ram_state_ena) 
				begin
					wr_state_ena	<= 1;
					ram_adr			<= 14;
					bin_lcd 		<= digitb[3:0];
					ram_state_ena 	<= 0;
					ram_state 		<= 2;
				end
		end
	2: 	begin
			if (ram_state_ena) 
				begin
					wr_state_ena	<= 1;
					ram_adr			<= 12;
					bin_lcd 		<= digitc[3:0];
					ram_state_ena 	<= 0;
					ram_state 		<= 3;
				end
		end
	3: 	begin
			if (ram_state_ena) 
				begin
					wr_state_ena	<= 1;
					ram_adr		 	<= 11;
					bin_lcd 		<= digitd[3:0];
					ram_state		<= 4;
					ram_state_ena 	<= 0;
				end
		end
	4: 	begin
			if (ram_state_ena) 
				begin
					wr_state_ena	<= 1;
					ram_adr			<= 9;
					bin_lcd 		<= digite[3:0];
					ram_state_ena 	<= 0;
					ram_state 		<= 5;
				end
		end
	5: 	begin
			if (ram_state_ena) 
				begin
					wr_state_ena	<= 1;
					ram_adr		 	<= 8;
					bin_lcd 		<= digitf[3:0];
					ram_state		<= 6;
					ram_state_ena 	<= 0;
				end
		end
	6: 	begin
			if (ram_state_ena) 
				begin
					ascii_ena		<= 1;
					ram_adr		 	<= 10;
						if (blink_cnt[3])
							ascii_reg 	<= 8'h3a;
						else 
							ascii_reg 	<= 8'h20;
					ram_state		<= 7;
					ram_state_ena 	<= 0;
				end
		end

	7: 	begin
			if (ram_state_ena)
				begin
					if  (!MS1)
						begin
							ascii_ena		<= 1;
							ram_adr		 	<= 16;
							ascii_reg 		<= 8'h20;
							ram_state		<= 8;
							ram_state_ena 	<= 0;
						end 
					else
						begin
							ram_state		<= 9;
						end
				end
		end
	8: 	begin
			if (ram_state_ena)
			begin
				if (ram_adr <= RAM_MAX-1) 
					begin
						ascii_ena		<= 1;
						ram_adr		 	<= ram_adr+1;
						ascii_reg 		<= 8'h20;
						ram_state_ena 	<= 0;
					end
				else
					begin
						ram_state		<= 0;
						ram_state_ena 	<= 0;
					end
			end 
		end

	9: 	begin
			led_reg[15:0]	<= leddisp_reg;
			ram_adr		 	<= LED_ZONE1_BEG-LED_REGEL_OFFSET;
			ram_state		<= 10;
		end

	10:	begin
			if (ram_state_ena)
			begin
				ram_state_ena 	<= 0;
				if (led_reg[0])
					ascii_reg 		<= 8'h01;
				else
					ascii_reg 		<= 8'h20;
				ascii_ena			<= 1;
				led_reg[14:0]		<= {led_reg[15:1]};
				if (ram_adr == LED_ZONE1_END - LED_REGEL_OFFSET) 
					begin 
						ram_adr <= LED_ZONE2_BEG;
					end 
				else
					if (ram_adr == LED_ZONE2_END) 
						ram_state <= 0;
					else ram_adr <= ram_adr + LED_REGEL_OFFSET;
			end
		end

	endcase

	case (wr_state)

	0: 	begin
		if (wr_state_ena)
			begin
				wr_state 		<= 1;
				wr_state_ena 	<= 0;
			end
		if (ascii_ena)
			begin
				wr_state 	<= 2;
				ascii_ena 	<= 0;
				ram_data	<= ascii_reg;
			end
		end
	1: 	begin
			wr_state 		<= 2;
			ram_data		<= ascii;
		end
	2: 	begin 
			wr_state 		<= 3;
			ram_wr			<= 1;
		end
	3: 	begin
			ram_wr			<= 0;
			wr_state 		<= 0;
			ram_state_ena 	<= 1;
		end
	endcase
end

always @ (posedge clk_1ms)
begin
	state <= state + 1;
	case (state)
	0: 	begin
			SEG_A <= 0;
			SEG_B <= 1;
			SEG_C <= 0;
			SEG_D <= 0;
			bin_in <= digita[3:0];
		end
	1: 	begin
			SEG_A <= 1;
			SEG_B <= 0;
			SEG_C <= 0;
			SEG_D <= 0;
			bin_in <= digitb[3:0];
		end
	2: 	begin
			SEG_A <= 0;
			SEG_B <= 0;
			SEG_C <= 0;
			SEG_D <= 1;
			bin_in <= digitc[3:0];
		end
	3: 	begin
			SEG_A <= 0;
			SEG_B <= 0;
			SEG_C <= 1;
			SEG_D <= 0;
			bin_in <= digitd[3:0];
		end
	endcase
end

always @ (posedge clk_1ms)	// bin to hex 7 segment
begin
		{G,F,E,D,C,B,A} <= hex;
		case(bin_in)
		4'h1: hex = 7'b0000110;	    // ---A----
		4'h2: hex = 7'b1011011; 	// |	  |
		4'h3: hex = 7'b1001111; 	// F	 B
		4'h4: hex = 7'b1100110; 	// |	  |
		4'h5: hex = 7'b1101101; 	// ---G----
		4'h6: hex = 7'b1111101; 	// |	  |
		4'h7: hex = 7'b0000111; 	// E	 C
		4'h8: hex = 7'b1111111; 	// |	  |
		4'h9: hex = 7'b1101111; 	// ---D----
		4'ha: hex = 7'b1110111;
		4'hb: hex = 7'b1111100;
		4'hc: hex = 7'b0111001;
		4'hd: hex = 7'b1011110;
		4'he: hex = 7'b1111001;
		4'hf: hex = 7'b1110001;
		4'h0: hex = 7'b0111111;
		endcase
end

always @ (posedge clk_vga)	// bin to ascii
begin
		case(bin_lcd)
		4'h1: ascii = 8'h31;
		4'h2: ascii = 8'h32;
		4'h3: ascii = 8'h33;
		4'h4: ascii = 8'h34;
		4'h5: ascii = 8'h35;
		4'h6: ascii = 8'h36;
		4'h7: ascii = 8'h37;
		4'h8: ascii = 8'h38;
		4'h9: ascii = 8'h39;
		4'ha: ascii = 8'h41;
		4'hb: ascii = 8'h42;
		4'hc: ascii = 8'h43;
		4'hd: ascii = 8'h44;
		4'he: ascii = 8'h45;
		4'hf: ascii = 8'h46;
		4'h0: ascii = 8'h30;
		endcase
end

endmodule