# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		vga_data_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name TOP_LEVEL_ENTITY vga_data
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:54:06  NOVEMBER 11, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 9.0
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name VERILOG_FILE clock_module.v
set_global_assignment -name VERILOG_FILE display_driver.v
set_global_assignment -name VERILOG_FILE dpram_32x128.v
set_global_assignment -name VERILOG_FILE font_ram.v
set_global_assignment -name SOURCE_FILE inc_1x4.h
set_global_assignment -name SOURCE_FILE inc_2x6.h
set_global_assignment -name SOURCE_FILE inc_4x12.h
set_global_assignment -name SOURCE_FILE inc_6x16.h
set_global_assignment -name SOURCE_FILE inc_8x19.h
set_global_assignment -name SOURCE_FILE inc_16x38.h
set_global_assignment -name SOURCE_FILE inc_32x76.h
set_global_assignment -name VERILOG_FILE pll_lcd.v
set_global_assignment -name VERILOG_FILE Reset_Delay.v
set_global_assignment -name VERILOG_FILE vga_data.v
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name MISC_FILE "E:/vga_data_restored/vga_data.dpf"