Analysis & Synthesis report for vga_data Sat May 09 04:57:35 2009 Quartus II 64-Bit Version 9.0 Build 132 02/25/2009 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Analysis & Synthesis Source Files Read 5. Analysis & Synthesis Resource Usage Summary 6. Analysis & Synthesis Resource Utilization by Entity 7. Analysis & Synthesis RAM Summary 8. State Machine - |vga_data|wr_state 9. State Machine - |vga_data|ram_state 10. State Machine - |vga_data|display_driver:vga640x480|h_state 11. State Machine - |vga_data|display_driver:vga640x480|zone 12. Registers Removed During Synthesis 13. Removed Registers Triggering Further Register Optimizations 14. General Register Statistics 15. Multiplexer Restructuring Statistics (Restructuring Performed) 16. Source assignments for display_driver:vga640x480|font_ram:font5x7|altsyncram:altsyncram_component|altsyncram_bld1:auto_generated 17. Source assignments for display_driver:vga640x480|dpram_32x128:dp_ram1|altsyncram:altsyncram_component|altsyncram_1io1:auto_generated 18. Parameter Settings for User Entity Instance: Top-level Entity: |vga_data 19. Parameter Settings for User Entity Instance: display_driver:vga640x480 20. Parameter Settings for User Entity Instance: display_driver:vga640x480|font_ram:font5x7|altsyncram:altsyncram_component 21. Parameter Settings for User Entity Instance: display_driver:vga640x480|dpram_32x128:dp_ram1|altsyncram:altsyncram_component 22. Parameter Settings for User Entity Instance: pll_lcd:vga_pll|altpll:altpll_component 23. altsyncram Parameter Settings by Entity Instance 24. altpll Parameter Settings by Entity Instance 25. Port Connectivity Checks: "clock_module:sys_clocks" 26. Port Connectivity Checks: "display_driver:vga640x480|dpram_32x128:dp_ram1" 27. Port Connectivity Checks: "display_driver:vga640x480|font_ram:font5x7" 28. Port Connectivity Checks: "display_driver:vga640x480" 29. Analysis & Synthesis Messages 30. Analysis & Synthesis Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2009 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Sat May 09 04:57:35 2009 ; ; Quartus II 64-Bit Version ; 9.0 Build 132 02/25/2009 SJ Full Version ; ; Revision Name ; vga_data ; ; Top-level Entity Name ; vga_data ; ; Family ; Cyclone II ; ; Total logic elements ; 611 ; ; Total combinational functions ; 574 ; ; Dedicated logic registers ; 306 ; ; Total registers ; 306 ; ; Total pins ; 89 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 45,056 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Total PLLs ; 1 ; +------------------------------------+------------------------------------------+ +----------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +----------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +----------------------------------------------------------------+--------------------+--------------------+ ; Device ; EP2C20F484C7 ; ; ; Top-level entity name ; vga_data ; vga_data ; ; Family name ; Cyclone II ; Stratix II ; ; Use Generated Physical Constraints File ; Off ; ; ; Use smart compilation ; Off ; Off ; ; Maximum processors allowed for parallel compilation ; 1 ; 1 ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL93 ; VHDL93 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Parallel Synthesis ; Off ; Off ; ; DSP Block Balancing ; Auto ; Auto ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique ; Balanced ; Balanced ; ; Carry Chain Length ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Strict RAM Replacement ; Off ; Off ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto RAM to Logic Cell Conversion ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Timing-Driven Synthesis ; Off ; Off ; ; Show Parameter Settings Tables in Synthesis Report ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Synchronization Register Chain Length ; 2 ; 2 ; ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Auto Gated Clock Conversion ; Off ; Off ; ; Block Design Naming ; Auto ; Auto ; ; SDC constraint protection ; Off ; Off ; ; Synthesis Effort ; Auto ; Auto ; ; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ; ; Analysis & Synthesis Message Level ; Medium ; Medium ; +----------------------------------------------------------------+--------------------+--------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------+-----------------+----------------------------------------+-----------------------------------------------------------------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; +----------------------------------+-----------------+----------------------------------------+-----------------------------------------------------------------+ ; clock_module.v ; yes ; User Verilog HDL File ; E:/vga_data_restored/clock_module.v ; ; display_driver.v ; yes ; User Verilog HDL File ; E:/vga_data_restored/display_driver.v ; ; dpram_32x128.v ; yes ; User Wizard-Generated File ; E:/vga_data_restored/dpram_32x128.v ; ; font_ram.v ; yes ; User Wizard-Generated File ; E:/vga_data_restored/font_ram.v ; ; inc_16x38.h ; yes ; User File ; E:/vga_data_restored/inc_16x38.h ; ; pll_lcd.v ; yes ; User Wizard-Generated File ; E:/vga_data_restored/pll_lcd.v ; ; Reset_Delay.v ; yes ; User Verilog HDL File ; E:/vga_data_restored/Reset_Delay.v ; ; vga_data.v ; yes ; User Verilog HDL File ; E:/vga_data_restored/vga_data.v ; ; altsyncram.tdf ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/altsyncram.tdf ; ; stratix_ram_block.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; lpm_mux.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/lpm_mux.inc ; ; lpm_decode.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/lpm_decode.inc ; ; aglobal90.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/aglobal90.inc ; ; a_rdenreg.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/a_rdenreg.inc ; ; altrom.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/altrom.inc ; ; altram.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/altram.inc ; ; altdpram.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/altdpram.inc ; ; altqpram.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/altqpram.inc ; ; db/altsyncram_bld1.tdf ; yes ; Auto-Generated Megafunction ; E:/vga_data_restored/db/altsyncram_bld1.tdf ; ; font_rom16.hex ; yes ; Auto-Found Memory Initialization File ; E:/vga_data_restored/font_rom16.hex ; ; db/altsyncram_1io1.tdf ; yes ; Auto-Generated Megafunction ; E:/vga_data_restored/db/altsyncram_1io1.tdf ; ; ascii_ram_32x128.hex ; yes ; Auto-Found Memory Initialization File ; E:/vga_data_restored/ascii_ram_32x128.hex ; ; altpll.tdf ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/altpll.tdf ; ; stratix_pll.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/stratix_pll.inc ; ; stratixii_pll.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/stratixii_pll.inc ; ; cycloneii_pll.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/cycloneii_pll.inc ; +----------------------------------+-----------------+----------------------------------------+-----------------------------------------------------------------+ +---------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +---------------------------------------------+-----------------------------------------------+ ; Resource ; Usage ; +---------------------------------------------+-----------------------------------------------+ ; Estimated Total logic elements ; 611 ; ; ; ; ; Total combinational functions ; 574 ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 239 ; ; -- 3 input functions ; 98 ; ; -- <=2 input functions ; 237 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 420 ; ; -- arithmetic mode ; 154 ; ; ; ; ; Total registers ; 306 ; ; -- Dedicated logic registers ; 306 ; ; -- I/O registers ; 0 ; ; ; ; ; I/O pins ; 89 ; ; Total memory bits ; 45056 ; ; Total PLLs ; 1 ; ; Maximum fan-out node ; pll_lcd:vga_pll|altpll:altpll_component|_clk0 ; ; Maximum fan-out ; 189 ; ; Total fan-out ; 2841 ; ; Average fan-out ; 2.88 ; +---------------------------------------------+-----------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; +----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------+--------------+ ; |vga_data ; 574 (252) ; 306 (135) ; 45056 ; 0 ; 0 ; 0 ; 89 ; 0 ; |vga_data ; work ; ; |Reset_Delay:rst| ; 20 (20) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vga_data|Reset_Delay:rst ; work ; ; |clock_module:sys_clocks| ; 103 (103) ; 52 (52) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vga_data|clock_module:sys_clocks ; work ; ; |display_driver:vga640x480| ; 199 (199) ; 103 (103) ; 45056 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vga_data|display_driver:vga640x480 ; work ; ; |dpram_32x128:dp_ram1| ; 0 (0) ; 0 (0) ; 28672 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vga_data|display_driver:vga640x480|dpram_32x128:dp_ram1 ; work ; ; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 28672 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vga_data|display_driver:vga640x480|dpram_32x128:dp_ram1|altsyncram:altsyncram_component ; work ; ; |altsyncram_1io1:auto_generated| ; 0 (0) ; 0 (0) ; 28672 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vga_data|display_driver:vga640x480|dpram_32x128:dp_ram1|altsyncram:altsyncram_component|altsyncram_1io1:auto_generated ; work ; ; |font_ram:font5x7| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vga_data|display_driver:vga640x480|font_ram:font5x7 ; work ; ; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vga_data|display_driver:vga640x480|font_ram:font5x7|altsyncram:altsyncram_component ; work ; ; |altsyncram_bld1:auto_generated| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vga_data|display_driver:vga640x480|font_ram:font5x7|altsyncram:altsyncram_component|altsyncram_bld1:auto_generated ; work ; ; |pll_lcd:vga_pll| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vga_data|pll_lcd:vga_pll ; work ; ; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |vga_data|pll_lcd:vga_pll|altpll:altpll_component ; work ; +----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis RAM Summary ; +--------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+----------------------+ ; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; +--------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+----------------------+ ; display_driver:vga640x480|dpram_32x128:dp_ram1|altsyncram:altsyncram_component|altsyncram_1io1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 4096 ; 8 ; 4096 ; 8 ; 32768 ; ascii_ram_32x128.hex ; ; display_driver:vga640x480|font_ram:font5x7|altsyncram:altsyncram_component|altsyncram_bld1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 2048 ; 8 ; -- ; -- ; 16384 ; font_rom16.hex ; +--------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+----------------------+ Encoding Type: One-Hot +---------------------------------------------------------------------+ ; State Machine - |vga_data|wr_state ; +-------------+-------------+-------------+-------------+-------------+ ; Name ; wr_state.11 ; wr_state.10 ; wr_state.01 ; wr_state.00 ; +-------------+-------------+-------------+-------------+-------------+ ; wr_state.00 ; 0 ; 0 ; 0 ; 0 ; ; wr_state.01 ; 0 ; 0 ; 1 ; 1 ; ; wr_state.10 ; 0 ; 1 ; 0 ; 1 ; ; wr_state.11 ; 1 ; 0 ; 0 ; 1 ; +-------------+-------------+-------------+-------------+-------------+ Encoding Type: One-Hot +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |vga_data|ram_state ; +----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+ ; Name ; ram_state.1010 ; ram_state.1001 ; ram_state.1000 ; ram_state.0111 ; ram_state.0110 ; ram_state.0101 ; ram_state.0100 ; ram_state.0011 ; ram_state.0010 ; ram_state.0001 ; ram_state.0000 ; +----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+ ; ram_state.0000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; ram_state.0001 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; ; ram_state.0010 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; ; ram_state.0011 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; ; ram_state.0100 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; ; ram_state.0101 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; ; ram_state.0110 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ; ram_state.0111 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ; ram_state.1000 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ; ram_state.1001 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ; ram_state.1010 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+ Encoding Type: One-Hot +----------------------------------------------------------------+ ; State Machine - |vga_data|display_driver:vga640x480|h_state ; +------------+------------+------------+------------+------------+ ; Name ; h_state.11 ; h_state.10 ; h_state.01 ; h_state.00 ; +------------+------------+------------+------------+------------+ ; h_state.00 ; 0 ; 0 ; 0 ; 0 ; ; h_state.01 ; 0 ; 0 ; 1 ; 1 ; ; h_state.10 ; 0 ; 1 ; 0 ; 1 ; ; h_state.11 ; 1 ; 0 ; 0 ; 1 ; +------------+------------+------------+------------+------------+ Encoding Type: One-Hot +---------------------------------------------------------------------+ ; State Machine - |vga_data|display_driver:vga640x480|zone ; +-----------------+-----------------+-----------------+---------------+ ; Name ; zone.ZONE_ZWART ; zone.ZONE_IMAGE ; zone.ZONE_DOT ; +-----------------+-----------------+-----------------+---------------+ ; zone.ZONE_IMAGE ; 0 ; 0 ; 0 ; ; zone.ZONE_DOT ; 0 ; 1 ; 1 ; ; zone.ZONE_ZWART ; 1 ; 1 ; 0 ; +-----------------+-----------------+-----------------+---------------+ +--------------------------------------------------------------------------------------------------+ ; Registers Removed During Synthesis ; +-------------------------------------------+------------------------------------------------------+ ; Register name ; Reason for Removal ; +-------------------------------------------+------------------------------------------------------+ ; ascii[7] ; Stuck at GND due to stuck port data_in ; ; display_driver:vga640x480|char_reg[7] ; Lost fanout ; ; ram_data[7] ; Lost fanout ; ; ascii_reg[7] ; Lost fanout ; ; ascii[4..5] ; Merged with ascii[6] ; ; display_driver:vga640x480|R_color[0..1] ; Merged with display_driver:vga640x480|B_color[0] ; ; display_driver:vga640x480|G_color[0..1] ; Merged with display_driver:vga640x480|B_color[0] ; ; display_driver:vga640x480|B_color[1] ; Stuck at GND due to stuck port data_in ; ; ascii_reg[3..4] ; Merged with ascii_reg[1] ; ; ascii_reg[6] ; Merged with ascii_reg[2] ; ; blink_cnt[0] ; Merged with leddisp_reg[0] ; ; wr_state~16 ; Lost fanout ; ; wr_state~17 ; Lost fanout ; ; ram_state~90 ; Lost fanout ; ; ram_state~91 ; Lost fanout ; ; ram_state~92 ; Lost fanout ; ; ram_state~93 ; Lost fanout ; ; display_driver:vga640x480|h_state~26 ; Lost fanout ; ; display_driver:vga640x480|h_state~27 ; Lost fanout ; ; display_driver:vga640x480|zone.ZONE_IMAGE ; Lost fanout ; ; display_driver:vga640x480|zone.ZONE_ZWART ; Lost fanout ; ; clock_module:sys_clocks|clk_10ms_cnt[0] ; Merged with clock_module:sys_clocks|clk_100ms_cnt[0] ; ; clock_module:sys_clocks|clk_1ms_cnt[0] ; Merged with clock_module:sys_clocks|clk_100ms_cnt[0] ; ; clock_module:sys_clocks|clk_10ms_cnt[1] ; Merged with clock_module:sys_clocks|clk_100ms_cnt[1] ; ; clock_module:sys_clocks|clk_1ms_cnt[1] ; Merged with clock_module:sys_clocks|clk_100ms_cnt[1] ; ; clock_module:sys_clocks|clk_10ms_cnt[2] ; Merged with clock_module:sys_clocks|clk_100ms_cnt[2] ; ; display_driver:vga640x480|char_pnt[12] ; Lost fanout ; ; ascii_reg[5] ; Merged with ascii_reg[0] ; ; ascii_reg[2] ; Stuck at GND due to stuck port data_in ; ; Total Number of Removed Registers = 33 ; ; +-------------------------------------------+------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------+ ; Removed Registers Triggering Further Register Optimizations ; +---------------------------------------+---------------------------+----------------------------------------+ ; Register name ; Reason for Removal ; Registers Removed due to This Register ; +---------------------------------------+---------------------------+----------------------------------------+ ; ascii[7] ; Stuck at GND ; ascii_reg[7] ; ; ; due to stuck port data_in ; ; ; display_driver:vga640x480|char_reg[7] ; Lost Fanouts ; ram_data[7] ; +---------------------------------------+---------------------------+----------------------------------------+ +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 306 ; ; Number of registers using Synchronous Clear ; 32 ; ; Number of registers using Synchronous Load ; 3 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 172 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Restructuring Statistics (Restructuring Performed) ; +--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------+ ; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |vga_data|bin_in[0] ; ; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |vga_data|ram_data[0] ; ; 4:1 ; 15 bits ; 30 LEs ; 15 LEs ; 15 LEs ; Yes ; |vga_data|led_reg[3] ; ; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; Yes ; |vga_data|display_driver:vga640x480|v_flag_dot ; ; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; Yes ; |vga_data|display_driver:vga640x480|h_flag_dot ; ; 5:1 ; 6 bits ; 18 LEs ; 6 LEs ; 12 LEs ; Yes ; |vga_data|display_driver:vga640x480|v_dot_pix[1] ; ; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |vga_data|digitb[2] ; ; 5:1 ; 6 bits ; 18 LEs ; 6 LEs ; 12 LEs ; Yes ; |vga_data|display_driver:vga640x480|v_dot_cnt[0] ; ; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |vga_data|digitc[3] ; ; 6:1 ; 7 bits ; 28 LEs ; 7 LEs ; 21 LEs ; Yes ; |vga_data|display_driver:vga640x480|h_dot_reg[5] ; ; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |vga_data|digitd[3] ; ; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |vga_data|digitf[0] ; ; 6:1 ; 7 bits ; 28 LEs ; 7 LEs ; 21 LEs ; Yes ; |vga_data|display_driver:vga640x480|char_pnt[1] ; ; 6:1 ; 5 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |vga_data|display_driver:vga640x480|char_pnt[10] ; ; 11:1 ; 2 bits ; 14 LEs ; 2 LEs ; 12 LEs ; Yes ; |vga_data|ascii_reg[5] ; ; 13:1 ; 4 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |vga_data|bin_lcd[2] ; ; 8:1 ; 4 bits ; 20 LEs ; 4 LEs ; 16 LEs ; Yes ; |vga_data|digite[0] ; ; 13:1 ; 4 bits ; 32 LEs ; 8 LEs ; 24 LEs ; Yes ; |vga_data|ram_adr[5] ; ; 13:1 ; 5 bits ; 40 LEs ; 15 LEs ; 25 LEs ; Yes ; |vga_data|ram_adr[9] ; ; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |vga_data|wr_state~4 ; ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |vga_data|display_driver:vga640x480|zone~4 ; ; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |vga_data|display_driver:vga640x480|h_dot_cnt~11 ; ; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |vga_data|display_driver:vga640x480|h_state~10 ; ; 12:1 ; 3 bits ; 24 LEs ; 12 LEs ; 12 LEs ; No ; |vga_data|Selector28 ; ; 14:1 ; 2 bits ; 18 LEs ; 4 LEs ; 14 LEs ; No ; |vga_data|Selector27 ; +--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for display_driver:vga640x480|font_ram:font5x7|altsyncram:altsyncram_component|altsyncram_bld1:auto_generated ; +---------------------------------+--------------------+------+--------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+--------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+--------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for display_driver:vga640x480|dpram_32x128:dp_ram1|altsyncram:altsyncram_component|altsyncram_1io1:auto_generated ; +---------------------------------+--------------------+------+------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+------------------------------------------------------------------------+ +--------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: Top-level Entity: |vga_data ; +------------------+----------------------------------+--------------------+ ; Parameter Name ; Value ; Type ; +------------------+----------------------------------+--------------------+ ; LED_ZONE1_BEG ; 010000000110 ; Unsigned Binary ; ; LED_ZONE2_BEG ; 010000010101 ; Unsigned Binary ; ; LED_ZONE1_END ; 00000000000000000000100000000110 ; Unsigned Binary ; ; LED_ZONE2_END ; 00000000000000000000100000010101 ; Unsigned Binary ; ; LED_REGEL_OFFSET ; 000010000000 ; Unsigned Binary ; ; RAM_MAX ; 111111111111 ; Unsigned Binary ; +------------------+----------------------------------+--------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: display_driver:vga640x480 ; +----------------------+--------------+----------------------------------+ ; Parameter Name ; Value ; Type ; +----------------------+--------------+----------------------------------+ ; H_DISPLAY_PIXELS ; 640 ; Signed Integer ; ; H_SYNC ; 96 ; Signed Integer ; ; H_BLANKING ; 28 ; Signed Integer ; ; H_PIXEL_RAND_LINKS ; 16 ; Signed Integer ; ; H_PIXEL_TO_IMAGE_BEG ; 124 ; Signed Integer ; ; H_PIXEL_TO_CHAR_BEG ; 140 ; Signed Integer ; ; H_PIXEL_TO_CHAR_END ; 748 ; Signed Integer ; ; H_PIXEL_TO_IMAGE_END ; 764 ; Signed Integer ; ; H_TOTAL_PIXELS ; 800 ; Signed Integer ; ; H_DOT_PIXELS ; 2 ; Signed Integer ; ; H_DOTS_PER_CHAR ; 8 ; Signed Integer ; ; H_CHAR ; 38 ; Signed Integer ; ; V_DISPLAY_PIXELS ; 480 ; Signed Integer ; ; V_SYNC ; 2 ; Signed Integer ; ; V_BLANKING ; 30 ; Signed Integer ; ; V_PIXEL_RAND_BOVEN ; 14 ; Signed Integer ; ; V_PIXEL_TO_IMAGE_BEG ; 32 ; Signed Integer ; ; V_PIXEL_TO_CHAR_BEG ; 46 ; Signed Integer ; ; V_PIXEL_TO_CHAR_END ; 494 ; Signed Integer ; ; V_PIXEL_TO_IMAGE_END ; 512 ; Signed Integer ; ; V_TOTAL_PIXELS ; 525 ; Signed Integer ; ; V_DOT_PIXELS ; 2 ; Signed Integer ; ; V_DOTS_PER_CHAR ; 8 ; Signed Integer ; ; V_CHAR ; 16 ; Signed Integer ; ; V_FONT_BLANK_START ; 2 ; Signed Integer ; ; V_FONT_BLANK_END ; 3 ; Signed Integer ; ; V_FONT_CHAR_END ; 11 ; Signed Integer ; ; V_FONT_TOTAL ; 14 ; Signed Integer ; ; BYTES_PER_FONT ; 16 ; Signed Integer ; ; DPRAM_AND_MASK ; 111110000000 ; Unsigned Binary ; ; DPRAM_ADD_MASK ; 000010000000 ; Unsigned Binary ; ; ZONE_ZWART ; 11 ; Unsigned Binary ; ; ZONE_IMAGE ; 01 ; Unsigned Binary ; ; ZONE_DOT ; 10 ; Unsigned Binary ; ; R_image ; 00 ; Unsigned Binary ; ; G_image ; 00 ; Unsigned Binary ; ; B_image ; 00 ; Unsigned Binary ; ; R_dot_L ; 00 ; Unsigned Binary ; ; G_dot_L ; 00 ; Unsigned Binary ; ; B_dot_L ; 00 ; Unsigned Binary ; ; R_dot_H ; 11 ; Unsigned Binary ; ; G_dot_H ; 11 ; Unsigned Binary ; ; B_dot_H ; 01 ; Unsigned Binary ; ; ZWART_LEVEL ; 0 ; Signed Integer ; +----------------------+--------------+----------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: display_driver:vga640x480|font_ram:font5x7|altsyncram:altsyncram_component ; +------------------------------------+----------------------+-------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+----------------------+-------------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; SINGLE_PORT ; Untyped ; ; WIDTH_A ; 8 ; Signed Integer ; ; WIDTHAD_A ; 11 ; Signed Integer ; ; NUMWORDS_A ; 2048 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 1 ; Untyped ; ; WIDTHAD_B ; 1 ; Untyped ; ; NUMWORDS_B ; 1 ; Untyped ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; font_rom16.hex ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; CBXI_PARAMETER ; altsyncram_bld1 ; Untyped ; +------------------------------------+----------------------+-------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: display_driver:vga640x480|dpram_32x128:dp_ram1|altsyncram:altsyncram_component ; +------------------------------------+----------------------+-----------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+----------------------+-----------------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; DUAL_PORT ; Untyped ; ; WIDTH_A ; 8 ; Signed Integer ; ; WIDTHAD_A ; 12 ; Signed Integer ; ; NUMWORDS_A ; 4096 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 8 ; Signed Integer ; ; WIDTHAD_B ; 12 ; Signed Integer ; ; NUMWORDS_B ; 4096 ; Signed Integer ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK0 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; ascii_ram_32x128.hex ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; CBXI_PARAMETER ; altsyncram_1io1 ; Untyped ; +------------------------------------+----------------------+-----------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pll_lcd:vga_pll|altpll:altpll_component ; +-------------------------------+-------------------+----------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------------+-------------------+----------------------------------+ ; OPERATION_MODE ; NORMAL ; Untyped ; ; PLL_TYPE ; AUTO ; Untyped ; ; QUALIFY_CONF_DONE ; OFF ; Untyped ; ; COMPENSATE_CLOCK ; CLK0 ; Untyped ; ; SCAN_CHAIN ; LONG ; Untyped ; ; PRIMARY_CLOCK ; INCLK0 ; Untyped ; ; INCLK0_INPUT_FREQUENCY ; 20000 ; Signed Integer ; ; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; ; GATE_LOCK_SIGNAL ; NO ; Untyped ; ; GATE_LOCK_COUNTER ; 0 ; Untyped ; ; LOCK_HIGH ; 1 ; Untyped ; ; LOCK_LOW ; 1 ; Untyped ; ; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; ; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; ; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; ; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; ; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; ; SKIP_VCO ; OFF ; Untyped ; ; SWITCH_OVER_COUNTER ; 0 ; Untyped ; ; SWITCH_OVER_TYPE ; AUTO ; Untyped ; ; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; ; BANDWIDTH ; 0 ; Untyped ; ; BANDWIDTH_TYPE ; AUTO ; Untyped ; ; SPREAD_FREQUENCY ; 0 ; Untyped ; ; DOWN_SPREAD ; 0 ; Untyped ; ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; ; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; ; CLK9_MULTIPLY_BY ; 0 ; Untyped ; ; CLK8_MULTIPLY_BY ; 0 ; Untyped ; ; CLK7_MULTIPLY_BY ; 0 ; Untyped ; ; CLK6_MULTIPLY_BY ; 0 ; Untyped ; ; CLK5_MULTIPLY_BY ; 1 ; Untyped ; ; CLK4_MULTIPLY_BY ; 1 ; Untyped ; ; CLK3_MULTIPLY_BY ; 1 ; Untyped ; ; CLK2_MULTIPLY_BY ; 1 ; Untyped ; ; CLK1_MULTIPLY_BY ; 1 ; Untyped ; ; CLK0_MULTIPLY_BY ; 27 ; Signed Integer ; ; CLK9_DIVIDE_BY ; 0 ; Untyped ; ; CLK8_DIVIDE_BY ; 0 ; Untyped ; ; CLK7_DIVIDE_BY ; 0 ; Untyped ; ; CLK6_DIVIDE_BY ; 0 ; Untyped ; ; CLK5_DIVIDE_BY ; 1 ; Untyped ; ; CLK4_DIVIDE_BY ; 1 ; Untyped ; ; CLK3_DIVIDE_BY ; 1 ; Untyped ; ; CLK2_DIVIDE_BY ; 1 ; Untyped ; ; CLK1_DIVIDE_BY ; 1 ; Untyped ; ; CLK0_DIVIDE_BY ; 50 ; Signed Integer ; ; CLK9_PHASE_SHIFT ; 0 ; Untyped ; ; CLK8_PHASE_SHIFT ; 0 ; Untyped ; ; CLK7_PHASE_SHIFT ; 0 ; Untyped ; ; CLK6_PHASE_SHIFT ; 0 ; Untyped ; ; CLK5_PHASE_SHIFT ; 0 ; Untyped ; ; CLK4_PHASE_SHIFT ; 0 ; Untyped ; ; CLK3_PHASE_SHIFT ; 0 ; Untyped ; ; CLK2_PHASE_SHIFT ; 0 ; Untyped ; ; CLK1_PHASE_SHIFT ; 0 ; Untyped ; ; CLK0_PHASE_SHIFT ; 0 ; Untyped ; ; CLK5_TIME_DELAY ; 0 ; Untyped ; ; CLK4_TIME_DELAY ; 0 ; Untyped ; ; CLK3_TIME_DELAY ; 0 ; Untyped ; ; CLK2_TIME_DELAY ; 0 ; Untyped ; ; CLK1_TIME_DELAY ; 0 ; Untyped ; ; CLK0_TIME_DELAY ; 0 ; Untyped ; ; CLK9_DUTY_CYCLE ; 50 ; Untyped ; ; CLK8_DUTY_CYCLE ; 50 ; Untyped ; ; CLK7_DUTY_CYCLE ; 50 ; Untyped ; ; CLK6_DUTY_CYCLE ; 50 ; Untyped ; ; CLK5_DUTY_CYCLE ; 50 ; Untyped ; ; CLK4_DUTY_CYCLE ; 50 ; Untyped ; ; CLK3_DUTY_CYCLE ; 50 ; Untyped ; ; CLK2_DUTY_CYCLE ; 50 ; Untyped ; ; CLK1_DUTY_CYCLE ; 50 ; Untyped ; ; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; ; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; LOCK_WINDOW_UI ; 0.05 ; Untyped ; ; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; ; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; ; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; ; DPA_MULTIPLY_BY ; 0 ; Untyped ; ; DPA_DIVIDE_BY ; 1 ; Untyped ; ; DPA_DIVIDER ; 0 ; Untyped ; ; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; ; VCO_MULTIPLY_BY ; 0 ; Untyped ; ; VCO_DIVIDE_BY ; 0 ; Untyped ; ; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; ; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; ; VCO_MIN ; 0 ; Untyped ; ; VCO_MAX ; 0 ; Untyped ; ; VCO_CENTER ; 0 ; Untyped ; ; PFD_MIN ; 0 ; Untyped ; ; PFD_MAX ; 0 ; Untyped ; ; M_INITIAL ; 0 ; Untyped ; ; M ; 0 ; Untyped ; ; N ; 1 ; Untyped ; ; M2 ; 1 ; Untyped ; ; N2 ; 1 ; Untyped ; ; SS ; 1 ; Untyped ; ; C0_HIGH ; 0 ; Untyped ; ; C1_HIGH ; 0 ; Untyped ; ; C2_HIGH ; 0 ; Untyped ; ; C3_HIGH ; 0 ; Untyped ; ; C4_HIGH ; 0 ; Untyped ; ; C5_HIGH ; 0 ; Untyped ; ; C6_HIGH ; 0 ; Untyped ; ; C7_HIGH ; 0 ; Untyped ; ; C8_HIGH ; 0 ; Untyped ; ; C9_HIGH ; 0 ; Untyped ; ; C0_LOW ; 0 ; Untyped ; ; C1_LOW ; 0 ; Untyped ; ; C2_LOW ; 0 ; Untyped ; ; C3_LOW ; 0 ; Untyped ; ; C4_LOW ; 0 ; Untyped ; ; C5_LOW ; 0 ; Untyped ; ; C6_LOW ; 0 ; Untyped ; ; C7_LOW ; 0 ; Untyped ; ; C8_LOW ; 0 ; Untyped ; ; C9_LOW ; 0 ; Untyped ; ; C0_INITIAL ; 0 ; Untyped ; ; C1_INITIAL ; 0 ; Untyped ; ; C2_INITIAL ; 0 ; Untyped ; ; C3_INITIAL ; 0 ; Untyped ; ; C4_INITIAL ; 0 ; Untyped ; ; C5_INITIAL ; 0 ; Untyped ; ; C6_INITIAL ; 0 ; Untyped ; ; C7_INITIAL ; 0 ; Untyped ; ; C8_INITIAL ; 0 ; Untyped ; ; C9_INITIAL ; 0 ; Untyped ; ; C0_MODE ; BYPASS ; Untyped ; ; C1_MODE ; BYPASS ; Untyped ; ; C2_MODE ; BYPASS ; Untyped ; ; C3_MODE ; BYPASS ; Untyped ; ; C4_MODE ; BYPASS ; Untyped ; ; C5_MODE ; BYPASS ; Untyped ; ; C6_MODE ; BYPASS ; Untyped ; ; C7_MODE ; BYPASS ; Untyped ; ; C8_MODE ; BYPASS ; Untyped ; ; C9_MODE ; BYPASS ; Untyped ; ; C0_PH ; 0 ; Untyped ; ; C1_PH ; 0 ; Untyped ; ; C2_PH ; 0 ; Untyped ; ; C3_PH ; 0 ; Untyped ; ; C4_PH ; 0 ; Untyped ; ; C5_PH ; 0 ; Untyped ; ; C6_PH ; 0 ; Untyped ; ; C7_PH ; 0 ; Untyped ; ; C8_PH ; 0 ; Untyped ; ; C9_PH ; 0 ; Untyped ; ; L0_HIGH ; 1 ; Untyped ; ; L1_HIGH ; 1 ; Untyped ; ; G0_HIGH ; 1 ; Untyped ; ; G1_HIGH ; 1 ; Untyped ; ; G2_HIGH ; 1 ; Untyped ; ; G3_HIGH ; 1 ; Untyped ; ; E0_HIGH ; 1 ; Untyped ; ; E1_HIGH ; 1 ; Untyped ; ; E2_HIGH ; 1 ; Untyped ; ; E3_HIGH ; 1 ; Untyped ; ; L0_LOW ; 1 ; Untyped ; ; L1_LOW ; 1 ; Untyped ; ; G0_LOW ; 1 ; Untyped ; ; G1_LOW ; 1 ; Untyped ; ; G2_LOW ; 1 ; Untyped ; ; G3_LOW ; 1 ; Untyped ; ; E0_LOW ; 1 ; Untyped ; ; E1_LOW ; 1 ; Untyped ; ; E2_LOW ; 1 ; Untyped ; ; E3_LOW ; 1 ; Untyped ; ; L0_INITIAL ; 1 ; Untyped ; ; L1_INITIAL ; 1 ; Untyped ; ; G0_INITIAL ; 1 ; Untyped ; ; G1_INITIAL ; 1 ; Untyped ; ; G2_INITIAL ; 1 ; Untyped ; ; G3_INITIAL ; 1 ; Untyped ; ; E0_INITIAL ; 1 ; Untyped ; ; E1_INITIAL ; 1 ; Untyped ; ; E2_INITIAL ; 1 ; Untyped ; ; E3_INITIAL ; 1 ; Untyped ; ; L0_MODE ; BYPASS ; Untyped ; ; L1_MODE ; BYPASS ; Untyped ; ; G0_MODE ; BYPASS ; Untyped ; ; G1_MODE ; BYPASS ; Untyped ; ; G2_MODE ; BYPASS ; Untyped ; ; G3_MODE ; BYPASS ; Untyped ; ; E0_MODE ; BYPASS ; Untyped ; ; E1_MODE ; BYPASS ; Untyped ; ; E2_MODE ; BYPASS ; Untyped ; ; E3_MODE ; BYPASS ; Untyped ; ; L0_PH ; 0 ; Untyped ; ; L1_PH ; 0 ; Untyped ; ; G0_PH ; 0 ; Untyped ; ; G1_PH ; 0 ; Untyped ; ; G2_PH ; 0 ; Untyped ; ; G3_PH ; 0 ; Untyped ; ; E0_PH ; 0 ; Untyped ; ; E1_PH ; 0 ; Untyped ; ; E2_PH ; 0 ; Untyped ; ; E3_PH ; 0 ; Untyped ; ; M_PH ; 0 ; Untyped ; ; C1_USE_CASC_IN ; OFF ; Untyped ; ; C2_USE_CASC_IN ; OFF ; Untyped ; ; C3_USE_CASC_IN ; OFF ; Untyped ; ; C4_USE_CASC_IN ; OFF ; Untyped ; ; C5_USE_CASC_IN ; OFF ; Untyped ; ; C6_USE_CASC_IN ; OFF ; Untyped ; ; C7_USE_CASC_IN ; OFF ; Untyped ; ; C8_USE_CASC_IN ; OFF ; Untyped ; ; C9_USE_CASC_IN ; OFF ; Untyped ; ; CLK0_COUNTER ; G0 ; Untyped ; ; CLK1_COUNTER ; G0 ; Untyped ; ; CLK2_COUNTER ; G0 ; Untyped ; ; CLK3_COUNTER ; G0 ; Untyped ; ; CLK4_COUNTER ; G0 ; Untyped ; ; CLK5_COUNTER ; G0 ; Untyped ; ; CLK6_COUNTER ; E0 ; Untyped ; ; CLK7_COUNTER ; E1 ; Untyped ; ; CLK8_COUNTER ; E2 ; Untyped ; ; CLK9_COUNTER ; E3 ; Untyped ; ; L0_TIME_DELAY ; 0 ; Untyped ; ; L1_TIME_DELAY ; 0 ; Untyped ; ; G0_TIME_DELAY ; 0 ; Untyped ; ; G1_TIME_DELAY ; 0 ; Untyped ; ; G2_TIME_DELAY ; 0 ; Untyped ; ; G3_TIME_DELAY ; 0 ; Untyped ; ; E0_TIME_DELAY ; 0 ; Untyped ; ; E1_TIME_DELAY ; 0 ; Untyped ; ; E2_TIME_DELAY ; 0 ; Untyped ; ; E3_TIME_DELAY ; 0 ; Untyped ; ; M_TIME_DELAY ; 0 ; Untyped ; ; N_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_COUNTER ; E3 ; Untyped ; ; EXTCLK2_COUNTER ; E2 ; Untyped ; ; EXTCLK1_COUNTER ; E1 ; Untyped ; ; EXTCLK0_COUNTER ; E0 ; Untyped ; ; ENABLE0_COUNTER ; L0 ; Untyped ; ; ENABLE1_COUNTER ; L0 ; Untyped ; ; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; ; LOOP_FILTER_R ; 1.000000 ; Untyped ; ; LOOP_FILTER_C ; 5 ; Untyped ; ; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; ; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; ; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; ; VCO_POST_SCALE ; 0 ; Untyped ; ; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; INTENDED_DEVICE_FAMILY ; Cyclone ; Untyped ; ; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; ; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; ; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; ; PORT_CLK0 ; PORT_USED ; Untyped ; ; PORT_CLK1 ; PORT_UNUSED ; Untyped ; ; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK3 ; PORT_UNUSED ; Untyped ; ; PORT_CLK4 ; PORT_UNUSED ; Untyped ; ; PORT_CLK5 ; PORT_UNUSED ; Untyped ; ; PORT_CLK6 ; PORT_UNUSED ; Untyped ; ; PORT_CLK7 ; PORT_UNUSED ; Untyped ; ; PORT_CLK8 ; PORT_UNUSED ; Untyped ; ; PORT_CLK9 ; PORT_UNUSED ; Untyped ; ; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; ; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; ; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; ; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; ; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; ; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; ; PORT_INCLK0 ; PORT_USED ; Untyped ; ; PORT_FBIN ; PORT_UNUSED ; Untyped ; ; PORT_PLLENA ; PORT_UNUSED ; Untyped ; ; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; ; PORT_ARESET ; PORT_UNUSED ; Untyped ; ; PORT_PFDENA ; PORT_UNUSED ; Untyped ; ; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; ; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; ; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; ; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; ; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_LOCKED ; PORT_UNUSED ; Untyped ; ; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; ; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; ; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; ; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; ; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; ; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; ; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; ; M_TEST_SOURCE ; 5 ; Untyped ; ; C0_TEST_SOURCE ; 5 ; Untyped ; ; C1_TEST_SOURCE ; 5 ; Untyped ; ; C2_TEST_SOURCE ; 5 ; Untyped ; ; C3_TEST_SOURCE ; 5 ; Untyped ; ; C4_TEST_SOURCE ; 5 ; Untyped ; ; C5_TEST_SOURCE ; 5 ; Untyped ; ; C6_TEST_SOURCE ; 5 ; Untyped ; ; C7_TEST_SOURCE ; 5 ; Untyped ; ; C8_TEST_SOURCE ; 5 ; Untyped ; ; C9_TEST_SOURCE ; 5 ; Untyped ; ; CBXI_PARAMETER ; NOTHING ; Untyped ; ; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; ; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; ; WIDTH_CLOCK ; 6 ; Untyped ; ; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; ; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; ; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +-------------------------------+-------------------+----------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------------------------------+ ; altsyncram Parameter Settings by Entity Instance ; +-------------------------------------------+--------------------------------------------------------------------------------+ ; Name ; Value ; +-------------------------------------------+--------------------------------------------------------------------------------+ ; Number of entity instances ; 2 ; ; Entity Instance ; display_driver:vga640x480|font_ram:font5x7|altsyncram:altsyncram_component ; ; -- OPERATION_MODE ; SINGLE_PORT ; ; -- WIDTH_A ; 8 ; ; -- NUMWORDS_A ; 2048 ; ; -- OUTDATA_REG_A ; UNREGISTERED ; ; -- WIDTH_B ; 1 ; ; -- NUMWORDS_B ; 1 ; ; -- ADDRESS_REG_B ; CLOCK1 ; ; -- OUTDATA_REG_B ; UNREGISTERED ; ; -- RAM_BLOCK_TYPE ; AUTO ; ; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; ; Entity Instance ; display_driver:vga640x480|dpram_32x128:dp_ram1|altsyncram:altsyncram_component ; ; -- OPERATION_MODE ; DUAL_PORT ; ; -- WIDTH_A ; 8 ; ; -- NUMWORDS_A ; 4096 ; ; -- OUTDATA_REG_A ; UNREGISTERED ; ; -- WIDTH_B ; 8 ; ; -- NUMWORDS_B ; 4096 ; ; -- ADDRESS_REG_B ; CLOCK0 ; ; -- OUTDATA_REG_B ; UNREGISTERED ; ; -- RAM_BLOCK_TYPE ; AUTO ; ; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +-------------------------------------------+--------------------------------------------------------------------------------+ +-------------------------------------------------------------------------+ ; altpll Parameter Settings by Entity Instance ; +-------------------------------+-----------------------------------------+ ; Name ; Value ; +-------------------------------+-----------------------------------------+ ; Number of entity instances ; 1 ; ; Entity Instance ; pll_lcd:vga_pll|altpll:altpll_component ; ; -- OPERATION_MODE ; NORMAL ; ; -- PLL_TYPE ; AUTO ; ; -- PRIMARY_CLOCK ; INCLK0 ; ; -- INCLK0_INPUT_FREQUENCY ; 20000 ; ; -- INCLK1_INPUT_FREQUENCY ; 0 ; ; -- VCO_MULTIPLY_BY ; 0 ; ; -- VCO_DIVIDE_BY ; 0 ; +-------------------------------+-----------------------------------------+ +---------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "clock_module:sys_clocks" ; +-----------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +-----------+--------+----------+-------------------------------------------------------------------------------------+ ; clk_1us ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; clk_10us ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; clk_100us ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +-----------+--------+----------+-------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "display_driver:vga640x480|dpram_32x128:dp_ram1" ; +-----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +-----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; rdaddress ; Input ; Warning ; Input port expression (13 bits) is wider than the input port (12 bits) it drives. The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +-----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------+ ; Port Connectivity Checks: "display_driver:vga640x480|font_ram:font5x7" ; +------+-------+----------+----------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------+-------+----------+----------------------------------------------+ ; data ; Input ; Info ; Stuck at GND ; ; wren ; Input ; Info ; Stuck at GND ; +------+-------+----------+----------------------------------------------+ +----------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "display_driver:vga640x480" ; +------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------+--------+----------+-------------------------------------------------------------------------------------+ ; disp ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +------+--------+----------+-------------------------------------------------------------------------------------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 9.0 Build 132 02/25/2009 SJ Full Version Info: Processing started: Sat May 09 04:57:18 2009 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga_data -c vga_data Info: Found 1 design units, including 1 entities, in source file clock_module.v Info: Found entity 1: clock_module Info: Found 1 design units, including 1 entities, in source file display_driver.v Info: Found entity 1: display_driver Info: Found 1 design units, including 1 entities, in source file dpram_32x128.v Info: Found entity 1: dpram_32x128 Info: Found 1 design units, including 1 entities, in source file font_ram.v Info: Found entity 1: font_ram Info: Found 1 design units, including 1 entities, in source file pll_lcd.v Info: Found entity 1: pll_lcd Info: Found 1 design units, including 1 entities, in source file Reset_Delay.v Info: Found entity 1: Reset_Delay Info: Found 1 design units, including 1 entities, in source file vga_data.v Info: Found entity 1: vga_data Warning (10236): Verilog HDL Implicit Net warning at vga_data.v(247): created implicit net for "clk_1us" Warning (10236): Verilog HDL Implicit Net warning at vga_data.v(248): created implicit net for "clk_10us" Warning (10236): Verilog HDL Implicit Net warning at vga_data.v(249): created implicit net for "clk_100us" Warning (10236): Verilog HDL Implicit Net warning at vga_data.v(250): created implicit net for "clk_1ms" Warning (10236): Verilog HDL Implicit Net warning at vga_data.v(251): created implicit net for "clk_10ms" Warning (10236): Verilog HDL Implicit Net warning at vga_data.v(252): created implicit net for "clk_100ms" Warning (10236): Verilog HDL Implicit Net warning at vga_data.v(253): created implicit net for "clk_1s" Info: Elaborating entity "vga_data" for the top level hierarchy Warning (10230): Verilog HDL assignment warning at vga_data.v(256): truncated value with size 32 to match size of target (16) Warning (10230): Verilog HDL assignment warning at vga_data.v(261): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at vga_data.v(262): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at vga_data.v(263): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at vga_data.v(268): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at vga_data.v(274): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at vga_data.v(277): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at vga_data.v(281): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at vga_data.v(285): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at vga_data.v(289): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at vga_data.v(293): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at vga_data.v(297): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at vga_data.v(316): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at vga_data.v(422): truncated value with size 32 to match size of target (12) Warning (10230): Verilog HDL assignment warning at vga_data.v(496): truncated value with size 32 to match size of target (2) Info: Elaborating entity "display_driver" for hierarchy "display_driver:vga640x480" Warning (10230): Verilog HDL assignment warning at display_driver.v(101): truncated value with size 32 to match size of target (5) Warning (10230): Verilog HDL assignment warning at display_driver.v(162): truncated value with size 32 to match size of target (10) Warning (10230): Verilog HDL assignment warning at display_driver.v(167): truncated value with size 32 to match size of target (10) Warning (10230): Verilog HDL assignment warning at display_driver.v(181): truncated value with size 32 to match size of target (11) Warning (10230): Verilog HDL assignment warning at display_driver.v(191): truncated value with size 32 to match size of target (2) Warning (10230): Verilog HDL assignment warning at display_driver.v(192): truncated value with size 32 to match size of target (2) Warning (10230): Verilog HDL assignment warning at display_driver.v(193): truncated value with size 32 to match size of target (2) Warning (10230): Verilog HDL assignment warning at display_driver.v(233): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at display_driver.v(240): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at display_driver.v(247): truncated value with size 32 to match size of target (13) Warning (10230): Verilog HDL assignment warning at display_driver.v(256): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at display_driver.v(262): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at display_driver.v(267): truncated value with size 32 to match size of target (13) Info: Elaborating entity "font_ram" for hierarchy "display_driver:vga640x480|font_ram:font5x7" Info: Elaborating entity "altsyncram" for hierarchy "display_driver:vga640x480|font_ram:font5x7|altsyncram:altsyncram_component" Info: Elaborated megafunction instantiation "display_driver:vga640x480|font_ram:font5x7|altsyncram:altsyncram_component" Info: Instantiated megafunction "display_driver:vga640x480|font_ram:font5x7|altsyncram:altsyncram_component" with the following parameter: Info: Parameter "address_aclr_a" = "NONE" Info: Parameter "indata_aclr_a" = "NONE" Info: Parameter "init_file" = "font_rom16.hex" Info: Parameter "intended_device_family" = "Cyclone" Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" Info: Parameter "lpm_type" = "altsyncram" Info: Parameter "numwords_a" = "2048" Info: Parameter "operation_mode" = "SINGLE_PORT" Info: Parameter "outdata_aclr_a" = "NONE" Info: Parameter "outdata_reg_a" = "UNREGISTERED" Info: Parameter "power_up_uninitialized" = "FALSE" Info: Parameter "widthad_a" = "11" Info: Parameter "width_a" = "8" Info: Parameter "width_byteena_a" = "1" Info: Parameter "wrcontrol_aclr_a" = "NONE" Info: Found 1 design units, including 1 entities, in source file db/altsyncram_bld1.tdf Info: Found entity 1: altsyncram_bld1 Info: Elaborating entity "altsyncram_bld1" for hierarchy "display_driver:vga640x480|font_ram:font5x7|altsyncram:altsyncram_component|altsyncram_bld1:auto_generated" Warning: Byte addressed memory initialization file "font_rom16.hex" was read in the word-addressed format Warning: Width of data items in "font_rom16.hex" is greater than the memory width. Wrapping data items to subsequent addresses. Found 256 warnings, reporting 10 Warning: Data at line (1) of memory initialization file "font_rom16.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (2) of memory initialization file "font_rom16.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (3) of memory initialization file "font_rom16.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (4) of memory initialization file "font_rom16.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (5) of memory initialization file "font_rom16.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (6) of memory initialization file "font_rom16.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (7) of memory initialization file "font_rom16.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (8) of memory initialization file "font_rom16.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (9) of memory initialization file "font_rom16.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (10) of memory initialization file "font_rom16.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Critical Warning: Memory depth (2048) in the design file differs from memory depth (4096) in the Memory Initialization File "font_rom16.hex" -- truncated remaining initial content value to fit RAM Info: Elaborating entity "dpram_32x128" for hierarchy "display_driver:vga640x480|dpram_32x128:dp_ram1" Info: Elaborating entity "altsyncram" for hierarchy "display_driver:vga640x480|dpram_32x128:dp_ram1|altsyncram:altsyncram_component" Info: Elaborated megafunction instantiation "display_driver:vga640x480|dpram_32x128:dp_ram1|altsyncram:altsyncram_component" Info: Instantiated megafunction "display_driver:vga640x480|dpram_32x128:dp_ram1|altsyncram:altsyncram_component" with the following parameter: Info: Parameter "address_aclr_a" = "NONE" Info: Parameter "address_aclr_b" = "NONE" Info: Parameter "address_reg_b" = "CLOCK0" Info: Parameter "indata_aclr_a" = "NONE" Info: Parameter "init_file" = "ascii_ram_32x128.hex" Info: Parameter "intended_device_family" = "Cyclone" Info: Parameter "lpm_type" = "altsyncram" Info: Parameter "numwords_a" = "4096" Info: Parameter "numwords_b" = "4096" Info: Parameter "operation_mode" = "DUAL_PORT" Info: Parameter "outdata_aclr_b" = "NONE" Info: Parameter "outdata_reg_b" = "UNREGISTERED" Info: Parameter "power_up_uninitialized" = "FALSE" Info: Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info: Parameter "widthad_a" = "12" Info: Parameter "widthad_b" = "12" Info: Parameter "width_a" = "8" Info: Parameter "width_b" = "8" Info: Parameter "width_byteena_a" = "1" Info: Parameter "wrcontrol_aclr_a" = "NONE" Info: Found 1 design units, including 1 entities, in source file db/altsyncram_1io1.tdf Info: Found entity 1: altsyncram_1io1 Info: Elaborating entity "altsyncram_1io1" for hierarchy "display_driver:vga640x480|dpram_32x128:dp_ram1|altsyncram:altsyncram_component|altsyncram_1io1:auto_generated" Warning: Byte addressed memory initialization file "ascii_ram_32x128.hex" was read in the word-addressed format Warning: Width of data items in "ascii_ram_32x128.hex" is greater than the memory width. Wrapping data items to subsequent addresses. Found 259 warnings, reporting 10 Warning: Data at line (1) of memory initialization file "ascii_ram_32x128.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (2) of memory initialization file "ascii_ram_32x128.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (3) of memory initialization file "ascii_ram_32x128.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (4) of memory initialization file "ascii_ram_32x128.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (5) of memory initialization file "ascii_ram_32x128.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (6) of memory initialization file "ascii_ram_32x128.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (7) of memory initialization file "ascii_ram_32x128.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (8) of memory initialization file "ascii_ram_32x128.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (9) of memory initialization file "ascii_ram_32x128.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Warning: Data at line (10) of memory initialization file "ascii_ram_32x128.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. Critical Warning: Memory depth (4096) in the design file differs from memory depth (4132) in the Memory Initialization File "ascii_ram_32x128.hex" -- truncated remaining initial content value to fit RAM Info: Elaborating entity "Reset_Delay" for hierarchy "Reset_Delay:rst" Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(11): truncated value with size 32 to match size of target (3) Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(18): truncated value with size 32 to match size of target (12) Info: Elaborating entity "pll_lcd" for hierarchy "pll_lcd:vga_pll" Info: Elaborating entity "altpll" for hierarchy "pll_lcd:vga_pll|altpll:altpll_component" Info: Elaborated megafunction instantiation "pll_lcd:vga_pll|altpll:altpll_component" Info: Instantiated megafunction "pll_lcd:vga_pll|altpll:altpll_component" with the following parameter: Info: Parameter "clk0_divide_by" = "50" Info: Parameter "clk0_duty_cycle" = "50" Info: Parameter "clk0_multiply_by" = "27" Info: Parameter "clk0_phase_shift" = "0" Info: Parameter "compensate_clock" = "CLK0" Info: Parameter "inclk0_input_frequency" = "20000" Info: Parameter "intended_device_family" = "Cyclone" Info: Parameter "lpm_type" = "altpll" Info: Parameter "operation_mode" = "NORMAL" Info: Parameter "pll_type" = "AUTO" Info: Parameter "port_activeclock" = "PORT_UNUSED" Info: Parameter "port_areset" = "PORT_UNUSED" Info: Parameter "port_clkbad0" = "PORT_UNUSED" Info: Parameter "port_clkbad1" = "PORT_UNUSED" Info: Parameter "port_clkloss" = "PORT_UNUSED" Info: Parameter "port_clkswitch" = "PORT_UNUSED" Info: Parameter "port_configupdate" = "PORT_UNUSED" Info: Parameter "port_fbin" = "PORT_UNUSED" Info: Parameter "port_inclk0" = "PORT_USED" Info: Parameter "port_inclk1" = "PORT_UNUSED" Info: Parameter "port_locked" = "PORT_UNUSED" Info: Parameter "port_pfdena" = "PORT_UNUSED" Info: Parameter "port_phasecounterselect" = "PORT_UNUSED" Info: Parameter "port_phasedone" = "PORT_UNUSED" Info: Parameter "port_phasestep" = "PORT_UNUSED" Info: Parameter "port_phaseupdown" = "PORT_UNUSED" Info: Parameter "port_pllena" = "PORT_UNUSED" Info: Parameter "port_scanaclr" = "PORT_UNUSED" Info: Parameter "port_scanclk" = "PORT_UNUSED" Info: Parameter "port_scanclkena" = "PORT_UNUSED" Info: Parameter "port_scandata" = "PORT_UNUSED" Info: Parameter "port_scandataout" = "PORT_UNUSED" Info: Parameter "port_scandone" = "PORT_UNUSED" Info: Parameter "port_scanread" = "PORT_UNUSED" Info: Parameter "port_scanwrite" = "PORT_UNUSED" Info: Parameter "port_clk0" = "PORT_USED" Info: Parameter "port_clk1" = "PORT_UNUSED" Info: Parameter "port_clk3" = "PORT_UNUSED" Info: Parameter "port_clk4" = "PORT_UNUSED" Info: Parameter "port_clk5" = "PORT_UNUSED" Info: Parameter "port_clkena0" = "PORT_UNUSED" Info: Parameter "port_clkena1" = "PORT_UNUSED" Info: Parameter "port_clkena3" = "PORT_UNUSED" Info: Parameter "port_clkena4" = "PORT_UNUSED" Info: Parameter "port_clkena5" = "PORT_UNUSED" Info: Parameter "port_extclk0" = "PORT_UNUSED" Info: Parameter "port_extclk1" = "PORT_UNUSED" Info: Parameter "port_extclk2" = "PORT_UNUSED" Info: Parameter "port_extclk3" = "PORT_UNUSED" Info: Elaborating entity "clock_module" for hierarchy "clock_module:sys_clocks" Warning (10230): Verilog HDL assignment warning at clock_module.v(46): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at clock_module.v(58): truncated value with size 32 to match size of target (9) Warning (10230): Verilog HDL assignment warning at clock_module.v(70): truncated value with size 32 to match size of target (13) Warning (10230): Verilog HDL assignment warning at clock_module.v(82): truncated value with size 32 to match size of target (7) Warning (10230): Verilog HDL assignment warning at clock_module.v(94): truncated value with size 32 to match size of target (10) Warning (10230): Verilog HDL assignment warning at clock_module.v(106): truncated value with size 32 to match size of target (14) Warning (10230): Verilog HDL assignment warning at clock_module.v(118): truncated value with size 32 to match size of target (7) Warning: Synthesized away the following node(s): Warning: Synthesized away the following RAM node(s): Warning (14320): Synthesized away node "display_driver:vga640x480|dpram_32x128:dp_ram1|altsyncram:altsyncram_component|altsyncram_1io1:auto_generated|q_b[7]" Warning: 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "CON1" is stuck at GND Warning (13410): Pin "CON2" is stuck at GND Warning (13410): Pin "CON3" is stuck at GND Warning (13410): Pin "CON4" is stuck at GND Warning (13410): Pin "CON5" is stuck at GND Warning (13410): Pin "CON6" is stuck at GND Warning (13410): Pin "CON7" is stuck at GND Warning (13410): Pin "CON8" is stuck at GND Warning (13410): Pin "CON9" is stuck at GND Warning (13410): Pin "CON10" is stuck at GND Warning (13410): Pin "CON11" is stuck at GND Warning (13410): Pin "CON12" is stuck at GND Warning (13410): Pin "CON13" is stuck at GND Warning (13410): Pin "CON14" is stuck at GND Warning (13410): Pin "CON15" is stuck at GND Warning (13410): Pin "CON16" is stuck at GND Warning (13410): Pin "CON17" is stuck at GND Warning (13410): Pin "CON18" is stuck at GND Warning (13410): Pin "CON19" is stuck at GND Warning (13410): Pin "CON20" is stuck at GND Warning (13410): Pin "TXD" is stuck at VCC Warning (13410): Pin "CS_FLASH" is stuck at VCC Warning (13410): Pin "SCK" is stuck at GND Warning (13410): Pin "LEDA" is stuck at VCC Warning (13410): Pin "LEDB" is stuck at VCC Warning (13410): Pin "MSB_B" is stuck at GND Warning (13410): Pin "DP" is stuck at GND Info: 14 registers lost all their fanouts during netlist optimizations. The first 14 are displayed below. Info: Register "display_driver:vga640x480|char_reg[7]" lost all its fanouts during netlist optimizations. Info: Register "ram_data[7]" lost all its fanouts during netlist optimizations. Info: Register "ascii_reg[7]" lost all its fanouts during netlist optimizations. Info: Register "wr_state~16" lost all its fanouts during netlist optimizations. Info: Register "wr_state~17" lost all its fanouts during netlist optimizations. Info: Register "ram_state~90" lost all its fanouts during netlist optimizations. Info: Register "ram_state~91" lost all its fanouts during netlist optimizations. Info: Register "ram_state~92" lost all its fanouts during netlist optimizations. Info: Register "ram_state~93" lost all its fanouts during netlist optimizations. Info: Register "display_driver:vga640x480|h_state~26" lost all its fanouts during netlist optimizations. Info: Register "display_driver:vga640x480|h_state~27" lost all its fanouts during netlist optimizations. Info: Register "display_driver:vga640x480|zone.ZONE_IMAGE" lost all its fanouts during netlist optimizations. Info: Register "display_driver:vga640x480|zone.ZONE_ZWART" lost all its fanouts during netlist optimizations. Info: Register "display_driver:vga640x480|char_pnt[12]" lost all its fanouts during netlist optimizations. Info: Generated suppressed messages file E:/vga_data_restored/vga_data.map.smsg Warning: Design contains 21 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "OSCO" Warning (15610): No output dependent on input pin "RXD" Warning (15610): No output dependent on input pin "RTS" Warning (15610): No output dependent on input pin "CTS" Warning (15610): No output dependent on input pin "DSR" Warning (15610): No output dependent on input pin "DTR" Warning (15610): No output dependent on input pin "DCD" Warning (15610): No output dependent on input pin "RI" Warning (15610): No output dependent on input pin "DS1" Warning (15610): No output dependent on input pin "DS2" Warning (15610): No output dependent on input pin "DS3" Warning (15610): No output dependent on input pin "DS4" Warning (15610): No output dependent on input pin "DS5" Warning (15610): No output dependent on input pin "DS6" Warning (15610): No output dependent on input pin "DS7" Warning (15610): No output dependent on input pin "DS8" Warning (15610): No output dependent on input pin "PS2_DATA" Warning (15610): No output dependent on input pin "PS2_CLK" Warning (15610): No output dependent on input pin "DI" Warning (15610): No output dependent on input pin "DO" Warning (15610): No output dependent on input pin "TSOP" Info: Implemented 720 device resources after synthesis - the final resource count might be different Info: Implemented 28 input pins Info: Implemented 61 output pins Info: Implemented 615 logic cells Info: Implemented 15 RAM segments Info: Implemented 1 ClockLock PLLs Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 124 warnings Info: Peak virtual memory: 265 megabytes Info: Processing ended: Sat May 09 04:57:35 2009 Info: Elapsed time: 00:00:17 Info: Total CPU time (on all processors): 00:00:05 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ The suppressed messages can be found in E:/vga_data_restored/vga_data.map.smsg.