{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II 64-Bit " "Info: Running Quartus II 64-Bit Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 04:58:13 2009 " "Info: Processing started: Sat May 09 04:58:13 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off vga_data -c vga_data --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga_data -c vga_data --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0 -1}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clock_module:sys_clocks\|clk_1ms " "Info: Detected ripple clock \"clock_module:sys_clocks\|clk_1ms\" as buffer" {  } { { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 7 -1 0 } } { "d:/altera/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/altera/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clock_module:sys_clocks\|clk_1ms" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "clock_module:sys_clocks\|clk_1s " "Info: Detected ripple clock \"clock_module:sys_clocks\|clk_1s\" as buffer" {  } { { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 11 -1 0 } } { "d:/altera/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/altera/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clock_module:sys_clocks\|clk_1s" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "clock_module:sys_clocks\|clk_10ms " "Info: Detected ripple clock \"clock_module:sys_clocks\|clk_10ms\" as buffer" {  } { { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 8 -1 0 } } { "d:/altera/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/altera/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clock_module:sys_clocks\|clk_10ms" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "Reset_Delay:rst\|pre_cnt\[2\] " "Info: Detected ripple clock \"Reset_Delay:rst\|pre_cnt\[2\]\" as buffer" {  } { { "Reset_Delay.v" "" { Text "E:/vga_data_restored/Reset_Delay.v" 9 -1 0 } } { "d:/altera/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/altera/quartus/bin64/Assignment Editor.qase" 1 { { 0 "Reset_Delay:rst\|pre_cnt\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "clock_module:sys_clocks\|clk_10us " "Info: Detected ripple clock \"clock_module:sys_clocks\|clk_10us\" as buffer" {  } { { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 5 -1 0 } } { "d:/altera/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/altera/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clock_module:sys_clocks\|clk_10us" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "clock_module:sys_clocks\|clk_100ms " "Info: Detected ripple clock \"clock_module:sys_clocks\|clk_100ms\" as buffer" {  } { { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 9 -1 0 } } { "d:/altera/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/altera/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clock_module:sys_clocks\|clk_100ms" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 -1}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_SLACK_RESULT" "pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 register leddisp_reg\[10\] register led_reg\[10\] -4.725 ns " "Info: Slack time is -4.725 ns for clock \"pll_lcd:vga_pll\|altpll:altpll_component\|_clk0\" between source register \"leddisp_reg\[10\]\" and destination register \"led_reg\[10\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-3.619 ns + Largest register register " "Info: + Largest register to register requirement is -3.619 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "0.541 ns + " "Info: + Setup relationship between source and destination is 0.541 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.541 ns " "Info: + Latch edge is 0.541 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 37.037 ns -2.419 ns  50 " "Info: Clock period of Destination clock \"pll_lcd:vga_pll\|altpll:altpll_component\|_clk0\" is 37.037 ns with  offset of -2.419 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source OSC 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"OSC\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.921 ns + Largest " "Info: + Largest clock skew is -3.921 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 destination 2.526 ns + Shortest register " "Info: + Shortest clock path from clock \"pll_lcd:vga_pll\|altpll:altpll_component\|_clk0\" to destination register is 2.526 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll_lcd:vga_pll\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.000 ns) 0.929 ns pll_lcd:vga_pll\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 423 " "Info: 2: + IC(0.929 ns) + CELL(0.000 ns) = 0.929 ns; Loc. = CLKCTRL_G3; Fanout = 423; COMB Node = 'pll_lcd:vga_pll\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.929 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.602 ns) 2.526 ns led_reg\[10\] 3 REG LCFF_X20_Y14_N23 1 " "Info: 3: + IC(0.995 ns) + CELL(0.602 ns) = 2.526 ns; Loc. = LCFF_X20_Y14_N23; Fanout = 1; REG Node = 'led_reg\[10\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.597 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl led_reg[10] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 319 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 23.83 % ) " "Info: Total cell delay = 0.602 ns ( 23.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.924 ns ( 76.17 % ) " "Info: Total interconnect delay = 1.924 ns ( 76.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.526 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl led_reg[10] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "2.526 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 {} pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl {} led_reg[10] {} } { 0.000ns 0.929ns 0.995ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC source 6.447 ns - Longest register " "Info: - Longest clock path from clock \"OSC\" to source register is 6.447 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns OSC 1 CLK PIN_L1 7 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 7; CLK Node = 'OSC'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OSC } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.019 ns) + CELL(0.879 ns) 3.924 ns clock_module:sys_clocks\|clk_100ms 2 REG LCFF_X23_Y23_N25 1 " "Info: 2: + IC(2.019 ns) + CELL(0.879 ns) = 3.924 ns; Loc. = LCFF_X23_Y23_N25; Fanout = 1; REG Node = 'clock_module:sys_clocks\|clk_100ms'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.898 ns" { OSC clock_module:sys_clocks|clk_100ms } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.934 ns) + CELL(0.000 ns) 4.858 ns clock_module:sys_clocks\|clk_100ms~clkctrl 3 COMB CLKCTRL_G9 19 " "Info: 3: + IC(0.934 ns) + CELL(0.000 ns) = 4.858 ns; Loc. = CLKCTRL_G9; Fanout = 19; COMB Node = 'clock_module:sys_clocks\|clk_100ms~clkctrl'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.934 ns" { clock_module:sys_clocks|clk_100ms clock_module:sys_clocks|clk_100ms~clkctrl } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.987 ns) + CELL(0.602 ns) 6.447 ns leddisp_reg\[10\] 4 REG LCFF_X19_Y14_N21 4 " "Info: 4: + IC(0.987 ns) + CELL(0.602 ns) = 6.447 ns; Loc. = LCFF_X19_Y14_N21; Fanout = 4; REG Node = 'leddisp_reg\[10\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.589 ns" { clock_module:sys_clocks|clk_100ms~clkctrl leddisp_reg[10] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 255 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 38.89 % ) " "Info: Total cell delay = 2.507 ns ( 38.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.940 ns ( 61.11 % ) " "Info: Total interconnect delay = 3.940 ns ( 61.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "6.447 ns" { OSC clock_module:sys_clocks|clk_100ms clock_module:sys_clocks|clk_100ms~clkctrl leddisp_reg[10] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "6.447 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_100ms {} clock_module:sys_clocks|clk_100ms~clkctrl {} leddisp_reg[10] {} } { 0.000ns 0.000ns 2.019ns 0.934ns 0.987ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.526 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl led_reg[10] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "2.526 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 {} pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl {} led_reg[10] {} } { 0.000ns 0.929ns 0.995ns } { 0.000ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "6.447 ns" { OSC clock_module:sys_clocks|clk_100ms clock_module:sys_clocks|clk_100ms~clkctrl leddisp_reg[10] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "6.447 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_100ms {} clock_module:sys_clocks|clk_100ms~clkctrl {} leddisp_reg[10] {} } { 0.000ns 0.000ns 2.019ns 0.934ns 0.987ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns - " "Info: - Micro clock to output delay of source is 0.277 ns" {  } { { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 255 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns - " "Info: - Micro setup delay of destination is -0.038 ns" {  } { { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 319 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.526 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl led_reg[10] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "2.526 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 {} pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl {} led_reg[10] {} } { 0.000ns 0.929ns 0.995ns } { 0.000ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "6.447 ns" { OSC clock_module:sys_clocks|clk_100ms clock_module:sys_clocks|clk_100ms~clkctrl leddisp_reg[10] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "6.447 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_100ms {} clock_module:sys_clocks|clk_100ms~clkctrl {} leddisp_reg[10] {} } { 0.000ns 0.000ns 2.019ns 0.934ns 0.987ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.106 ns - Longest register register " "Info: - Longest register to register delay is 1.106 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns leddisp_reg\[10\] 1 REG LCFF_X19_Y14_N21 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y14_N21; Fanout = 4; REG Node = 'leddisp_reg\[10\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { leddisp_reg[10] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 255 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.688 ns) + CELL(0.322 ns) 1.010 ns Selector42~0 2 COMB LCCOMB_X20_Y14_N22 1 " "Info: 2: + IC(0.688 ns) + CELL(0.322 ns) = 1.010 ns; Loc. = LCCOMB_X20_Y14_N22; Fanout = 1; COMB Node = 'Selector42~0'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.010 ns" { leddisp_reg[10] Selector42~0 } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 324 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 1.106 ns led_reg\[10\] 3 REG LCFF_X20_Y14_N23 1 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 1.106 ns; Loc. = LCFF_X20_Y14_N23; Fanout = 1; REG Node = 'led_reg\[10\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.096 ns" { Selector42~0 led_reg[10] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 319 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.418 ns ( 37.79 % ) " "Info: Total cell delay = 0.418 ns ( 37.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.688 ns ( 62.21 % ) " "Info: Total interconnect delay = 0.688 ns ( 62.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.106 ns" { leddisp_reg[10] Selector42~0 led_reg[10] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "1.106 ns" { leddisp_reg[10] {} Selector42~0 {} led_reg[10] {} } { 0.000ns 0.688ns 0.000ns } { 0.000ns 0.322ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.526 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl led_reg[10] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "2.526 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 {} pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl {} led_reg[10] {} } { 0.000ns 0.929ns 0.995ns } { 0.000ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "6.447 ns" { OSC clock_module:sys_clocks|clk_100ms clock_module:sys_clocks|clk_100ms~clkctrl leddisp_reg[10] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "6.447 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_100ms {} clock_module:sys_clocks|clk_100ms~clkctrl {} leddisp_reg[10] {} } { 0.000ns 0.000ns 2.019ns 0.934ns 0.987ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.106 ns" { leddisp_reg[10] Selector42~0 led_reg[10] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "1.106 ns" { leddisp_reg[10] {} Selector42~0 {} led_reg[10] {} } { 0.000ns 0.688ns 0.000ns } { 0.000ns 0.322ns 0.096ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'pll_lcd:vga_pll\|altpll:altpll_component\|_clk0' 42 " "Warning: Can't achieve timing requirement Clock Setup: 'pll_lcd:vga_pll\|altpll:altpll_component\|_clk0' along 42 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_SLACK_RESULT" "OSC register digitf\[2\] register digite\[1\] 13.634 ns " "Info: Slack time is 13.634 ns for clock \"OSC\" between source register \"digitf\[2\]\" and destination register \"digite\[1\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "157.08 MHz 6.366 ns " "Info: Fmax is 157.08 MHz (period= 6.366 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.761 ns + Largest register register " "Info: + Largest register to register requirement is 19.761 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination OSC 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"OSC\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source OSC 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"OSC\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC destination 4.611 ns + Shortest register " "Info: + Shortest clock path from clock \"OSC\" to destination register is 4.611 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns OSC 1 CLK PIN_L1 7 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 7; CLK Node = 'OSC'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OSC } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.879 ns) 2.309 ns clock_module:sys_clocks\|clk_1s 2 REG LCFF_X1_Y13_N21 1 " "Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 1; REG Node = 'clock_module:sys_clocks\|clk_1s'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.283 ns" { OSC clock_module:sys_clocks|clk_1s } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.000 ns) 3.012 ns clock_module:sys_clocks\|clk_1s~clkctrl 3 COMB CLKCTRL_G1 24 " "Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G1; Fanout = 24; COMB Node = 'clock_module:sys_clocks\|clk_1s~clkctrl'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.703 ns" { clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.997 ns) + CELL(0.602 ns) 4.611 ns digite\[1\] 4 REG LCFF_X30_Y14_N19 6 " "Info: 4: + IC(0.997 ns) + CELL(0.602 ns) = 4.611 ns; Loc. = LCFF_X30_Y14_N19; Fanout = 6; REG Node = 'digite\[1\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.599 ns" { clock_module:sys_clocks|clk_1s~clkctrl digite[1] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 259 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 54.37 % ) " "Info: Total cell delay = 2.507 ns ( 54.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.104 ns ( 45.63 % ) " "Info: Total interconnect delay = 2.104 ns ( 45.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "4.611 ns" { OSC clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl digite[1] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "4.611 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1s {} clock_module:sys_clocks|clk_1s~clkctrl {} digite[1] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.997ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC source 4.611 ns - Longest register " "Info: - Longest clock path from clock \"OSC\" to source register is 4.611 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns OSC 1 CLK PIN_L1 7 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 7; CLK Node = 'OSC'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OSC } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.879 ns) 2.309 ns clock_module:sys_clocks\|clk_1s 2 REG LCFF_X1_Y13_N21 1 " "Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 1; REG Node = 'clock_module:sys_clocks\|clk_1s'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.283 ns" { OSC clock_module:sys_clocks|clk_1s } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.000 ns) 3.012 ns clock_module:sys_clocks\|clk_1s~clkctrl 3 COMB CLKCTRL_G1 24 " "Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G1; Fanout = 24; COMB Node = 'clock_module:sys_clocks\|clk_1s~clkctrl'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.703 ns" { clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.997 ns) + CELL(0.602 ns) 4.611 ns digitf\[2\] 4 REG LCFF_X30_Y14_N5 5 " "Info: 4: + IC(0.997 ns) + CELL(0.602 ns) = 4.611 ns; Loc. = LCFF_X30_Y14_N5; Fanout = 5; REG Node = 'digitf\[2\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.599 ns" { clock_module:sys_clocks|clk_1s~clkctrl digitf[2] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 259 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 54.37 % ) " "Info: Total cell delay = 2.507 ns ( 54.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.104 ns ( 45.63 % ) " "Info: Total interconnect delay = 2.104 ns ( 45.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "4.611 ns" { OSC clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl digitf[2] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "4.611 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1s {} clock_module:sys_clocks|clk_1s~clkctrl {} digitf[2] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.997ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "4.611 ns" { OSC clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl digite[1] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "4.611 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1s {} clock_module:sys_clocks|clk_1s~clkctrl {} digite[1] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.997ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "4.611 ns" { OSC clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl digitf[2] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "4.611 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1s {} clock_module:sys_clocks|clk_1s~clkctrl {} digitf[2] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.997ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns - " "Info: - Micro clock to output delay of source is 0.277 ns" {  } { { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 259 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns - " "Info: - Micro setup delay of destination is -0.038 ns" {  } { { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 259 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "4.611 ns" { OSC clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl digite[1] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "4.611 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1s {} clock_module:sys_clocks|clk_1s~clkctrl {} digite[1] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.997ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "4.611 ns" { OSC clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl digitf[2] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "4.611 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1s {} clock_module:sys_clocks|clk_1s~clkctrl {} digitf[2] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.997ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.127 ns - Longest register register " "Info: - Longest register to register delay is 6.127 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns digitf\[2\] 1 REG LCFF_X30_Y14_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y14_N5; Fanout = 5; REG Node = 'digitf\[2\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { digitf[2] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 259 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.959 ns) + CELL(0.545 ns) 1.504 ns always1~7 2 COMB LCCOMB_X30_Y14_N10 1 " "Info: 2: + IC(0.959 ns) + CELL(0.545 ns) = 1.504 ns; Loc. = LCCOMB_X30_Y14_N10; Fanout = 1; COMB Node = 'always1~7'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.504 ns" { digitf[2] always1~7 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.545 ns) 2.609 ns always1~0 3 COMB LCCOMB_X31_Y14_N14 3 " "Info: 3: + IC(0.560 ns) + CELL(0.545 ns) = 2.609 ns; Loc. = LCCOMB_X31_Y14_N14; Fanout = 3; COMB Node = 'always1~0'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.105 ns" { always1~7 always1~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.790 ns) + CELL(0.322 ns) 3.721 ns digite\[0\]~58 4 COMB LCCOMB_X34_Y14_N20 1 " "Info: 4: + IC(0.790 ns) + CELL(0.322 ns) = 3.721 ns; Loc. = LCCOMB_X34_Y14_N20; Fanout = 1; COMB Node = 'digite\[0\]~58'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.112 ns" { always1~0 digite[0]~58 } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 259 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.314 ns) + CELL(0.544 ns) 4.579 ns digite\[0\]~59 5 COMB LCCOMB_X34_Y14_N12 4 " "Info: 5: + IC(0.314 ns) + CELL(0.544 ns) = 4.579 ns; Loc. = LCCOMB_X34_Y14_N12; Fanout = 4; COMB Node = 'digite\[0\]~59'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.858 ns" { digite[0]~58 digite[0]~59 } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 259 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.790 ns) + CELL(0.758 ns) 6.127 ns digite\[1\] 6 REG LCFF_X30_Y14_N19 6 " "Info: 6: + IC(0.790 ns) + CELL(0.758 ns) = 6.127 ns; Loc. = LCFF_X30_Y14_N19; Fanout = 6; REG Node = 'digite\[1\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.548 ns" { digite[0]~59 digite[1] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 259 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.714 ns ( 44.30 % ) " "Info: Total cell delay = 2.714 ns ( 44.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.413 ns ( 55.70 % ) " "Info: Total interconnect delay = 3.413 ns ( 55.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "6.127 ns" { digitf[2] always1~7 always1~0 digite[0]~58 digite[0]~59 digite[1] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "6.127 ns" { digitf[2] {} always1~7 {} always1~0 {} digite[0]~58 {} digite[0]~59 {} digite[1] {} } { 0.000ns 0.959ns 0.560ns 0.790ns 0.314ns 0.790ns } { 0.000ns 0.545ns 0.545ns 0.322ns 0.544ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "4.611 ns" { OSC clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl digite[1] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "4.611 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1s {} clock_module:sys_clocks|clk_1s~clkctrl {} digite[1] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.997ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "4.611 ns" { OSC clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl digitf[2] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "4.611 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1s {} clock_module:sys_clocks|clk_1s~clkctrl {} digitf[2] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.997ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "6.127 ns" { digitf[2] always1~7 always1~0 digite[0]~58 digite[0]~59 digite[1] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "6.127 ns" { digitf[2] {} always1~7 {} always1~0 {} digite[0]~58 {} digite[0]~59 {} digite[1] {} } { 0.000ns 0.959ns 0.560ns 0.790ns 0.314ns 0.790ns } { 0.000ns 0.545ns 0.545ns 0.322ns 0.544ns 0.758ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 register display_driver:vga640x480\|v_sync register display_driver:vga640x480\|v_sync 445 ps " "Info: Minimum slack time is 445 ps for clock \"pll_lcd:vga_pll\|altpll:altpll_component\|_clk0\" between source register \"display_driver:vga640x480\|v_sync\" and destination register \"display_driver:vga640x480\|v_sync\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.454 ns + Shortest register register " "Info: + Shortest register to register delay is 0.454 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns display_driver:vga640x480\|v_sync 1 REG LCFF_X38_Y14_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X38_Y14_N9; Fanout = 2; REG Node = 'display_driver:vga640x480\|v_sync'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { display_driver:vga640x480|v_sync } "NODE_NAME" } } { "display_driver.v" "" { Text "E:/vga_data_restored/display_driver.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.358 ns) 0.358 ns display_driver:vga640x480\|v_sync~6 2 COMB LCCOMB_X38_Y14_N8 1 " "Info: 2: + IC(0.000 ns) + CELL(0.358 ns) = 0.358 ns; Loc. = LCCOMB_X38_Y14_N8; Fanout = 1; COMB Node = 'display_driver:vga640x480\|v_sync~6'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.358 ns" { display_driver:vga640x480|v_sync display_driver:vga640x480|v_sync~6 } "NODE_NAME" } } { "display_driver.v" "" { Text "E:/vga_data_restored/display_driver.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 0.454 ns display_driver:vga640x480\|v_sync 3 REG LCFF_X38_Y14_N9 2 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 0.454 ns; Loc. = LCFF_X38_Y14_N9; Fanout = 2; REG Node = 'display_driver:vga640x480\|v_sync'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.096 ns" { display_driver:vga640x480|v_sync~6 display_driver:vga640x480|v_sync } "NODE_NAME" } } { "display_driver.v" "" { Text "E:/vga_data_restored/display_driver.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.454 ns ( 100.00 % ) " "Info: Total cell delay = 0.454 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.454 ns" { display_driver:vga640x480|v_sync display_driver:vga640x480|v_sync~6 display_driver:vga640x480|v_sync } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "0.454 ns" { display_driver:vga640x480|v_sync {} display_driver:vga640x480|v_sync~6 {} display_driver:vga640x480|v_sync {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.358ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.009 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.009 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.419 ns " "Info: + Latch edge is -2.419 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 37.037 ns -2.419 ns  50 " "Info: Clock period of Destination clock \"pll_lcd:vga_pll\|altpll:altpll_component\|_clk0\" is 37.037 ns with  offset of -2.419 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.419 ns " "Info: - Launch edge is -2.419 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 37.037 ns -2.419 ns  50 " "Info: Clock period of Source clock \"pll_lcd:vga_pll\|altpll:altpll_component\|_clk0\" is 37.037 ns with  offset of -2.419 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 destination 2.531 ns + Longest register " "Info: + Longest clock path from clock \"pll_lcd:vga_pll\|altpll:altpll_component\|_clk0\" to destination register is 2.531 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll_lcd:vga_pll\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.000 ns) 0.929 ns pll_lcd:vga_pll\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 423 " "Info: 2: + IC(0.929 ns) + CELL(0.000 ns) = 0.929 ns; Loc. = CLKCTRL_G3; Fanout = 423; COMB Node = 'pll_lcd:vga_pll\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.929 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.602 ns) 2.531 ns display_driver:vga640x480\|v_sync 3 REG LCFF_X38_Y14_N9 2 " "Info: 3: + IC(1.000 ns) + CELL(0.602 ns) = 2.531 ns; Loc. = LCFF_X38_Y14_N9; Fanout = 2; REG Node = 'display_driver:vga640x480\|v_sync'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.602 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl display_driver:vga640x480|v_sync } "NODE_NAME" } } { "display_driver.v" "" { Text "E:/vga_data_restored/display_driver.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 23.79 % ) " "Info: Total cell delay = 0.602 ns ( 23.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.929 ns ( 76.21 % ) " "Info: Total interconnect delay = 1.929 ns ( 76.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.531 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl display_driver:vga640x480|v_sync } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "2.531 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 {} pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl {} display_driver:vga640x480|v_sync {} } { 0.000ns 0.929ns 1.000ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 source 2.531 ns - Shortest register " "Info: - Shortest clock path from clock \"pll_lcd:vga_pll\|altpll:altpll_component\|_clk0\" to source register is 2.531 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll_lcd:vga_pll\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.000 ns) 0.929 ns pll_lcd:vga_pll\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 423 " "Info: 2: + IC(0.929 ns) + CELL(0.000 ns) = 0.929 ns; Loc. = CLKCTRL_G3; Fanout = 423; COMB Node = 'pll_lcd:vga_pll\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.929 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.602 ns) 2.531 ns display_driver:vga640x480\|v_sync 3 REG LCFF_X38_Y14_N9 2 " "Info: 3: + IC(1.000 ns) + CELL(0.602 ns) = 2.531 ns; Loc. = LCFF_X38_Y14_N9; Fanout = 2; REG Node = 'display_driver:vga640x480\|v_sync'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.602 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl display_driver:vga640x480|v_sync } "NODE_NAME" } } { "display_driver.v" "" { Text "E:/vga_data_restored/display_driver.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 23.79 % ) " "Info: Total cell delay = 0.602 ns ( 23.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.929 ns ( 76.21 % ) " "Info: Total interconnect delay = 1.929 ns ( 76.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.531 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl display_driver:vga640x480|v_sync } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "2.531 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 {} pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl {} display_driver:vga640x480|v_sync {} } { 0.000ns 0.929ns 1.000ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.531 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl display_driver:vga640x480|v_sync } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "2.531 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 {} pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl {} display_driver:vga640x480|v_sync {} } { 0.000ns 0.929ns 1.000ns } { 0.000ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "2.531 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 {} pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl {} display_driver:vga640x480|v_sync {} } { 0.000ns 0.929ns 1.000ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns - " "Info: - Micro clock to output delay of source is 0.277 ns" {  } { { "display_driver.v" "" { Text "E:/vga_data_restored/display_driver.v" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "display_driver.v" "" { Text "E:/vga_data_restored/display_driver.v" 27 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.531 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl display_driver:vga640x480|v_sync } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "2.531 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 {} pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl {} display_driver:vga640x480|v_sync {} } { 0.000ns 0.929ns 1.000ns } { 0.000ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "2.531 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 {} pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl {} display_driver:vga640x480|v_sync {} } { 0.000ns 0.929ns 1.000ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.454 ns" { display_driver:vga640x480|v_sync display_driver:vga640x480|v_sync~6 display_driver:vga640x480|v_sync } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "0.454 ns" { display_driver:vga640x480|v_sync {} display_driver:vga640x480|v_sync~6 {} display_driver:vga640x480|v_sync {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.358ns 0.096ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.531 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl display_driver:vga640x480|v_sync } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "2.531 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 {} pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl {} display_driver:vga640x480|v_sync {} } { 0.000ns 0.929ns 1.000ns } { 0.000ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "2.531 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 {} pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl {} display_driver:vga640x480|v_sync {} } { 0.000ns 0.929ns 1.000ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "OSC register digitc\[0\] register bin_in\[0\] -891 ps " "Info: Minimum slack time is -891 ps for clock \"OSC\" between source register \"digitc\[0\]\" and destination register \"bin_in\[0\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.209 ns + Shortest register register " "Info: + Shortest register to register delay is 1.209 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns digitc\[0\] 1 REG LCFF_X32_Y14_N21 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y14_N21; Fanout = 7; REG Node = 'digitc\[0\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { digitc[0] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 259 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.935 ns) + CELL(0.178 ns) 1.113 ns Mux3~1 2 COMB LCCOMB_X33_Y15_N2 1 " "Info: 2: + IC(0.935 ns) + CELL(0.178 ns) = 1.113 ns; Loc. = LCCOMB_X33_Y15_N2; Fanout = 1; COMB Node = 'Mux3~1'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.113 ns" { digitc[0] Mux3~1 } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 497 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 1.209 ns bin_in\[0\] 3 REG LCFF_X33_Y15_N3 7 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 1.209 ns; Loc. = LCFF_X33_Y15_N3; Fanout = 7; REG Node = 'bin_in\[0\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.096 ns" { Mux3~1 bin_in[0] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 494 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.274 ns ( 22.66 % ) " "Info: Total cell delay = 0.274 ns ( 22.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.935 ns ( 77.34 % ) " "Info: Total interconnect delay = 0.935 ns ( 77.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.209 ns" { digitc[0] Mux3~1 bin_in[0] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "1.209 ns" { digitc[0] {} Mux3~1 {} bin_in[0] {} } { 0.000ns 0.935ns 0.000ns } { 0.000ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "2.100 ns - Smallest register register " "Info: - Smallest register to register requirement is 2.100 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination OSC 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"OSC\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source OSC 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"OSC\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.091 ns + Smallest " "Info: + Smallest clock skew is 2.091 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC destination 6.703 ns + Longest register " "Info: + Longest clock path from clock \"OSC\" to destination register is 6.703 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns OSC 1 CLK PIN_L1 7 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 7; CLK Node = 'OSC'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OSC } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.019 ns) + CELL(0.879 ns) 3.924 ns clock_module:sys_clocks\|clk_1ms 2 REG LCFF_X23_Y23_N1 1 " "Info: 2: + IC(2.019 ns) + CELL(0.879 ns) = 3.924 ns; Loc. = LCFF_X23_Y23_N1; Fanout = 1; REG Node = 'clock_module:sys_clocks\|clk_1ms'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.898 ns" { OSC clock_module:sys_clocks|clk_1ms } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.188 ns) + CELL(0.000 ns) 5.112 ns clock_module:sys_clocks\|clk_1ms~clkctrl 3 COMB CLKCTRL_G8 24 " "Info: 3: + IC(1.188 ns) + CELL(0.000 ns) = 5.112 ns; Loc. = CLKCTRL_G8; Fanout = 24; COMB Node = 'clock_module:sys_clocks\|clk_1ms~clkctrl'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.188 ns" { clock_module:sys_clocks|clk_1ms clock_module:sys_clocks|clk_1ms~clkctrl } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.989 ns) + CELL(0.602 ns) 6.703 ns bin_in\[0\] 4 REG LCFF_X33_Y15_N3 7 " "Info: 4: + IC(0.989 ns) + CELL(0.602 ns) = 6.703 ns; Loc. = LCFF_X33_Y15_N3; Fanout = 7; REG Node = 'bin_in\[0\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.591 ns" { clock_module:sys_clocks|clk_1ms~clkctrl bin_in[0] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 494 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 37.40 % ) " "Info: Total cell delay = 2.507 ns ( 37.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.196 ns ( 62.60 % ) " "Info: Total interconnect delay = 4.196 ns ( 62.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "6.703 ns" { OSC clock_module:sys_clocks|clk_1ms clock_module:sys_clocks|clk_1ms~clkctrl bin_in[0] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "6.703 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1ms {} clock_module:sys_clocks|clk_1ms~clkctrl {} bin_in[0] {} } { 0.000ns 0.000ns 2.019ns 1.188ns 0.989ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC source 4.612 ns - Shortest register " "Info: - Shortest clock path from clock \"OSC\" to source register is 4.612 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns OSC 1 CLK PIN_L1 7 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 7; CLK Node = 'OSC'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OSC } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.879 ns) 2.309 ns clock_module:sys_clocks\|clk_1s 2 REG LCFF_X1_Y13_N21 1 " "Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 1; REG Node = 'clock_module:sys_clocks\|clk_1s'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.283 ns" { OSC clock_module:sys_clocks|clk_1s } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.000 ns) 3.012 ns clock_module:sys_clocks\|clk_1s~clkctrl 3 COMB CLKCTRL_G1 24 " "Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G1; Fanout = 24; COMB Node = 'clock_module:sys_clocks\|clk_1s~clkctrl'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.703 ns" { clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.602 ns) 4.612 ns digitc\[0\] 4 REG LCFF_X32_Y14_N21 7 " "Info: 4: + IC(0.998 ns) + CELL(0.602 ns) = 4.612 ns; Loc. = LCFF_X32_Y14_N21; Fanout = 7; REG Node = 'digitc\[0\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.600 ns" { clock_module:sys_clocks|clk_1s~clkctrl digitc[0] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 259 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 54.36 % ) " "Info: Total cell delay = 2.507 ns ( 54.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.105 ns ( 45.64 % ) " "Info: Total interconnect delay = 2.105 ns ( 45.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "4.612 ns" { OSC clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl digitc[0] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "4.612 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1s {} clock_module:sys_clocks|clk_1s~clkctrl {} digitc[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.998ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "6.703 ns" { OSC clock_module:sys_clocks|clk_1ms clock_module:sys_clocks|clk_1ms~clkctrl bin_in[0] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "6.703 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1ms {} clock_module:sys_clocks|clk_1ms~clkctrl {} bin_in[0] {} } { 0.000ns 0.000ns 2.019ns 1.188ns 0.989ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "4.612 ns" { OSC clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl digitc[0] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "4.612 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1s {} clock_module:sys_clocks|clk_1s~clkctrl {} digitc[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.998ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns - " "Info: - Micro clock to output delay of source is 0.277 ns" {  } { { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 259 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 494 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "6.703 ns" { OSC clock_module:sys_clocks|clk_1ms clock_module:sys_clocks|clk_1ms~clkctrl bin_in[0] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "6.703 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1ms {} clock_module:sys_clocks|clk_1ms~clkctrl {} bin_in[0] {} } { 0.000ns 0.000ns 2.019ns 1.188ns 0.989ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "4.612 ns" { OSC clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl digitc[0] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "4.612 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1s {} clock_module:sys_clocks|clk_1s~clkctrl {} digitc[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.998ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.209 ns" { digitc[0] Mux3~1 bin_in[0] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "1.209 ns" { digitc[0] {} Mux3~1 {} bin_in[0] {} } { 0.000ns 0.935ns 0.000ns } { 0.000ns 0.178ns 0.096ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "6.703 ns" { OSC clock_module:sys_clocks|clk_1ms clock_module:sys_clocks|clk_1ms~clkctrl bin_in[0] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "6.703 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1ms {} clock_module:sys_clocks|clk_1ms~clkctrl {} bin_in[0] {} } { 0.000ns 0.000ns 2.019ns 1.188ns 0.989ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "4.612 ns" { OSC clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl digitc[0] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "4.612 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1s {} clock_module:sys_clocks|clk_1s~clkctrl {} digitc[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 0.998ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "OSC 9 " "Warning: Can't achieve minimum setup and hold requirement OSC along 9 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve minimum setup and hold requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "ram_adr\[4\] MS1 OSC 10.246 ns register " "Info: tsu for register \"ram_adr\[4\]\" (data pin = \"MS1\", clock pin = \"OSC\") is 10.246 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.390 ns + Longest pin register " "Info: + Longest pin to register delay is 10.390 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.863 ns) 0.863 ns MS1 1 PIN PIN_AA11 10 " "Info: 1: + IC(0.000 ns) + CELL(0.863 ns) = 0.863 ns; Loc. = PIN_AA11; Fanout = 10; PIN Node = 'MS1'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { MS1 } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.831 ns) + CELL(0.544 ns) 7.238 ns ram_adr\[5\]~122 2 COMB LCCOMB_X24_Y15_N4 1 " "Info: 2: + IC(5.831 ns) + CELL(0.544 ns) = 7.238 ns; Loc. = LCCOMB_X24_Y15_N4; Fanout = 1; COMB Node = 'ram_adr\[5\]~122'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "6.375 ns" { MS1 ram_adr[5]~122 } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 319 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.297 ns) + CELL(0.521 ns) 8.056 ns ram_adr\[5\]~123 3 COMB LCCOMB_X24_Y15_N6 1 " "Info: 3: + IC(0.297 ns) + CELL(0.521 ns) = 8.056 ns; Loc. = LCCOMB_X24_Y15_N6; Fanout = 1; COMB Node = 'ram_adr\[5\]~123'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.818 ns" { ram_adr[5]~122 ram_adr[5]~123 } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 319 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.313 ns) + CELL(0.455 ns) 8.824 ns ram_adr\[5\]~125 4 COMB LCCOMB_X24_Y15_N30 4 " "Info: 4: + IC(0.313 ns) + CELL(0.455 ns) = 8.824 ns; Loc. = LCCOMB_X24_Y15_N30; Fanout = 4; COMB Node = 'ram_adr\[5\]~125'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.768 ns" { ram_adr[5]~123 ram_adr[5]~125 } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 319 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.808 ns) + CELL(0.758 ns) 10.390 ns ram_adr\[4\] 5 REG LCFF_X25_Y15_N1 12 " "Info: 5: + IC(0.808 ns) + CELL(0.758 ns) = 10.390 ns; Loc. = LCFF_X25_Y15_N1; Fanout = 12; REG Node = 'ram_adr\[4\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.566 ns" { ram_adr[5]~125 ram_adr[4] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 319 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.141 ns ( 30.23 % ) " "Info: Total cell delay = 3.141 ns ( 30.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.249 ns ( 69.77 % ) " "Info: Total interconnect delay = 7.249 ns ( 69.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "10.390 ns" { MS1 ram_adr[5]~122 ram_adr[5]~123 ram_adr[5]~125 ram_adr[4] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "10.390 ns" { MS1 {} MS1~combout {} ram_adr[5]~122 {} ram_adr[5]~123 {} ram_adr[5]~125 {} ram_adr[4] {} } { 0.000ns 0.000ns 5.831ns 0.297ns 0.313ns 0.808ns } { 0.000ns 0.863ns 0.544ns 0.521ns 0.455ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 319 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_PLL_OFFSET" "OSC pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 -2.419 ns - " "Info: - Offset between input clock \"OSC\" and output clock \"pll_lcd:vga_pll\|altpll:altpll_component\|_clk0\" is -2.419 ns" {  } { { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 30 -1 0 } } { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 destination 2.525 ns - Shortest register " "Info: - Shortest clock path from clock \"pll_lcd:vga_pll\|altpll:altpll_component\|_clk0\" to destination register is 2.525 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll_lcd:vga_pll\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.000 ns) 0.929 ns pll_lcd:vga_pll\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 423 " "Info: 2: + IC(0.929 ns) + CELL(0.000 ns) = 0.929 ns; Loc. = CLKCTRL_G3; Fanout = 423; COMB Node = 'pll_lcd:vga_pll\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.929 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.602 ns) 2.525 ns ram_adr\[4\] 3 REG LCFF_X25_Y15_N1 12 " "Info: 3: + IC(0.994 ns) + CELL(0.602 ns) = 2.525 ns; Loc. = LCFF_X25_Y15_N1; Fanout = 12; REG Node = 'ram_adr\[4\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.596 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl ram_adr[4] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 319 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 23.84 % ) " "Info: Total cell delay = 0.602 ns ( 23.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.923 ns ( 76.16 % ) " "Info: Total interconnect delay = 1.923 ns ( 76.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.525 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl ram_adr[4] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "2.525 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 {} pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl {} ram_adr[4] {} } { 0.000ns 0.929ns 0.994ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "10.390 ns" { MS1 ram_adr[5]~122 ram_adr[5]~123 ram_adr[5]~125 ram_adr[4] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "10.390 ns" { MS1 {} MS1~combout {} ram_adr[5]~122 {} ram_adr[5]~123 {} ram_adr[5]~125 {} ram_adr[4] {} } { 0.000ns 0.000ns 5.831ns 0.297ns 0.313ns 0.808ns } { 0.000ns 0.863ns 0.544ns 0.521ns 0.455ns 0.758ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.525 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl ram_adr[4] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "2.525 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 {} pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl {} ram_adr[4] {} } { 0.000ns 0.929ns 0.994ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "OSC LD12 leddisp_reg\[11\] 11.914 ns register " "Info: tco from clock \"OSC\" to destination pin \"LD12\" through register \"leddisp_reg\[11\]\" is 11.914 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC source 6.447 ns + Longest register " "Info: + Longest clock path from clock \"OSC\" to source register is 6.447 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns OSC 1 CLK PIN_L1 7 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 7; CLK Node = 'OSC'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OSC } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.019 ns) + CELL(0.879 ns) 3.924 ns clock_module:sys_clocks\|clk_100ms 2 REG LCFF_X23_Y23_N25 1 " "Info: 2: + IC(2.019 ns) + CELL(0.879 ns) = 3.924 ns; Loc. = LCFF_X23_Y23_N25; Fanout = 1; REG Node = 'clock_module:sys_clocks\|clk_100ms'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.898 ns" { OSC clock_module:sys_clocks|clk_100ms } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.934 ns) + CELL(0.000 ns) 4.858 ns clock_module:sys_clocks\|clk_100ms~clkctrl 3 COMB CLKCTRL_G9 19 " "Info: 3: + IC(0.934 ns) + CELL(0.000 ns) = 4.858 ns; Loc. = CLKCTRL_G9; Fanout = 19; COMB Node = 'clock_module:sys_clocks\|clk_100ms~clkctrl'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.934 ns" { clock_module:sys_clocks|clk_100ms clock_module:sys_clocks|clk_100ms~clkctrl } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.987 ns) + CELL(0.602 ns) 6.447 ns leddisp_reg\[11\] 4 REG LCFF_X19_Y14_N23 4 " "Info: 4: + IC(0.987 ns) + CELL(0.602 ns) = 6.447 ns; Loc. = LCFF_X19_Y14_N23; Fanout = 4; REG Node = 'leddisp_reg\[11\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.589 ns" { clock_module:sys_clocks|clk_100ms~clkctrl leddisp_reg[11] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 255 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 38.89 % ) " "Info: Total cell delay = 2.507 ns ( 38.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.940 ns ( 61.11 % ) " "Info: Total interconnect delay = 3.940 ns ( 61.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "6.447 ns" { OSC clock_module:sys_clocks|clk_100ms clock_module:sys_clocks|clk_100ms~clkctrl leddisp_reg[11] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "6.447 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_100ms {} clock_module:sys_clocks|clk_100ms~clkctrl {} leddisp_reg[11] {} } { 0.000ns 0.000ns 2.019ns 0.934ns 0.987ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 255 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.190 ns + Longest register pin " "Info: + Longest register to pin delay is 5.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns leddisp_reg\[11\] 1 REG LCFF_X19_Y14_N23 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y14_N23; Fanout = 4; REG Node = 'leddisp_reg\[11\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { leddisp_reg[11] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 255 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.350 ns) + CELL(2.840 ns) 5.190 ns LD12 2 PIN PIN_N2 0 " "Info: 2: + IC(2.350 ns) + CELL(2.840 ns) = 5.190 ns; Loc. = PIN_N2; Fanout = 0; PIN Node = 'LD12'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "5.190 ns" { leddisp_reg[11] LD12 } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.840 ns ( 54.72 % ) " "Info: Total cell delay = 2.840 ns ( 54.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.350 ns ( 45.28 % ) " "Info: Total interconnect delay = 2.350 ns ( 45.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "5.190 ns" { leddisp_reg[11] LD12 } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "5.190 ns" { leddisp_reg[11] {} LD12 {} } { 0.000ns 2.350ns } { 0.000ns 2.840ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "6.447 ns" { OSC clock_module:sys_clocks|clk_100ms clock_module:sys_clocks|clk_100ms~clkctrl leddisp_reg[11] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "6.447 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_100ms {} clock_module:sys_clocks|clk_100ms~clkctrl {} leddisp_reg[11] {} } { 0.000ns 0.000ns 2.019ns 0.934ns 0.987ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "5.190 ns" { leddisp_reg[11] LD12 } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "5.190 ns" { leddisp_reg[11] {} LD12 {} } { 0.000ns 2.350ns } { 0.000ns 2.840ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_TH_RESULT" "digite\[0\] MS6 OSC -2.635 ns register " "Info: th for register \"digite\[0\]\" (data pin = \"MS6\", clock pin = \"OSC\") is -2.635 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC destination 4.614 ns + Longest register " "Info: + Longest clock path from clock \"OSC\" to destination register is 4.614 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns OSC 1 CLK PIN_L1 7 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 7; CLK Node = 'OSC'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OSC } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.879 ns) 2.309 ns clock_module:sys_clocks\|clk_1s 2 REG LCFF_X1_Y13_N21 1 " "Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 1; REG Node = 'clock_module:sys_clocks\|clk_1s'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.283 ns" { OSC clock_module:sys_clocks|clk_1s } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.000 ns) 3.012 ns clock_module:sys_clocks\|clk_1s~clkctrl 3 COMB CLKCTRL_G1 24 " "Info: 3: + IC(0.703 ns) + CELL(0.000 ns) = 3.012 ns; Loc. = CLKCTRL_G1; Fanout = 24; COMB Node = 'clock_module:sys_clocks\|clk_1s~clkctrl'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.703 ns" { clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.602 ns) 4.614 ns digite\[0\] 4 REG LCFF_X35_Y14_N27 7 " "Info: 4: + IC(1.000 ns) + CELL(0.602 ns) = 4.614 ns; Loc. = LCFF_X35_Y14_N27; Fanout = 7; REG Node = 'digite\[0\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.602 ns" { clock_module:sys_clocks|clk_1s~clkctrl digite[0] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 259 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 54.33 % ) " "Info: Total cell delay = 2.507 ns ( 54.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.107 ns ( 45.67 % ) " "Info: Total interconnect delay = 2.107 ns ( 45.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "4.614 ns" { OSC clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl digite[0] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "4.614 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1s {} clock_module:sys_clocks|clk_1s~clkctrl {} digite[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 1.000ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 259 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.535 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.833 ns) 0.833 ns MS6 1 PIN PIN_F13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.833 ns) = 0.833 ns; Loc. = PIN_F13; Fanout = 4; PIN Node = 'MS6'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { MS6 } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.727 ns) + CELL(0.178 ns) 6.738 ns digite\[0\]~56 2 COMB LCCOMB_X34_Y14_N2 4 " "Info: 2: + IC(5.727 ns) + CELL(0.178 ns) = 6.738 ns; Loc. = LCCOMB_X34_Y14_N2; Fanout = 4; COMB Node = 'digite\[0\]~56'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "5.905 ns" { MS6 digite[0]~56 } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 259 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.524 ns) + CELL(0.177 ns) 7.439 ns digite~57 3 COMB LCCOMB_X35_Y14_N26 1 " "Info: 3: + IC(0.524 ns) + CELL(0.177 ns) = 7.439 ns; Loc. = LCCOMB_X35_Y14_N26; Fanout = 1; COMB Node = 'digite~57'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.701 ns" { digite[0]~56 digite~57 } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 7.535 ns digite\[0\] 4 REG LCFF_X35_Y14_N27 7 " "Info: 4: + IC(0.000 ns) + CELL(0.096 ns) = 7.535 ns; Loc. = LCFF_X35_Y14_N27; Fanout = 7; REG Node = 'digite\[0\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.096 ns" { digite~57 digite[0] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 259 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.284 ns ( 17.04 % ) " "Info: Total cell delay = 1.284 ns ( 17.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.251 ns ( 82.96 % ) " "Info: Total interconnect delay = 6.251 ns ( 82.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "7.535 ns" { MS6 digite[0]~56 digite~57 digite[0] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "7.535 ns" { MS6 {} MS6~combout {} digite[0]~56 {} digite~57 {} digite[0] {} } { 0.000ns 0.000ns 5.727ns 0.524ns 0.000ns } { 0.000ns 0.833ns 0.178ns 0.177ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "4.614 ns" { OSC clock_module:sys_clocks|clk_1s clock_module:sys_clocks|clk_1s~clkctrl digite[0] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "4.614 ns" { OSC {} OSC~combout {} clock_module:sys_clocks|clk_1s {} clock_module:sys_clocks|clk_1s~clkctrl {} digite[0] {} } { 0.000ns 0.000ns 0.404ns 0.703ns 1.000ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "7.535 ns" { MS6 digite[0]~56 digite~57 digite[0] } "NODE_NAME" } } { "d:/altera/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin64/Technology_Viewer.qrui" "7.535 ns" { MS6 {} MS6~combout {} digite[0]~56 {} digite~57 {} digite[0] {} } { 0.000ns 0.000ns 5.727ns 0.524ns 0.000ns } { 0.000ns 0.833ns 0.178ns 0.177ns 0.096ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WTAN_REQUIREMENTS_NOT_MET_SLOW" "" "Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details." {  } {  } 1 0 "Timing requirements for slow timing model timing analysis were not met. See Report window for details." 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Info: Quartus II 64-Bit Classic Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "208 " "Info: Peak virtual memory: 208 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 04:58:14 2009 " "Info: Processing ended: Sat May 09 04:58:14 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}