|vga_data OSC => OSC~0.IN2 OSCO => ~NO_FANOUT~ RXD => ~NO_FANOUT~ RTS => ~NO_FANOUT~ CTS => ~NO_FANOUT~ DSR => ~NO_FANOUT~ DTR => ~NO_FANOUT~ DCD => ~NO_FANOUT~ RI => ~NO_FANOUT~ DS1 => ~NO_FANOUT~ DS2 => ~NO_FANOUT~ DS3 => ~NO_FANOUT~ DS4 => ~NO_FANOUT~ DS5 => ~NO_FANOUT~ DS6 => ~NO_FANOUT~ DS7 => ~NO_FANOUT~ DS8 => ~NO_FANOUT~ MS1 => ram_state~29.DATAB MS1 => ram_state~28.DATAB MS1 => ram_state_ena~1.OUTPUTSELECT MS1 => ascii_reg~15.OUTPUTSELECT MS1 => ascii_reg~14.OUTPUTSELECT MS1 => ascii_reg~13.OUTPUTSELECT MS1 => ascii_reg~12.OUTPUTSELECT MS1 => ascii_reg~11.OUTPUTSELECT MS1 => ascii_reg~10.OUTPUTSELECT MS1 => ascii_reg~9.OUTPUTSELECT MS1 => ascii_reg~8.OUTPUTSELECT MS1 => ram_adr~50.OUTPUTSELECT MS1 => ram_adr~49.OUTPUTSELECT MS1 => ram_adr~48.OUTPUTSELECT MS1 => ram_adr~47.OUTPUTSELECT MS1 => ram_adr~46.OUTPUTSELECT MS1 => ram_adr~45.OUTPUTSELECT MS1 => ram_adr~44.OUTPUTSELECT MS1 => ram_adr~43.OUTPUTSELECT MS1 => ram_adr~42.OUTPUTSELECT MS1 => ram_adr~41.OUTPUTSELECT MS1 => ram_adr~40.OUTPUTSELECT MS1 => ram_adr~39.OUTPUTSELECT MS1 => ascii_ena~1.OUTPUTSELECT MS2 => always1~1.IN0 MS2 => digitb~7.OUTPUTSELECT MS2 => digitb~6.OUTPUTSELECT MS2 => digitb~5.OUTPUTSELECT MS2 => digitb~4.OUTPUTSELECT MS3 => always1~1.IN1 MS3 => digitc~7.OUTPUTSELECT MS3 => digitc~6.OUTPUTSELECT MS3 => digitc~5.OUTPUTSELECT MS3 => digitc~4.OUTPUTSELECT MS4 => always1~2.IN1 MS4 => digitd~7.OUTPUTSELECT MS4 => digitd~6.OUTPUTSELECT MS4 => digitd~5.OUTPUTSELECT MS4 => digitd~4.OUTPUTSELECT MS5 => always1~3.IN1 MS5 => digite~11.OUTPUTSELECT MS5 => digite~10.OUTPUTSELECT MS5 => digite~9.OUTPUTSELECT MS5 => digite~8.OUTPUTSELECT MS6 => always1~4.IN1 MS6 => digite~23.OUTPUTSELECT MS6 => digite~22.OUTPUTSELECT MS6 => digite~21.OUTPUTSELECT MS6 => digite~20.OUTPUTSELECT MS6 => digitf~11.OUTPUTSELECT MS6 => digitf~10.OUTPUTSELECT MS6 => digitf~9.OUTPUTSELECT MS6 => digitf~8.OUTPUTSELECT PS2_DATA => ~NO_FANOUT~ PS2_CLK => ~NO_FANOUT~ CON1 <= CON2 <= CON3 <= CON4 <= CON5 <= CON6 <= CON7 <= CON8 <= CON9 <= CON10 <= CON11 <= CON12 <= CON13 <= CON14 <= CON15 <= CON16 <= CON17 <= CON18 <= CON19 <= CON20 <= DI => ~NO_FANOUT~ DO => ~NO_FANOUT~ TSOP => ~NO_FANOUT~ TXD <= CS_FLASH <= LD1 <= leddisp_reg[0].DB_MAX_OUTPUT_PORT_TYPE LD2 <= leddisp_reg[1].DB_MAX_OUTPUT_PORT_TYPE LD3 <= leddisp_reg[2].DB_MAX_OUTPUT_PORT_TYPE LD4 <= leddisp_reg[3].DB_MAX_OUTPUT_PORT_TYPE LD5 <= leddisp_reg[4].DB_MAX_OUTPUT_PORT_TYPE LD6 <= leddisp_reg[5].DB_MAX_OUTPUT_PORT_TYPE LD7 <= leddisp_reg[6].DB_MAX_OUTPUT_PORT_TYPE LD8 <= leddisp_reg[7].DB_MAX_OUTPUT_PORT_TYPE LD9 <= leddisp_reg[8].DB_MAX_OUTPUT_PORT_TYPE LD10 <= leddisp_reg[9].DB_MAX_OUTPUT_PORT_TYPE LD11 <= leddisp_reg[10].DB_MAX_OUTPUT_PORT_TYPE LD12 <= leddisp_reg[11].DB_MAX_OUTPUT_PORT_TYPE LD13 <= leddisp_reg[12].DB_MAX_OUTPUT_PORT_TYPE LD14 <= leddisp_reg[13].DB_MAX_OUTPUT_PORT_TYPE LD15 <= leddisp_reg[14].DB_MAX_OUTPUT_PORT_TYPE LD16 <= leddisp_reg[15].DB_MAX_OUTPUT_PORT_TYPE SCK <= LEDA <= LEDB <= SEG_A <= SEG_A~reg0.DB_MAX_OUTPUT_PORT_TYPE SEG_B <= SEG_B~reg0.DB_MAX_OUTPUT_PORT_TYPE SEG_C <= SEG_C~reg0.DB_MAX_OUTPUT_PORT_TYPE SEG_D <= SEG_D~reg0.DB_MAX_OUTPUT_PORT_TYPE LSB_R <= display_driver:vga640x480.R_color MSB_R <= display_driver:vga640x480.R_color LSB_G <= display_driver:vga640x480.G_color MSB_G <= display_driver:vga640x480.G_color LSB_B <= display_driver:vga640x480.B_color MSB_B <= display_driver:vga640x480.B_color A <= A~reg0.DB_MAX_OUTPUT_PORT_TYPE B <= B~reg0.DB_MAX_OUTPUT_PORT_TYPE C <= C~reg0.DB_MAX_OUTPUT_PORT_TYPE D <= D~reg0.DB_MAX_OUTPUT_PORT_TYPE E <= E~reg0.DB_MAX_OUTPUT_PORT_TYPE F <= F~reg0.DB_MAX_OUTPUT_PORT_TYPE G <= G~reg0.DB_MAX_OUTPUT_PORT_TYPE DP <= HS <= display_driver:vga640x480.h_sync VS <= display_driver:vga640x480.v_sync |vga_data|display_driver:vga640x480 clk_vga => clk_vga~0.IN2 resetn => disp1_reg~0.IN1 resetn => h_state~12.OUTPUTSELECT resetn => h_state~11.OUTPUTSELECT resetn => h_state~10.OUTPUTSELECT resetn => h_state~9.OUTPUTSELECT resetn => font_pnt~21.OUTPUTSELECT resetn => font_pnt~20.OUTPUTSELECT resetn => font_pnt~19.OUTPUTSELECT resetn => font_pnt~18.OUTPUTSELECT resetn => font_pnt~17.OUTPUTSELECT resetn => font_pnt~16.OUTPUTSELECT resetn => font_pnt~15.OUTPUTSELECT resetn => font_pnt~14.OUTPUTSELECT resetn => font_pnt~13.OUTPUTSELECT resetn => font_pnt~12.OUTPUTSELECT resetn => font_pnt~11.OUTPUTSELECT resetn => char_pnt~103.OUTPUTSELECT resetn => char_pnt~102.OUTPUTSELECT resetn => char_pnt~101.OUTPUTSELECT resetn => char_pnt~100.OUTPUTSELECT resetn => char_pnt~99.OUTPUTSELECT resetn => char_pnt~98.OUTPUTSELECT resetn => char_pnt~97.OUTPUTSELECT resetn => char_pnt~96.OUTPUTSELECT resetn => char_pnt~95.OUTPUTSELECT resetn => char_pnt~94.OUTPUTSELECT resetn => char_pnt~93.OUTPUTSELECT resetn => char_pnt~92.OUTPUTSELECT resetn => char_pnt~91.OUTPUTSELECT resetn => zone~4.OUTPUTSELECT resetn => zone~3.OUTPUTSELECT resetn => zone~2.OUTPUTSELECT resetn => disp_dly~9.OUTPUTSELECT resetn => disp_dly~8.OUTPUTSELECT resetn => disp_dly~7.OUTPUTSELECT resetn => disp_dly~6.OUTPUTSELECT resetn => disp_dly~5.OUTPUTSELECT resetn => disp1_reg~2.OUTPUTSELECT resetn => disp_reg~0.OUTPUTSELECT resetn => disp~1.OUTPUTSELECT resetn => h_dot_reg[7].ENA resetn => h_dot_reg[6].ENA resetn => h_dot_reg[5].ENA resetn => h_dot_reg[4].ENA resetn => h_dot_reg[3].ENA resetn => h_dot_reg[2].ENA resetn => h_dot_reg[1].ENA resetn => h_dot_reg[0].ENA resetn => h_dot_pix[0].ENA resetn => h_dot_pix[1].ENA resetn => h_dot_pix[2].ENA resetn => h_dot_pix[3].ENA resetn => h_dot_pix[4].ENA resetn => h_dot_pix[5].ENA resetn => h_dot_cnt[0].ENA resetn => h_dot_cnt[1].ENA resetn => h_dot_cnt[2].ENA resetn => h_dot_cnt[3].ENA resetn => h_dot_cnt[4].ENA resetn => h_dot_cnt[5].ENA resetn => B_color[0]~reg0.ENA resetn => B_color[1]~reg0.ENA resetn => G_color[0]~reg0.ENA resetn => G_color[1]~reg0.ENA resetn => R_color[0]~reg0.ENA resetn => R_color[1]~reg0.ENA resetn => char_ena.ENA resetn => font_reg[0].ENA resetn => font_reg[1].ENA resetn => font_reg[2].ENA resetn => font_reg[3].ENA resetn => font_reg[4].ENA resetn => font_reg[5].ENA resetn => font_reg[6].ENA resetn => font_reg[7].ENA resetn => char_reg[0].ENA resetn => char_reg[1].ENA resetn => char_reg[2].ENA resetn => char_reg[3].ENA resetn => char_reg[4].ENA resetn => char_reg[5].ENA resetn => char_reg[6].ENA resetn => char_reg[7].ENA resetn => v_dot_cnt[0].ENA resetn => v_dot_cnt[1].ENA resetn => v_dot_cnt[2].ENA resetn => v_dot_cnt[3].ENA resetn => v_dot_cnt[4].ENA resetn => v_dot_cnt[5].ENA resetn => v_dot_pix[0].ENA resetn => v_dot_pix[1].ENA resetn => v_dot_pix[2].ENA resetn => v_dot_pix[3].ENA resetn => v_dot_pix[4].ENA resetn => v_dot_pix[5].ENA resetn => v_pixel_cnt[0].ENA resetn => v_pixel_cnt[1].ENA resetn => v_pixel_cnt[2].ENA resetn => v_pixel_cnt[3].ENA resetn => v_pixel_cnt[4].ENA resetn => v_pixel_cnt[5].ENA resetn => v_pixel_cnt[6].ENA resetn => v_pixel_cnt[7].ENA resetn => v_pixel_cnt[8].ENA resetn => v_pixel_cnt[9].ENA resetn => v_sync~reg0.ENA resetn => h_pixel_cnt[0].ENA resetn => h_pixel_cnt[1].ENA resetn => h_pixel_cnt[2].ENA resetn => h_pixel_cnt[3].ENA resetn => h_pixel_cnt[4].ENA resetn => h_pixel_cnt[5].ENA resetn => h_pixel_cnt[6].ENA resetn => h_pixel_cnt[7].ENA resetn => h_pixel_cnt[8].ENA resetn => h_pixel_cnt[9].ENA resetn => h_sync~reg0.ENA resetn => v_flag_img.ENA resetn => v_flag_dot.ENA resetn => h_flag_dot.ENA resetn => h_flag_img.ENA dpram_wr => dpram_wr~0.IN1 dpram_data[0] => dpram_data[0]~7.IN1 dpram_data[1] => dpram_data[1]~6.IN1 dpram_data[2] => dpram_data[2]~5.IN1 dpram_data[3] => dpram_data[3]~4.IN1 dpram_data[4] => dpram_data[4]~3.IN1 dpram_data[5] => dpram_data[5]~2.IN1 dpram_data[6] => dpram_data[6]~1.IN1 dpram_data[7] => dpram_data[7]~0.IN1 dpram_adr[0] => dpram_adr[0]~11.IN1 dpram_adr[1] => dpram_adr[1]~10.IN1 dpram_adr[2] => dpram_adr[2]~9.IN1 dpram_adr[3] => dpram_adr[3]~8.IN1 dpram_adr[4] => dpram_adr[4]~7.IN1 dpram_adr[5] => dpram_adr[5]~6.IN1 dpram_adr[6] => dpram_adr[6]~5.IN1 dpram_adr[7] => dpram_adr[7]~4.IN1 dpram_adr[8] => dpram_adr[8]~3.IN1 dpram_adr[9] => dpram_adr[9]~2.IN1 dpram_adr[10] => dpram_adr[10]~1.IN1 dpram_adr[11] => dpram_adr[11]~0.IN1 h_sync <= h_sync~reg0.DB_MAX_OUTPUT_PORT_TYPE v_sync <= v_sync~reg0.DB_MAX_OUTPUT_PORT_TYPE disp <= disp~reg0.DB_MAX_OUTPUT_PORT_TYPE R_color[0] <= R_color[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE R_color[1] <= R_color[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE G_color[0] <= G_color[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE G_color[1] <= G_color[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE B_color[0] <= B_color[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE B_color[1] <= B_color[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |vga_data|display_driver:vga640x480|font_ram:font5x7 address[0] => address[0]~10.IN1 address[1] => address[1]~9.IN1 address[2] => address[2]~8.IN1 address[3] => address[3]~7.IN1 address[4] => address[4]~6.IN1 address[5] => address[5]~5.IN1 address[6] => address[6]~4.IN1 address[7] => address[7]~3.IN1 address[8] => address[8]~2.IN1 address[9] => address[9]~1.IN1 address[10] => address[10]~0.IN1 clock => clock~0.IN1 data[0] => data[0]~7.IN1 data[1] => data[1]~6.IN1 data[2] => data[2]~5.IN1 data[3] => data[3]~4.IN1 data[4] => data[4]~3.IN1 data[5] => data[5]~2.IN1 data[6] => data[6]~1.IN1 data[7] => data[7]~0.IN1 wren => wren~0.IN1 q[0] <= altsyncram:altsyncram_component.q_a q[1] <= altsyncram:altsyncram_component.q_a q[2] <= altsyncram:altsyncram_component.q_a q[3] <= altsyncram:altsyncram_component.q_a q[4] <= altsyncram:altsyncram_component.q_a q[5] <= altsyncram:altsyncram_component.q_a q[6] <= altsyncram:altsyncram_component.q_a q[7] <= altsyncram:altsyncram_component.q_a |vga_data|display_driver:vga640x480|font_ram:font5x7|altsyncram:altsyncram_component wren_a => altsyncram_bld1:auto_generated.wren_a rden_a => ~NO_FANOUT~ wren_b => ~NO_FANOUT~ rden_b => ~NO_FANOUT~ data_a[0] => altsyncram_bld1:auto_generated.data_a[0] data_a[1] => altsyncram_bld1:auto_generated.data_a[1] data_a[2] => altsyncram_bld1:auto_generated.data_a[2] data_a[3] => altsyncram_bld1:auto_generated.data_a[3] data_a[4] => altsyncram_bld1:auto_generated.data_a[4] data_a[5] => altsyncram_bld1:auto_generated.data_a[5] data_a[6] => altsyncram_bld1:auto_generated.data_a[6] data_a[7] => altsyncram_bld1:auto_generated.data_a[7] data_b[0] => ~NO_FANOUT~ address_a[0] => altsyncram_bld1:auto_generated.address_a[0] address_a[1] => altsyncram_bld1:auto_generated.address_a[1] address_a[2] => altsyncram_bld1:auto_generated.address_a[2] address_a[3] => altsyncram_bld1:auto_generated.address_a[3] address_a[4] => altsyncram_bld1:auto_generated.address_a[4] address_a[5] => altsyncram_bld1:auto_generated.address_a[5] address_a[6] => altsyncram_bld1:auto_generated.address_a[6] address_a[7] => altsyncram_bld1:auto_generated.address_a[7] address_a[8] => altsyncram_bld1:auto_generated.address_a[8] address_a[9] => altsyncram_bld1:auto_generated.address_a[9] address_a[10] => altsyncram_bld1:auto_generated.address_a[10] address_b[0] => ~NO_FANOUT~ addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_bld1:auto_generated.clock0 clock1 => ~NO_FANOUT~ clocken0 => ~NO_FANOUT~ clocken1 => ~NO_FANOUT~ clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= altsyncram_bld1:auto_generated.q_a[0] q_a[1] <= altsyncram_bld1:auto_generated.q_a[1] q_a[2] <= altsyncram_bld1:auto_generated.q_a[2] q_a[3] <= altsyncram_bld1:auto_generated.q_a[3] q_a[4] <= altsyncram_bld1:auto_generated.q_a[4] q_a[5] <= altsyncram_bld1:auto_generated.q_a[5] q_a[6] <= altsyncram_bld1:auto_generated.q_a[6] q_a[7] <= altsyncram_bld1:auto_generated.q_a[7] q_b[0] <= eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |vga_data|display_driver:vga640x480|font_ram:font5x7|altsyncram:altsyncram_component|altsyncram_bld1:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[5] => ram_block1a0.PORTAADDR5 address_a[5] => ram_block1a1.PORTAADDR5 address_a[5] => ram_block1a2.PORTAADDR5 address_a[5] => ram_block1a3.PORTAADDR5 address_a[5] => ram_block1a4.PORTAADDR5 address_a[5] => ram_block1a5.PORTAADDR5 address_a[5] => ram_block1a6.PORTAADDR5 address_a[5] => ram_block1a7.PORTAADDR5 address_a[6] => ram_block1a0.PORTAADDR6 address_a[6] => ram_block1a1.PORTAADDR6 address_a[6] => ram_block1a2.PORTAADDR6 address_a[6] => ram_block1a3.PORTAADDR6 address_a[6] => ram_block1a4.PORTAADDR6 address_a[6] => ram_block1a5.PORTAADDR6 address_a[6] => ram_block1a6.PORTAADDR6 address_a[6] => ram_block1a7.PORTAADDR6 address_a[7] => ram_block1a0.PORTAADDR7 address_a[7] => ram_block1a1.PORTAADDR7 address_a[7] => ram_block1a2.PORTAADDR7 address_a[7] => ram_block1a3.PORTAADDR7 address_a[7] => ram_block1a4.PORTAADDR7 address_a[7] => ram_block1a5.PORTAADDR7 address_a[7] => ram_block1a6.PORTAADDR7 address_a[7] => ram_block1a7.PORTAADDR7 address_a[8] => ram_block1a0.PORTAADDR8 address_a[8] => ram_block1a1.PORTAADDR8 address_a[8] => ram_block1a2.PORTAADDR8 address_a[8] => ram_block1a3.PORTAADDR8 address_a[8] => ram_block1a4.PORTAADDR8 address_a[8] => ram_block1a5.PORTAADDR8 address_a[8] => ram_block1a6.PORTAADDR8 address_a[8] => ram_block1a7.PORTAADDR8 address_a[9] => ram_block1a0.PORTAADDR9 address_a[9] => ram_block1a1.PORTAADDR9 address_a[9] => ram_block1a2.PORTAADDR9 address_a[9] => ram_block1a3.PORTAADDR9 address_a[9] => ram_block1a4.PORTAADDR9 address_a[9] => ram_block1a5.PORTAADDR9 address_a[9] => ram_block1a6.PORTAADDR9 address_a[9] => ram_block1a7.PORTAADDR9 address_a[10] => ram_block1a0.PORTAADDR10 address_a[10] => ram_block1a1.PORTAADDR10 address_a[10] => ram_block1a2.PORTAADDR10 address_a[10] => ram_block1a3.PORTAADDR10 address_a[10] => ram_block1a4.PORTAADDR10 address_a[10] => ram_block1a5.PORTAADDR10 address_a[10] => ram_block1a6.PORTAADDR10 address_a[10] => ram_block1a7.PORTAADDR10 clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 data_a[0] => ram_block1a0.PORTADATAIN data_a[1] => ram_block1a1.PORTADATAIN data_a[2] => ram_block1a2.PORTADATAIN data_a[3] => ram_block1a3.PORTADATAIN data_a[4] => ram_block1a4.PORTADATAIN data_a[5] => ram_block1a5.PORTADATAIN data_a[6] => ram_block1a6.PORTADATAIN data_a[7] => ram_block1a7.PORTADATAIN q_a[0] <= ram_block1a0.PORTADATAOUT q_a[1] <= ram_block1a1.PORTADATAOUT q_a[2] <= ram_block1a2.PORTADATAOUT q_a[3] <= ram_block1a3.PORTADATAOUT q_a[4] <= ram_block1a4.PORTADATAOUT q_a[5] <= ram_block1a5.PORTADATAOUT q_a[6] <= ram_block1a6.PORTADATAOUT q_a[7] <= ram_block1a7.PORTADATAOUT wren_a => ram_block1a0.PORTAWE wren_a => ram_block1a1.PORTAWE wren_a => ram_block1a2.PORTAWE wren_a => ram_block1a3.PORTAWE wren_a => ram_block1a4.PORTAWE wren_a => ram_block1a5.PORTAWE wren_a => ram_block1a6.PORTAWE wren_a => ram_block1a7.PORTAWE |vga_data|display_driver:vga640x480|dpram_32x128:dp_ram1 clock => clock~0.IN1 data[0] => data[0]~7.IN1 data[1] => data[1]~6.IN1 data[2] => data[2]~5.IN1 data[3] => data[3]~4.IN1 data[4] => data[4]~3.IN1 data[5] => data[5]~2.IN1 data[6] => data[6]~1.IN1 data[7] => data[7]~0.IN1 rdaddress[0] => rdaddress[0]~11.IN1 rdaddress[1] => rdaddress[1]~10.IN1 rdaddress[2] => rdaddress[2]~9.IN1 rdaddress[3] => rdaddress[3]~8.IN1 rdaddress[4] => rdaddress[4]~7.IN1 rdaddress[5] => rdaddress[5]~6.IN1 rdaddress[6] => rdaddress[6]~5.IN1 rdaddress[7] => rdaddress[7]~4.IN1 rdaddress[8] => rdaddress[8]~3.IN1 rdaddress[9] => rdaddress[9]~2.IN1 rdaddress[10] => rdaddress[10]~1.IN1 rdaddress[11] => rdaddress[11]~0.IN1 wraddress[0] => wraddress[0]~11.IN1 wraddress[1] => wraddress[1]~10.IN1 wraddress[2] => wraddress[2]~9.IN1 wraddress[3] => wraddress[3]~8.IN1 wraddress[4] => wraddress[4]~7.IN1 wraddress[5] => wraddress[5]~6.IN1 wraddress[6] => wraddress[6]~5.IN1 wraddress[7] => wraddress[7]~4.IN1 wraddress[8] => wraddress[8]~3.IN1 wraddress[9] => wraddress[9]~2.IN1 wraddress[10] => wraddress[10]~1.IN1 wraddress[11] => wraddress[11]~0.IN1 wren => wren~0.IN1 q[0] <= altsyncram:altsyncram_component.q_b q[1] <= altsyncram:altsyncram_component.q_b q[2] <= altsyncram:altsyncram_component.q_b q[3] <= altsyncram:altsyncram_component.q_b q[4] <= altsyncram:altsyncram_component.q_b q[5] <= altsyncram:altsyncram_component.q_b q[6] <= altsyncram:altsyncram_component.q_b q[7] <= altsyncram:altsyncram_component.q_b |vga_data|display_driver:vga640x480|dpram_32x128:dp_ram1|altsyncram:altsyncram_component wren_a => altsyncram_1io1:auto_generated.wren_a rden_a => ~NO_FANOUT~ wren_b => ~NO_FANOUT~ rden_b => ~NO_FANOUT~ data_a[0] => altsyncram_1io1:auto_generated.data_a[0] data_a[1] => altsyncram_1io1:auto_generated.data_a[1] data_a[2] => altsyncram_1io1:auto_generated.data_a[2] data_a[3] => altsyncram_1io1:auto_generated.data_a[3] data_a[4] => altsyncram_1io1:auto_generated.data_a[4] data_a[5] => altsyncram_1io1:auto_generated.data_a[5] data_a[6] => altsyncram_1io1:auto_generated.data_a[6] data_a[7] => altsyncram_1io1:auto_generated.data_a[7] data_b[0] => ~NO_FANOUT~ data_b[1] => ~NO_FANOUT~ data_b[2] => ~NO_FANOUT~ data_b[3] => ~NO_FANOUT~ data_b[4] => ~NO_FANOUT~ data_b[5] => ~NO_FANOUT~ data_b[6] => ~NO_FANOUT~ data_b[7] => ~NO_FANOUT~ address_a[0] => altsyncram_1io1:auto_generated.address_a[0] address_a[1] => altsyncram_1io1:auto_generated.address_a[1] address_a[2] => altsyncram_1io1:auto_generated.address_a[2] address_a[3] => altsyncram_1io1:auto_generated.address_a[3] address_a[4] => altsyncram_1io1:auto_generated.address_a[4] address_a[5] => altsyncram_1io1:auto_generated.address_a[5] address_a[6] => altsyncram_1io1:auto_generated.address_a[6] address_a[7] => altsyncram_1io1:auto_generated.address_a[7] address_a[8] => altsyncram_1io1:auto_generated.address_a[8] address_a[9] => altsyncram_1io1:auto_generated.address_a[9] address_a[10] => altsyncram_1io1:auto_generated.address_a[10] address_a[11] => altsyncram_1io1:auto_generated.address_a[11] address_b[0] => altsyncram_1io1:auto_generated.address_b[0] address_b[1] => altsyncram_1io1:auto_generated.address_b[1] address_b[2] => altsyncram_1io1:auto_generated.address_b[2] address_b[3] => altsyncram_1io1:auto_generated.address_b[3] address_b[4] => altsyncram_1io1:auto_generated.address_b[4] address_b[5] => altsyncram_1io1:auto_generated.address_b[5] address_b[6] => altsyncram_1io1:auto_generated.address_b[6] address_b[7] => altsyncram_1io1:auto_generated.address_b[7] address_b[8] => altsyncram_1io1:auto_generated.address_b[8] address_b[9] => altsyncram_1io1:auto_generated.address_b[9] address_b[10] => altsyncram_1io1:auto_generated.address_b[10] address_b[11] => altsyncram_1io1:auto_generated.address_b[11] addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_1io1:auto_generated.clock0 clock1 => ~NO_FANOUT~ clocken0 => ~NO_FANOUT~ clocken1 => ~NO_FANOUT~ clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= q_a[1] <= q_a[2] <= q_a[3] <= q_a[4] <= q_a[5] <= q_a[6] <= q_a[7] <= q_b[0] <= altsyncram_1io1:auto_generated.q_b[0] q_b[1] <= altsyncram_1io1:auto_generated.q_b[1] q_b[2] <= altsyncram_1io1:auto_generated.q_b[2] q_b[3] <= altsyncram_1io1:auto_generated.q_b[3] q_b[4] <= altsyncram_1io1:auto_generated.q_b[4] q_b[5] <= altsyncram_1io1:auto_generated.q_b[5] q_b[6] <= altsyncram_1io1:auto_generated.q_b[6] q_b[7] <= altsyncram_1io1:auto_generated.q_b[7] eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |vga_data|display_driver:vga640x480|dpram_32x128:dp_ram1|altsyncram:altsyncram_component|altsyncram_1io1:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[5] => ram_block1a0.PORTAADDR5 address_a[5] => ram_block1a1.PORTAADDR5 address_a[5] => ram_block1a2.PORTAADDR5 address_a[5] => ram_block1a3.PORTAADDR5 address_a[5] => ram_block1a4.PORTAADDR5 address_a[5] => ram_block1a5.PORTAADDR5 address_a[5] => ram_block1a6.PORTAADDR5 address_a[5] => ram_block1a7.PORTAADDR5 address_a[6] => ram_block1a0.PORTAADDR6 address_a[6] => ram_block1a1.PORTAADDR6 address_a[6] => ram_block1a2.PORTAADDR6 address_a[6] => ram_block1a3.PORTAADDR6 address_a[6] => ram_block1a4.PORTAADDR6 address_a[6] => ram_block1a5.PORTAADDR6 address_a[6] => ram_block1a6.PORTAADDR6 address_a[6] => ram_block1a7.PORTAADDR6 address_a[7] => ram_block1a0.PORTAADDR7 address_a[7] => ram_block1a1.PORTAADDR7 address_a[7] => ram_block1a2.PORTAADDR7 address_a[7] => ram_block1a3.PORTAADDR7 address_a[7] => ram_block1a4.PORTAADDR7 address_a[7] => ram_block1a5.PORTAADDR7 address_a[7] => ram_block1a6.PORTAADDR7 address_a[7] => ram_block1a7.PORTAADDR7 address_a[8] => ram_block1a0.PORTAADDR8 address_a[8] => ram_block1a1.PORTAADDR8 address_a[8] => ram_block1a2.PORTAADDR8 address_a[8] => ram_block1a3.PORTAADDR8 address_a[8] => ram_block1a4.PORTAADDR8 address_a[8] => ram_block1a5.PORTAADDR8 address_a[8] => ram_block1a6.PORTAADDR8 address_a[8] => ram_block1a7.PORTAADDR8 address_a[9] => ram_block1a0.PORTAADDR9 address_a[9] => ram_block1a1.PORTAADDR9 address_a[9] => ram_block1a2.PORTAADDR9 address_a[9] => ram_block1a3.PORTAADDR9 address_a[9] => ram_block1a4.PORTAADDR9 address_a[9] => ram_block1a5.PORTAADDR9 address_a[9] => ram_block1a6.PORTAADDR9 address_a[9] => ram_block1a7.PORTAADDR9 address_a[10] => ram_block1a0.PORTAADDR10 address_a[10] => ram_block1a1.PORTAADDR10 address_a[10] => ram_block1a2.PORTAADDR10 address_a[10] => ram_block1a3.PORTAADDR10 address_a[10] => ram_block1a4.PORTAADDR10 address_a[10] => ram_block1a5.PORTAADDR10 address_a[10] => ram_block1a6.PORTAADDR10 address_a[10] => ram_block1a7.PORTAADDR10 address_a[11] => ram_block1a0.PORTAADDR11 address_a[11] => ram_block1a1.PORTAADDR11 address_a[11] => ram_block1a2.PORTAADDR11 address_a[11] => ram_block1a3.PORTAADDR11 address_a[11] => ram_block1a4.PORTAADDR11 address_a[11] => ram_block1a5.PORTAADDR11 address_a[11] => ram_block1a6.PORTAADDR11 address_a[11] => ram_block1a7.PORTAADDR11 address_b[0] => ram_block1a0.PORTBADDR address_b[0] => ram_block1a1.PORTBADDR address_b[0] => ram_block1a2.PORTBADDR address_b[0] => ram_block1a3.PORTBADDR address_b[0] => ram_block1a4.PORTBADDR address_b[0] => ram_block1a5.PORTBADDR address_b[0] => ram_block1a6.PORTBADDR address_b[0] => ram_block1a7.PORTBADDR address_b[1] => ram_block1a0.PORTBADDR1 address_b[1] => ram_block1a1.PORTBADDR1 address_b[1] => ram_block1a2.PORTBADDR1 address_b[1] => ram_block1a3.PORTBADDR1 address_b[1] => ram_block1a4.PORTBADDR1 address_b[1] => ram_block1a5.PORTBADDR1 address_b[1] => ram_block1a6.PORTBADDR1 address_b[1] => ram_block1a7.PORTBADDR1 address_b[2] => ram_block1a0.PORTBADDR2 address_b[2] => ram_block1a1.PORTBADDR2 address_b[2] => ram_block1a2.PORTBADDR2 address_b[2] => ram_block1a3.PORTBADDR2 address_b[2] => ram_block1a4.PORTBADDR2 address_b[2] => ram_block1a5.PORTBADDR2 address_b[2] => ram_block1a6.PORTBADDR2 address_b[2] => ram_block1a7.PORTBADDR2 address_b[3] => ram_block1a0.PORTBADDR3 address_b[3] => ram_block1a1.PORTBADDR3 address_b[3] => ram_block1a2.PORTBADDR3 address_b[3] => ram_block1a3.PORTBADDR3 address_b[3] => ram_block1a4.PORTBADDR3 address_b[3] => ram_block1a5.PORTBADDR3 address_b[3] => ram_block1a6.PORTBADDR3 address_b[3] => ram_block1a7.PORTBADDR3 address_b[4] => ram_block1a0.PORTBADDR4 address_b[4] => ram_block1a1.PORTBADDR4 address_b[4] => ram_block1a2.PORTBADDR4 address_b[4] => ram_block1a3.PORTBADDR4 address_b[4] => ram_block1a4.PORTBADDR4 address_b[4] => ram_block1a5.PORTBADDR4 address_b[4] => ram_block1a6.PORTBADDR4 address_b[4] => ram_block1a7.PORTBADDR4 address_b[5] => ram_block1a0.PORTBADDR5 address_b[5] => ram_block1a1.PORTBADDR5 address_b[5] => ram_block1a2.PORTBADDR5 address_b[5] => ram_block1a3.PORTBADDR5 address_b[5] => ram_block1a4.PORTBADDR5 address_b[5] => ram_block1a5.PORTBADDR5 address_b[5] => ram_block1a6.PORTBADDR5 address_b[5] => ram_block1a7.PORTBADDR5 address_b[6] => ram_block1a0.PORTBADDR6 address_b[6] => ram_block1a1.PORTBADDR6 address_b[6] => ram_block1a2.PORTBADDR6 address_b[6] => ram_block1a3.PORTBADDR6 address_b[6] => ram_block1a4.PORTBADDR6 address_b[6] => ram_block1a5.PORTBADDR6 address_b[6] => ram_block1a6.PORTBADDR6 address_b[6] => ram_block1a7.PORTBADDR6 address_b[7] => ram_block1a0.PORTBADDR7 address_b[7] => ram_block1a1.PORTBADDR7 address_b[7] => ram_block1a2.PORTBADDR7 address_b[7] => ram_block1a3.PORTBADDR7 address_b[7] => ram_block1a4.PORTBADDR7 address_b[7] => ram_block1a5.PORTBADDR7 address_b[7] => ram_block1a6.PORTBADDR7 address_b[7] => ram_block1a7.PORTBADDR7 address_b[8] => ram_block1a0.PORTBADDR8 address_b[8] => ram_block1a1.PORTBADDR8 address_b[8] => ram_block1a2.PORTBADDR8 address_b[8] => ram_block1a3.PORTBADDR8 address_b[8] => ram_block1a4.PORTBADDR8 address_b[8] => ram_block1a5.PORTBADDR8 address_b[8] => ram_block1a6.PORTBADDR8 address_b[8] => ram_block1a7.PORTBADDR8 address_b[9] => ram_block1a0.PORTBADDR9 address_b[9] => ram_block1a1.PORTBADDR9 address_b[9] => ram_block1a2.PORTBADDR9 address_b[9] => ram_block1a3.PORTBADDR9 address_b[9] => ram_block1a4.PORTBADDR9 address_b[9] => ram_block1a5.PORTBADDR9 address_b[9] => ram_block1a6.PORTBADDR9 address_b[9] => ram_block1a7.PORTBADDR9 address_b[10] => ram_block1a0.PORTBADDR10 address_b[10] => ram_block1a1.PORTBADDR10 address_b[10] => ram_block1a2.PORTBADDR10 address_b[10] => ram_block1a3.PORTBADDR10 address_b[10] => ram_block1a4.PORTBADDR10 address_b[10] => ram_block1a5.PORTBADDR10 address_b[10] => ram_block1a6.PORTBADDR10 address_b[10] => ram_block1a7.PORTBADDR10 address_b[11] => ram_block1a0.PORTBADDR11 address_b[11] => ram_block1a1.PORTBADDR11 address_b[11] => ram_block1a2.PORTBADDR11 address_b[11] => ram_block1a3.PORTBADDR11 address_b[11] => ram_block1a4.PORTBADDR11 address_b[11] => ram_block1a5.PORTBADDR11 address_b[11] => ram_block1a6.PORTBADDR11 address_b[11] => ram_block1a7.PORTBADDR11 clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 data_a[0] => ram_block1a0.PORTADATAIN data_a[1] => ram_block1a1.PORTADATAIN data_a[2] => ram_block1a2.PORTADATAIN data_a[3] => ram_block1a3.PORTADATAIN data_a[4] => ram_block1a4.PORTADATAIN data_a[5] => ram_block1a5.PORTADATAIN data_a[6] => ram_block1a6.PORTADATAIN data_a[7] => ram_block1a7.PORTADATAIN q_b[0] <= ram_block1a0.PORTBDATAOUT q_b[1] <= ram_block1a1.PORTBDATAOUT q_b[2] <= ram_block1a2.PORTBDATAOUT q_b[3] <= ram_block1a3.PORTBDATAOUT q_b[4] <= ram_block1a4.PORTBDATAOUT q_b[5] <= ram_block1a5.PORTBDATAOUT q_b[6] <= ram_block1a6.PORTBDATAOUT q_b[7] <= ram_block1a7.PORTBDATAOUT wren_a => ram_block1a0.PORTAWE wren_a => ram_block1a1.PORTAWE wren_a => ram_block1a2.PORTAWE wren_a => ram_block1a3.PORTAWE wren_a => ram_block1a4.PORTAWE wren_a => ram_block1a5.PORTAWE wren_a => ram_block1a6.PORTAWE wren_a => ram_block1a7.PORTAWE |vga_data|Reset_Delay:rst iCLK => pre_cnt[2].CLK iCLK => pre_cnt[1].CLK iCLK => pre_cnt[0].CLK oRESET <= oRESET~reg0.DB_MAX_OUTPUT_PORT_TYPE |vga_data|pll_lcd:vga_pll inclk0 => sub_wire3[0].IN1 c0 <= altpll:altpll_component.clk |vga_data|pll_lcd:vga_pll|altpll:altpll_component inclk[0] => pll.CLK inclk[1] => ~NO_FANOUT~ fbin => ~NO_FANOUT~ pllena => ~NO_FANOUT~ clkswitch => ~NO_FANOUT~ areset => ~NO_FANOUT~ pfdena => ~NO_FANOUT~ clkena[0] => ~NO_FANOUT~ clkena[1] => ~NO_FANOUT~ clkena[2] => ~NO_FANOUT~ clkena[3] => ~NO_FANOUT~ clkena[4] => ~NO_FANOUT~ clkena[5] => ~NO_FANOUT~ extclkena[0] => ~NO_FANOUT~ extclkena[1] => ~NO_FANOUT~ extclkena[2] => ~NO_FANOUT~ extclkena[3] => ~NO_FANOUT~ scanclk => ~NO_FANOUT~ scanclkena => ~NO_FANOUT~ scanaclr => ~NO_FANOUT~ scanread => ~NO_FANOUT~ scanwrite => ~NO_FANOUT~ scandata => ~NO_FANOUT~ phasecounterselect[0] => ~NO_FANOUT~ phasecounterselect[1] => ~NO_FANOUT~ phasecounterselect[2] => ~NO_FANOUT~ phasecounterselect[3] => ~NO_FANOUT~ phaseupdown => ~NO_FANOUT~ phasestep => ~NO_FANOUT~ configupdate => ~NO_FANOUT~ fbmimicbidir <= clk[0] <= clk[0]~1.DB_MAX_OUTPUT_PORT_TYPE clk[1] <= clk[2] <= clk[2]~0.DB_MAX_OUTPUT_PORT_TYPE clk[3] <= clk[4] <= clk[5] <= extclk[0] <= extclk[1] <= extclk[2] <= extclk[3] <= clkbad[0] <= clkbad[1] <= enable1 <= enable0 <= activeclock <= clkloss <= locked <= scandataout <= scandone <= sclkout0 <= sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE phasedone <= vcooverrange <= vcounderrange <= fbout <= |vga_data|clock_module:sys_clocks clk_50mhz => clk_1us~reg0.CLK clk_50mhz => clk_10us~reg0.CLK clk_50mhz => clk_100us~reg0.CLK clk_50mhz => clk_1ms~reg0.CLK clk_50mhz => clk_10ms~reg0.CLK clk_50mhz => clk_100ms~reg0.CLK clk_50mhz => clk_1s~reg0.CLK clk_50mhz => clk_1us_cnt[5].CLK clk_50mhz => clk_1us_cnt[4].CLK clk_50mhz => clk_1us_cnt[3].CLK clk_50mhz => clk_1us_cnt[2].CLK clk_50mhz => clk_1us_cnt[1].CLK clk_50mhz => clk_1us_cnt[0].CLK clk_50mhz => clk_1us_reg.CLK clk_50mhz => clk_10us_cnt[8].CLK clk_50mhz => clk_10us_cnt[7].CLK clk_50mhz => clk_10us_cnt[6].CLK clk_50mhz => clk_10us_cnt[5].CLK clk_50mhz => clk_10us_cnt[4].CLK clk_50mhz => clk_10us_cnt[3].CLK clk_50mhz => clk_10us_cnt[2].CLK clk_50mhz => clk_10us_cnt[1].CLK clk_50mhz => clk_10us_cnt[0].CLK clk_50mhz => clk_10us_reg.CLK clk_50mhz => clk_100us_cnt[12].CLK clk_50mhz => clk_100us_cnt[11].CLK clk_50mhz => clk_100us_cnt[10].CLK clk_50mhz => clk_100us_cnt[9].CLK clk_50mhz => clk_100us_cnt[8].CLK clk_50mhz => clk_100us_cnt[7].CLK clk_50mhz => clk_100us_cnt[6].CLK clk_50mhz => clk_100us_cnt[5].CLK clk_50mhz => clk_100us_cnt[4].CLK clk_50mhz => clk_100us_cnt[3].CLK clk_50mhz => clk_100us_cnt[2].CLK clk_50mhz => clk_100us_cnt[1].CLK clk_50mhz => clk_100us_cnt[0].CLK clk_50mhz => clk_100us_reg.CLK clk_1us <= clk_1us~reg0.DB_MAX_OUTPUT_PORT_TYPE clk_10us <= clk_10us~reg0.DB_MAX_OUTPUT_PORT_TYPE clk_100us <= clk_100us~reg0.DB_MAX_OUTPUT_PORT_TYPE clk_1ms <= clk_1ms~reg0.DB_MAX_OUTPUT_PORT_TYPE clk_10ms <= clk_10ms~reg0.DB_MAX_OUTPUT_PORT_TYPE clk_100ms <= clk_100ms~reg0.DB_MAX_OUTPUT_PORT_TYPE clk_1s <= clk_1s~reg0.DB_MAX_OUTPUT_PORT_TYPE