{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Info: Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 04:57:37 2009 " "Info: Processing started: Sat May 09 04:57:37 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off vga_data -c vga_data " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off vga_data -c vga_data" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "vga_data EP2C20F484C7 " "Info: Selected device EP2C20F484C7 for design \"vga_data\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "pll_lcd:vga_pll\|altpll:altpll_component\|pll Cyclone II PLL " "Info: Implemented PLL \"pll_lcd:vga_pll\|altpll:altpll_component\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 27 50 0 0 " "Info: Implementing clock multiplication of 27, clock division of 50, and phase shift of 0 degrees (0 ps) for pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 port" {  } { { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 592 3 0 } }  } 0 0 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Info: Found following RAM instances in design that are actually implemented ROM function because the write is always disabled" { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a7 " "Info: Atom \"display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a7\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a6 " "Info: Atom \"display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a6\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a5 " "Info: Atom \"display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a5\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a4 " "Info: Atom \"display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a4\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a3 " "Info: Atom \"display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a3\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a2 " "Info: Atom \"display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a2\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a1 " "Info: Atom \"display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a1\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" 0 0 "" 0 -1} { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a0 " "Info: Atom \"display_driver:vga640x480\|font_ram:font5x7\|altsyncram:altsyncram_component\|altsyncram_bld1:auto_generated\|ram_block1a0\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" {  } {  } 0 0 "Atom \"%1!s!\" is instantiated as RAM, but it actually implements ROM function because the write is always disabled" 0 0 "" 0 -1}  } {  } 0 0 "Found following RAM instances in design that are actually implemented ROM function because the write is always disabled" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Info: Device EP2C15AF484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Info: Device EP2C35F484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Info: Device EP2C50F484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Info: Pin ~ASDO~ is reserved at location C4" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Info: Pin ~nCSO~ is reserved at location C3" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Info: Pin ~LVDS91p/nCEO~ is reserved at location W20" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "89 89 " "Warning: No exact pin location assignment(s) for 89 pins of 89 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OSCO " "Info: Pin OSCO not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { OSCO } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 31 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OSCO } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RXD " "Info: Pin RXD not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { RXD } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 32 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { RXD } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RTS " "Info: Pin RTS not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { RTS } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 33 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { RTS } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CTS " "Info: Pin CTS not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CTS } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 34 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CTS } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DSR " "Info: Pin DSR not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { DSR } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 35 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DSR } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DTR " "Info: Pin DTR not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { DTR } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 36 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DTR } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DCD " "Info: Pin DCD not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { DCD } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 37 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DCD } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RI " "Info: Pin RI not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { RI } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 38 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { RI } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DS1 " "Info: Pin DS1 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { DS1 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 39 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DS1 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DS2 " "Info: Pin DS2 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { DS2 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 40 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DS2 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DS3 " "Info: Pin DS3 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { DS3 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 41 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DS3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DS4 " "Info: Pin DS4 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { DS4 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 42 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DS4 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DS5 " "Info: Pin DS5 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { DS5 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 43 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DS5 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DS6 " "Info: Pin DS6 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { DS6 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 44 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DS6 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DS7 " "Info: Pin DS7 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { DS7 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 45 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DS7 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DS8 " "Info: Pin DS8 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { DS8 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 46 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DS8 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PS2_DATA " "Info: Pin PS2_DATA not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { PS2_DATA } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 53 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_DATA } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PS2_CLK " "Info: Pin PS2_CLK not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { PS2_CLK } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 54 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON1 " "Info: Pin CON1 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON1 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 55 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON1 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON2 " "Info: Pin CON2 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON2 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 56 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON2 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON3 " "Info: Pin CON3 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON3 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 57 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON4 " "Info: Pin CON4 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON4 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 58 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON4 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON5 " "Info: Pin CON5 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON5 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 59 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON5 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON6 " "Info: Pin CON6 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON6 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 60 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON6 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON7 " "Info: Pin CON7 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON7 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 61 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON7 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON8 " "Info: Pin CON8 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON8 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 62 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON8 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON9 " "Info: Pin CON9 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON9 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 63 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON9 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON10 " "Info: Pin CON10 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON10 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 64 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON10 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON11 " "Info: Pin CON11 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON11 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 65 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON11 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON12 " "Info: Pin CON12 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON12 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 66 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON12 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON13 " "Info: Pin CON13 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON13 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 67 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON13 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON14 " "Info: Pin CON14 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON14 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 68 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON14 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON15 " "Info: Pin CON15 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON15 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 69 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON15 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON16 " "Info: Pin CON16 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON16 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 70 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON16 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON17 " "Info: Pin CON17 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON17 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 71 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON17 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON18 " "Info: Pin CON18 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON18 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 72 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON18 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON19 " "Info: Pin CON19 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON19 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 73 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON19 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CON20 " "Info: Pin CON20 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON20 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 74 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON20 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DI " "Info: Pin DI not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { DI } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 75 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DI } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DO " "Info: Pin DO not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { DO } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 76 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DO } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "TSOP " "Info: Pin TSOP not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { TSOP } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 77 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TSOP } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "TXD " "Info: Pin TXD not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { TXD } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 78 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TXD } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CS_FLASH " "Info: Pin CS_FLASH not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CS_FLASH } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 79 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CS_FLASH } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD1 " "Info: Pin LD1 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD1 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 80 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD1 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD2 " "Info: Pin LD2 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD2 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 81 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD2 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD3 " "Info: Pin LD3 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD3 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 82 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD4 " "Info: Pin LD4 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD4 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 83 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD4 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD5 " "Info: Pin LD5 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD5 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 84 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD5 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD6 " "Info: Pin LD6 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD6 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 85 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD6 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD7 " "Info: Pin LD7 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD7 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 86 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD7 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD8 " "Info: Pin LD8 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD8 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 87 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD8 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD9 " "Info: Pin LD9 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD9 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 88 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD9 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD10 " "Info: Pin LD10 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD10 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 89 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD10 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD11 " "Info: Pin LD11 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD11 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 90 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD11 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD12 " "Info: Pin LD12 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD12 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 91 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD12 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD13 " "Info: Pin LD13 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD13 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 92 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD13 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD14 " "Info: Pin LD14 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD14 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 93 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD14 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD15 " "Info: Pin LD15 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD15 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 94 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD15 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LD16 " "Info: Pin LD16 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LD16 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 95 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LD16 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SCK " "Info: Pin SCK not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { SCK } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 96 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SCK } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LEDA " "Info: Pin LEDA not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LEDA } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 97 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LEDA } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LEDB " "Info: Pin LEDB not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LEDB } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 98 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LEDB } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SEG_A " "Info: Pin SEG_A not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { SEG_A } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 99 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SEG_A } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SEG_B " "Info: Pin SEG_B not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { SEG_B } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 100 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SEG_B } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SEG_C " "Info: Pin SEG_C not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { SEG_C } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 101 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SEG_C } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SEG_D " "Info: Pin SEG_D not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { SEG_D } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 102 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SEG_D } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LSB_R " "Info: Pin LSB_R not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LSB_R } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 103 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LSB_R } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MSB_R " "Info: Pin MSB_R not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { MSB_R } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 104 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { MSB_R } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LSB_G " "Info: Pin LSB_G not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LSB_G } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 105 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LSB_G } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MSB_G " "Info: Pin MSB_G not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { MSB_G } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 106 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { MSB_G } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LSB_B " "Info: Pin LSB_B not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LSB_B } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 107 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LSB_B } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MSB_B " "Info: Pin MSB_B not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { MSB_B } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 108 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { MSB_B } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A " "Info: Pin A not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { A } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 109 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { A } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B " "Info: Pin B not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { B } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 110 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { B } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C " "Info: Pin C not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { C } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 111 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { C } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D " "Info: Pin D not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { D } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 112 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { D } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "E " "Info: Pin E not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { E } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 113 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { E } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "F " "Info: Pin F not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { F } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 114 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { F } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "G " "Info: Pin G not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { G } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 115 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { G } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DP " "Info: Pin DP not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { DP } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 116 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DP } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "HS " "Info: Pin HS not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { HS } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 117 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { HS } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "VS " "Info: Pin VS not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { VS } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 119 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { VS } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "OSC " "Info: Pin OSC not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { OSC } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 30 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OSC } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MS3 " "Info: Pin MS3 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { MS3 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 49 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { MS3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MS2 " "Info: Pin MS2 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { MS2 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 48 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { MS2 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MS5 " "Info: Pin MS5 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { MS5 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 51 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { MS5 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MS6 " "Info: Pin MS6 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { MS6 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 52 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { MS6 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MS4 " "Info: Pin MS4 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { MS4 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 50 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { MS4 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MS1 " "Info: Pin MS1 not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { MS1 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 47 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { MS1 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "OSC (placed in PIN L1 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node OSC (placed in PIN L1 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock_module:sys_clocks\|clk_1ms " "Info: Destination node clock_module:sys_clocks\|clk_1ms" {  } { { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 7 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock_module:sys_clocks|clk_1ms } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock_module:sys_clocks\|clk_100ms " "Info: Destination node clock_module:sys_clocks\|clk_100ms" {  } { { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 9 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock_module:sys_clocks|clk_100ms } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock_module:sys_clocks\|clk_10us " "Info: Destination node clock_module:sys_clocks\|clk_10us" {  } { { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 5 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock_module:sys_clocks|clk_10us } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock_module:sys_clocks\|clk_1s " "Info: Destination node clock_module:sys_clocks\|clk_1s" {  } { { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 11 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock_module:sys_clocks|clk_1s } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock_module:sys_clocks\|clk_10ms " "Info: Destination node clock_module:sys_clocks\|clk_10ms" {  } { { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 8 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock_module:sys_clocks|clk_10ms } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { OSC } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 30 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OSC } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_1) " "Info: Automatically promoted node pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 592 3 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clock_module:sys_clocks\|clk_10us  " "Info: Automatically promoted node clock_module:sys_clocks\|clk_10us " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 5 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock_module:sys_clocks|clk_10us } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clock_module:sys_clocks\|clk_1ms  " "Info: Automatically promoted node clock_module:sys_clocks\|clk_1ms " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 7 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock_module:sys_clocks|clk_1ms } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clock_module:sys_clocks\|clk_1s  " "Info: Automatically promoted node clock_module:sys_clocks\|clk_1s " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 11 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock_module:sys_clocks|clk_1s } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clock_module:sys_clocks\|clk_100ms  " "Info: Automatically promoted node clock_module:sys_clocks\|clk_100ms " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 9 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock_module:sys_clocks|clk_100ms } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Reset_Delay:rst\|pre_cnt\[2\]  " "Info: Automatically promoted node Reset_Delay:rst\|pre_cnt\[2\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Reset_Delay:rst\|pre_cnt\[2\]~0 " "Info: Destination node Reset_Delay:rst\|pre_cnt\[2\]~0" {  } { { "Reset_Delay.v" "" { Text "E:/vga_data_restored/Reset_Delay.v" 9 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Reset_Delay:rst|pre_cnt[2]~0 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "Reset_Delay.v" "" { Text "E:/vga_data_restored/Reset_Delay.v" 9 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Reset_Delay:rst|pre_cnt[2] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clock_module:sys_clocks\|clk_10ms  " "Info: Automatically promoted node clock_module:sys_clocks\|clk_10ms " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_10ms_reg\[0\] " "Info: Destination node clk_10ms_reg\[0\]" {  } { { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 319 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_10ms_reg[0] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 8 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock_module:sys_clocks|clk_10ms } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "15 EC " "Extra Info: Packed 15 registers into blocks of type EC" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "88 unused 3.3V 27 61 0 " "Info: Number of I/O pins in group: 88 (unused VREF, 3.3V VCCIO, 27 input, 61 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 0 41 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 3 30 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 3 total pin(s) used --  30 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 43 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 40 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 39 " "Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  39 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 35 " "Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  35 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 40 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Info: Fitter preparation operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:04 " "Info: Fitter placement operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_SLACK_TPD_RESULT" "register leddisp_reg\[1\] register led_reg\[1\] -4.84 ns " "Info: Slack time is -4.84 ns between source register \"leddisp_reg\[1\]\" and destination register \"led_reg\[1\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-3.773 ns + Largest register register " "Info: + Largest register to register requirement is -3.773 ns" {  } {  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 destination 2.512 ns   Shortest register " "Info:   Shortest clock path from clock \"pll_lcd:vga_pll\|altpll:altpll_component\|_clk0\" to destination register is 2.512 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll_lcd:vga_pll\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.922 ns) + CELL(0.000 ns) 0.922 ns pll_lcd:vga_pll\|altpll:altpll_component\|_clk0~clkctrl 2 COMB Unassigned 467 " "Info: 2: + IC(0.922 ns) + CELL(0.000 ns) = 0.922 ns; Loc. = Unassigned; Fanout = 467; COMB Node = 'pll_lcd:vga_pll\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.922 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.602 ns) 2.512 ns led_reg\[1\] 3 REG Unassigned 1 " "Info: 3: + IC(0.988 ns) + CELL(0.602 ns) = 2.512 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'led_reg\[1\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.590 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl led_reg[1] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 319 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 23.96 % ) " "Info: Total cell delay = 0.602 ns ( 23.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.910 ns ( 76.04 % ) " "Info: Total interconnect delay = 1.910 ns ( 76.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 destination 2.512 ns   Longest register " "Info:   Longest clock path from clock \"pll_lcd:vga_pll\|altpll:altpll_component\|_clk0\" to destination register is 2.512 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll_lcd:vga_pll\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll_lcd:vga_pll\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.922 ns) + CELL(0.000 ns) 0.922 ns pll_lcd:vga_pll\|altpll:altpll_component\|_clk0~clkctrl 2 COMB Unassigned 467 " "Info: 2: + IC(0.922 ns) + CELL(0.000 ns) = 0.922 ns; Loc. = Unassigned; Fanout = 467; COMB Node = 'pll_lcd:vga_pll\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.922 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0 pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.602 ns) 2.512 ns led_reg\[1\] 3 REG Unassigned 1 " "Info: 3: + IC(0.988 ns) + CELL(0.602 ns) = 2.512 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'led_reg\[1\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.590 ns" { pll_lcd:vga_pll|altpll:altpll_component|_clk0~clkctrl led_reg[1] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 319 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 23.96 % ) " "Info: Total cell delay = 0.602 ns ( 23.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.910 ns ( 76.04 % ) " "Info: Total interconnect delay = 1.910 ns ( 76.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "d:/altera/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC source 6.375 ns   Shortest register " "Info:   Shortest clock path from clock \"OSC\" to source register is 6.375 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.783 ns) 0.783 ns OSC 1 CLK Unassigned 7 " "Info: 1: + IC(0.000 ns) + CELL(0.783 ns) = 0.783 ns; Loc. = Unassigned; Fanout = 7; CLK Node = 'OSC'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OSC } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.944 ns) + CELL(0.879 ns) 3.606 ns clock_module:sys_clocks\|clk_100ms 2 REG Unassigned 1 " "Info: 2: + IC(1.944 ns) + CELL(0.879 ns) = 3.606 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'clock_module:sys_clocks\|clk_100ms'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.823 ns" { OSC clock_module:sys_clocks|clk_100ms } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.179 ns) + CELL(0.000 ns) 4.785 ns clock_module:sys_clocks\|clk_100ms~clkctrl 3 COMB Unassigned 19 " "Info: 3: + IC(1.179 ns) + CELL(0.000 ns) = 4.785 ns; Loc. = Unassigned; Fanout = 19; COMB Node = 'clock_module:sys_clocks\|clk_100ms~clkctrl'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.179 ns" { clock_module:sys_clocks|clk_100ms clock_module:sys_clocks|clk_100ms~clkctrl } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.602 ns) 6.375 ns leddisp_reg\[1\] 4 REG Unassigned 4 " "Info: 4: + IC(0.988 ns) + CELL(0.602 ns) = 6.375 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'leddisp_reg\[1\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.590 ns" { clock_module:sys_clocks|clk_100ms~clkctrl leddisp_reg[1] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 255 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.264 ns ( 35.51 % ) " "Info: Total cell delay = 2.264 ns ( 35.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.111 ns ( 64.49 % ) " "Info: Total interconnect delay = 4.111 ns ( 64.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 30 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC source 6.375 ns   Longest register " "Info:   Longest clock path from clock \"OSC\" to source register is 6.375 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.783 ns) 0.783 ns OSC 1 CLK Unassigned 7 " "Info: 1: + IC(0.000 ns) + CELL(0.783 ns) = 0.783 ns; Loc. = Unassigned; Fanout = 7; CLK Node = 'OSC'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { OSC } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.944 ns) + CELL(0.879 ns) 3.606 ns clock_module:sys_clocks\|clk_100ms 2 REG Unassigned 1 " "Info: 2: + IC(1.944 ns) + CELL(0.879 ns) = 3.606 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'clock_module:sys_clocks\|clk_100ms'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "2.823 ns" { OSC clock_module:sys_clocks|clk_100ms } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.179 ns) + CELL(0.000 ns) 4.785 ns clock_module:sys_clocks\|clk_100ms~clkctrl 3 COMB Unassigned 19 " "Info: 3: + IC(1.179 ns) + CELL(0.000 ns) = 4.785 ns; Loc. = Unassigned; Fanout = 19; COMB Node = 'clock_module:sys_clocks\|clk_100ms~clkctrl'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.179 ns" { clock_module:sys_clocks|clk_100ms clock_module:sys_clocks|clk_100ms~clkctrl } "NODE_NAME" } } { "clock_module.v" "" { Text "E:/vga_data_restored/clock_module.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.602 ns) 6.375 ns leddisp_reg\[1\] 4 REG Unassigned 4 " "Info: 4: + IC(0.988 ns) + CELL(0.602 ns) = 6.375 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'leddisp_reg\[1\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.590 ns" { clock_module:sys_clocks|clk_100ms~clkctrl leddisp_reg[1] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 255 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.264 ns ( 35.51 % ) " "Info: Total cell delay = 2.264 ns ( 35.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.111 ns ( 64.49 % ) " "Info: Total interconnect delay = 4.111 ns ( 64.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 30 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns   " "Info:   Micro clock to output delay of source is 0.277 ns" {  } { { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 255 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns   " "Info:   Micro setup delay of destination is -0.038 ns" {  } { { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 319 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.067 ns - Longest register register " "Info: - Longest register to register delay is 1.067 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns leddisp_reg\[1\] 1 REG Unassigned 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'leddisp_reg\[1\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { leddisp_reg[1] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 255 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.521 ns) 0.971 ns Selector51~0 2 COMB Unassigned 1 " "Info: 2: + IC(0.450 ns) + CELL(0.521 ns) = 0.971 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'Selector51~0'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.971 ns" { leddisp_reg[1] Selector51~0 } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 324 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 1.067 ns led_reg\[1\] 3 REG Unassigned 1 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 1.067 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'led_reg\[1\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.096 ns" { Selector51~0 led_reg[1] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 319 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.617 ns ( 57.83 % ) " "Info: Total cell delay = 0.617 ns ( 57.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.450 ns ( 42.17 % ) " "Info: Total interconnect delay = 0.450 ns ( 42.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.067 ns" { leddisp_reg[1] Selector51~0 led_reg[1] } "NODE_NAME" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.067 ns" { leddisp_reg[1] Selector51~0 led_reg[1] } "NODE_NAME" } }  } 0 0 "Slack time is %5!s! between source %1!s! \"%2!s!\" and destination %3!s! \"%4!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.067 ns register register " "Info: Estimated most critical path is register to register delay of 1.067 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns leddisp_reg\[1\] 1 REG LAB_X19_Y14 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y14; Fanout = 4; REG Node = 'leddisp_reg\[1\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { leddisp_reg[1] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 255 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.521 ns) 0.971 ns Selector51~0 2 COMB LAB_X20_Y14 1 " "Info: 2: + IC(0.450 ns) + CELL(0.521 ns) = 0.971 ns; Loc. = LAB_X20_Y14; Fanout = 1; COMB Node = 'Selector51~0'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.971 ns" { leddisp_reg[1] Selector51~0 } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 324 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 1.067 ns led_reg\[1\] 3 REG LAB_X20_Y14 1 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 1.067 ns; Loc. = LAB_X20_Y14; Fanout = 1; REG Node = 'led_reg\[1\]'" {  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "0.096 ns" { Selector51~0 led_reg[1] } "NODE_NAME" } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 319 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.617 ns ( 57.83 % ) " "Info: Total cell delay = 0.617 ns ( 57.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.450 ns ( 42.17 % ) " "Info: Total interconnect delay = 0.450 ns ( 42.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "1.067 ns" { leddisp_reg[1] Selector51~0 led_reg[1] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X25_Y14 X37_Y27 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X25_Y14 to location X37_Y27" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "61 " "Warning: Found 61 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON1 0 " "Info: Pin \"CON1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON2 0 " "Info: Pin \"CON2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON3 0 " "Info: Pin \"CON3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON4 0 " "Info: Pin \"CON4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON5 0 " "Info: Pin \"CON5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON6 0 " "Info: Pin \"CON6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON7 0 " "Info: Pin \"CON7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON8 0 " "Info: Pin \"CON8\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON9 0 " "Info: Pin \"CON9\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON10 0 " "Info: Pin \"CON10\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON11 0 " "Info: Pin \"CON11\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON12 0 " "Info: Pin \"CON12\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON13 0 " "Info: Pin \"CON13\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON14 0 " "Info: Pin \"CON14\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON15 0 " "Info: Pin \"CON15\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON16 0 " "Info: Pin \"CON16\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON17 0 " "Info: Pin \"CON17\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON18 0 " "Info: Pin \"CON18\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON19 0 " "Info: Pin \"CON19\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CON20 0 " "Info: Pin \"CON20\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TXD 0 " "Info: Pin \"TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CS_FLASH 0 " "Info: Pin \"CS_FLASH\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD1 0 " "Info: Pin \"LD1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD2 0 " "Info: Pin \"LD2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD3 0 " "Info: Pin \"LD3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD4 0 " "Info: Pin \"LD4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD5 0 " "Info: Pin \"LD5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD6 0 " "Info: Pin \"LD6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD7 0 " "Info: Pin \"LD7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD8 0 " "Info: Pin \"LD8\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD9 0 " "Info: Pin \"LD9\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD10 0 " "Info: Pin \"LD10\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD11 0 " "Info: Pin \"LD11\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD12 0 " "Info: Pin \"LD12\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD13 0 " "Info: Pin \"LD13\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD14 0 " "Info: Pin \"LD14\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD15 0 " "Info: Pin \"LD15\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LD16 0 " "Info: Pin \"LD16\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SCK 0 " "Info: Pin \"SCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDA 0 " "Info: Pin \"LEDA\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDB 0 " "Info: Pin \"LEDB\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SEG_A 0 " "Info: Pin \"SEG_A\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SEG_B 0 " "Info: Pin \"SEG_B\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SEG_C 0 " "Info: Pin \"SEG_C\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SEG_D 0 " "Info: Pin \"SEG_D\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LSB_R 0 " "Info: Pin \"LSB_R\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MSB_R 0 " "Info: Pin \"MSB_R\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LSB_G 0 " "Info: Pin \"LSB_G\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MSB_G 0 " "Info: Pin \"MSB_G\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LSB_B 0 " "Info: Pin \"LSB_B\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "MSB_B 0 " "Info: Pin \"MSB_B\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "A 0 " "Info: Pin \"A\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "B 0 " "Info: Pin \"B\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "C 0 " "Info: Pin \"C\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "D 0 " "Info: Pin \"D\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "E 0 " "Info: Pin \"E\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "F 0 " "Info: Pin \"F\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "G 0 " "Info: Pin \"G\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DP 0 " "Info: Pin \"DP\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HS 0 " "Info: Pin \"HS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VS 0 " "Info: Pin \"VS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "27 " "Warning: Following 27 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON1 GND " "Info: Pin CON1 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON1 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 55 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON1 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON2 GND " "Info: Pin CON2 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON2 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 56 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON2 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON3 GND " "Info: Pin CON3 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON3 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 57 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON4 GND " "Info: Pin CON4 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON4 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 58 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON4 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON5 GND " "Info: Pin CON5 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON5 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 59 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON5 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON6 GND " "Info: Pin CON6 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON6 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 60 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON6 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON7 GND " "Info: Pin CON7 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON7 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 61 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON7 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON8 GND " "Info: Pin CON8 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON8 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 62 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON8 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON9 GND " "Info: Pin CON9 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON9 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 63 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON9 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON10 GND " "Info: Pin CON10 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON10 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 64 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON10 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON11 GND " "Info: Pin CON11 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON11 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 65 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON11 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON12 GND " "Info: Pin CON12 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON12 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 66 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON12 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON13 GND " "Info: Pin CON13 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON13 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 67 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON13 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON14 GND " "Info: Pin CON14 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON14 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 68 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON14 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON15 GND " "Info: Pin CON15 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON15 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 69 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON15 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON16 GND " "Info: Pin CON16 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON16 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 70 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON16 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON17 GND " "Info: Pin CON17 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON17 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 71 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON17 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON18 GND " "Info: Pin CON18 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON18 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 72 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON18 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON19 GND " "Info: Pin CON19 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON19 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 73 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON19 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CON20 GND " "Info: Pin CON20 has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CON20 } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 74 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CON20 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TXD VCC " "Info: Pin TXD has VCC driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { TXD } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 78 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TXD } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CS_FLASH VCC " "Info: Pin CS_FLASH has VCC driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { CS_FLASH } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 79 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CS_FLASH } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SCK GND " "Info: Pin SCK has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { SCK } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 96 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SCK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDA VCC " "Info: Pin LEDA has VCC driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LEDA } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 97 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LEDA } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDB VCC " "Info: Pin LEDB has VCC driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { LEDB } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 98 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LEDB } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "MSB_B GND " "Info: Pin MSB_B has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { MSB_B } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 108 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { MSB_B } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DP GND " "Info: Pin DP has GND driving its datain port" {  } { { "d:/altera/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin64/pin_planner.ppl" { DP } } } { "vga_data.v" "" { Text "E:/vga_data_restored/vga_data.v" 116 -1 0 } } { "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DP } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/vga_data_restored/vga_data.fit.smsg " "Info: Generated suppressed messages file E:/vga_data_restored/vga_data.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 64-Bit " "Info: Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "305 " "Info: Peak virtual memory: 305 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 04:58:00 2009 " "Info: Processing ended: Sat May 09 04:58:00 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:23 " "Info: Elapsed time: 00:00:23" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Info: Total CPU time (on all processors): 00:00:11" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}