module clock_module
	(
input			clk_50mhz,
output	reg		clk_1us,
output	reg		clk_10us,
output	reg		clk_100us,
output	reg		clk_1ms,
output	reg		clk_10ms,
output	reg		clk_100ms,
output	reg		clk_1s
	);

reg	[5:0]	clk_1us_cnt;
reg	[8:0]	clk_10us_cnt;
reg	[12:0]	clk_100us_cnt;
reg	[6:0]	clk_1ms_cnt;
reg	[9:0]	clk_10ms_cnt;
reg	[13:0]	clk_100ms_cnt;
reg	[6:0]	clk_1s_cnt;
reg			clk_1us_reg;
reg			clk_10us_reg;
reg			clk_100us_reg;
reg			clk_1ms_reg;
reg			clk_10ms_reg;
reg			clk_100ms_reg;
reg			clk_1s_reg;

// sync_clock.
always @ (posedge clk_50mhz)
begin
	clk_1us 	<= clk_1us_reg;
	clk_10us 	<= clk_10us_reg;
	clk_100us 	<= clk_100us_reg;
	clk_1ms 	<= clk_1ms_reg;
	clk_10ms 	<= clk_10ms_reg;
	clk_100ms 	<= clk_100ms_reg;
	clk_1s 		<= clk_1s_reg;
end

// clock 1us.
always @ (posedge clk_50mhz)
begin
	if (clk_1us_cnt == 49) clk_1us_cnt <= 0;
	else
	begin
		clk_1us_cnt <= clk_1us_cnt + 1;
		if (clk_1us_cnt == 0) 	clk_1us_reg <= 1;
		if (clk_1us_cnt == 24) 	clk_1us_reg <= 0;
	end
end

// clock 10us.
always @ (posedge clk_50mhz)
begin
	if (clk_10us_cnt == 499) clk_10us_cnt <= 0;
	else
	begin
		clk_10us_cnt <= clk_10us_cnt + 1;
		if (clk_10us_cnt == 0) 	clk_10us_reg <= 1;
		if (clk_10us_cnt == 249) 	clk_10us_reg <= 0;
	end
end

// clock 100us.
always @ (posedge clk_50mhz)
begin
	if (clk_100us_cnt == 4999) clk_100us_cnt <= 0;
	else
	begin
		clk_100us_cnt <= clk_100us_cnt + 1;
		if (clk_100us_cnt == 0) 	clk_100us_reg <= 1;
		if (clk_100us_cnt == 2499) 	clk_100us_reg <= 0;
	end
end

// clock 1ms.
always @ (posedge clk_10us)
begin
	if (clk_1ms_cnt == 99) clk_1ms_cnt <= 0;
	else
	begin
		clk_1ms_cnt <= clk_1ms_cnt + 1;
		if (clk_1ms_cnt == 0) 	clk_1ms_reg <= 1;
		if (clk_1ms_cnt == 50) 	clk_1ms_reg <= 0;
	end
end

// clock 10ms.
always @ (posedge clk_10us)
begin
	if (clk_10ms_cnt == 999) clk_10ms_cnt <= 0;
	else
	begin
		clk_10ms_cnt <= clk_10ms_cnt + 1;
		if (clk_10ms_cnt == 0)	 clk_10ms_reg <= 1;
		if (clk_10ms_cnt == 500) clk_10ms_reg <= 0;
	end
end

// clock 100ms.
always @ (posedge clk_10us)
begin
	if (clk_100ms_cnt == 9999) clk_100ms_cnt <= 0;
	else
	begin
		clk_100ms_cnt <= clk_100ms_cnt + 1;
		if (clk_100ms_cnt == 0) 	clk_100ms_reg <= 1;
		if (clk_100ms_cnt == 5000) 	clk_100ms_reg <= 0;
	end
end

// clock 1s.
always @ (posedge clk_10ms)
begin
	if (clk_1s_cnt == 99) clk_1s_cnt <= 0;
	else
	begin
		clk_1s_cnt <= clk_1s_cnt + 1;
		if (clk_1s_cnt == 0) 	clk_1s_reg <= 0;
		if (clk_1s_cnt == 50) 	clk_1s_reg <= 1;
	end
end
endmodule