module	Reset_Delay(
	input		iCLK,
	output reg	oRESET
	);

reg	[11:0]	Cont;
reg	[2:0]	pre_cnt;

always@(posedge iCLK)
begin
		pre_cnt	<=	pre_cnt+1;
end

always@(posedge pre_cnt[2])
begin
	if(Cont!=12'hFFF)
	begin
		Cont	<=	Cont+1;
		oRESET	<=	1'b0;
	end
	else
	oRESET	<=	1'b1;
end
endmodule