// fotoopa 12 nov 2007
// VGA monitor 16 regels van 38 characters
// functie's:
// KEY[0] wissen scherm, maar teksten blijven gewist!
// SW[0] instellen tientallen seconden
// SW[1] instellen eenheden   minuten
// SW[2] instellen tientallen minuten
// SW[3] instellen eenheden   uren
// SW[4] instellen tientallen uren

module DE1_vga_640
	(
		CLOCK_24,						//	24 MHz
		CLOCK_27,						//	27 MHz
		CLOCK_50,						//	50 MHz
		EXT_CLOCK,						//	External Clock
		KEY,							//	Pushbutton[3:0]
		SW,								//	Toggle Switch[9:0]
		HEX0,							//	Seven Segment Digit 0
		HEX1,							//	Seven Segment Digit 1
		HEX2,							//	Seven Segment Digit 2
		HEX3,							//	Seven Segment Digit 3
		LEDG,							//	LED Green[7:0]
		LEDR,							//	LED Red[9:0]
		UART_TXD,						//	UART Transmitter
		UART_RXD,						//	UART Receiver
		DRAM_DQ,						//	SDRAM Data bus 16 Bits
		DRAM_ADDR,						//	SDRAM Address bus 12 Bits
		DRAM_LDQM,						//	SDRAM Low-byte Data Mask 
		DRAM_UDQM,						//	SDRAM High-byte Data Mask
		DRAM_WE_N,						//	SDRAM Write Enable
		DRAM_CAS_N,						//	SDRAM Column Address Strobe
		DRAM_RAS_N,						//	SDRAM Row Address Strobe
		DRAM_CS_N,						//	SDRAM Chip Select
		DRAM_BA_0,						//	SDRAM Bank Address 0
		DRAM_BA_1,						//	SDRAM Bank Address 0
		DRAM_CLK,						//	SDRAM Clock
		DRAM_CKE,						//	SDRAM Clock Enable
		FL_DQ,							//	FLASH Data bus 8 Bits
		FL_ADDR,						//	FLASH Address bus 22 Bits
		FL_WE_N,						//	FLASH Write Enable
		FL_RST_N,						//	FLASH Reset
		FL_OE_N,						//	FLASH Output Enable
		FL_CE_N,						//	FLASH Chip Enable
		SRAM_DQ,						//	SRAM Data bus 16 Bits
		SRAM_ADDR,						//	SRAM Address bus 18 Bits
		SRAM_UB_N,						//	SRAM High-byte Data Mask 
		SRAM_LB_N,						//	SRAM Low-byte Data Mask 
		SRAM_WE_N,						//	SRAM Write Enable
		SRAM_CE_N,						//	SRAM Chip Enable
		SRAM_OE_N,						//	SRAM Output Enable
		SD_DAT,							//	SD Card Data
		SD_DAT3,						//	SD Card Data 3
		SD_CMD,							//	SD Card Command Signal
		SD_CLK,							//	SD Card Clock
		TDI,  							// CPLD -> FPGA (data in)
		TCK,  							// CPLD -> FPGA (clk)
		TCS,  							// CPLD -> FPGA (CS)
	    TDO,  							// FPGA -> CPLD (data out)
		I2C_SDAT,						//	I2C Data
		I2C_SCLK,						//	I2C Clock
		PS2_DAT,						//	PS2 Data
		PS2_CLK,						//	PS2 Clock
		VGA_HS,							//	VGA H_SYNC
		VGA_VS,							//	VGA V_SYNC
		VGA_R,   						//	VGA Red[3:0]
		VGA_G,	 						//	VGA Green[3:0]
		VGA_B,  						//	VGA Blue[3:0]
		AUD_ADCLRCK,					//	Audio CODEC ADC LR Clock
		AUD_ADCDAT,						//	Audio CODEC ADC Data
		AUD_DACLRCK,					//	Audio CODEC DAC LR Clock
		AUD_DACDAT,						//	Audio CODEC DAC Data
		AUD_BCLK,						//	Audio CODEC Bit-Stream Clock
		AUD_XCK,						//	Audio CODEC Chip Clock
		Pa0,						//	GPIO Connection 0
		Pa1,
		Pa2,
		Pa3,
		Pa4,
		Pa5,
		Pa6,
		Pa7,
		Pa8,
		Pa9,
		Pa10,
		Pa11,
		Pa12,
		Pa13,
		Pa14,
		Pa15,
		Pa16,
		Pa17,
		Pa18,
		Pa19,
		Pa20,
		Pa21,
		Pa22,
		Pa23,
		Pa24,
		Pa25,
		Pa26,
		Pa27,
		Pa28,
		Pa29,
		Pa30,
		Pa31,
		Pa32,
		Pa33,
		Pa34,
		Pa35,

		Pb0,
		Pb1,
		Pb2,
		Pb3,
		Pb4,
		Pb5,
		Pb6,
		Pb7,
		Pb8,
		Pb9,
		Pb10,
		Pb11,
		Pb12,
		Pb13,
		Pb14,
		Pb15,
		Pb16,
		Pb17,
		Pb18,
		Pb19,
		Pb20,
		Pb21,
		Pb22,
		Pb23,
		Pb24,
		Pb25,
		Pb26,
		Pb27,
		Pb28,
		Pb29,
		Pb30,
		Pb31,
		Pb32,
		Pb33,
		Pb34,
		Pb35
		
	);
	
input		Pa0;
input		Pa1;
input		Pa2;
input		Pa3;
input		Pa4;
input		Pa5;
input		Pa6;
input		Pa7;
input		Pa8;
input		Pa9;
inout		Pa10;
input		Pa11;
inout		Pa12;
input		Pa13;
inout		Pa14;
input		Pa15;
inout		Pa16;
input		Pa17;
inout		Pa18;
input		Pa19;
inout		Pa20;
input		Pa21;
inout		Pa22;
input		Pa23;
inout		Pa24;
input		Pa25;
input		Pa26;
input		Pa27;
input		Pa28;
input		Pa29;
input		Pa30;
input		Pa31;
input		Pa32;
input		Pa33;
input		Pa34;
input		Pa35;

input		Pb0;
input		Pb1;
input		Pb2;
input		Pb3;
input		Pb4;
input		Pb5;
input		Pb6;
input		Pb7;
input		Pb8;
input		Pb9;
input		Pb10;
input		Pb11;
input		Pb12;
input		Pb13;
input		Pb14;
input		Pb15;
input		Pb16;
input		Pb17;
input		Pb18;
input		Pb19;
input		Pb20;
input		Pb21;
input		Pb22;
input		Pb23;
input		Pb24;
input		Pb25;
input		Pb26;
input		Pb27;
input		Pb28;
input		Pb29;
input		Pb30;
input		Pb31;
input		Pb32;
input		Pb33;
input		Pb34;
input		Pb35;

input	[1:0]	CLOCK_24;				//	24 MHz
input	[1:0]	CLOCK_27;				//	27 MHz
input			CLOCK_50;				//	50 MHz
input			EXT_CLOCK;				//	External Clock
input	[3:0]	KEY;					//	Pushbutton[3:0]
input	[9:0]	SW;						//	Toggle Switch[9:0]
output	[6:0]	HEX0;					//	Seven Segment Digit 0
output	[6:0]	HEX1;					//	Seven Segment Digit 1
output	[6:0]	HEX2;					//	Seven Segment Digit 2
output	[6:0]	HEX3;					//	Seven Segment Digit 3
output	[7:0]	LEDG;					//	LED Green[7:0]
output	[9:0]	LEDR;					//	LED Red[9:0]
output			UART_TXD;				//	UART Transmitter
input			UART_RXD;				//	UART Receiver
inout	[15:0]	DRAM_DQ;				//	SDRAM Data bus 16 Bits
output	[11:0]	DRAM_ADDR;				//	SDRAM Address bus 12 Bits
output			DRAM_LDQM;				//	SDRAM Low-byte Data Mask 
output			DRAM_UDQM;				//	SDRAM High-byte Data Mask
output			DRAM_WE_N;				//	SDRAM Write Enable
output			DRAM_CAS_N;				//	SDRAM Column Address Strobe
output			DRAM_RAS_N;				//	SDRAM Row Address Strobe
output			DRAM_CS_N;				//	SDRAM Chip Select
output			DRAM_BA_0;				//	SDRAM Bank Address 0
output			DRAM_BA_1;				//	SDRAM Bank Address 0
output			DRAM_CLK;				//	SDRAM Clock
output			DRAM_CKE;				//	SDRAM Clock Enable
inout	[7:0]	FL_DQ;					//	FLASH Data bus 8 Bits
output	[21:0]	FL_ADDR;				//	FLASH Address bus 22 Bits
output			FL_WE_N;				//	FLASH Write Enable
output			FL_RST_N;				//	FLASH Reset
output			FL_OE_N;				//	FLASH Output Enable
output			FL_CE_N;				//	FLASH Chip Enable
inout	[15:0]	SRAM_DQ;				//	SRAM Data bus 16 Bits
output	[17:0]	SRAM_ADDR;				//	SRAM Address bus 18 Bits
output			SRAM_UB_N;				//	SRAM High-byte Data Mask 
output			SRAM_LB_N;				//	SRAM Low-byte Data Mask 
output			SRAM_WE_N;				//	SRAM Write Enable
output			SRAM_CE_N;				//	SRAM Chip Enable
output			SRAM_OE_N;				//	SRAM Output Enable
inout			SD_DAT;					//	SD Card Data
inout			SD_DAT3;				//	SD Card Data 3
inout			SD_CMD;					//	SD Card Command Signal
output			SD_CLK;					//	SD Card Clock
inout			I2C_SDAT;				//	I2C Data
output			I2C_SCLK;				//	I2C Clock
input		 	PS2_DAT;				//	PS2 Data
input			PS2_CLK;				//	PS2 Clock
input  			TDI;					// CPLD -> FPGA (data in)
input  			TCK;					// CPLD -> FPGA (clk)
input  			TCS;					// CPLD -> FPGA (CS)
output 			TDO;					// FPGA -> CPLD (data out)
output			VGA_HS;					//	VGA H_SYNC
output			VGA_VS;					//	VGA V_SYNC
output	[3:0]	VGA_R;   				//	VGA Red[3:0]
output	[3:0]	VGA_G;	 				//	VGA Green[3:0]
output	[3:0]	VGA_B;   				//	VGA Blue[3:0]
inout			AUD_ADCLRCK;			//	Audio CODEC ADC LR Clock
input			AUD_ADCDAT;				//	Audio CODEC ADC Data
inout			AUD_DACLRCK;			//	Audio CODEC DAC LR Clock
output			AUD_DACDAT;				//	Audio CODEC DAC Data
inout			AUD_BCLK;				//	Audio CODEC Bit-Stream Clock
output			AUD_XCK;				//	Audio CODEC Chip Clock

assign	HEX0		=	7'h00;
assign	HEX1		=	7'h00;
assign	HEX2		=	7'h00;
assign	HEX3		=	7'h00;

assign	DRAM_DQ		=	16'hzzzz;
assign	FL_DQ		=	8'hzz;
assign	SRAM_DQ		=	16'hzzzz;
assign	SD_DAT		=	1'bz;
assign	I2C_SDAT	=	1'bz;
assign	AUD_ADCLRCK	=	1'bz;
assign	AUD_DACLRCK	=	1'bz;
assign	AUD_BCLK	=	1'bz;

assign	LEDG[0]		= leddisp_reg[0];
assign	LEDG[1]		= leddisp_reg[1];
assign	LEDG[2]		= leddisp_reg[2];
assign	LEDG[3]		= leddisp_reg[3];
assign	LEDG[4]		= leddisp_reg[4];
assign	LEDG[5]		= leddisp_reg[5];
assign	LEDG[6]		= leddisp_reg[6];
assign	LEDG[7]		= leddisp_reg[7];
                           
assign	LEDR[0]		= leddisp_reg[8];
assign	LEDR[1]		= leddisp_reg[9];
assign	LEDR[2]		= leddisp_reg[10];
assign	LEDR[3]		= leddisp_reg[11];
assign	LEDR[4]		= leddisp_reg[12];
assign	LEDR[5]		= leddisp_reg[13];
assign	LEDR[6]		= leddisp_reg[14];
assign	LEDR[7]		= leddisp_reg[15];
assign	LEDR[8]		= 1'b0;
assign	LEDR[9]		= 1'b0;

assign 	VGA_HS		= h_sync;
assign 	VGA_VS		= v_sync;
assign  VGA_R		= R_out;
assign  VGA_G		= G_out;
assign  VGA_B		= B_out;


reg		[6:0]		hex;
reg		[7:0]		ascii;
reg		[7:0]		ascii_reg;
reg		[1:0]		state;
reg		[3:0]		ram_state;
reg		[1:0]		wr_state;
reg					wr_state_ena;
reg					ram_state_ena;
reg		[1:0]		clk_10ms_reg;
reg					flank_10ms_reg;
reg		[11:0]		ram_adr;
reg	 				ram_wr;
reg		[7:0]		ram_data;
reg	 				ascii_ena;
reg		[3:0]		digita;			// sec aanduiding op VGA monitor
reg		[3:0]		digitb;			// sec aanduiding op VGA monitor
reg		[3:0]		digitc;			// min aanduiding op VGA monitor
reg		[3:0]		digitd;			// min aanduiding op VGA monitor
reg		[3:0]		digite;			// uur aanduiding op VGA monitor
reg		[3:0]		digitf;			// uur aanduiding op VGA monitor
reg		[3:0]		blink_cnt;		// dubbelpunt blinking op VGA monitor
reg		[3:0]		bin_in;
reg		[3:0]		bin_lcd;
reg		[15:0]		led_reg;
reg		[15:0]		leddisp_reg;

// wire connectie's tussen de modules
wire	[3:0]		R_out;			// rood
wire	[3:0]		G_out;			// groen
wire	[3:0]		B_out;			// blauw
wire	 			v_sync;			// horizontale sync
wire	 			h_sync;			// vertikale sync
wire	 			disp;			// display enable LCD 4.3"
wire				clk_vga;		// clock  LCD 4.3"
wire	 			resetn;			// algemene powerup reset, actief laag.

parameter	LED_ZONE1_BEG		= 12'h406;
parameter	LED_ZONE2_BEG		= 12'h415;
parameter	LED_ZONE1_END		= LED_ZONE1_BEG+(8*LED_REGEL_OFFSET);
parameter	LED_ZONE2_END		= LED_ZONE2_BEG+(8*LED_REGEL_OFFSET);
parameter	LED_REGEL_OFFSET	= 12'h080;
parameter	RAM_MAX				= 12'hfff;
display_driver vga640x480
	(
	.clk_vga	(clk_vga),
	.resetn		(resetn),
	.dpram_wr	(ram_wr),	
	.dpram_data	(ram_data),	
	.dpram_adr	(ram_adr),	
	.h_sync		(h_sync),	
	.v_sync		(v_sync),
	.disp		(disp),
	.R_color	(R_out),
	.G_color	(G_out),
	.B_color	(B_out)
	);

Reset_Delay rst(
	.iCLK	(clk_vga),
	.oRESET	(resetn)		// algemene reset
	);

pll_lcd vga_pll(
	.inclk0(CLOCK_50),
	.c0(clk_vga)			// vga clk
);

clock_module sys_clocks
	(
	.clk_50mhz	(CLOCK_50),
	.clk_1us	(clk_1us),
	.clk_10us	(clk_10us),
	.clk_100us	(clk_100us),
	.clk_1ms	(clk_1ms),
	.clk_10ms	(clk_10ms),
	.clk_100ms	(clk_100ms),
	.clk_1s		(clk_1s)
	);
always @(posedge clk_100ms)
leddisp_reg <= leddisp_reg+1;

// seconden teller tot 5 digits (tot 99.999) als bcd waarde.
always @(posedge clk_1s)
begin 
if (SW[0]) if(digitb != 5) digitb <= digitb + 1; else digitb <= 0;
if (SW[1]) if(digitc != 9) digitc <= digitc + 1; else digitc <= 0;
if (SW[2]) if(digitd != 5) digitd <= digitd + 1; else digitd <= 0;
if (SW[3]) if(digite == 9) digite <= 0; 
	else 
		if((digite == 3)&(digitf == 2)) digite <= 0;
			else
			digite <= digite+1;
if (SW[4]) if(digitf == 2) digitf <= 0;
	else if((digitf == 1) & (digite >= 3))
			begin 
				digitf <= 2;
				digite <= 0;
			end else digitf <= digitf+1;
if (!SW[0] & !SW[1] & !SW[2] & !SW[3] & !SW[4])
begin
	if(digita != 9) digita <= digita + 1;
	else  
	begin 
		digita <= 0;
		if(digitb != 5) digitb <= digitb + 1; 
		else  
		begin 
			digitb <= 0;
			if(digitc != 9) digitc <= digitc + 1;
			else 
			begin
				digitc <= 0; 
				if(digitd != 5) digitd <= digitd + 1; 
				else  
				begin 
					digitd <= 0;
					if(digite != 9) digite <= digite + 1;
					if(digite == 9) 
						begin
							digite <= 0;
							digitf <= digitf + 1;
						end
					if((digitf == 2) & (digite == 3))
						begin
							digite <= 0; 
							digitf <= 0; 
						end
				end
			end
		end
	end
end
end

always @ (posedge clk_100ms)
begin
	if (blink_cnt == 9)	
		blink_cnt <= 0;
	else
		blink_cnt <= blink_cnt+1;
end

always @ (posedge clk_vga)
begin
	clk_10ms_reg[1:0]	<= {clk_10ms_reg[0],clk_10ms};			// ander clock domain, hersync!
	flank_10ms_reg 		<= !clk_10ms_reg[1] & clk_10ms_reg[0];
	
	case (ram_state)
	0: 	begin
			if (flank_10ms_reg) // 100 x per seconde refresch schermdata
				begin
					wr_state_ena	<= 1;
					ram_adr			<= 15;
					bin_lcd 		<= digita[3:0];
					ram_state_ena 	<= 0;
					ram_state		<= 1;
				end
		end
	1: 	begin
			if (ram_state_ena) 
				begin
					wr_state_ena	<= 1;
					ram_adr			<= 14;
					bin_lcd 		<= digitb[3:0];
					ram_state_ena 	<= 0;
					ram_state 		<= 2;
				end
		end
	2: 	begin
			if (ram_state_ena) 
				begin
					wr_state_ena	<= 1;
					ram_adr			<= 12;
					bin_lcd 		<= digitc[3:0];
					ram_state_ena 	<= 0;
					ram_state 		<= 3;
				end
		end
	3: 	begin
			if (ram_state_ena) 
				begin
					wr_state_ena	<= 1;
					ram_adr		 	<= 11;
					bin_lcd 		<= digitd[3:0];
					ram_state		<= 4;
					ram_state_ena 	<= 0;
				end
		end
	4: 	begin
			if (ram_state_ena) 
				begin
					wr_state_ena	<= 1;
					ram_adr			<= 9;
					bin_lcd 		<= digite[3:0];
					ram_state_ena 	<= 0;
					ram_state 		<= 5;
				end
		end
	5: 	begin
			if (ram_state_ena) 
				begin
					wr_state_ena	<= 1;
					ram_adr		 	<= 8;
					bin_lcd 		<= digitf[3:0];
					ram_state		<= 6;
					ram_state_ena 	<= 0;
				end
		end
	6: 	begin
			if (ram_state_ena) 
				begin
					ascii_ena		<= 1;
					ram_adr		 	<= 10;
						if (blink_cnt[3])
							ascii_reg 	<= 8'h3a;
						else 
							ascii_reg 	<= 8'h20;
					ram_state		<= 7;
					ram_state_ena 	<= 0;
				end
		end

	7: 	begin
			if (ram_state_ena)
				begin
					if  (!KEY[0])
						begin
							ascii_ena		<= 1;
							ram_adr		 	<= 16;
							ascii_reg 		<= 8'h20;
							ram_state		<= 8;
							ram_state_ena 	<= 0;
						end 
					else
						begin
							ram_state		<= 9;
						end
				end
		end
	8: 	begin
			if (ram_state_ena)
			begin
				if (ram_adr <= RAM_MAX-1) 
					begin
						ascii_ena		<= 1;
						ram_adr		 	<= ram_adr+1;
						ascii_reg 		<= 8'h20;
						ram_state_ena 	<= 0;
					end
				else
					begin
						ram_state		<= 0;
						ram_state_ena 	<= 0;
					end
			end 
		end

	9: 	begin
			led_reg[15:0]	<= leddisp_reg;
			ram_adr		 	<= LED_ZONE1_BEG-LED_REGEL_OFFSET;
			ram_state		<= 10;
		end

	10:	begin
			if (ram_state_ena)
			begin
				ram_state_ena 	<= 0;
				if (led_reg[0])
					ascii_reg 		<= 8'h01;
				else
					ascii_reg 		<= 8'h20;
				ascii_ena			<= 1;
				led_reg[14:0]		<= {led_reg[15:1]};
				if (ram_adr == LED_ZONE1_END - LED_REGEL_OFFSET) 
					begin 
						ram_adr <= LED_ZONE2_BEG;
					end 
				else
					if (ram_adr == LED_ZONE2_END) 
						ram_state <= 0;
					else ram_adr <= ram_adr + LED_REGEL_OFFSET;
			end
		end

	endcase

	case (wr_state)

	0: 	begin
		if (wr_state_ena)
			begin
				wr_state 		<= 1;
				wr_state_ena 	<= 0;
			end
		if (ascii_ena)
			begin
				wr_state 	<= 2;
				ascii_ena 	<= 0;
				ram_data	<= ascii_reg;
			end
		end
	1: 	begin
			wr_state 		<= 2;
			ram_data		<= ascii;
		end
	2: 	begin 
			wr_state 		<= 3;
			ram_wr			<= 1;
		end
	3: 	begin
			ram_wr			<= 0;
			wr_state 		<= 0;
			ram_state_ena 	<= 1;
		end
	endcase
end

always @ (posedge clk_vga)	// bin to ascii
begin
		case(bin_lcd)
		4'h1: ascii = 8'h31;
		4'h2: ascii = 8'h32;
		4'h3: ascii = 8'h33;
		4'h4: ascii = 8'h34;
		4'h5: ascii = 8'h35;
		4'h6: ascii = 8'h36;
		4'h7: ascii = 8'h37;
		4'h8: ascii = 8'h38;
		4'h9: ascii = 8'h39;
		4'ha: ascii = 8'h41;
		4'hb: ascii = 8'h42;
		4'hc: ascii = 8'h43;
		4'hd: ascii = 8'h44;
		4'he: ascii = 8'h45;
		4'hf: ascii = 8'h46;
		4'h0: ascii = 8'h30;
		endcase
end

endmodule