Analysis & Synthesis report for DE1_synthesizer Thu Aug 30 15:51:56 2007 Quartus II Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Analysis & Synthesis Source Files Read 5. Analysis & Synthesis Resource Usage Summary 6. Analysis & Synthesis Resource Utilization by Entity 7. Analysis & Synthesis RAM Summary 8. State Machine - |DE1_synthesizer|I2C_AV_Config:u7|mSetup_ST 9. Registers Removed During Synthesis 10. Removed Registers Triggering Further Register Optimizations 11. General Register Statistics 12. Inverted Register Statistics 13. Multiplexer Restructuring Statistics (Restructuring Performed) 14. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body 15. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1|lpm_counter:post_trigger_counter 16. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter 17. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter 18. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9ui2:auto_generated 19. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9ui2:auto_generated|altsyncram_k4l1:altsyncram1 20. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter 21. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter 22. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr 23. Source assignments for sld_hub:sld_hub_inst 24. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG 25. Parameter Settings for User Entity Instance: VGA_Audio_PLL:u1|altpll:altpll_component 26. Parameter Settings for User Entity Instance: I2C_AV_Config:u7 27. Parameter Settings for User Entity Instance: adio_codec:ad1 28. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0 29. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9ui2:auto_generated|altsyncram_k4l1:altsyncram1 30. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst 31. SignalTap II Logic Analyzer Settings 32. Analysis & Synthesis INI Usage 33. Analysis & Synthesis Messages 34. Analysis & Synthesis Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2007 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +------------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+-----------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Thu Aug 30 15:51:56 2007 ; ; Quartus II Version ; 7.1 Build 178 06/25/2007 SP 1 SJ Full Version ; ; Revision Name ; DE1_synthesizer ; ; Top-level Entity Name ; DE1_synthesizer ; ; Family ; Cyclone II ; ; Total logic elements ; 1,854 ; ; Total combinational functions ; 1,854 ; ; Dedicated logic registers ; 766 ; ; Total registers ; 766 ; ; Total pins ; 287 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 59,392 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Total PLLs ; 1 ; +------------------------------------+-----------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +--------------------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +--------------------------------------------------------------------------------+--------------------+--------------------+ ; Device ; EP2C20F484C7 ; ; ; Top-level entity name ; DE1_synthesizer ; DE1_synthesizer ; ; Family name ; Cyclone II ; Stratix ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL93 ; VHDL93 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; DSP Block Balancing ; Auto ; Auto ; ; Maximum DSP Block Usage ; Unlimited ; Unlimited ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique -- Cyclone II/Cyclone III ; Balanced ; Balanced ; ; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Perform gate-level register retiming ; Off ; Off ; ; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto RAM to Logic Cell Conversion ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Maximum Number of M4K/M9K Memory Blocks ; Unlimited ; Unlimited ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Show Parameter Settings Tables in Synthesis Report ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ; ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Use smart compilation ; Off ; Off ; +--------------------------------------------------------------------------------+--------------------+--------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------+-----------------+-------------------------+------------------------------------------------------------------------------------------------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; +----------------------------------+-----------------+-------------------------+------------------------------------------------------------------------------------------------+ ; DE1_synthesizer.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/DE1_synthesizer.v ; ; SEG7_LUT_4.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/SEG7_LUT_4.v ; ; SEG7_LUT.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/SEG7_LUT.v ; ; VGA_Audio_PLL.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/VGA_Audio_PLL.v ; ; altpll.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altpll.tdf ; ; aglobal71.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/aglobal71.inc ; ; stratix_pll.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/stratix_pll.inc ; ; stratixii_pll.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/stratixii_pll.inc ; ; cycloneii_pll.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/cycloneii_pll.inc ; ; I2C_AV_Config.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/I2C_AV_Config.v ; ; I2C_Controller.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/I2C_Controller.v ; ; demo_sound1.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/demo_sound1.v ; ; demo_sound2.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/demo_sound2.v ; ; PS2_KEYBOARD.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/PS2_KEYBOARD.v ; ; staff.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/staff.v ; ; vga_time_generator.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/vga_time_generator.v ; ; bar_white.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/bar_white.v ; ; bar_big.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/bar_big.v ; ; bar_blank.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/bar_blank.v ; ; adio_codec.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/adio_codec.v ; ; wave_gen_string.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/wave_gen_string.v ; ; wave_gen_brass.v ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/wave_gen_brass.v ; ; sld_signaltap.vhd ; yes ; Encrypted Megafunction ; c:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd ; ; sld_ela_control.vhd ; yes ; Encrypted Megafunction ; c:/altera/71/quartus/libraries/megafunctions/sld_ela_control.vhd ; ; lpm_shiftreg.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf ; ; lpm_constant.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_constant.inc ; ; dffeea.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/dffeea.inc ; ; sld_mbpmg.vhd ; yes ; Encrypted Megafunction ; c:/altera/71/quartus/libraries/megafunctions/sld_mbpmg.vhd ; ; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf ; ; lpm_decode.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_decode.inc ; ; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_add_sub.inc ; ; cmpconst.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/cmpconst.inc ; ; lpm_compare.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_compare.inc ; ; lpm_counter.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_counter.inc ; ; alt_synch_counter.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/alt_synch_counter.inc ; ; alt_synch_counter_f.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/alt_synch_counter_f.inc ; ; alt_counter_f10ke.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.inc ; ; alt_counter_stratix.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/alt_counter_stratix.inc ; ; cntr_3hj.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/cntr_3hj.tdf ; ; cntr_2qi.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/cntr_2qi.tdf ; ; lpm_compare.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_compare.tdf ; ; comptree.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/comptree.inc ; ; altshift.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altshift.inc ; ; cmpr_2vh.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/cmpr_2vh.tdf ; ; sld_acquisition_buffer.vhd ; yes ; Encrypted Megafunction ; c:/altera/71/quartus/libraries/megafunctions/sld_acquisition_buffer.vhd ; ; cntr_bmk.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/cntr_bmk.tdf ; ; lpm_ff.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf ; ; altsyncram.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf ; ; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; lpm_mux.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_mux.inc ; ; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/a_rdenreg.inc ; ; altrom.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altrom.inc ; ; altram.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altram.inc ; ; altdpram.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altdpram.inc ; ; altqpram.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altqpram.inc ; ; altsyncram_9ui2.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/altsyncram_9ui2.tdf ; ; altsyncram_k4l1.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/altsyncram_k4l1.tdf ; ; cntr_5nh.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/cntr_5nh.tdf ; ; cntr_1gi.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/cntr_1gi.tdf ; ; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; c:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd ; ; sld_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd ; ; lpm_decode.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_decode.tdf ; ; declut.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/declut.inc ; ; decode_aoi.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/decode_aoi.tdf ; ; sld_dffex.vhd ; yes ; Encrypted Megafunction ; c:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd ; +----------------------------------+-----------------+-------------------------+------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +---------------------------------------------+--------------------------+ ; Resource ; Usage ; +---------------------------------------------+--------------------------+ ; Estimated Total logic elements ; 1,854 ; ; ; ; ; Total combinational functions ; 1854 ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 1141 ; ; -- 3 input functions ; 321 ; ; -- <=2 input functions ; 392 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 1541 ; ; -- arithmetic mode ; 313 ; ; ; ; ; Total registers ; 766 ; ; -- Dedicated logic registers ; 766 ; ; -- I/O registers ; 0 ; ; ; ; ; I/O pins ; 287 ; ; Total memory bits ; 59392 ; ; Total PLLs ; 1 ; ; Maximum fan-out node ; altera_internal_jtag~TDO ; ; Maximum fan-out ; 305 ; ; Total fan-out ; 9592 ; ; Average fan-out ; 3.26 ; +---------------------------------------------+--------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; +------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ ; |DE1_synthesizer ; 1854 (68) ; 766 (30) ; 59392 ; 0 ; 0 ; 0 ; 287 ; 0 ; |DE1_synthesizer ; work ; ; |I2C_AV_Config:u7| ; 87 (45) ; 58 (36) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|I2C_AV_Config:u7 ; work ; ; |I2C_Controller:u0| ; 42 (42) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|I2C_AV_Config:u7|I2C_Controller:u0 ; work ; ; |PS2_KEYBOARD:keyboard| ; 88 (88) ; 54 (54) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|PS2_KEYBOARD:keyboard ; work ; ; |VGA_Audio_PLL:u1| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|VGA_Audio_PLL:u1 ; work ; ; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|VGA_Audio_PLL:u1|altpll:altpll_component ; work ; ; |adio_codec:ad1| ; 446 (446) ; 50 (50) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|adio_codec:ad1 ; work ; ; |demo_sound1:dd1| ; 190 (190) ; 45 (45) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|demo_sound1:dd1 ; work ; ; |demo_sound2:dd2| ; 186 (186) ; 45 (45) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|demo_sound2:dd2 ; work ; ; |sld_hub:sld_hub_inst| ; 92 (44) ; 73 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_hub:sld_hub_inst ; work ; ; |lpm_decode:instruction_decoder| ; 5 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder ; work ; ; |decode_aoi:auto_generated| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated ; work ; ; |lpm_shiftreg:jtag_ir_register| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register ; work ; ; |sld_dffex:BROADCAST| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_hub:sld_hub_inst|sld_dffex:BROADCAST ; work ; ; |sld_dffex:IRF_ENA_0| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0 ; work ; ; |sld_dffex:IRF_ENA| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA ; work ; ; |sld_dffex:IRSR| ; 4 (4) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_hub:sld_hub_inst|sld_dffex:IRSR ; work ; ; |sld_dffex:RESET| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_hub:sld_hub_inst|sld_dffex:RESET ; work ; ; |sld_dffex:\GEN_IRF:1:IRF| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF ; work ; ; |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF ; work ; ; |sld_jtag_state_machine:jtag_state_machine| ; 19 (19) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine ; work ; ; |sld_rom_sr:HUB_INFO_REG| ; 17 (17) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ; work ; ; |sld_signaltap:auto_signaltap_0| ; 232 (0) ; 359 (0) ; 59392 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0 ; work ; ; |sld_signaltap_impl:sld_signaltap_body| ; 232 (7) ; 359 (62) ; 59392 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body ; work ; ; |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram| ; 0 (0) ; 0 (0) ; 59392 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram ; work ; ; |altsyncram_9ui2:auto_generated| ; 0 (0) ; 0 (0) ; 59392 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9ui2:auto_generated ; work ; ; |altsyncram_k4l1:altsyncram1| ; 0 (0) ; 0 (0) ; 59392 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9ui2:auto_generated|altsyncram_k4l1:altsyncram1 ; work ; ; |sld_acquisition_buffer:sld_acquisition_buffer_inst| ; 15 (3) ; 23 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst ; work ; ; |lpm_counter:\write_address_non_zero_gen:write_pointer_counter| ; 12 (0) ; 11 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter ; work ; ; |cntr_bmk:auto_generated| ; 12 (12) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_bmk:auto_generated ; work ; ; |lpm_ff:\gen_non_zero_sample_depth:trigger_address_register| ; 0 (0) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_ff:\gen_non_zero_sample_depth:trigger_address_register ; work ; ; |sld_ela_control:ela_control| ; 118 (5) ; 198 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control ; work ; ; |lpm_shiftreg:trigger_config_deserialize| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize ; work ; ; |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 58 (0) ; 145 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm ; work ; ; |lpm_shiftreg:trigger_condition_deserialize| ; 0 (0) ; 87 (87) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize ; work ; ; |sld_mbpmg:\trigger_modules_gen:0:trigger_match| ; 58 (0) ; 58 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1 ; work ; ; |sld_ela_level_seq_mgr:ela_level_seq_mgr| ; 15 (15) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr ; work ; ; |sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1| ; 12 (1) ; 11 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1 ; work ; ; |lpm_counter:post_trigger_counter| ; 11 (0) ; 11 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1|lpm_counter:post_trigger_counter ; work ; ; |cntr_3hj:auto_generated| ; 11 (11) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1|lpm_counter:post_trigger_counter|cntr_3hj:auto_generated ; work ; ; |sld_ela_seg_state_machine:sm2| ; 2 (2) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2 ; work ; ; |sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr| ; 20 (1) ; 12 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr ; work ; ; |lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare| ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare ; work ; ; |cmpr_2vh:auto_generated| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|cmpr_2vh:auto_generated ; work ; ; |lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter| ; 12 (0) ; 11 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter ; work ; ; |cntr_2qi:auto_generated| ; 12 (12) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_2qi:auto_generated ; work ; ; |sld_ela_state_machine:sm1| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_state_machine:sm1 ; work ; ; |sld_mbpmg:\trigger_in_trigger_module_enabled_gen:trigger_in_match| ; 2 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_mbpmg:\trigger_in_trigger_module_enabled_gen:trigger_in_match ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_mbpmg:\trigger_in_trigger_module_enabled_gen:trigger_in_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1 ; work ; ; |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst| ; 75 (5) ; 68 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst ; work ; ; |lpm_counter:\adv_point_3_and_more:advance_pointer_counter| ; 7 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter ; work ; ; |cntr_5nh:auto_generated| ; 7 (7) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_5nh:auto_generated ; work ; ; |lpm_counter:read_pointer_counter| ; 11 (0) ; 11 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter ; work ; ; |cntr_1gi:auto_generated| ; 11 (11) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_1gi:auto_generated ; work ; ; |lpm_shiftreg:info_data_shift_out| ; 23 (23) ; 23 (23) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out ; work ; ; |lpm_shiftreg:ram_data_shift_out| ; 29 (29) ; 29 (29) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out ; work ; ; |sld_rom_sr:crc_rom_sr| ; 17 (17) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr ; work ; ; |staff:st1| ; 465 (348) ; 52 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|staff:st1 ; work ; ; |bar_big:b0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|staff:st1|bar_big:b0 ; work ; ; |bar_big:b2| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|staff:st1|bar_big:b2 ; work ; ; |bar_blank:bar_blank1| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|staff:st1|bar_blank:bar_blank1 ; work ; ; |bar_white:bar1| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|staff:st1|bar_white:bar1 ; work ; ; |vga_time_generator:vga0| ; 76 (76) ; 52 (52) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_synthesizer|staff:st1|vga_time_generator:vga0 ; work ; +------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis RAM Summary ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+-------+------+ ; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+-------+------+ ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9ui2:auto_generated|altsyncram_k4l1:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 2048 ; 29 ; 2048 ; 29 ; 59392 ; None ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+-------+------+ Encoding Type: One-Hot +-------------------------------------------------------------+ ; State Machine - |DE1_synthesizer|I2C_AV_Config:u7|mSetup_ST ; +--------------+--------------+--------------+----------------+ ; Name ; mSetup_ST.00 ; mSetup_ST.10 ; mSetup_ST.01 ; +--------------+--------------+--------------+----------------+ ; mSetup_ST.00 ; 0 ; 0 ; 0 ; ; mSetup_ST.01 ; 1 ; 0 ; 1 ; ; mSetup_ST.10 ; 1 ; 1 ; 0 ; +--------------+--------------+--------------+----------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Registers Removed During Synthesis ; +------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Register name ; Reason for Removal ; +------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; ad1/ramp4[0] ; Stuck at GND due to stuck port clear ; ; ad1/ramp3[0..15] ; Stuck at GND due to stuck port clear ; ; ad1/ramp4[1..15] ; Stuck at GND due to stuck port clear ; ; u7/mI2C_DATA[22..23] ; Stuck at GND due to stuck port data_in ; ; u7/mI2C_DATA[20..21] ; Stuck at VCC due to stuck port data_in ; ; u7/mI2C_DATA[19] ; Stuck at GND due to stuck port data_in ; ; u7/mI2C_DATA[18] ; Stuck at VCC due to stuck port data_in ; ; u7/mI2C_DATA[8,13..17] ; Stuck at GND due to stuck port data_in ; ; u7/u0/SD[22..23] ; Stuck at GND due to stuck port data_in ; ; u7/u0/SD[20..21] ; Stuck at VCC due to stuck port data_in ; ; u7/u0/SD[19] ; Stuck at GND due to stuck port data_in ; ; u7/u0/SD[18] ; Stuck at VCC due to stuck port data_in ; ; u7/u0/SD[8,13..17] ; Stuck at GND due to stuck port data_in ; ; dd2/st[4] ; Merged with dd2/st[5] ; ; dd1/st[4] ; Merged with dd1/st[5] ; ; u7/mI2C_DATA[5] ; Merged with u7/mI2C_DATA[6] ; ; u7/mI2C_DATA[3] ; Merged with u7/mI2C_DATA[4] ; ; u7/u0/SD[5] ; Merged with u7/u0/SD[6] ; ; u7/u0/SD[3] ; Merged with u7/u0/SD[4] ; ; dd1/st[3,5] ; Stuck at GND due to stuck port data_in ; ; dd2/st[3,5] ; Stuck at GND due to stuck port data_in ; ; DELAY[7] ; Stuck at VCC due to stuck port data_in ; ; DELAY[0..6] ; Stuck at GND due to stuck port clock_enable ; ; VGA_CLK_o[19..31] ; Lost fanout ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[28] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[28] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][28] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[0] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[0] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][0] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/trigger_in_reg ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[1] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[1] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[1] ; ; auto_signaltap_0/sld_signaltap_body/ela_control/\trigger_in_trigger_module_enabled_gen:trigger_in_match/\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1/holdff ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][1] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[2] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[2] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][2] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[3] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[3] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][3] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[4] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[4] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][4] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[5] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[5] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][5] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[6] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[6] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][6] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[7] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[7] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][7] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[8] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[8] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][8] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[9] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[9] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][9] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[10] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[10] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][10] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[11] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[11] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][11] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[12] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[12] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][12] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[13] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[13] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][13] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[14] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[14] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][14] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[15] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[15] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][15] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[16] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[16] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][16] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[17] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[17] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][17] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[18] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[18] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][18] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[19] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[19] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][19] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[20] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[20] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][20] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[21] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[21] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][21] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[22] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[22] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][22] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[23] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[23] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][23] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[24] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[24] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][24] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[25] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[25] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][25] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[27] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[27] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][27] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1/holdff ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_reg[26] ; Merged with auto_signaltap_0/sld_signaltap_body/acq_trigger_in_reg[26] ; ; auto_signaltap_0/sld_signaltap_body/acq_data_in_pipe_reg[1][26] ; Merged with auto_signaltap_0/sld_signaltap_body/ela_control/\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm/\trigger_modules_gen:0:trigger_match/\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1/holdff ; ; ad1/BCK_DIV[3] ; Stuck at GND due to stuck port data_in ; ; Total Number of Removed Registers = 148 ; ; +------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------+ ; Removed Registers Triggering Further Register Optimizations ; +------------------+---------------------------+------------------------------------------------------------+ ; Register name ; Reason for Removal ; Registers Removed due to This Register ; +------------------+---------------------------+------------------------------------------------------------+ ; DELAY[7] ; Stuck at VCC ; DELAY[1], DELAY[2], DELAY[3], DELAY[4], DELAY[5], DELAY[6] ; ; ; due to stuck port data_in ; ; ; u7/mI2C_DATA[23] ; Stuck at GND ; u7/u0/SD[23] ; ; ; due to stuck port data_in ; ; ; u7/mI2C_DATA[22] ; Stuck at GND ; u7/u0/SD[22] ; ; ; due to stuck port data_in ; ; ; u7/mI2C_DATA[21] ; Stuck at VCC ; u7/u0/SD[21] ; ; ; due to stuck port data_in ; ; ; u7/mI2C_DATA[20] ; Stuck at VCC ; u7/u0/SD[20] ; ; ; due to stuck port data_in ; ; ; u7/mI2C_DATA[19] ; Stuck at GND ; u7/u0/SD[19] ; ; ; due to stuck port data_in ; ; ; u7/mI2C_DATA[18] ; Stuck at VCC ; u7/u0/SD[18] ; ; ; due to stuck port data_in ; ; ; u7/mI2C_DATA[17] ; Stuck at GND ; u7/u0/SD[17] ; ; ; due to stuck port data_in ; ; ; u7/mI2C_DATA[16] ; Stuck at GND ; u7/u0/SD[16] ; ; ; due to stuck port data_in ; ; ; u7/mI2C_DATA[15] ; Stuck at GND ; u7/u0/SD[15] ; ; ; due to stuck port data_in ; ; ; u7/mI2C_DATA[14] ; Stuck at GND ; u7/u0/SD[14] ; ; ; due to stuck port data_in ; ; ; u7/mI2C_DATA[13] ; Stuck at GND ; u7/u0/SD[13] ; ; ; due to stuck port data_in ; ; ; u7/mI2C_DATA[8] ; Stuck at GND ; u7/u0/SD[8] ; ; ; due to stuck port data_in ; ; +------------------+---------------------------+------------------------------------------------------------+ +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 766 ; ; Number of registers using Synchronous Clear ; 119 ; ; Number of registers using Synchronous Load ; 22 ; ; Number of registers using Asynchronous Clear ; 481 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 353 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +------------------------------------------------------------+ ; Inverted Register Statistics ; +--------------------------------------------------+---------+ ; Inverted Register ; Fan out ; +--------------------------------------------------+---------+ ; PS2_KEYBOARD:keyboard|key1_code[6] ; 2 ; ; PS2_KEYBOARD:keyboard|key1_code[7] ; 2 ; ; PS2_KEYBOARD:keyboard|key1_code[5] ; 2 ; ; PS2_KEYBOARD:keyboard|key1_code[4] ; 2 ; ; PS2_KEYBOARD:keyboard|key2_code[6] ; 2 ; ; PS2_KEYBOARD:keyboard|key2_code[7] ; 2 ; ; PS2_KEYBOARD:keyboard|key2_code[5] ; 2 ; ; PS2_KEYBOARD:keyboard|key2_code[4] ; 2 ; ; I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[0] ; 18 ; ; I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[2] ; 15 ; ; I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[3] ; 18 ; ; I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[1] ; 13 ; ; I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[4] ; 11 ; ; I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[5] ; 12 ; ; I2C_AV_Config:u7|I2C_Controller:u0|SCLK ; 2 ; ; sld_hub:sld_hub_inst|hub_tdo_reg ; 2 ; ; ps_clk ; 19 ; ; I2C_AV_Config:u7|I2C_Controller:u0|END ; 5 ; ; I2C_AV_Config:u7|I2C_Controller:u0|SDO ; 4 ; ; Total number of inverted registers = 19 ; ; +--------------------------------------------------+---------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Restructuring Statistics (Restructuring Performed) ; +--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------+ ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |DE1_synthesizer|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] ; ; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |DE1_synthesizer|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0] ; ; 5:1 ; 4 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |DE1_synthesizer|PS2_KEYBOARD:keyboard|key1_code[3] ; ; 33:1 ; 5 bits ; 110 LEs ; 105 LEs ; 5 LEs ; Yes ; |DE1_synthesizer|demo_sound1:dd1|st[3] ; ; 33:1 ; 5 bits ; 110 LEs ; 105 LEs ; 5 LEs ; Yes ; |DE1_synthesizer|demo_sound2:dd2|st[5] ; ; 7:1 ; 4 bits ; 16 LEs ; 4 LEs ; 12 LEs ; Yes ; |DE1_synthesizer|PS2_KEYBOARD:keyboard|key2_code[3] ; ; 20:1 ; 4 bits ; 52 LEs ; 32 LEs ; 20 LEs ; Yes ; |DE1_synthesizer|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] ; ; 5:1 ; 4 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |DE1_synthesizer|PS2_KEYBOARD:keyboard|key1_code[4] ; ; 7:1 ; 4 bits ; 16 LEs ; 4 LEs ; 12 LEs ; Yes ; |DE1_synthesizer|PS2_KEYBOARD:keyboard|key2_code[7] ; ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |DE1_synthesizer|staff:st1|sound1[5] ; ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |DE1_synthesizer|staff:st1|sound1[7] ; ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |DE1_synthesizer|staff:st1|sound2[5] ; ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |DE1_synthesizer|staff:st1|sound2[7] ; ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |DE1_synthesizer|sound_code1[5] ; ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |DE1_synthesizer|sound_code2[7] ; ; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |DE1_synthesizer|staff:st1|sound1[5] ; ; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |DE1_synthesizer|staff:st1|sound2[5] ; ; 5:1 ; 2 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |DE1_synthesizer|demo_sound1:dd1|tmpa[5] ; ; 5:1 ; 2 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |DE1_synthesizer|demo_sound2:dd2|tmpa[6] ; ; 9:1 ; 2 bits ; 12 LEs ; 2 LEs ; 10 LEs ; No ; |DE1_synthesizer|staff:st1|blank_x[1] ; ; 10:1 ; 2 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |DE1_synthesizer|staff:st1|by_org[6] ; ; 13:1 ; 2 bits ; 16 LEs ; 8 LEs ; 8 LEs ; No ; |DE1_synthesizer|staff:st1|sound1[8] ; ; 13:1 ; 2 bits ; 16 LEs ; 8 LEs ; 8 LEs ; No ; |DE1_synthesizer|staff:st1|sound2[9] ; ; 14:1 ; 2 bits ; 18 LEs ; 18 LEs ; 0 LEs ; No ; |DE1_synthesizer|staff:st1|y_org[5] ; ; 5:1 ; 4 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[2] ; ; 12:1 ; 4 bits ; 32 LEs ; 24 LEs ; 8 LEs ; Yes ; |DE1_synthesizer|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[3] ; +--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------+ ; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body ; +---------------------------------+-------+------+--------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+-------+------+--------------------------------------------+ ; NOT_GATE_PUSH_BACK ; OFF ; - ; - ; ; POWER_UP_LEVEL ; LOW ; - ; - ; ; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; +---------------------------------+-------+------+--------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1|lpm_counter:post_trigger_counter ; +---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; ; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; ; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; +---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter ; +---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; ; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; ; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; +---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter ; +---------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; ; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; ; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; +---------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9ui2:auto_generated ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9ui2:auto_generated|altsyncram_k4l1:altsyncram1 ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter ; +---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; ; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; ; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; +---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter ; +---------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; ; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; ; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; +---------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------+ ; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr ; +----------------------+-------+------+-----------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +----------------------+-------+------+-----------------------------------------------------------------------------+ ; AUTO_ROM_RECOGNITION ; OFF ; - ; - ; +----------------------+-------+------+-----------------------------------------------------------------------------+ +----------------------------------------------------------+ ; Source assignments for sld_hub:sld_hub_inst ; +------------------------------+-------+------+------------+ ; Assignment ; Value ; From ; To ; +------------------------------+-------+------+------------+ ; IGNORE_LCELL_BUFFERS ; OFF ; - ; - ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF ; - ; - ; ; NOT_GATE_PUSH_BACK ; OFF ; - ; CLR_SIGNAL ; ; POWER_UP_LEVEL ; LOW ; - ; CLR_SIGNAL ; +------------------------------+-------+------+------------+ +---------------------------------------------------------------------+ ; Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ; +----------------------+-------+------+-------------------------------+ ; Assignment ; Value ; From ; To ; +----------------------+-------+------+-------------------------------+ ; AUTO_ROM_RECOGNITION ; OFF ; - ; - ; +----------------------+-------+------+-------------------------------+ +---------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: VGA_Audio_PLL:u1|altpll:altpll_component ; +-------------------------------+-------------------+-----------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------------+-------------------+-----------------------------------+ ; OPERATION_MODE ; NORMAL ; Untyped ; ; PLL_TYPE ; AUTO ; Untyped ; ; QUALIFY_CONF_DONE ; OFF ; Untyped ; ; COMPENSATE_CLOCK ; CLK0 ; Untyped ; ; SCAN_CHAIN ; LONG ; Untyped ; ; PRIMARY_CLOCK ; INCLK0 ; Untyped ; ; INCLK0_INPUT_FREQUENCY ; 37037 ; Signed Integer ; ; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; ; GATE_LOCK_SIGNAL ; NO ; Untyped ; ; GATE_LOCK_COUNTER ; 0 ; Untyped ; ; LOCK_HIGH ; 1 ; Untyped ; ; LOCK_LOW ; 1 ; Untyped ; ; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; ; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; ; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; ; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; ; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; ; SKIP_VCO ; OFF ; Untyped ; ; SWITCH_OVER_COUNTER ; 0 ; Untyped ; ; SWITCH_OVER_TYPE ; AUTO ; Untyped ; ; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; ; BANDWIDTH ; 0 ; Untyped ; ; BANDWIDTH_TYPE ; AUTO ; Untyped ; ; SPREAD_FREQUENCY ; 0 ; Untyped ; ; DOWN_SPREAD ; 0 ; Untyped ; ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; ; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; ; CLK9_MULTIPLY_BY ; 0 ; Untyped ; ; CLK8_MULTIPLY_BY ; 0 ; Untyped ; ; CLK7_MULTIPLY_BY ; 0 ; Untyped ; ; CLK6_MULTIPLY_BY ; 0 ; Untyped ; ; CLK5_MULTIPLY_BY ; 1 ; Untyped ; ; CLK4_MULTIPLY_BY ; 1 ; Untyped ; ; CLK3_MULTIPLY_BY ; 1 ; Untyped ; ; CLK2_MULTIPLY_BY ; 1 ; Untyped ; ; CLK1_MULTIPLY_BY ; 2 ; Signed Integer ; ; CLK0_MULTIPLY_BY ; 14 ; Signed Integer ; ; CLK9_DIVIDE_BY ; 0 ; Untyped ; ; CLK8_DIVIDE_BY ; 0 ; Untyped ; ; CLK7_DIVIDE_BY ; 0 ; Untyped ; ; CLK6_DIVIDE_BY ; 0 ; Untyped ; ; CLK5_DIVIDE_BY ; 1 ; Untyped ; ; CLK4_DIVIDE_BY ; 1 ; Untyped ; ; CLK3_DIVIDE_BY ; 1 ; Untyped ; ; CLK2_DIVIDE_BY ; 1 ; Untyped ; ; CLK1_DIVIDE_BY ; 3 ; Signed Integer ; ; CLK0_DIVIDE_BY ; 15 ; Signed Integer ; ; CLK9_PHASE_SHIFT ; 0 ; Untyped ; ; CLK8_PHASE_SHIFT ; 0 ; Untyped ; ; CLK7_PHASE_SHIFT ; 0 ; Untyped ; ; CLK6_PHASE_SHIFT ; 0 ; Untyped ; ; CLK5_PHASE_SHIFT ; 0 ; Untyped ; ; CLK4_PHASE_SHIFT ; 0 ; Untyped ; ; CLK3_PHASE_SHIFT ; 0 ; Untyped ; ; CLK2_PHASE_SHIFT ; 0 ; Untyped ; ; CLK1_PHASE_SHIFT ; 0 ; Untyped ; ; CLK0_PHASE_SHIFT ; 0 ; Untyped ; ; CLK5_TIME_DELAY ; 0 ; Untyped ; ; CLK4_TIME_DELAY ; 0 ; Untyped ; ; CLK3_TIME_DELAY ; 0 ; Untyped ; ; CLK2_TIME_DELAY ; 0 ; Untyped ; ; CLK1_TIME_DELAY ; 0 ; Untyped ; ; CLK0_TIME_DELAY ; 0 ; Untyped ; ; CLK9_DUTY_CYCLE ; 50 ; Untyped ; ; CLK8_DUTY_CYCLE ; 50 ; Untyped ; ; CLK7_DUTY_CYCLE ; 50 ; Untyped ; ; CLK6_DUTY_CYCLE ; 50 ; Untyped ; ; CLK5_DUTY_CYCLE ; 50 ; Untyped ; ; CLK4_DUTY_CYCLE ; 50 ; Untyped ; ; CLK3_DUTY_CYCLE ; 50 ; Untyped ; ; CLK2_DUTY_CYCLE ; 50 ; Untyped ; ; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; ; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; ; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; LOCK_WINDOW_UI ; 0.05 ; Untyped ; ; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; ; VCO_MULTIPLY_BY ; 0 ; Untyped ; ; VCO_DIVIDE_BY ; 0 ; Untyped ; ; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; ; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; ; VCO_MIN ; 0 ; Untyped ; ; VCO_MAX ; 0 ; Untyped ; ; VCO_CENTER ; 0 ; Untyped ; ; PFD_MIN ; 0 ; Untyped ; ; PFD_MAX ; 0 ; Untyped ; ; M_INITIAL ; 0 ; Untyped ; ; M ; 0 ; Untyped ; ; N ; 1 ; Untyped ; ; M2 ; 1 ; Untyped ; ; N2 ; 1 ; Untyped ; ; SS ; 1 ; Untyped ; ; C0_HIGH ; 0 ; Untyped ; ; C1_HIGH ; 0 ; Untyped ; ; C2_HIGH ; 0 ; Untyped ; ; C3_HIGH ; 0 ; Untyped ; ; C4_HIGH ; 0 ; Untyped ; ; C5_HIGH ; 0 ; Untyped ; ; C6_HIGH ; 0 ; Untyped ; ; C7_HIGH ; 0 ; Untyped ; ; C8_HIGH ; 0 ; Untyped ; ; C9_HIGH ; 0 ; Untyped ; ; C0_LOW ; 0 ; Untyped ; ; C1_LOW ; 0 ; Untyped ; ; C2_LOW ; 0 ; Untyped ; ; C3_LOW ; 0 ; Untyped ; ; C4_LOW ; 0 ; Untyped ; ; C5_LOW ; 0 ; Untyped ; ; C6_LOW ; 0 ; Untyped ; ; C7_LOW ; 0 ; Untyped ; ; C8_LOW ; 0 ; Untyped ; ; C9_LOW ; 0 ; Untyped ; ; C0_INITIAL ; 0 ; Untyped ; ; C1_INITIAL ; 0 ; Untyped ; ; C2_INITIAL ; 0 ; Untyped ; ; C3_INITIAL ; 0 ; Untyped ; ; C4_INITIAL ; 0 ; Untyped ; ; C5_INITIAL ; 0 ; Untyped ; ; C6_INITIAL ; 0 ; Untyped ; ; C7_INITIAL ; 0 ; Untyped ; ; C8_INITIAL ; 0 ; Untyped ; ; C9_INITIAL ; 0 ; Untyped ; ; C0_MODE ; BYPASS ; Untyped ; ; C1_MODE ; BYPASS ; Untyped ; ; C2_MODE ; BYPASS ; Untyped ; ; C3_MODE ; BYPASS ; Untyped ; ; C4_MODE ; BYPASS ; Untyped ; ; C5_MODE ; BYPASS ; Untyped ; ; C6_MODE ; BYPASS ; Untyped ; ; C7_MODE ; BYPASS ; Untyped ; ; C8_MODE ; BYPASS ; Untyped ; ; C9_MODE ; BYPASS ; Untyped ; ; C0_PH ; 0 ; Untyped ; ; C1_PH ; 0 ; Untyped ; ; C2_PH ; 0 ; Untyped ; ; C3_PH ; 0 ; Untyped ; ; C4_PH ; 0 ; Untyped ; ; C5_PH ; 0 ; Untyped ; ; C6_PH ; 0 ; Untyped ; ; C7_PH ; 0 ; Untyped ; ; C8_PH ; 0 ; Untyped ; ; C9_PH ; 0 ; Untyped ; ; L0_HIGH ; 1 ; Untyped ; ; L1_HIGH ; 1 ; Untyped ; ; G0_HIGH ; 1 ; Untyped ; ; G1_HIGH ; 1 ; Untyped ; ; G2_HIGH ; 1 ; Untyped ; ; G3_HIGH ; 1 ; Untyped ; ; E0_HIGH ; 1 ; Untyped ; ; E1_HIGH ; 1 ; Untyped ; ; E2_HIGH ; 1 ; Untyped ; ; E3_HIGH ; 1 ; Untyped ; ; L0_LOW ; 1 ; Untyped ; ; L1_LOW ; 1 ; Untyped ; ; G0_LOW ; 1 ; Untyped ; ; G1_LOW ; 1 ; Untyped ; ; G2_LOW ; 1 ; Untyped ; ; G3_LOW ; 1 ; Untyped ; ; E0_LOW ; 1 ; Untyped ; ; E1_LOW ; 1 ; Untyped ; ; E2_LOW ; 1 ; Untyped ; ; E3_LOW ; 1 ; Untyped ; ; L0_INITIAL ; 1 ; Untyped ; ; L1_INITIAL ; 1 ; Untyped ; ; G0_INITIAL ; 1 ; Untyped ; ; G1_INITIAL ; 1 ; Untyped ; ; G2_INITIAL ; 1 ; Untyped ; ; G3_INITIAL ; 1 ; Untyped ; ; E0_INITIAL ; 1 ; Untyped ; ; E1_INITIAL ; 1 ; Untyped ; ; E2_INITIAL ; 1 ; Untyped ; ; E3_INITIAL ; 1 ; Untyped ; ; L0_MODE ; BYPASS ; Untyped ; ; L1_MODE ; BYPASS ; Untyped ; ; G0_MODE ; BYPASS ; Untyped ; ; G1_MODE ; BYPASS ; Untyped ; ; G2_MODE ; BYPASS ; Untyped ; ; G3_MODE ; BYPASS ; Untyped ; ; E0_MODE ; BYPASS ; Untyped ; ; E1_MODE ; BYPASS ; Untyped ; ; E2_MODE ; BYPASS ; Untyped ; ; E3_MODE ; BYPASS ; Untyped ; ; L0_PH ; 0 ; Untyped ; ; L1_PH ; 0 ; Untyped ; ; G0_PH ; 0 ; Untyped ; ; G1_PH ; 0 ; Untyped ; ; G2_PH ; 0 ; Untyped ; ; G3_PH ; 0 ; Untyped ; ; E0_PH ; 0 ; Untyped ; ; E1_PH ; 0 ; Untyped ; ; E2_PH ; 0 ; Untyped ; ; E3_PH ; 0 ; Untyped ; ; M_PH ; 0 ; Untyped ; ; C1_USE_CASC_IN ; OFF ; Untyped ; ; C2_USE_CASC_IN ; OFF ; Untyped ; ; C3_USE_CASC_IN ; OFF ; Untyped ; ; C4_USE_CASC_IN ; OFF ; Untyped ; ; C5_USE_CASC_IN ; OFF ; Untyped ; ; C6_USE_CASC_IN ; OFF ; Untyped ; ; C7_USE_CASC_IN ; OFF ; Untyped ; ; C8_USE_CASC_IN ; OFF ; Untyped ; ; C9_USE_CASC_IN ; OFF ; Untyped ; ; CLK0_COUNTER ; G0 ; Untyped ; ; CLK1_COUNTER ; G0 ; Untyped ; ; CLK2_COUNTER ; G0 ; Untyped ; ; CLK3_COUNTER ; G0 ; Untyped ; ; CLK4_COUNTER ; G0 ; Untyped ; ; CLK5_COUNTER ; G0 ; Untyped ; ; L0_TIME_DELAY ; 0 ; Untyped ; ; L1_TIME_DELAY ; 0 ; Untyped ; ; G0_TIME_DELAY ; 0 ; Untyped ; ; G1_TIME_DELAY ; 0 ; Untyped ; ; G2_TIME_DELAY ; 0 ; Untyped ; ; G3_TIME_DELAY ; 0 ; Untyped ; ; E0_TIME_DELAY ; 0 ; Untyped ; ; E1_TIME_DELAY ; 0 ; Untyped ; ; E2_TIME_DELAY ; 0 ; Untyped ; ; E3_TIME_DELAY ; 0 ; Untyped ; ; M_TIME_DELAY ; 0 ; Untyped ; ; N_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_COUNTER ; E3 ; Untyped ; ; EXTCLK2_COUNTER ; E2 ; Untyped ; ; EXTCLK1_COUNTER ; E1 ; Untyped ; ; EXTCLK0_COUNTER ; E0 ; Untyped ; ; ENABLE0_COUNTER ; L0 ; Untyped ; ; ENABLE1_COUNTER ; L0 ; Untyped ; ; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; ; LOOP_FILTER_R ; 1.000000 ; Untyped ; ; LOOP_FILTER_C ; 5 ; Untyped ; ; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; ; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; ; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; ; VCO_POST_SCALE ; 0 ; Untyped ; ; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; INTENDED_DEVICE_FAMILY ; Cyclone II ; Untyped ; ; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; ; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; ; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; ; PORT_CLK0 ; PORT_USED ; Untyped ; ; PORT_CLK1 ; PORT_USED ; Untyped ; ; PORT_CLK2 ; PORT_UNUSED ; Untyped ; ; PORT_CLK3 ; PORT_UNUSED ; Untyped ; ; PORT_CLK4 ; PORT_UNUSED ; Untyped ; ; PORT_CLK5 ; PORT_UNUSED ; Untyped ; ; PORT_CLK6 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK7 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK8 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK9 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; ; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; ; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; ; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; ; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; ; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; ; PORT_INCLK0 ; PORT_USED ; Untyped ; ; PORT_FBIN ; PORT_UNUSED ; Untyped ; ; PORT_PLLENA ; PORT_UNUSED ; Untyped ; ; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; ; PORT_ARESET ; PORT_USED ; Untyped ; ; PORT_PFDENA ; PORT_UNUSED ; Untyped ; ; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; ; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; ; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; ; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; ; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_LOCKED ; PORT_UNUSED ; Untyped ; ; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; ; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; ; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; ; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; ; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; ; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; ; M_TEST_SOURCE ; 5 ; Untyped ; ; C0_TEST_SOURCE ; 5 ; Untyped ; ; C1_TEST_SOURCE ; 5 ; Untyped ; ; C2_TEST_SOURCE ; 5 ; Untyped ; ; C3_TEST_SOURCE ; 5 ; Untyped ; ; C4_TEST_SOURCE ; 5 ; Untyped ; ; C5_TEST_SOURCE ; 5 ; Untyped ; ; C6_TEST_SOURCE ; 5 ; Untyped ; ; C7_TEST_SOURCE ; 5 ; Untyped ; ; C8_TEST_SOURCE ; 5 ; Untyped ; ; C9_TEST_SOURCE ; 5 ; Untyped ; ; CBXI_PARAMETER ; NOTHING ; Untyped ; ; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; ; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; ; WIDTH_CLOCK ; 6 ; Untyped ; ; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; ; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +-------------------------------+-------------------+-----------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: I2C_AV_Config:u7 ; +----------------+----------+-----------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+----------+-----------------------------------+ ; CLK_Freq ; 50000000 ; Signed Integer ; ; I2C_Freq ; 20000 ; Signed Integer ; ; LUT_SIZE ; 12 ; Signed Integer ; ; Dummy_DATA ; 0 ; Signed Integer ; ; SET_LIN_L ; 1 ; Signed Integer ; ; SET_LIN_R ; 2 ; Signed Integer ; ; SET_HEAD_L ; 3 ; Signed Integer ; ; SET_HEAD_R ; 4 ; Signed Integer ; ; A_PATH_CTRL ; 5 ; Signed Integer ; ; D_PATH_CTRL ; 6 ; Signed Integer ; ; POWER_ON ; 7 ; Signed Integer ; ; SET_FORMAT ; 8 ; Signed Integer ; ; SAMPLE_CTRL ; 9 ; Signed Integer ; ; SET_ACTIVE ; 10 ; Signed Integer ; +----------------+----------+-----------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: adio_codec:ad1 ; +-----------------+----------+--------------------------------+ ; Parameter Name ; Value ; Type ; +-----------------+----------+--------------------------------+ ; REF_CLK ; 18432000 ; Signed Integer ; ; SAMPLE_RATE ; 48000 ; Signed Integer ; ; DATA_WIDTH ; 16 ; Signed Integer ; ; CHANNEL_NUM ; 2 ; Signed Integer ; ; SIN_SAMPLE_DATA ; 48 ; Signed Integer ; ; SIN_SANPLE ; 0 ; Signed Integer ; +-----------------+----------+--------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0 ; +-----------------------------+-------------------------------------------------------------------------------------------------------------+----------------+ ; Parameter Name ; Value ; Type ; +-----------------------------+-------------------------------------------------------------------------------------------------------------+----------------+ ; lpm_type ; sld_signaltap ; String ; ; sld_node_info ; 671116800 ; Untyped ; ; sld_ip_version ; 5 ; Signed Integer ; ; sld_ip_minor_version ; 0 ; Signed Integer ; ; sld_common_ip_version ; 0 ; Signed Integer ; ; sld_data_bits ; 29 ; Untyped ; ; sld_trigger_bits ; 29 ; Untyped ; ; sld_data_bit_cntr_bits ; 5 ; Untyped ; ; sld_node_crc_bits ; 32 ; Signed Integer ; ; sld_node_crc_hiword ; 42047 ; Untyped ; ; sld_node_crc_loword ; 43267 ; Untyped ; ; sld_incremental_routing ; 0 ; Signed Integer ; ; sld_sample_depth ; 2048 ; Untyped ; ; sld_mem_address_bits ; 11 ; Untyped ; ; sld_ram_block_type ; AUTO ; String ; ; sld_trigger_level ; 1 ; Untyped ; ; sld_trigger_in_enabled ; 1 ; Untyped ; ; sld_advanced_trigger_entity ; basic,1, ; Untyped ; ; sld_trigger_level_pipeline ; 1 ; Untyped ; ; sld_enable_advanced_trigger ; 0 ; Untyped ; ; sld_advanced_trigger_1 ; NONE ; String ; ; sld_advanced_trigger_2 ; NONE ; String ; ; sld_advanced_trigger_3 ; NONE ; String ; ; sld_advanced_trigger_4 ; NONE ; String ; ; sld_advanced_trigger_5 ; NONE ; String ; ; sld_advanced_trigger_6 ; NONE ; String ; ; sld_advanced_trigger_7 ; NONE ; String ; ; sld_advanced_trigger_8 ; NONE ; String ; ; sld_advanced_trigger_9 ; NONE ; String ; ; sld_advanced_trigger_10 ; NONE ; String ; ; sld_inversion_mask_length ; 107 ; Untyped ; ; sld_inversion_mask ; 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Untyped ; ; sld_power_up_trigger ; 0 ; Untyped ; +-----------------------------+-------------------------------------------------------------------------------------------------------------+----------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9ui2:auto_generated|altsyncram_k4l1:altsyncram1 ; +-------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; PORT_A_ADDRESS_WIDTH ; 1 ; Untyped ; ; PORT_A_BYTE_ENABLE_MASK_WIDTH ; 1 ; Untyped ; ; PORT_A_DATA_WIDTH ; 1 ; Untyped ; ; PORT_B_ADDRESS_WIDTH ; 1 ; Untyped ; ; PORT_B_BYTE_ENABLE_MASK_WIDTH ; 1 ; Untyped ; ; PORT_B_DATA_WIDTH ; 1 ; Untyped ; +-------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst ; +--------------------------+----------------------------------+-----------------+ ; Parameter Name ; Value ; Type ; +--------------------------+----------------------------------+-----------------+ ; sld_hub_ip_version ; 1 ; Untyped ; ; sld_hub_ip_minor_version ; 3 ; Untyped ; ; sld_common_ip_version ; 0 ; Untyped ; ; device_family ; Cyclone II ; Untyped ; ; n_nodes ; 1 ; Untyped ; ; n_sel_bits ; 1 ; Untyped ; ; n_node_ir_bits ; 8 ; Untyped ; ; node_info ; 00101000000000000110111000000000 ; Unsigned Binary ; ; compilation_mode ; 0 ; Untyped ; +--------------------------+----------------------------------+-----------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; SignalTap II Logic Analyzer Settings ; +----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+--------------------------+----------------------------+-------------------------+ ; Instance Index ; Instance Name ; Trigger Input Width ; Data Input Width ; Sample Depth ; Trigger Levels ; Advanced Trigger Levels ; Trigger In Used ; Trigger Out Used ; Power-Up Trigger Enabled ; Incremental Trigger Inputs ; Incremental Data Inputs ; +----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+--------------------------+----------------------------+-------------------------+ ; 0 ; auto_signaltap_0 ; 29 ; 29 ; 2048 ; 1 ; 0 ; yes ; no ; no ; 0 ; 0 ; +----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+--------------------------+----------------------------+-------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis INI Usage ; +----------------------+--------------------------------------------------------------------------------------------------------------------+ ; Option ; Usage ; +----------------------+--------------------------------------------------------------------------------------------------------------------+ ; Initialization file: ; c:/altera/71/quartus/bin/quartus.ini ; ; dev_password ; e81f0e65b8afc1da24522b894c886f598ff5e3fafae3453dd1029e508011004342234235215526025211557545361520042000410042555455 ; +----------------------+--------------------------------------------------------------------------------------------------------------------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version Info: Processing started: Thu Aug 30 15:50:47 2007 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE1_synthesizer -c DE1_synthesizer Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/DE1_synthesizer.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: DE1_synthesizer Info: Elaborating entity "DE1_synthesizer" for the top level hierarchy Warning (10230): Verilog HDL assignment warning at DE1_synthesizer.v(173): truncated value with size 32 to match size of target (8) Warning (10230): Verilog HDL assignment warning at DE1_synthesizer.v(221): truncated value with size 32 to match size of target (10) Warning (10230): Verilog HDL assignment warning at DE1_synthesizer.v(269): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at DE1_synthesizer.v(270): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at DE1_synthesizer.v(271): truncated value with size 32 to match size of target (4) Warning (10034): Output port "LEDR[5]" at DE1_synthesizer.v(80) has no driver Warning (10034): Output port "LEDR[4]" at DE1_synthesizer.v(80) has no driver Warning (10034): Output port "LEDR[3]" at DE1_synthesizer.v(80) has no driver Warning (10034): Output port "LEDR[2]" at DE1_synthesizer.v(80) has no driver Warning (10034): Output port "LEDR[1]" at DE1_synthesizer.v(80) has no driver Warning (10034): Output port "UART_TXD" at DE1_synthesizer.v(82) has no driver Warning (10034): Output port "DRAM_ADDR[11]" at DE1_synthesizer.v(86) has no driver Warning (10034): Output port "DRAM_ADDR[10]" at DE1_synthesizer.v(86) has no driver Warning (10034): Output port "DRAM_ADDR[9]" at DE1_synthesizer.v(86) has no driver Warning (10034): Output port "DRAM_ADDR[8]" at DE1_synthesizer.v(86) has no driver Warning (10034): Output port "DRAM_ADDR[7]" at DE1_synthesizer.v(86) has no driver Warning (10034): Output port "DRAM_ADDR[6]" at DE1_synthesizer.v(86) has no driver Warning (10034): Output port "DRAM_ADDR[5]" at DE1_synthesizer.v(86) has no driver Warning (10034): Output port "DRAM_ADDR[4]" at DE1_synthesizer.v(86) has no driver Warning (10034): Output port "DRAM_ADDR[3]" at DE1_synthesizer.v(86) has no driver Warning (10034): Output port "DRAM_ADDR[2]" at DE1_synthesizer.v(86) has no driver Warning (10034): Output port "DRAM_ADDR[1]" at DE1_synthesizer.v(86) has no driver Warning (10034): Output port "DRAM_ADDR[0]" at DE1_synthesizer.v(86) has no driver Warning (10034): Output port "DRAM_LDQM" at DE1_synthesizer.v(87) has no driver Warning (10034): Output port "DRAM_UDQM" at DE1_synthesizer.v(88) has no driver Warning (10034): Output port "DRAM_WE_N" at DE1_synthesizer.v(89) has no driver Warning (10034): Output port "DRAM_CAS_N" at DE1_synthesizer.v(90) has no driver Warning (10034): Output port "DRAM_RAS_N" at DE1_synthesizer.v(91) has no driver Warning (10034): Output port "DRAM_CS_N" at DE1_synthesizer.v(92) has no driver Warning (10034): Output port "DRAM_BA_0" at DE1_synthesizer.v(93) has no driver Warning (10034): Output port "DRAM_BA_1" at DE1_synthesizer.v(94) has no driver Warning (10034): Output port "DRAM_CLK" at DE1_synthesizer.v(95) has no driver Warning (10034): Output port "DRAM_CKE" at DE1_synthesizer.v(96) has no driver Warning (10034): Output port "FL_ADDR[21]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[20]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[19]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[18]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[17]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[16]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[15]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[14]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[13]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[12]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[11]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[10]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[9]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[8]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[7]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[6]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[5]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[4]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[3]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[2]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[1]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_ADDR[0]" at DE1_synthesizer.v(99) has no driver Warning (10034): Output port "FL_WE_N" at DE1_synthesizer.v(100) has no driver Warning (10034): Output port "FL_RST_N" at DE1_synthesizer.v(101) has no driver Warning (10034): Output port "FL_OE_N" at DE1_synthesizer.v(102) has no driver Warning (10034): Output port "FL_CE_N" at DE1_synthesizer.v(103) has no driver Warning (10034): Output port "SRAM_ADDR[17]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[16]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[15]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[14]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[13]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[12]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[11]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[10]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[9]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[8]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[7]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[6]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[5]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[4]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[3]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[2]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[1]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_ADDR[0]" at DE1_synthesizer.v(106) has no driver Warning (10034): Output port "SRAM_UB_N" at DE1_synthesizer.v(107) has no driver Warning (10034): Output port "SRAM_LB_N" at DE1_synthesizer.v(108) has no driver Warning (10034): Output port "SRAM_WE_N" at DE1_synthesizer.v(109) has no driver Warning (10034): Output port "SRAM_CE_N" at DE1_synthesizer.v(110) has no driver Warning (10034): Output port "SRAM_OE_N" at DE1_synthesizer.v(111) has no driver Warning (10034): Output port "SD_CLK" at DE1_synthesizer.v(116) has no driver Warning (10034): Output port "TDO" at DE1_synthesizer.v(127) has no driver Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/SEG7_LUT_4.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: SEG7_LUT_4 Info: Elaborating entity "SEG7_LUT_4" for hierarchy "SEG7_LUT_4:u0" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/SEG7_LUT.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: SEG7_LUT Info: Elaborating entity "SEG7_LUT" for hierarchy "SEG7_LUT_4:u0|SEG7_LUT:u0" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/VGA_Audio_PLL.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: VGA_Audio_PLL Info: Elaborating entity "VGA_Audio_PLL" for hierarchy "VGA_Audio_PLL:u1" Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/altpll.tdf Info: Found entity 1: altpll Info: Elaborating entity "altpll" for hierarchy "VGA_Audio_PLL:u1|altpll:altpll_component" Info: Elaborated megafunction instantiation "VGA_Audio_PLL:u1|altpll:altpll_component" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/I2C_AV_Config.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: I2C_AV_Config Info: Elaborating entity "I2C_AV_Config" for hierarchy "I2C_AV_Config:u7" Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(55): truncated value with size 32 to match size of target (16) Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(104): truncated value with size 32 to match size of target (4) Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/I2C_Controller.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: I2C_Controller Info: Elaborating entity "I2C_Controller" for hierarchy "I2C_AV_Config:u7|I2C_Controller:u0" Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(78): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(77): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(90): truncated value with size 32 to match size of target (6) Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/demo_sound1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: demo_sound1 Info: Elaborating entity "demo_sound1" for hierarchy "demo_sound1:dd1" Warning (10230): Verilog HDL assignment warning at demo_sound1.v(26): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at demo_sound1.v(27): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at demo_sound1.v(28): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at demo_sound1.v(29): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at demo_sound1.v(30): truncated value with size 32 to match size of target (16) Warning (10230): Verilog HDL assignment warning at demo_sound1.v(50): truncated value with size 32 to match size of target (16) Warning (10230): Verilog HDL assignment warning at demo_sound1.v(131): truncated value with size 32 to match size of target (16) Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/demo_sound2.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: demo_sound2 Info: Elaborating entity "demo_sound2" for hierarchy "demo_sound2:dd2" Warning (10230): Verilog HDL assignment warning at demo_sound2.v(26): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at demo_sound2.v(27): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at demo_sound2.v(28): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at demo_sound2.v(29): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at demo_sound2.v(30): truncated value with size 32 to match size of target (16) Warning (10230): Verilog HDL assignment warning at demo_sound2.v(50): truncated value with size 32 to match size of target (16) Warning (10230): Verilog HDL assignment warning at demo_sound2.v(144): truncated value with size 32 to match size of target (16) Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/PS2_KEYBOARD.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: PS2_KEYBOARD Info: Elaborating entity "PS2_KEYBOARD" for hierarchy "PS2_KEYBOARD:keyboard" Warning (10230): Verilog HDL assignment warning at PS2_KEYBOARD.v(32): truncated value with size 32 to match size of target (11) Warning (10230): Verilog HDL assignment warning at PS2_KEYBOARD.v(38): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at PS2_KEYBOARD.v(44): truncated value with size 32 to match size of target (8) Warning (10230): Verilog HDL assignment warning at PS2_KEYBOARD.v(63): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at PS2_KEYBOARD.v(80): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at PS2_KEYBOARD.v(104): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at PS2_KEYBOARD.v(106): truncated value with size 10 to match size of target (8) Warning (10230): Verilog HDL assignment warning at PS2_KEYBOARD.v(126): truncated value with size 10 to match size of target (8) Warning (10230): Verilog HDL assignment warning at PS2_KEYBOARD.v(129): truncated value with size 10 to match size of target (8) Warning (10030): Net "keycode_o[9]" at PS2_KEYBOARD.v(49) has no driver or initial value, using a default initial value '0' Warning (10030): Net "keycode_o[8]" at PS2_KEYBOARD.v(49) has no driver or initial value, using a default initial value '0' Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/staff.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: staff Info: Elaborating entity "staff" for hierarchy "staff:st1" Warning (10230): Verilog HDL assignment warning at staff.v(23): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(24): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(25): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(26): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(51): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(52): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(53): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(54): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(55): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(56): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(57): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(58): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(59): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(60): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(61): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(68): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(69): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(70): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(71): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(72): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(73): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(74): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(75): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(76): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(78): truncated value with size 32 to match size of target (16) Warning (10230): Verilog HDL assignment warning at staff.v(103): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(104): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(105): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(106): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(107): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(108): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(109): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(110): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(111): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(112): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(113): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(120): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(121): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(122): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(123): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(124): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(125): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(126): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(127): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(128): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(130): truncated value with size 32 to match size of target (16) Warning (10230): Verilog HDL assignment warning at staff.v(155): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(156): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(157): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(158): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(159): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(160): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(161): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(162): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(163): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(164): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(165): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(172): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(173): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(174): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(175): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(176): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(177): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(178): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(179): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(180): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(182): truncated value with size 32 to match size of target (16) Warning (10230): Verilog HDL assignment warning at staff.v(207): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(208): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(209): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(210): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(211): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(212): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(213): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(214): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(215): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(216): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(217): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(224): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(225): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(226): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(227): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(228): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(229): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(230): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(231): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(232): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at staff.v(234): truncated value with size 32 to match size of target (16) Warning (10230): Verilog HDL assignment warning at staff.v(293): truncated value with size 32 to match size of target (12) Warning (10230): Verilog HDL assignment warning at staff.v(295): truncated value with size 32 to match size of target (12) Warning (10230): Verilog HDL assignment warning at staff.v(315): truncated value with size 32 to match size of target (12) Warning (10230): Verilog HDL assignment warning at staff.v(373): truncated value with size 32 to match size of target (12) Warning (10230): Verilog HDL assignment warning at staff.v(375): truncated value with size 32 to match size of target (12) Warning (10230): Verilog HDL assignment warning at staff.v(391): truncated value with size 32 to match size of target (12) Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/vga_time_generator.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: vga_time_generator Info: Elaborating entity "vga_time_generator" for hierarchy "staff:st1|vga_time_generator:vga0" Warning (10230): Verilog HDL assignment warning at vga_time_generator.v(32): truncated value with size 32 to match size of target (12) Warning (10763): Verilog HDL warning at vga_time_generator.v(37): overlapping case item expressions are non-constant or contain don't care bits - unable to check case statement for completeness Warning (10230): Verilog HDL assignment warning at vga_time_generator.v(54): truncated value with size 32 to match size of target (12) Warning (10763): Verilog HDL warning at vga_time_generator.v(59): overlapping case item expressions are non-constant or contain don't care bits - unable to check case statement for completeness Warning (10230): Verilog HDL assignment warning at vga_time_generator.v(74): truncated value with size 32 to match size of target (12) Warning (10230): Verilog HDL assignment warning at vga_time_generator.v(79): truncated value with size 32 to match size of target (12) Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/bar_white.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: bar_white Info: Elaborating entity "bar_white" for hierarchy "staff:st1|bar_white:bar1" Warning (10230): Verilog HDL assignment warning at bar_white.v(22): truncated value with size 32 to match size of target (12) Warning (10230): Verilog HDL assignment warning at bar_white.v(23): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_white.v(24): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_white.v(25): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_white.v(26): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_white.v(27): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_white.v(28): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_white.v(29): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_white.v(30): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_white.v(31): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_white.v(32): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_white.v(33): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_white.v(34): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_white.v(35): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_white.v(36): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_white.v(37): truncated value with size 32 to match size of target (1) Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/bar_big.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: bar_big Info: Elaborating entity "bar_big" for hierarchy "staff:st1|bar_big:b0" Warning (10230): Verilog HDL assignment warning at bar_big.v(12): truncated value with size 32 to match size of target (1) Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/bar_blank.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: bar_blank Info: Elaborating entity "bar_blank" for hierarchy "staff:st1|bar_blank:bar_blank1" Warning (10230): Verilog HDL assignment warning at bar_blank.v(17): truncated value with size 32 to match size of target (12) Warning (10230): Verilog HDL assignment warning at bar_blank.v(19): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_blank.v(20): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_blank.v(21): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_blank.v(22): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_blank.v(23): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_blank.v(24): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_blank.v(25): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_blank.v(26): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_blank.v(27): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_blank.v(28): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at bar_blank.v(29): truncated value with size 32 to match size of target (1) Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/adio_codec.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: adio_codec Info: Elaborating entity "adio_codec" for hierarchy "adio_codec:ad1" Warning (10230): Verilog HDL assignment warning at adio_codec.v(63): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at adio_codec.v(88): truncated value with size 32 to match size of target (9) Warning (10230): Verilog HDL assignment warning at adio_codec.v(96): truncated value with size 32 to match size of target (8) Warning (10230): Verilog HDL assignment warning at adio_codec.v(104): truncated value with size 32 to match size of target (7) Warning (10230): Verilog HDL assignment warning at adio_codec.v(117): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at adio_codec.v(144): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at adio_codec.v(146): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at adio_codec.v(187): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at adio_codec.v(188): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at adio_codec.v(189): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at adio_codec.v(190): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at adio_codec.v(191): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at adio_codec.v(192): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at adio_codec.v(193): truncated value with size 32 to match size of target (6) Warning (10230): Verilog HDL assignment warning at adio_codec.v(194): truncated value with size 32 to match size of target (6) Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(53): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(54): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(55): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(56): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(57): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(58): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(59): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(60): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(61): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(62): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(63): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(64): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(65): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(66): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(67): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(68): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(69): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(70): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(71): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(72): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(73): truncated literal to match 16 bits Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/wave_gen_string.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: wave_gen_string Info: Elaborating entity "wave_gen_string" for hierarchy "adio_codec:ad1|wave_gen_string:r1" Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(40): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(41): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(42): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(43): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(44): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(45): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(46): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(47): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(48): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(49): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(50): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(51): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(52): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(53): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(54): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(55): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(56): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(57): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(58): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(59): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(60): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(61): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(62): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(63): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(64): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(65): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(66): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(67): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(68): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(69): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(70): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(71): truncated literal to match 16 bits Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(72): truncated literal to match 16 bits Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/wave_gen_brass.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: wave_gen_brass Info: Elaborating entity "wave_gen_brass" for hierarchy "adio_codec:ad1|wave_gen_brass:s1" Warning: Port "org_x" on the entity instantiation of "b2" is connected to a signal of width 32. The formal width of the signal in the module is 12. Extra bits will be ignored. Warning: Port "org_x" on the entity instantiation of "b0" is connected to a signal of width 32. The formal width of the signal in the module is 12. Extra bits will be ignored. Warning: Port "h_bporch" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12. Extra bits will be ignored. Warning: Port "h_disp" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12. Extra bits will be ignored. Warning: Port "h_fporch" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12. Extra bits will be ignored. Warning: Port "h_sync" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12. Extra bits will be ignored. Warning: Port "v_bporch" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12. Extra bits will be ignored. Warning: Port "v_disp" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12. Extra bits will be ignored. Warning: Port "v_fporch" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12. Extra bits will be ignored. Warning: Port "v_sync" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12. Extra bits will be ignored. Warning: Port "inclk0" on the entity instantiation of "u1" is connected to a signal of width 2. The formal width of the signal in the module is 1. Extra bits will be ignored. Info: Found 5 design units, including 2 entities, in source file c:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd Info: Found design unit 1: sld_signaltap_pack Info: Found design unit 2: sld_signaltap-rtl Info: Found design unit 3: sld_signaltap_impl-rtl Info: Found entity 1: sld_signaltap Info: Found entity 2: sld_signaltap_impl Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Found 14 design units, including 7 entities, in source file c:/altera/71/quartus/libraries/megafunctions/sld_ela_control.vhd Info: Found design unit 1: sld_ela_control-rtl Info: Found design unit 2: sld_ela_level_seq_mgr-rtl Info: Found design unit 3: sld_ela_state_machine-rtl Info: Found design unit 4: sld_ela_seg_state_machine-rtl Info: Found design unit 5: sld_ela_post_trigger_counter-rtl Info: Found design unit 6: sld_ela_segment_mgr-rtl Info: Found design unit 7: sld_ela_basic_multi_level_trigger-rtl Info: Found entity 1: sld_ela_control Info: Found entity 2: sld_ela_level_seq_mgr Info: Found entity 3: sld_ela_state_machine Info: Found entity 4: sld_ela_seg_state_machine Info: Found entity 5: sld_ela_post_trigger_counter Info: Found entity 6: sld_ela_segment_mgr Info: Found entity 7: sld_ela_basic_multi_level_trigger Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf Info: Found entity 1: lpm_shiftreg Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Found 4 design units, including 2 entities, in source file c:/altera/71/quartus/libraries/megafunctions/sld_mbpmg.vhd Info: Found design unit 1: sld_mbpmg-rtl Info: Found design unit 2: sld_sbpmg-rtl Info: Found entity 1: sld_mbpmg Info: Found entity 2: sld_sbpmg Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_mbpmg:\trigger_in_trigger_module_enabled_gen:trigger_in_match", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_state_machine:sm1", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf Info: Found entity 1: lpm_counter Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1|lpm_counter:post_trigger_counter", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/cntr_3hj.tdf Info: Found entity 1: cntr_3hj Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/cntr_2qi.tdf Info: Found entity 1: cntr_2qi Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/lpm_compare.tdf Info: Found entity 1: lpm_compare Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/cmpr_2vh.tdf Info: Found entity 1: cmpr_2vh Info: Found 4 design units, including 2 entities, in source file c:/altera/71/quartus/libraries/megafunctions/sld_acquisition_buffer.vhd Info: Found design unit 1: sld_acquisition_buffer-rtl Info: Found design unit 2: sld_offload_buffer_mgr-rtl Info: Found entity 1: sld_acquisition_buffer Info: Found entity 2: sld_offload_buffer_mgr Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/cntr_bmk.tdf Info: Found entity 1: cntr_bmk Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf Info: Found entity 1: lpm_ff Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_ff:\gen_non_zero_sample_depth:trigger_address_register", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Warning: Entity "altsyncram" obtained from "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" instead of from Quartus II megafunction library Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf Info: Found entity 1: altsyncram Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/altsyncram_9ui2.tdf Info: Found entity 1: altsyncram_9ui2 Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/altsyncram_k4l1.tdf Info: Found entity 1: altsyncram_k4l1 Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/cntr_5nh.tdf Info: Found entity 1: cntr_5nh Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/cntr_1gi.tdf Info: Found entity 1: cntr_1gi Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Found 2 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd Info: Found design unit 1: sld_rom_sr-INFO_REG Info: Found entity 1: sld_rom_sr Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0" Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter: Info: Parameter "SLD_NODE_INFO" = "671116800" Info: Parameter "SLD_POWER_UP_TRIGGER" = "0" Info: Parameter "SLD_TRIGGER_LEVEL" = "1" Info: Parameter "SLD_SAMPLE_DEPTH" = "2048" Info: Parameter "SLD_MEM_ADDRESS_BITS" = "11" Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "1" Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1," Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1" Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0" Info: Parameter "SLD_DATA_BITS" = "29" Info: Parameter "SLD_TRIGGER_BITS" = "29" Info: Parameter "SLD_INVERSION_MASK" = "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "107" Info: Parameter "SLD_NODE_CRC_LOWORD" = "43267" Info: Parameter "SLD_NODE_CRC_HIWORD" = "42047" Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "5" Info: Analysis and Synthesis generated SignalTap II or debug node instance "auto_signaltap_0" Info: Source node "|DE1_synthesizer|PS2_CLK" connects to port "acq_trigger_in[0]" Info: Source node "|DE1_synthesizer|PS2_CLK" connects to port "acq_data_in[0]" Info: Source node "|DE1_synthesizer|PS2_DAT" connects to port "acq_trigger_in[1]" Info: Source node "|DE1_synthesizer|PS2_DAT" connects to port "acq_data_in[1]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|ps2_dat" connects to port "trigger_in" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[0]" connects to port "acq_trigger_in[2]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[0]" connects to port "acq_data_in[2]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[1]" connects to port "acq_trigger_in[3]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[1]" connects to port "acq_data_in[3]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[2]" connects to port "acq_trigger_in[4]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[2]" connects to port "acq_data_in[4]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[3]" connects to port "acq_trigger_in[5]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[3]" connects to port "acq_data_in[5]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[4]" connects to port "acq_trigger_in[6]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[4]" connects to port "acq_data_in[6]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[5]" connects to port "acq_trigger_in[7]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[5]" connects to port "acq_data_in[7]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[6]" connects to port "acq_trigger_in[8]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[6]" connects to port "acq_data_in[8]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[7]" connects to port "acq_trigger_in[9]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|revcnt[7]" connects to port "acq_data_in[9]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[0]" connects to port "acq_trigger_in[10]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[0]" connects to port "acq_data_in[10]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[1]" connects to port "acq_trigger_in[11]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[1]" connects to port "acq_data_in[11]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[2]" connects to port "acq_trigger_in[12]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[2]" connects to port "acq_data_in[12]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[3]" connects to port "acq_trigger_in[13]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[3]" connects to port "acq_data_in[13]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[4]" connects to port "acq_trigger_in[14]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[4]" connects to port "acq_data_in[14]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[5]" connects to port "acq_trigger_in[15]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[5]" connects to port "acq_data_in[15]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[6]" connects to port "acq_trigger_in[16]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[6]" connects to port "acq_data_in[16]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[7]" connects to port "acq_trigger_in[17]" Info: Source node "|DE1_synthesizer|PS2_KEYBOARD:keyboard|scandata[7]" connects to port "acq_data_in[17]" Info: Source node "|DE1_synthesizer|VGA_CLK_o[4]" connects to port "acq_clk" Info: Source node "|DE1_synthesizer|ps_clk" connects to port "acq_trigger_in[18]" Info: Source node "|DE1_synthesizer|ps_clk" connects to port "acq_data_in[18]" Info: Source node "|DE1_synthesizer|ps_cnt[0]" connects to port "acq_trigger_in[19]" Info: Source node "|DE1_synthesizer|ps_cnt[0]" connects to port "acq_data_in[19]" Info: Source node "|DE1_synthesizer|ps_cnt[1]" connects to port "acq_trigger_in[20]" Info: Source node "|DE1_synthesizer|ps_cnt[1]" connects to port "acq_data_in[20]" Info: Source node "|DE1_synthesizer|ps_cnt[2]" connects to port "acq_trigger_in[21]" Info: Source node "|DE1_synthesizer|ps_cnt[2]" connects to port "acq_data_in[21]" Info: Source node "|DE1_synthesizer|ps_cnt[3]" connects to port "acq_trigger_in[22]" Info: Source node "|DE1_synthesizer|ps_cnt[3]" connects to port "acq_data_in[22]" Info: Source node "|DE1_synthesizer|ps_cnt[4]" connects to port "acq_trigger_in[23]" Info: Source node "|DE1_synthesizer|ps_cnt[4]" connects to port "acq_data_in[23]" Info: Source node "|DE1_synthesizer|ps_cnt[5]" connects to port "acq_trigger_in[24]" Info: Source node "|DE1_synthesizer|ps_cnt[5]" connects to port "acq_data_in[24]" Info: Source node "|DE1_synthesizer|ps_cnt[6]" connects to port "acq_trigger_in[25]" Info: Source node "|DE1_synthesizer|ps_cnt[6]" connects to port "acq_data_in[25]" Info: Source node "|DE1_synthesizer|ps_cnt[7]" connects to port "acq_trigger_in[26]" Info: Source node "|DE1_synthesizer|ps_cnt[7]" connects to port "acq_data_in[26]" Info: Source node "|DE1_synthesizer|ps_cnt[8]" connects to port "acq_trigger_in[27]" Info: Source node "|DE1_synthesizer|ps_cnt[8]" connects to port "acq_data_in[27]" Info: Source node "|DE1_synthesizer|ps_cnt[9]" connects to port "acq_trigger_in[28]" Info: Source node "|DE1_synthesizer|ps_cnt[9]" connects to port "acq_data_in[28]" Info: Found 6 design units, including 2 entities, in source file c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd Info: Found design unit 1: HUB_PACK Info: Found design unit 2: JTAG_PACK Info: Found design unit 3: sld_hub-rtl Info: Found design unit 4: sld_jtag_state_machine-rtl Info: Found entity 1: sld_hub Info: Found entity 2: sld_jtag_state_machine Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst" Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "1" Info: Parameter "N_SEL_BITS" = "1" Info: Parameter "N_NODE_IR_BITS" = "8" Info: Parameter "NODE_INFO" = "00101000000000000110111000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Cyclone II" Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "1" Info: Parameter "N_SEL_BITS" = "1" Info: Parameter "N_NODE_IR_BITS" = "8" Info: Parameter "NODE_INFO" = "00101000000000000110111000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Cyclone II" Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/lpm_decode.tdf Info: Found entity 1: lpm_decode Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|lpm_decode:instruction_decoder", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "1" Info: Parameter "N_SEL_BITS" = "1" Info: Parameter "N_NODE_IR_BITS" = "8" Info: Parameter "NODE_INFO" = "00101000000000000110111000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Cyclone II" Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/db/decode_aoi.tdf Info: Found entity 1: decode_aoi Info: Found 2 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd Info: Found design unit 1: sld_dffex-DFFEX Info: Found entity 1: sld_dffex Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:RESET", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "1" Info: Parameter "N_SEL_BITS" = "1" Info: Parameter "N_NODE_IR_BITS" = "8" Info: Parameter "NODE_INFO" = "00101000000000000110111000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Cyclone II" Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:IRSR", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "1" Info: Parameter "N_SEL_BITS" = "1" Info: Parameter "N_NODE_IR_BITS" = "8" Info: Parameter "NODE_INFO" = "00101000000000000110111000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Cyclone II" Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "1" Info: Parameter "N_SEL_BITS" = "1" Info: Parameter "N_NODE_IR_BITS" = "8" Info: Parameter "NODE_INFO" = "00101000000000000110111000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Cyclone II" Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "1" Info: Parameter "N_SEL_BITS" = "1" Info: Parameter "N_NODE_IR_BITS" = "8" Info: Parameter "NODE_INFO" = "00101000000000000110111000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Cyclone II" Warning: Reduced register "adio_codec:ad1|ramp4[0]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[15]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[14]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[13]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[12]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[11]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[10]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[9]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[8]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[7]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[6]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[5]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[4]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[3]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[2]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[1]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp3[0]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp4[15]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp4[14]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp4[13]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp4[12]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp4[11]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp4[10]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp4[9]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp4[8]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp4[7]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp4[6]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp4[5]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp4[4]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp4[3]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp4[2]" with stuck clear port to stuck value GND Warning: Reduced register "adio_codec:ad1|ramp4[1]" with stuck clear port to stuck value GND Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[23]" with stuck data_in port to stuck value GND Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[22]" with stuck data_in port to stuck value GND Info: Power-up level of register "I2C_AV_Config:u7|mI2C_DATA[21]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[21]" with stuck data_in port to stuck value VCC Info: Power-up level of register "I2C_AV_Config:u7|mI2C_DATA[20]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[20]" with stuck data_in port to stuck value VCC Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[19]" with stuck data_in port to stuck value GND Info: Power-up level of register "I2C_AV_Config:u7|mI2C_DATA[18]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[18]" with stuck data_in port to stuck value VCC Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[17]" with stuck data_in port to stuck value GND Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[16]" with stuck data_in port to stuck value GND Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[15]" with stuck data_in port to stuck value GND Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[14]" with stuck data_in port to stuck value GND Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[13]" with stuck data_in port to stuck value GND Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[8]" with stuck data_in port to stuck value GND Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[23]" with stuck data_in port to stuck value GND Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[22]" with stuck data_in port to stuck value GND Info: Power-up level of register "I2C_AV_Config:u7|I2C_Controller:u0|SD[21]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[21]" with stuck data_in port to stuck value VCC Info: Power-up level of register "I2C_AV_Config:u7|I2C_Controller:u0|SD[20]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[20]" with stuck data_in port to stuck value VCC Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[19]" with stuck data_in port to stuck value GND Info: Power-up level of register "I2C_AV_Config:u7|I2C_Controller:u0|SD[18]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[18]" with stuck data_in port to stuck value VCC Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[17]" with stuck data_in port to stuck value GND Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[16]" with stuck data_in port to stuck value GND Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[15]" with stuck data_in port to stuck value GND Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[14]" with stuck data_in port to stuck value GND Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[13]" with stuck data_in port to stuck value GND Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[8]" with stuck data_in port to stuck value GND Info: Duplicate registers merged to single register Info: Duplicate register "demo_sound2:dd2|st[4]" merged to single register "demo_sound2:dd2|st[5]" Info: Duplicate register "demo_sound1:dd1|st[4]" merged to single register "demo_sound1:dd1|st[5]" Info: Duplicate register "I2C_AV_Config:u7|mI2C_DATA[5]" merged to single register "I2C_AV_Config:u7|mI2C_DATA[6]" Info: Duplicate register "I2C_AV_Config:u7|mI2C_DATA[3]" merged to single register "I2C_AV_Config:u7|mI2C_DATA[4]" Info: Duplicate register "I2C_AV_Config:u7|I2C_Controller:u0|SD[5]" merged to single register "I2C_AV_Config:u7|I2C_Controller:u0|SD[6]" Info: Duplicate register "I2C_AV_Config:u7|I2C_Controller:u0|SD[3]" merged to single register "I2C_AV_Config:u7|I2C_Controller:u0|SD[4]" Warning: Reduced register "demo_sound1:dd1|st[5]" with stuck data_in port to stuck value GND Warning: Reduced register "demo_sound1:dd1|st[3]" with stuck data_in port to stuck value GND Warning: Reduced register "demo_sound2:dd2|st[5]" with stuck data_in port to stuck value GND Warning: Reduced register "demo_sound2:dd2|st[3]" with stuck data_in port to stuck value GND Info: State machine "|DE1_synthesizer|I2C_AV_Config:u7|mSetup_ST" contains 3 states Info: Selected Auto state machine encoding method for state machine "|DE1_synthesizer|I2C_AV_Config:u7|mSetup_ST" Info: Encoding result for state machine "|DE1_synthesizer|I2C_AV_Config:u7|mSetup_ST" Info: Completed encoding using 3 state bits Info: Encoded state bit "I2C_AV_Config:u7|mSetup_ST.00" Info: Encoded state bit "I2C_AV_Config:u7|mSetup_ST.10" Info: Encoded state bit "I2C_AV_Config:u7|mSetup_ST.01" Info: State "|DE1_synthesizer|I2C_AV_Config:u7|mSetup_ST.00" uses code string "000" Info: State "|DE1_synthesizer|I2C_AV_Config:u7|mSetup_ST.01" uses code string "101" Info: State "|DE1_synthesizer|I2C_AV_Config:u7|mSetup_ST.10" uses code string "110" Info: Power-up level of register "DELAY[7]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "DELAY[7]" with stuck data_in port to stuck value VCC Warning: No clock transition on "DELAY[1]" register due to stuck clock or clock enable Warning: Reduced register "DELAY[1]" with stuck clock_enable port to stuck value GND Warning: No clock transition on "DELAY[0]" register due to stuck clock or clock enable Warning: Reduced register "DELAY[0]" with stuck clock_enable port to stuck value GND Warning: No clock transition on "DELAY[2]" register due to stuck clock or clock enable Warning: Reduced register "DELAY[2]" with stuck clock_enable port to stuck value GND Warning: No clock transition on "DELAY[3]" register due to stuck clock or clock enable Warning: Reduced register "DELAY[3]" with stuck clock_enable port to stuck value GND Warning: No clock transition on "DELAY[4]" register due to stuck clock or clock enable Warning: Reduced register "DELAY[4]" with stuck clock_enable port to stuck value GND Warning: No clock transition on "DELAY[5]" register due to stuck clock or clock enable Warning: Reduced register "DELAY[5]" with stuck clock_enable port to stuck value GND Warning: No clock transition on "DELAY[6]" register due to stuck clock or clock enable Warning: Reduced register "DELAY[6]" with stuck clock_enable port to stuck value GND Warning: The bidir "SD_DAT3" has no source; inserted an always disabled tri-state buffer. Warning: The bidir "SD_CMD" has no source; inserted an always disabled tri-state buffer. Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus AUD_BCLK~0 that it feeds Warning: Removed fan-in from always-disabled I/O buffer I2C_SDAT~4 to tri-state bus I2C_SDAT~1 Info: Duplicate registers merged to single register Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[28]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][28]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[0]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][0]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|trigger_in_reg" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[1]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_mbpmg:\trigger_in_trigger_module_enabled_gen:trigger_in_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|holdff" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][1]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[2]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[2]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][2]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[3]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[3]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][3]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[4]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[4]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][4]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[5]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[5]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][5]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[6]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[6]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][6]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[7]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[7]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][7]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[8]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[8]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][8]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[9]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[9]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][9]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[10]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][10]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[11]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[11]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][11]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[12]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[12]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][12]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[13]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[13]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][13]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[14]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[14]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][14]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[15]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[15]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][15]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[16]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[16]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][16]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[17]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[17]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][17]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[18]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[18]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][18]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[19]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[19]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][19]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[20]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[20]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][20]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[21]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[21]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][21]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[22]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[22]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][22]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[23]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[23]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][23]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[24]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[24]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][24]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[25]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[25]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][25]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[27]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[27]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][27]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1|holdff" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[26]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[26]" Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][26]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1|holdff" Info: Registers with preset signals will power-up high Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back Warning: Reduced register "adio_codec:ad1|BCK_DIV[3]" with stuck data_in port to stuck value GND Warning: TRI or OPNDRN buffers permanently enabled Warning: Node "AUD_BCLK~1" Warning: Output pins are stuck at VCC or GND Warning: Pin "HEX0[0]" stuck at GND Warning: Pin "HEX0[1]" stuck at GND Warning: Pin "HEX0[2]" stuck at GND Warning: Pin "HEX0[3]" stuck at GND Warning: Pin "HEX0[4]" stuck at VCC Warning: Pin "HEX0[5]" stuck at VCC Warning: Pin "HEX0[6]" stuck at GND Warning: Pin "HEX1[0]" stuck at VCC Warning: Pin "HEX1[1]" stuck at GND Warning: Pin "HEX1[2]" stuck at GND Warning: Pin "HEX1[3]" stuck at VCC Warning: Pin "HEX1[4]" stuck at VCC Warning: Pin "HEX1[5]" stuck at VCC Warning: Pin "HEX1[6]" stuck at VCC Warning: Pin "HEX2[0]" stuck at VCC Warning: Pin "HEX2[1]" stuck at GND Warning: Pin "HEX2[2]" stuck at GND Warning: Pin "HEX2[3]" stuck at VCC Warning: Pin "HEX2[4]" stuck at VCC Warning: Pin "HEX2[5]" stuck at VCC Warning: Pin "HEX2[6]" stuck at VCC Warning: Pin "HEX3[0]" stuck at VCC Warning: Pin "HEX3[1]" stuck at GND Warning: Pin "HEX3[2]" stuck at GND Warning: Pin "HEX3[3]" stuck at VCC Warning: Pin "HEX3[4]" stuck at VCC Warning: Pin "HEX3[5]" stuck at VCC Warning: Pin "HEX3[6]" stuck at VCC Warning: Pin "LEDR[1]" stuck at GND Warning: Pin "LEDR[2]" stuck at GND Warning: Pin "LEDR[3]" stuck at GND Warning: Pin "LEDR[4]" stuck at GND Warning: Pin "LEDR[5]" stuck at GND Warning: Pin "LEDR[8]" stuck at GND Warning: Pin "LEDR[9]" stuck at GND Warning: Pin "UART_TXD" stuck at GND Warning: Pin "DRAM_ADDR[0]" stuck at GND Warning: Pin "DRAM_ADDR[1]" stuck at GND Warning: Pin "DRAM_ADDR[2]" stuck at GND Warning: Pin "DRAM_ADDR[3]" stuck at GND Warning: Pin "DRAM_ADDR[4]" stuck at GND Warning: Pin "DRAM_ADDR[5]" stuck at GND Warning: Pin "DRAM_ADDR[6]" stuck at GND Warning: Pin "DRAM_ADDR[7]" stuck at GND Warning: Pin "DRAM_ADDR[8]" stuck at GND Warning: Pin "DRAM_ADDR[9]" stuck at GND Warning: Pin "DRAM_ADDR[10]" stuck at GND Warning: Pin "DRAM_ADDR[11]" stuck at GND Warning: Pin "DRAM_LDQM" stuck at GND Warning: Pin "DRAM_UDQM" stuck at GND Warning: Pin "DRAM_WE_N" stuck at GND Warning: Pin "DRAM_CAS_N" stuck at GND Warning: Pin "DRAM_RAS_N" stuck at GND Warning: Pin "DRAM_CS_N" stuck at GND Warning: Pin "DRAM_BA_0" stuck at GND Warning: Pin "DRAM_BA_1" stuck at GND Warning: Pin "DRAM_CLK" stuck at GND Warning: Pin "DRAM_CKE" stuck at GND Warning: Pin "FL_ADDR[0]" stuck at GND Warning: Pin "FL_ADDR[1]" stuck at GND Warning: Pin "FL_ADDR[2]" stuck at GND Warning: Pin "FL_ADDR[3]" stuck at GND Warning: Pin "FL_ADDR[4]" stuck at GND Warning: Pin "FL_ADDR[5]" stuck at GND Warning: Pin "FL_ADDR[6]" stuck at GND Warning: Pin "FL_ADDR[7]" stuck at GND Warning: Pin "FL_ADDR[8]" stuck at GND Warning: Pin "FL_ADDR[9]" stuck at GND Warning: Pin "FL_ADDR[10]" stuck at GND Warning: Pin "FL_ADDR[11]" stuck at GND Warning: Pin "FL_ADDR[12]" stuck at GND Warning: Pin "FL_ADDR[13]" stuck at GND Warning: Pin "FL_ADDR[14]" stuck at GND Warning: Pin "FL_ADDR[15]" stuck at GND Warning: Pin "FL_ADDR[16]" stuck at GND Warning: Pin "FL_ADDR[17]" stuck at GND Warning: Pin "FL_ADDR[18]" stuck at GND Warning: Pin "FL_ADDR[19]" stuck at GND Warning: Pin "FL_ADDR[20]" stuck at GND Warning: Pin "FL_ADDR[21]" stuck at GND Warning: Pin "FL_WE_N" stuck at GND Warning: Pin "FL_RST_N" stuck at GND Warning: Pin "FL_OE_N" stuck at GND Warning: Pin "FL_CE_N" stuck at GND Warning: Pin "SRAM_ADDR[0]" stuck at GND Warning: Pin "SRAM_ADDR[1]" stuck at GND Warning: Pin "SRAM_ADDR[2]" stuck at GND Warning: Pin "SRAM_ADDR[3]" stuck at GND Warning: Pin "SRAM_ADDR[4]" stuck at GND Warning: Pin "SRAM_ADDR[5]" stuck at GND Warning: Pin "SRAM_ADDR[6]" stuck at GND Warning: Pin "SRAM_ADDR[7]" stuck at GND Warning: Pin "SRAM_ADDR[8]" stuck at GND Warning: Pin "SRAM_ADDR[9]" stuck at GND Warning: Pin "SRAM_ADDR[10]" stuck at GND Warning: Pin "SRAM_ADDR[11]" stuck at GND Warning: Pin "SRAM_ADDR[12]" stuck at GND Warning: Pin "SRAM_ADDR[13]" stuck at GND Warning: Pin "SRAM_ADDR[14]" stuck at GND Warning: Pin "SRAM_ADDR[15]" stuck at GND Warning: Pin "SRAM_ADDR[16]" stuck at GND Warning: Pin "SRAM_ADDR[17]" stuck at GND Warning: Pin "SRAM_UB_N" stuck at GND Warning: Pin "SRAM_LB_N" stuck at GND Warning: Pin "SRAM_WE_N" stuck at GND Warning: Pin "SRAM_CE_N" stuck at GND Warning: Pin "SRAM_OE_N" stuck at GND Warning: Pin "SD_CLK" stuck at GND Warning: Pin "TDO" stuck at GND Info: 13 registers lost all their fanouts during netlist optimizations. The first 13 are displayed below. Info: Register "VGA_CLK_o[19]" lost all its fanouts during netlist optimizations. Info: Register "VGA_CLK_o[20]" lost all its fanouts during netlist optimizations. Info: Register "VGA_CLK_o[21]" lost all its fanouts during netlist optimizations. Info: Register "VGA_CLK_o[22]" lost all its fanouts during netlist optimizations. Info: Register "VGA_CLK_o[23]" lost all its fanouts during netlist optimizations. Info: Register "VGA_CLK_o[24]" lost all its fanouts during netlist optimizations. Info: Register "VGA_CLK_o[25]" lost all its fanouts during netlist optimizations. Info: Register "VGA_CLK_o[26]" lost all its fanouts during netlist optimizations. Info: Register "VGA_CLK_o[27]" lost all its fanouts during netlist optimizations. Info: Register "VGA_CLK_o[28]" lost all its fanouts during netlist optimizations. Info: Register "VGA_CLK_o[29]" lost all its fanouts during netlist optimizations. Info: Register "VGA_CLK_o[30]" lost all its fanouts during netlist optimizations. Info: Register "VGA_CLK_o[31]" lost all its fanouts during netlist optimizations. Warning: Design contains 15 input pin(s) that do not drive logic Warning: No output dependent on input pin "CLOCK_24[0]" Warning: No output dependent on input pin "CLOCK_24[1]" Warning: No output dependent on input pin "CLOCK_27[1]" Warning: No output dependent on input pin "EXT_CLOCK" Warning: No output dependent on input pin "SW[3]" Warning: No output dependent on input pin "SW[4]" Warning: No output dependent on input pin "SW[5]" Warning: No output dependent on input pin "SW[6]" Warning: No output dependent on input pin "SW[7]" Warning: No output dependent on input pin "SW[8]" Warning: No output dependent on input pin "UART_RXD" Warning: No output dependent on input pin "TDI" Warning: No output dependent on input pin "TCK" Warning: No output dependent on input pin "TCS" Warning: No output dependent on input pin "AUD_ADCDAT" Info: Implemented 2445 device resources after synthesis - the final resource count might be different Info: Implemented 29 input pins Info: Implemented 140 output pins Info: Implemented 118 bidirectional pins Info: Implemented 2127 logic cells Info: Implemented 29 RAM segments Info: Implemented 1 ClockLock PLLs Info: Generated suppressed messages file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/DE1_synthesizer.map.smsg Info: Quartus II Analysis & Synthesis was successful. 0 errors, 549 warnings Info: Allocated 203 megabytes of memory during processing Info: Processing ended: Thu Aug 30 15:51:58 2007 Info: Elapsed time: 00:01:11 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ The suppressed messages can be found in //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_synthesizer/DE1_synthesizer.map.smsg.