{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version " "Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 30 15:41:12 2007 " "Info: Processing started: Thu Aug 30 15:41:12 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off DE1_i2sound -c DE1_i2sound --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DE1_i2sound -c DE1_i2sound --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "KEY\[0\] " "Info: Assuming node \"KEY\[0\]\" is an undefined clock" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 133 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLOCK_50 " "Info: Assuming node \"CLOCK_50\" is an undefined clock" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 130 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "I2C_AV_Config:u1\|mI2C_CTRL_CLK " "Info: Detected ripple clock \"I2C_AV_Config:u1\|mI2C_CTRL_CLK\" as buffer" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 18 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u1\|mI2C_CTRL_CLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "PLL:u0\|altpll:altpll_component\|_clk0 " "Info: No valid register-to-register data paths exist for clock \"PLL:u0\|altpll:altpll_component\|_clk0\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CLOCK_27\[0\] " "Info: No valid register-to-register data paths exist for clock \"CLOCK_27\[0\]\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "KEY\[0\] register VOL\[2\] register VOL\[0\] 328.73 MHz 3.042 ns Internal " "Info: Clock \"KEY\[0\]\" has Internal fmax of 328.73 MHz between source register \"VOL\[2\]\" and destination register \"VOL\[0\]\" (period= 3.042 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.803 ns + Longest register register " "Info: + Longest register to register delay is 2.803 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VOL\[2\] 1 REG LCFF_X23_Y4_N21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X23_Y4_N21; Fanout = 5; REG Node = 'VOL\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VOL[2] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 242 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.322 ns) 0.722 ns VOL\[5\]~120 2 COMB LCCOMB_X23_Y4_N2 1 " "Info: 2: + IC(0.400 ns) + CELL(0.322 ns) = 0.722 ns; Loc. = LCCOMB_X23_Y4_N2; Fanout = 1; COMB Node = 'VOL\[5\]~120'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.722 ns" { VOL[2] VOL[5]~120 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 242 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.536 ns) + CELL(0.545 ns) 1.803 ns LessThan0~61 3 COMB LCCOMB_X23_Y4_N10 7 " "Info: 3: + IC(0.536 ns) + CELL(0.545 ns) = 1.803 ns; Loc. = LCCOMB_X23_Y4_N10; Fanout = 7; COMB Node = 'LessThan0~61'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.081 ns" { VOL[5]~120 LessThan0~61 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.260 ns) + CELL(0.740 ns) 2.803 ns VOL\[0\] 4 REG LCFF_X23_Y4_N17 4 " "Info: 4: + IC(0.260 ns) + CELL(0.740 ns) = 2.803 ns; Loc. = LCFF_X23_Y4_N17; Fanout = 4; REG Node = 'VOL\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { LessThan0~61 VOL[0] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 242 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.607 ns ( 57.33 % ) " "Info: Total cell delay = 1.607 ns ( 57.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.196 ns ( 42.67 % ) " "Info: Total interconnect delay = 1.196 ns ( 42.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.803 ns" { VOL[2] VOL[5]~120 LessThan0~61 VOL[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.803 ns" { VOL[2] VOL[5]~120 LessThan0~61 VOL[0] } { 0.000ns 0.400ns 0.536ns 0.260ns } { 0.000ns 0.322ns 0.545ns 0.740ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY\[0\] destination 3.759 ns + Shortest register " "Info: + Shortest clock path from clock \"KEY\[0\]\" to destination register is 3.759 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns KEY\[0\] 1 CLK PIN_R22 46 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R22; Fanout = 46; CLK Node = 'KEY\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.293 ns) + CELL(0.602 ns) 3.759 ns VOL\[0\] 2 REG LCFF_X23_Y4_N17 4 " "Info: 2: + IC(2.293 ns) + CELL(0.602 ns) = 3.759 ns; Loc. = LCFF_X23_Y4_N17; Fanout = 4; REG Node = 'VOL\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.895 ns" { KEY[0] VOL[0] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 242 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.466 ns ( 39.00 % ) " "Info: Total cell delay = 1.466 ns ( 39.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.293 ns ( 61.00 % ) " "Info: Total interconnect delay = 2.293 ns ( 61.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.759 ns" { KEY[0] VOL[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.759 ns" { KEY[0] KEY[0]~combout VOL[0] } { 0.000ns 0.000ns 2.293ns } { 0.000ns 0.864ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY\[0\] source 3.759 ns - Longest register " "Info: - Longest clock path from clock \"KEY\[0\]\" to source register is 3.759 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns KEY\[0\] 1 CLK PIN_R22 46 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R22; Fanout = 46; CLK Node = 'KEY\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.293 ns) + CELL(0.602 ns) 3.759 ns VOL\[2\] 2 REG LCFF_X23_Y4_N21 5 " "Info: 2: + IC(2.293 ns) + CELL(0.602 ns) = 3.759 ns; Loc. = LCFF_X23_Y4_N21; Fanout = 5; REG Node = 'VOL\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.895 ns" { KEY[0] VOL[2] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 242 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.466 ns ( 39.00 % ) " "Info: Total cell delay = 1.466 ns ( 39.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.293 ns ( 61.00 % ) " "Info: Total interconnect delay = 2.293 ns ( 61.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.759 ns" { KEY[0] VOL[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.759 ns" { KEY[0] KEY[0]~combout VOL[2] } { 0.000ns 0.000ns 2.293ns } { 0.000ns 0.864ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.759 ns" { KEY[0] VOL[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.759 ns" { KEY[0] KEY[0]~combout VOL[0] } { 0.000ns 0.000ns 2.293ns } { 0.000ns 0.864ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.759 ns" { KEY[0] VOL[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.759 ns" { KEY[0] KEY[0]~combout VOL[2] } { 0.000ns 0.000ns 2.293ns } { 0.000ns 0.864ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 242 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 242 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.803 ns" { VOL[2] VOL[5]~120 LessThan0~61 VOL[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.803 ns" { VOL[2] VOL[5]~120 LessThan0~61 VOL[0] } { 0.000ns 0.400ns 0.536ns 0.260ns } { 0.000ns 0.322ns 0.545ns 0.740ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.759 ns" { KEY[0] VOL[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.759 ns" { KEY[0] KEY[0]~combout VOL[0] } { 0.000ns 0.000ns 2.293ns } { 0.000ns 0.864ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.759 ns" { KEY[0] VOL[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.759 ns" { KEY[0] KEY[0]~combout VOL[2] } { 0.000ns 0.000ns 2.293ns } { 0.000ns 0.864ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[3\] register I2C_AV_Config:u1\|I2C_Controller:u0\|SDO 210.66 MHz 4.747 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 210.66 MHz between source register \"I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[3\]\" and destination register \"I2C_AV_Config:u1\|I2C_Controller:u0\|SDO\" (period= 4.747 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.512 ns + Longest register register " "Info: + Longest register to register delay is 4.512 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[3\] 1 REG LCFF_X21_Y5_N27 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y5_N27; Fanout = 20; REG Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.974 ns) + CELL(0.544 ns) 1.518 ns I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~503 2 COMB LCCOMB_X21_Y4_N2 1 " "Info: 2: + IC(0.974 ns) + CELL(0.544 ns) = 1.518 ns; Loc. = LCCOMB_X21_Y4_N2; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~503'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.518 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] I2C_AV_Config:u1|I2C_Controller:u0|Mux0~503 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.295 ns) + CELL(0.178 ns) 1.991 ns I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~504 3 COMB LCCOMB_X21_Y4_N14 1 " "Info: 3: + IC(0.295 ns) + CELL(0.178 ns) = 1.991 ns; Loc. = LCCOMB_X21_Y4_N14; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~504'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.473 ns" { I2C_AV_Config:u1|I2C_Controller:u0|Mux0~503 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~504 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.302 ns) + CELL(0.322 ns) 2.615 ns I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~505 4 COMB LCCOMB_X21_Y4_N24 1 " "Info: 4: + IC(0.302 ns) + CELL(0.322 ns) = 2.615 ns; Loc. = LCCOMB_X21_Y4_N24; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~505'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.624 ns" { I2C_AV_Config:u1|I2C_Controller:u0|Mux0~504 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~505 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.316 ns) + CELL(0.544 ns) 3.475 ns I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~508 5 COMB LCCOMB_X21_Y4_N26 1 " "Info: 5: + IC(0.316 ns) + CELL(0.544 ns) = 3.475 ns; Loc. = LCCOMB_X21_Y4_N26; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~508'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.860 ns" { I2C_AV_Config:u1|I2C_Controller:u0|Mux0~505 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~508 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.178 ns) 3.953 ns I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~512 6 COMB LCCOMB_X21_Y4_N10 1 " "Info: 6: + IC(0.300 ns) + CELL(0.178 ns) = 3.953 ns; Loc. = LCCOMB_X21_Y4_N10; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~512'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.478 ns" { I2C_AV_Config:u1|I2C_Controller:u0|Mux0~508 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~512 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.285 ns) + CELL(0.178 ns) 4.416 ns I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~513 7 COMB LCCOMB_X21_Y4_N30 1 " "Info: 7: + IC(0.285 ns) + CELL(0.178 ns) = 4.416 ns; Loc. = LCCOMB_X21_Y4_N30; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~513'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.463 ns" { I2C_AV_Config:u1|I2C_Controller:u0|Mux0~512 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~513 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 4.512 ns I2C_AV_Config:u1\|I2C_Controller:u0\|SDO 8 REG LCFF_X21_Y4_N31 4 " "Info: 8: + IC(0.000 ns) + CELL(0.096 ns) = 4.512 ns; Loc. = LCFF_X21_Y4_N31; Fanout = 4; REG Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|SDO'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { I2C_AV_Config:u1|I2C_Controller:u0|Mux0~513 I2C_AV_Config:u1|I2C_Controller:u0|SDO } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.040 ns ( 45.21 % ) " "Info: Total cell delay = 2.040 ns ( 45.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.472 ns ( 54.79 % ) " "Info: Total interconnect delay = 2.472 ns ( 54.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.512 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] I2C_AV_Config:u1|I2C_Controller:u0|Mux0~503 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~504 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~505 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~508 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~512 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~513 I2C_AV_Config:u1|I2C_Controller:u0|SDO } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.512 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] I2C_AV_Config:u1|I2C_Controller:u0|Mux0~503 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~504 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~505 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~508 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~512 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~513 I2C_AV_Config:u1|I2C_Controller:u0|SDO } { 0.000ns 0.974ns 0.295ns 0.302ns 0.316ns 0.300ns 0.285ns 0.000ns } { 0.000ns 0.544ns 0.178ns 0.322ns 0.544ns 0.178ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.004 ns - Smallest " "Info: - Smallest clock skew is 0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 6.763 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 6.763 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.879 ns) 3.547 ns I2C_AV_Config:u1\|mI2C_CTRL_CLK 2 REG LCFF_X22_Y5_N9 3 " "Info: 2: + IC(1.642 ns) + CELL(0.879 ns) = 3.547 ns; Loc. = LCFF_X22_Y5_N9; Fanout = 3; REG Node = 'I2C_AV_Config:u1\|mI2C_CTRL_CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.521 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.625 ns) + CELL(0.000 ns) 5.172 ns I2C_AV_Config:u1\|mI2C_CTRL_CLK~clkctrl 3 COMB CLKCTRL_G14 44 " "Info: 3: + IC(1.625 ns) + CELL(0.000 ns) = 5.172 ns; Loc. = CLKCTRL_G14; Fanout = 44; COMB Node = 'I2C_AV_Config:u1\|mI2C_CTRL_CLK~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.625 ns" { I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.989 ns) + CELL(0.602 ns) 6.763 ns I2C_AV_Config:u1\|I2C_Controller:u0\|SDO 4 REG LCFF_X21_Y4_N31 4 " "Info: 4: + IC(0.989 ns) + CELL(0.602 ns) = 6.763 ns; Loc. = LCFF_X21_Y4_N31; Fanout = 4; REG Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|SDO'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.591 ns" { I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SDO } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 37.07 % ) " "Info: Total cell delay = 2.507 ns ( 37.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.256 ns ( 62.93 % ) " "Info: Total interconnect delay = 4.256 ns ( 62.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.763 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SDO } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.763 ns" { CLOCK_50 CLOCK_50~combout I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SDO } { 0.000ns 0.000ns 1.642ns 1.625ns 0.989ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 6.759 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 6.759 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.879 ns) 3.547 ns I2C_AV_Config:u1\|mI2C_CTRL_CLK 2 REG LCFF_X22_Y5_N9 3 " "Info: 2: + IC(1.642 ns) + CELL(0.879 ns) = 3.547 ns; Loc. = LCFF_X22_Y5_N9; Fanout = 3; REG Node = 'I2C_AV_Config:u1\|mI2C_CTRL_CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.521 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.625 ns) + CELL(0.000 ns) 5.172 ns I2C_AV_Config:u1\|mI2C_CTRL_CLK~clkctrl 3 COMB CLKCTRL_G14 44 " "Info: 3: + IC(1.625 ns) + CELL(0.000 ns) = 5.172 ns; Loc. = CLKCTRL_G14; Fanout = 44; COMB Node = 'I2C_AV_Config:u1\|mI2C_CTRL_CLK~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.625 ns" { I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.985 ns) + CELL(0.602 ns) 6.759 ns I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[3\] 4 REG LCFF_X21_Y5_N27 20 " "Info: 4: + IC(0.985 ns) + CELL(0.602 ns) = 6.759 ns; Loc. = LCFF_X21_Y5_N27; Fanout = 20; REG Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 37.09 % ) " "Info: Total cell delay = 2.507 ns ( 37.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.252 ns ( 62.91 % ) " "Info: Total interconnect delay = 4.252 ns ( 62.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.759 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.759 ns" { CLOCK_50 CLOCK_50~combout I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] } { 0.000ns 0.000ns 1.642ns 1.625ns 0.985ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.763 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SDO } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.763 ns" { CLOCK_50 CLOCK_50~combout I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SDO } { 0.000ns 0.000ns 1.642ns 1.625ns 0.989ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.759 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.759 ns" { CLOCK_50 CLOCK_50~combout I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] } { 0.000ns 0.000ns 1.642ns 1.625ns 0.985ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 91 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 68 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.512 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] I2C_AV_Config:u1|I2C_Controller:u0|Mux0~503 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~504 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~505 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~508 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~512 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~513 I2C_AV_Config:u1|I2C_Controller:u0|SDO } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.512 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] I2C_AV_Config:u1|I2C_Controller:u0|Mux0~503 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~504 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~505 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~508 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~512 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~513 I2C_AV_Config:u1|I2C_Controller:u0|SDO } { 0.000ns 0.974ns 0.295ns 0.302ns 0.316ns 0.300ns 0.285ns 0.000ns } { 0.000ns 0.544ns 0.178ns 0.322ns 0.544ns 0.178ns 0.178ns 0.096ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.763 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SDO } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.763 ns" { CLOCK_50 CLOCK_50~combout I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SDO } { 0.000ns 0.000ns 1.642ns 1.625ns 0.989ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.759 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.759 ns" { CLOCK_50 CLOCK_50~combout I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3] } { 0.000ns 0.000ns 1.642ns 1.625ns 0.985ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "I2C_AV_Config:u1\|mI2C_DATA\[7\] KEY\[0\] CLOCK_50 2.965 ns register " "Info: tsu for register \"I2C_AV_Config:u1\|mI2C_DATA\[7\]\" (data pin = \"KEY\[0\]\", clock pin = \"CLOCK_50\") is 2.965 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.765 ns + Longest pin register " "Info: + Longest pin to register delay is 9.765 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns KEY\[0\] 1 CLK PIN_R22 46 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R22; Fanout = 46; CLK Node = 'KEY\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.834 ns) + CELL(0.513 ns) 8.211 ns I2C_AV_Config:u1\|mI2C_DATA\[12\]~699 2 COMB LCCOMB_X22_Y4_N20 12 " "Info: 2: + IC(6.834 ns) + CELL(0.513 ns) = 8.211 ns; Loc. = LCCOMB_X22_Y4_N20; Fanout = 12; COMB Node = 'I2C_AV_Config:u1\|mI2C_DATA\[12\]~699'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.347 ns" { KEY[0] I2C_AV_Config:u1|mI2C_DATA[12]~699 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.796 ns) + CELL(0.758 ns) 9.765 ns I2C_AV_Config:u1\|mI2C_DATA\[7\] 3 REG LCFF_X20_Y4_N25 1 " "Info: 3: + IC(0.796 ns) + CELL(0.758 ns) = 9.765 ns; Loc. = LCFF_X20_Y4_N25; Fanout = 1; REG Node = 'I2C_AV_Config:u1\|mI2C_DATA\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.554 ns" { I2C_AV_Config:u1|mI2C_DATA[12]~699 I2C_AV_Config:u1|mI2C_DATA[7] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.135 ns ( 21.86 % ) " "Info: Total cell delay = 2.135 ns ( 21.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.630 ns ( 78.14 % ) " "Info: Total interconnect delay = 7.630 ns ( 78.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.765 ns" { KEY[0] I2C_AV_Config:u1|mI2C_DATA[12]~699 I2C_AV_Config:u1|mI2C_DATA[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.765 ns" { KEY[0] KEY[0]~combout I2C_AV_Config:u1|mI2C_DATA[12]~699 I2C_AV_Config:u1|mI2C_DATA[7] } { 0.000ns 0.000ns 6.834ns 0.796ns } { 0.000ns 0.864ns 0.513ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 108 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 6.762 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination register is 6.762 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.879 ns) 3.547 ns I2C_AV_Config:u1\|mI2C_CTRL_CLK 2 REG LCFF_X22_Y5_N9 3 " "Info: 2: + IC(1.642 ns) + CELL(0.879 ns) = 3.547 ns; Loc. = LCFF_X22_Y5_N9; Fanout = 3; REG Node = 'I2C_AV_Config:u1\|mI2C_CTRL_CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.521 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.625 ns) + CELL(0.000 ns) 5.172 ns I2C_AV_Config:u1\|mI2C_CTRL_CLK~clkctrl 3 COMB CLKCTRL_G14 44 " "Info: 3: + IC(1.625 ns) + CELL(0.000 ns) = 5.172 ns; Loc. = CLKCTRL_G14; Fanout = 44; COMB Node = 'I2C_AV_Config:u1\|mI2C_CTRL_CLK~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.625 ns" { I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.602 ns) 6.762 ns I2C_AV_Config:u1\|mI2C_DATA\[7\] 4 REG LCFF_X20_Y4_N25 1 " "Info: 4: + IC(0.988 ns) + CELL(0.602 ns) = 6.762 ns; Loc. = LCFF_X20_Y4_N25; Fanout = 1; REG Node = 'I2C_AV_Config:u1\|mI2C_DATA\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.590 ns" { I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|mI2C_DATA[7] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 37.07 % ) " "Info: Total cell delay = 2.507 ns ( 37.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.255 ns ( 62.93 % ) " "Info: Total interconnect delay = 4.255 ns ( 62.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.762 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|mI2C_DATA[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.762 ns" { CLOCK_50 CLOCK_50~combout I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|mI2C_DATA[7] } { 0.000ns 0.000ns 1.642ns 1.625ns 0.988ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.765 ns" { KEY[0] I2C_AV_Config:u1|mI2C_DATA[12]~699 I2C_AV_Config:u1|mI2C_DATA[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.765 ns" { KEY[0] KEY[0]~combout I2C_AV_Config:u1|mI2C_DATA[12]~699 I2C_AV_Config:u1|mI2C_DATA[7] } { 0.000ns 0.000ns 6.834ns 0.796ns } { 0.000ns 0.864ns 0.513ns 0.758ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.762 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|mI2C_DATA[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.762 ns" { CLOCK_50 CLOCK_50~combout I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|mI2C_DATA[7] } { 0.000ns 0.000ns 1.642ns 1.625ns 0.988ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 I2C_SCLK I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[1\] 16.800 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"I2C_SCLK\" through register \"I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[1\]\" is 16.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 6.759 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 6.759 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.879 ns) 3.547 ns I2C_AV_Config:u1\|mI2C_CTRL_CLK 2 REG LCFF_X22_Y5_N9 3 " "Info: 2: + IC(1.642 ns) + CELL(0.879 ns) = 3.547 ns; Loc. = LCFF_X22_Y5_N9; Fanout = 3; REG Node = 'I2C_AV_Config:u1\|mI2C_CTRL_CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.521 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.625 ns) + CELL(0.000 ns) 5.172 ns I2C_AV_Config:u1\|mI2C_CTRL_CLK~clkctrl 3 COMB CLKCTRL_G14 44 " "Info: 3: + IC(1.625 ns) + CELL(0.000 ns) = 5.172 ns; Loc. = CLKCTRL_G14; Fanout = 44; COMB Node = 'I2C_AV_Config:u1\|mI2C_CTRL_CLK~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.625 ns" { I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.985 ns) + CELL(0.602 ns) 6.759 ns I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[1\] 4 REG LCFF_X21_Y5_N23 14 " "Info: 4: + IC(0.985 ns) + CELL(0.602 ns) = 6.759 ns; Loc. = LCFF_X21_Y5_N23; Fanout = 14; REG Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 37.09 % ) " "Info: Total cell delay = 2.507 ns ( 37.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.252 ns ( 62.91 % ) " "Info: Total interconnect delay = 4.252 ns ( 62.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.759 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.759 ns" { CLOCK_50 CLOCK_50~combout I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] } { 0.000ns 0.000ns 1.642ns 1.625ns 0.985ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 91 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.764 ns + Longest register pin " "Info: + Longest register to pin delay is 9.764 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[1\] 1 REG LCFF_X21_Y5_N23 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y5_N23; Fanout = 14; REG Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.948 ns) + CELL(0.545 ns) 1.493 ns I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~253 2 COMB LCCOMB_X22_Y5_N0 1 " "Info: 2: + IC(0.948 ns) + CELL(0.545 ns) = 1.493 ns; Loc. = LCCOMB_X22_Y5_N0; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~253'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~253 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.307 ns) + CELL(0.521 ns) 2.321 ns I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~254 3 COMB LCCOMB_X22_Y5_N18 1 " "Info: 3: + IC(0.307 ns) + CELL(0.521 ns) = 2.321 ns; Loc. = LCCOMB_X22_Y5_N18; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~254'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.828 ns" { I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~253 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~254 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.308 ns) + CELL(0.178 ns) 2.807 ns I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~255 4 COMB LCCOMB_X22_Y5_N26 1 " "Info: 4: + IC(0.308 ns) + CELL(0.178 ns) = 2.807 ns; Loc. = LCCOMB_X22_Y5_N26; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~255'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.486 ns" { I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~254 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.941 ns) + CELL(3.016 ns) 9.764 ns I2C_SCLK 5 PIN PIN_A3 0 " "Info: 5: + IC(3.941 ns) + CELL(3.016 ns) = 9.764 ns; Loc. = PIN_A3; Fanout = 0; PIN Node = 'I2C_SCLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.957 ns" { I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 I2C_SCLK } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 182 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.260 ns ( 43.63 % ) " "Info: Total cell delay = 4.260 ns ( 43.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.504 ns ( 56.37 % ) " "Info: Total interconnect delay = 5.504 ns ( 56.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.764 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~253 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~254 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 I2C_SCLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.764 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~253 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~254 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 I2C_SCLK } { 0.000ns 0.948ns 0.307ns 0.308ns 3.941ns } { 0.000ns 0.545ns 0.521ns 0.178ns 3.016ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.759 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.759 ns" { CLOCK_50 CLOCK_50~combout I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] } { 0.000ns 0.000ns 1.642ns 1.625ns 0.985ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.764 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~253 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~254 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 I2C_SCLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.764 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~253 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~254 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 I2C_SCLK } { 0.000ns 0.948ns 0.307ns 0.308ns 3.941ns } { 0.000ns 0.545ns 0.521ns 0.178ns 3.016ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "AUD_ADCDAT AUD_DACLRCK 9.521 ns Longest " "Info: Longest tpd from source pin \"AUD_ADCDAT\" to destination pin \"AUD_DACLRCK\" is 9.521 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.863 ns) 0.863 ns AUD_ADCDAT 1 PIN PIN_B6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.863 ns) = 0.863 ns; Loc. = PIN_B6; Fanout = 1; PIN Node = 'AUD_ADCDAT'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCDAT } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.642 ns) + CELL(3.016 ns) 9.521 ns AUD_DACLRCK 2 PIN PIN_A5 0 " "Info: 2: + IC(5.642 ns) + CELL(3.016 ns) = 9.521 ns; Loc. = PIN_A5; Fanout = 0; PIN Node = 'AUD_DACLRCK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.658 ns" { AUD_ADCDAT AUD_DACLRCK } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 200 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.879 ns ( 40.74 % ) " "Info: Total cell delay = 3.879 ns ( 40.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.642 ns ( 59.26 % ) " "Info: Total interconnect delay = 5.642 ns ( 59.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.521 ns" { AUD_ADCDAT AUD_DACLRCK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.521 ns" { AUD_ADCDAT AUD_ADCDAT~combout AUD_DACLRCK } { 0.000ns 0.000ns 5.642ns } { 0.000ns 0.863ns 3.016ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "I2C_AV_Config:u1\|I2C_Controller:u0\|ACK3 I2C_SDAT CLOCK_50 -1.188 ns register " "Info: th for register \"I2C_AV_Config:u1\|I2C_Controller:u0\|ACK3\" (data pin = \"I2C_SDAT\", clock pin = \"CLOCK_50\") is -1.188 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 6.759 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 6.759 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.879 ns) 3.547 ns I2C_AV_Config:u1\|mI2C_CTRL_CLK 2 REG LCFF_X22_Y5_N9 3 " "Info: 2: + IC(1.642 ns) + CELL(0.879 ns) = 3.547 ns; Loc. = LCFF_X22_Y5_N9; Fanout = 3; REG Node = 'I2C_AV_Config:u1\|mI2C_CTRL_CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.521 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.625 ns) + CELL(0.000 ns) 5.172 ns I2C_AV_Config:u1\|mI2C_CTRL_CLK~clkctrl 3 COMB CLKCTRL_G14 44 " "Info: 3: + IC(1.625 ns) + CELL(0.000 ns) = 5.172 ns; Loc. = CLKCTRL_G14; Fanout = 44; COMB Node = 'I2C_AV_Config:u1\|mI2C_CTRL_CLK~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.625 ns" { I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.985 ns) + CELL(0.602 ns) 6.759 ns I2C_AV_Config:u1\|I2C_Controller:u0\|ACK3 4 REG LCFF_X22_Y5_N17 2 " "Info: 4: + IC(0.985 ns) + CELL(0.602 ns) = 6.759 ns; Loc. = LCFF_X22_Y5_N17; Fanout = 2; REG Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|ACK3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|ACK3 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 37.09 % ) " "Info: Total cell delay = 2.507 ns ( 37.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.252 ns ( 62.91 % ) " "Info: Total interconnect delay = 4.252 ns ( 62.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.759 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|ACK3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.759 ns" { CLOCK_50 CLOCK_50~combout I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|ACK3 } { 0.000ns 0.000ns 1.642ns 1.625ns 0.985ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 80 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.233 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.233 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2C_SDAT 1 PIN PIN_B3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_B3; Fanout = 1; PIN Node = 'I2C_SDAT'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 181 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.883 ns) 0.883 ns I2C_SDAT~1 2 COMB IOC_X1_Y27_N3 3 " "Info: 2: + IC(0.000 ns) + CELL(0.883 ns) = 0.883 ns; Loc. = IOC_X1_Y27_N3; Fanout = 3; COMB Node = 'I2C_SDAT~1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.883 ns" { I2C_SDAT I2C_SDAT~1 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 181 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.733 ns) + CELL(0.521 ns) 8.137 ns I2C_AV_Config:u1\|I2C_Controller:u0\|ACK3~216 3 COMB LCCOMB_X22_Y5_N16 1 " "Info: 3: + IC(6.733 ns) + CELL(0.521 ns) = 8.137 ns; Loc. = LCCOMB_X22_Y5_N16; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|ACK3~216'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.254 ns" { I2C_SDAT~1 I2C_AV_Config:u1|I2C_Controller:u0|ACK3~216 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 8.233 ns I2C_AV_Config:u1\|I2C_Controller:u0\|ACK3 4 REG LCFF_X22_Y5_N17 2 " "Info: 4: + IC(0.000 ns) + CELL(0.096 ns) = 8.233 ns; Loc. = LCFF_X22_Y5_N17; Fanout = 2; REG Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|ACK3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { I2C_AV_Config:u1|I2C_Controller:u0|ACK3~216 I2C_AV_Config:u1|I2C_Controller:u0|ACK3 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 18.22 % ) " "Info: Total cell delay = 1.500 ns ( 18.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.733 ns ( 81.78 % ) " "Info: Total interconnect delay = 6.733 ns ( 81.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.233 ns" { I2C_SDAT I2C_SDAT~1 I2C_AV_Config:u1|I2C_Controller:u0|ACK3~216 I2C_AV_Config:u1|I2C_Controller:u0|ACK3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.233 ns" { I2C_SDAT I2C_SDAT~1 I2C_AV_Config:u1|I2C_Controller:u0|ACK3~216 I2C_AV_Config:u1|I2C_Controller:u0|ACK3 } { 0.000ns 0.000ns 6.733ns 0.000ns } { 0.000ns 0.883ns 0.521ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.759 ns" { CLOCK_50 I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|ACK3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.759 ns" { CLOCK_50 CLOCK_50~combout I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|ACK3 } { 0.000ns 0.000ns 1.642ns 1.625ns 0.985ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.233 ns" { I2C_SDAT I2C_SDAT~1 I2C_AV_Config:u1|I2C_Controller:u0|ACK3~216 I2C_AV_Config:u1|I2C_Controller:u0|ACK3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.233 ns" { I2C_SDAT I2C_SDAT~1 I2C_AV_Config:u1|I2C_Controller:u0|ACK3~216 I2C_AV_Config:u1|I2C_Controller:u0|ACK3 } { 0.000ns 0.000ns 6.733ns 0.000ns } { 0.000ns 0.883ns 0.521ns 0.096ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "118 " "Info: Allocated 118 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 30 15:41:15 2007 " "Info: Processing ended: Thu Aug 30 15:41:15 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}