|DE1_i2sound CLOCK_24[0] => ~NO_FANOUT~ CLOCK_24[1] => ~NO_FANOUT~ CLOCK_27[0] => CLOCK_27[0]~0.IN1 CLOCK_27[1] => ~NO_FANOUT~ CLOCK_50 => CLOCK_50~0.IN1 EXT_CLOCK => ~NO_FANOUT~ KEY[0] => KEY[0]~0.IN1 KEY[1] => ~NO_FANOUT~ KEY[2] => ~NO_FANOUT~ KEY[3] => ~NO_FANOUT~ SW[0] => ~NO_FANOUT~ SW[1] => ~NO_FANOUT~ SW[2] => ~NO_FANOUT~ SW[3] => ~NO_FANOUT~ SW[4] => ~NO_FANOUT~ SW[5] => ~NO_FANOUT~ SW[6] => ~NO_FANOUT~ SW[7] => ~NO_FANOUT~ SW[8] => ~NO_FANOUT~ SW[9] => ~NO_FANOUT~ HEX0[0] <= <GND> HEX0[1] <= <GND> HEX0[2] <= <GND> HEX0[3] <= <GND> HEX0[4] <= <GND> HEX0[5] <= <GND> HEX0[6] <= <GND> HEX1[0] <= <GND> HEX1[1] <= <GND> HEX1[2] <= <GND> HEX1[3] <= <GND> HEX1[4] <= <GND> HEX1[5] <= <GND> HEX1[6] <= <GND> HEX2[0] <= <GND> HEX2[1] <= <GND> HEX2[2] <= <GND> HEX2[3] <= <GND> HEX2[4] <= <GND> HEX2[5] <= <GND> HEX2[6] <= <GND> HEX3[0] <= <GND> HEX3[1] <= <GND> HEX3[2] <= <GND> HEX3[3] <= <GND> HEX3[4] <= <GND> HEX3[5] <= <GND> HEX3[6] <= <GND> LEDG[0] <= VOL[0]~6.DB_MAX_OUTPUT_PORT_TYPE LEDG[1] <= VOL[1]~5.DB_MAX_OUTPUT_PORT_TYPE LEDG[2] <= VOL[2]~4.DB_MAX_OUTPUT_PORT_TYPE LEDG[3] <= VOL[3]~3.DB_MAX_OUTPUT_PORT_TYPE LEDG[4] <= VOL[4]~2.DB_MAX_OUTPUT_PORT_TYPE LEDG[5] <= VOL[5]~1.DB_MAX_OUTPUT_PORT_TYPE LEDG[6] <= VOL[6]~0.DB_MAX_OUTPUT_PORT_TYPE LEDG[7] <= <GND> LEDR[0] <= <VCC> LEDR[1] <= <VCC> LEDR[2] <= <VCC> LEDR[3] <= <VCC> LEDR[4] <= <VCC> LEDR[5] <= <VCC> LEDR[6] <= <VCC> LEDR[7] <= <VCC> LEDR[8] <= <VCC> LEDR[9] <= <VCC> UART_TXD <= <GND> UART_RXD => ~NO_FANOUT~ DRAM_DQ[0] <= DRAM_DQ[0]~0 DRAM_DQ[1] <= DRAM_DQ[1]~1 DRAM_DQ[2] <= DRAM_DQ[2]~2 DRAM_DQ[3] <= DRAM_DQ[3]~3 DRAM_DQ[4] <= DRAM_DQ[4]~4 DRAM_DQ[5] <= DRAM_DQ[5]~5 DRAM_DQ[6] <= DRAM_DQ[6]~6 DRAM_DQ[7] <= DRAM_DQ[7]~7 DRAM_DQ[8] <= DRAM_DQ[8]~8 DRAM_DQ[9] <= DRAM_DQ[9]~9 DRAM_DQ[10] <= DRAM_DQ[10]~10 DRAM_DQ[11] <= DRAM_DQ[11]~11 DRAM_DQ[12] <= DRAM_DQ[12]~12 DRAM_DQ[13] <= DRAM_DQ[13]~13 DRAM_DQ[14] <= DRAM_DQ[14]~14 DRAM_DQ[15] <= DRAM_DQ[15]~16 DRAM_ADDR[0] <= <GND> DRAM_ADDR[1] <= <GND> DRAM_ADDR[2] <= <GND> DRAM_ADDR[3] <= <GND> DRAM_ADDR[4] <= <GND> DRAM_ADDR[5] <= <GND> DRAM_ADDR[6] <= <GND> DRAM_ADDR[7] <= <GND> DRAM_ADDR[8] <= <GND> DRAM_ADDR[9] <= <GND> DRAM_ADDR[10] <= <GND> DRAM_ADDR[11] <= <GND> DRAM_LDQM <= <GND> DRAM_UDQM <= <GND> DRAM_WE_N <= <GND> DRAM_CAS_N <= <GND> DRAM_RAS_N <= <GND> DRAM_CS_N <= <GND> DRAM_BA_0 <= <GND> DRAM_BA_1 <= <GND> DRAM_CLK <= <GND> DRAM_CKE <= <GND> FL_DQ[0] <= FL_DQ[0]~0 FL_DQ[1] <= FL_DQ[1]~1 FL_DQ[2] <= FL_DQ[2]~2 FL_DQ[3] <= FL_DQ[3]~3 FL_DQ[4] <= FL_DQ[4]~4 FL_DQ[5] <= FL_DQ[5]~5 FL_DQ[6] <= FL_DQ[6]~6 FL_DQ[7] <= FL_DQ[7]~7 FL_ADDR[0] <= <GND> FL_ADDR[1] <= <GND> FL_ADDR[2] <= <GND> FL_ADDR[3] <= <GND> FL_ADDR[4] <= <GND> FL_ADDR[5] <= <GND> FL_ADDR[6] <= <GND> FL_ADDR[7] <= <GND> FL_ADDR[8] <= <GND> FL_ADDR[9] <= <GND> FL_ADDR[10] <= <GND> FL_ADDR[11] <= <GND> FL_ADDR[12] <= <GND> FL_ADDR[13] <= <GND> FL_ADDR[14] <= <GND> FL_ADDR[15] <= <GND> FL_ADDR[16] <= <GND> FL_ADDR[17] <= <GND> FL_ADDR[18] <= <GND> FL_ADDR[19] <= <GND> FL_ADDR[20] <= <GND> FL_ADDR[21] <= <GND> FL_WE_N <= <GND> FL_RST_N <= <GND> FL_OE_N <= <GND> FL_CE_N <= <GND> SRAM_DQ[0] <= SRAM_DQ[0]~0 SRAM_DQ[1] <= SRAM_DQ[1]~1 SRAM_DQ[2] <= SRAM_DQ[2]~2 SRAM_DQ[3] <= SRAM_DQ[3]~3 SRAM_DQ[4] <= SRAM_DQ[4]~4 SRAM_DQ[5] <= SRAM_DQ[5]~5 SRAM_DQ[6] <= SRAM_DQ[6]~6 SRAM_DQ[7] <= SRAM_DQ[7]~7 SRAM_DQ[8] <= SRAM_DQ[8]~8 SRAM_DQ[9] <= SRAM_DQ[9]~9 SRAM_DQ[10] <= SRAM_DQ[10]~10 SRAM_DQ[11] <= SRAM_DQ[11]~11 SRAM_DQ[12] <= SRAM_DQ[12]~12 SRAM_DQ[13] <= SRAM_DQ[13]~13 SRAM_DQ[14] <= SRAM_DQ[14]~14 SRAM_DQ[15] <= SRAM_DQ[15]~15 SRAM_ADDR[0] <= <GND> SRAM_ADDR[1] <= <GND> SRAM_ADDR[2] <= <GND> SRAM_ADDR[3] <= <GND> SRAM_ADDR[4] <= <GND> SRAM_ADDR[5] <= <GND> SRAM_ADDR[6] <= <GND> SRAM_ADDR[7] <= <GND> SRAM_ADDR[8] <= <GND> SRAM_ADDR[9] <= <GND> SRAM_ADDR[10] <= <GND> SRAM_ADDR[11] <= <GND> SRAM_ADDR[12] <= <GND> SRAM_ADDR[13] <= <GND> SRAM_ADDR[14] <= <GND> SRAM_ADDR[15] <= <GND> SRAM_ADDR[16] <= <GND> SRAM_ADDR[17] <= <GND> SRAM_UB_N <= <GND> SRAM_LB_N <= <GND> SRAM_WE_N <= <GND> SRAM_CE_N <= <GND> SRAM_OE_N <= <GND> SD_DAT <= SD_DAT~0 SD_DAT3 <= <UNC> SD_CMD <= <UNC> SD_CLK <= <GND> TDI => ~NO_FANOUT~ TCK => ~NO_FANOUT~ TCS => ~NO_FANOUT~ TDO <= <GND> I2C_SDAT <= I2C_AV_Config:u1.I2C_SDAT I2C_SDAT <= I2C_SDAT~0 I2C_SCLK <= I2C_AV_Config:u1.I2C_SCLK PS2_DAT => ~NO_FANOUT~ PS2_CLK => ~NO_FANOUT~ VGA_HS <= <GND> VGA_VS <= <GND> VGA_R[0] <= <GND> VGA_R[1] <= <GND> VGA_R[2] <= <GND> VGA_R[3] <= <GND> VGA_G[0] <= <GND> VGA_G[1] <= <GND> VGA_G[2] <= <GND> VGA_G[3] <= <GND> VGA_B[0] <= <GND> VGA_B[1] <= <GND> VGA_B[2] <= <GND> VGA_B[3] <= <GND> AUD_ADCLRCK <= <UNC> AUD_ADCDAT => AUD_DACLRCK~0.DATAIN AUD_DACLRCK <= AUD_DACLRCK~0 AUD_DACDAT <= <GND> AUD_BCLK <= <UNC> AUD_XCK <= PLL:u0.c0 GPIO_0[0] <= GPIO_0[0]~0 GPIO_0[1] <= GPIO_0[1]~1 GPIO_0[2] <= GPIO_0[2]~2 GPIO_0[3] <= GPIO_0[3]~3 GPIO_0[4] <= GPIO_0[4]~4 GPIO_0[5] <= GPIO_0[5]~5 GPIO_0[6] <= GPIO_0[6]~6 GPIO_0[7] <= GPIO_0[7]~7 GPIO_0[8] <= GPIO_0[8]~8 GPIO_0[9] <= GPIO_0[9]~9 GPIO_0[10] <= GPIO_0[10]~10 GPIO_0[11] <= GPIO_0[11]~11 GPIO_0[12] <= GPIO_0[12]~12 GPIO_0[13] <= GPIO_0[13]~13 GPIO_0[14] <= GPIO_0[14]~14 GPIO_0[15] <= GPIO_0[15]~15 GPIO_0[16] <= GPIO_0[16]~16 GPIO_0[17] <= GPIO_0[17]~17 GPIO_0[18] <= GPIO_0[18]~18 GPIO_0[19] <= GPIO_0[19]~19 GPIO_0[20] <= GPIO_0[20]~20 GPIO_0[21] <= GPIO_0[21]~21 GPIO_0[22] <= GPIO_0[22]~22 GPIO_0[23] <= GPIO_0[23]~23 GPIO_0[24] <= GPIO_0[24]~24 GPIO_0[25] <= GPIO_0[25]~25 GPIO_0[26] <= GPIO_0[26]~26 GPIO_0[27] <= GPIO_0[27]~27 GPIO_0[28] <= GPIO_0[28]~28 GPIO_0[29] <= GPIO_0[29]~29 GPIO_0[30] <= GPIO_0[30]~30 GPIO_0[31] <= GPIO_0[31]~31 GPIO_0[32] <= GPIO_0[32]~32 GPIO_0[33] <= GPIO_0[33]~33 GPIO_0[34] <= GPIO_0[34]~34 GPIO_0[35] <= GPIO_0[35]~35 GPIO_1[0] <= GPIO_1[0]~0 GPIO_1[1] <= GPIO_1[1]~1 GPIO_1[2] <= GPIO_1[2]~2 GPIO_1[3] <= GPIO_1[3]~3 GPIO_1[4] <= GPIO_1[4]~4 GPIO_1[5] <= GPIO_1[5]~5 GPIO_1[6] <= GPIO_1[6]~6 GPIO_1[7] <= GPIO_1[7]~7 GPIO_1[8] <= GPIO_1[8]~8 GPIO_1[9] <= GPIO_1[9]~9 GPIO_1[10] <= GPIO_1[10]~10 GPIO_1[11] <= GPIO_1[11]~11 GPIO_1[12] <= GPIO_1[12]~12 GPIO_1[13] <= GPIO_1[13]~13 GPIO_1[14] <= GPIO_1[14]~14 GPIO_1[15] <= GPIO_1[15]~15 GPIO_1[16] <= GPIO_1[16]~16 GPIO_1[17] <= GPIO_1[17]~17 GPIO_1[18] <= GPIO_1[18]~18 GPIO_1[19] <= GPIO_1[19]~19 GPIO_1[20] <= GPIO_1[20]~20 GPIO_1[21] <= GPIO_1[21]~21 GPIO_1[22] <= GPIO_1[22]~22 GPIO_1[23] <= GPIO_1[23]~23 GPIO_1[24] <= GPIO_1[24]~24 GPIO_1[25] <= GPIO_1[25]~25 GPIO_1[26] <= GPIO_1[26]~26 GPIO_1[27] <= GPIO_1[27]~27 GPIO_1[28] <= GPIO_1[28]~28 GPIO_1[29] <= GPIO_1[29]~29 GPIO_1[30] <= GPIO_1[30]~30 GPIO_1[31] <= GPIO_1[31]~31 GPIO_1[32] <= GPIO_1[32]~32 GPIO_1[33] <= GPIO_1[33]~33 GPIO_1[34] <= GPIO_1[34]~34 GPIO_1[35] <= GPIO_1[35]~35 |DE1_i2sound|PLL:u0 inclk0 => sub_wire3[0].IN1 c0 <= altpll:altpll_component.clk |DE1_i2sound|PLL:u0|altpll:altpll_component inclk[0] => pll.CLK inclk[1] => ~NO_FANOUT~ fbin => ~NO_FANOUT~ pllena => ~NO_FANOUT~ clkswitch => ~NO_FANOUT~ areset => ~NO_FANOUT~ pfdena => ~NO_FANOUT~ clkena[0] => ~NO_FANOUT~ clkena[1] => ~NO_FANOUT~ clkena[2] => ~NO_FANOUT~ clkena[3] => ~NO_FANOUT~ clkena[4] => ~NO_FANOUT~ clkena[5] => ~NO_FANOUT~ extclkena[0] => ~NO_FANOUT~ extclkena[1] => ~NO_FANOUT~ extclkena[2] => ~NO_FANOUT~ extclkena[3] => ~NO_FANOUT~ scanclk => ~NO_FANOUT~ scanclkena => ~NO_FANOUT~ scanaclr => ~NO_FANOUT~ scanread => ~NO_FANOUT~ scanwrite => ~NO_FANOUT~ scandata => ~NO_FANOUT~ phasecounterselect[0] => ~NO_FANOUT~ phasecounterselect[1] => ~NO_FANOUT~ phasecounterselect[2] => ~NO_FANOUT~ phasecounterselect[3] => ~NO_FANOUT~ phaseupdown => ~NO_FANOUT~ phasestep => ~NO_FANOUT~ configupdate => ~NO_FANOUT~ fbmimicbidir <= <GND> clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE clk[1] <= <GND> clk[2] <= <GND> clk[3] <= <GND> clk[4] <= <GND> clk[5] <= <GND> extclk[0] <= <GND> extclk[1] <= <GND> extclk[2] <= <GND> extclk[3] <= <GND> clkbad[0] <= <GND> clkbad[1] <= <GND> enable1 <= <GND> enable0 <= <GND> activeclock <= <GND> clkloss <= <GND> locked <= <GND> scandataout <= <GND> scandone <= <GND> sclkout0 <= <GND> sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE phasedone <= <GND> vcooverrange <= <GND> vcounderrange <= <GND> fbout <= <GND> |DE1_i2sound|I2C_AV_Config:u1 iCLK => mI2C_CTRL_CLK.CLK iCLK => mI2C_CLK_DIV[15].CLK iCLK => mI2C_CLK_DIV[14].CLK iCLK => mI2C_CLK_DIV[13].CLK iCLK => mI2C_CLK_DIV[12].CLK iCLK => mI2C_CLK_DIV[11].CLK iCLK => mI2C_CLK_DIV[10].CLK iCLK => mI2C_CLK_DIV[9].CLK iCLK => mI2C_CLK_DIV[8].CLK iCLK => mI2C_CLK_DIV[7].CLK iCLK => mI2C_CLK_DIV[6].CLK iCLK => mI2C_CLK_DIV[5].CLK iCLK => mI2C_CLK_DIV[4].CLK iCLK => mI2C_CLK_DIV[3].CLK iCLK => mI2C_CLK_DIV[2].CLK iCLK => mI2C_CLK_DIV[1].CLK iCLK => mI2C_CLK_DIV[0].CLK iRST_N => iRST_N~0.IN1 iVOL[0] => Mux6.IN14 iVOL[0] => Mux6.IN15 iVOL[1] => Mux5.IN14 iVOL[1] => Mux5.IN15 iVOL[2] => Mux4.IN14 iVOL[2] => Mux4.IN15 iVOL[3] => Mux3.IN14 iVOL[3] => Mux3.IN15 iVOL[4] => Mux2.IN14 iVOL[4] => Mux2.IN15 iVOL[5] => Mux1.IN14 iVOL[5] => Mux1.IN15 iVOL[6] => Mux0.IN14 iVOL[6] => Mux0.IN15 I2C_SCLK <= I2C_Controller:u0.I2C_SCLK I2C_SDAT <= I2C_Controller:u0.I2C_SDAT |DE1_i2sound|I2C_AV_Config:u1|I2C_Controller:u0 CLOCK => SD_COUNTER[5]~reg0.CLK CLOCK => SD_COUNTER[4]~reg0.CLK CLOCK => SD_COUNTER[3]~reg0.CLK CLOCK => SD_COUNTER[2]~reg0.CLK CLOCK => SD_COUNTER[1]~reg0.CLK CLOCK => SD_COUNTER[0]~reg0.CLK CLOCK => SCLK.CLK CLOCK => SDO~reg0.CLK CLOCK => ACK1.CLK CLOCK => ACK2.CLK CLOCK => ACK3.CLK CLOCK => END~reg0.CLK CLOCK => SD[23].CLK CLOCK => SD[22].CLK CLOCK => SD[21].CLK CLOCK => SD[20].CLK CLOCK => SD[19].CLK CLOCK => SD[18].CLK CLOCK => SD[17].CLK CLOCK => SD[16].CLK CLOCK => SD[15].CLK CLOCK => SD[14].CLK CLOCK => SD[13].CLK CLOCK => SD[12].CLK CLOCK => SD[11].CLK CLOCK => SD[10].CLK CLOCK => SD[9].CLK CLOCK => SD[8].CLK CLOCK => SD[7].CLK CLOCK => SD[6].CLK CLOCK => SD[5].CLK CLOCK => SD[4].CLK CLOCK => SD[3].CLK CLOCK => SD[2].CLK CLOCK => SD[1].CLK CLOCK => SD[0].CLK CLOCK => comb~1.DATAB I2C_SCLK <= comb~2.DB_MAX_OUTPUT_PORT_TYPE I2C_SDAT <= I2C_SDAT~0 I2C_DATA[0] => SD~23.DATAB I2C_DATA[1] => SD~22.DATAB I2C_DATA[2] => SD~21.DATAB I2C_DATA[3] => SD~20.DATAB I2C_DATA[4] => SD~19.DATAB I2C_DATA[5] => SD~18.DATAB I2C_DATA[6] => SD~17.DATAB I2C_DATA[7] => SD~16.DATAB I2C_DATA[8] => SD~15.DATAB I2C_DATA[9] => SD~14.DATAB I2C_DATA[10] => SD~13.DATAB I2C_DATA[11] => SD~12.DATAB I2C_DATA[12] => SD~11.DATAB I2C_DATA[13] => SD~10.DATAB I2C_DATA[14] => SD~9.DATAB I2C_DATA[15] => SD~8.DATAB I2C_DATA[16] => SD~7.DATAB I2C_DATA[17] => SD~6.DATAB I2C_DATA[18] => SD~5.DATAB I2C_DATA[19] => SD~4.DATAB I2C_DATA[20] => SD~3.DATAB I2C_DATA[21] => SD~2.DATAB I2C_DATA[22] => SD~1.DATAB I2C_DATA[23] => SD~0.DATAB GO => SD_COUNTER~11.OUTPUTSELECT GO => SD_COUNTER~10.OUTPUTSELECT GO => SD_COUNTER~9.OUTPUTSELECT GO => SD_COUNTER~8.OUTPUTSELECT GO => SD_COUNTER~7.OUTPUTSELECT GO => SD_COUNTER~6.OUTPUTSELECT END <= END~reg0.DB_MAX_OUTPUT_PORT_TYPE W_R => ~NO_FANOUT~ ACK <= comb~4.DB_MAX_OUTPUT_PORT_TYPE RESET => SD_COUNTER[0]~reg0.PRESET RESET => SD_COUNTER[1]~reg0.PRESET RESET => SD_COUNTER[2]~reg0.PRESET RESET => SD_COUNTER[3]~reg0.PRESET RESET => SD_COUNTER[4]~reg0.PRESET RESET => SD_COUNTER[5]~reg0.PRESET RESET => SCLK.PRESET RESET => SDO~reg0.PRESET RESET => ACK1.ACLR RESET => ACK2.ACLR RESET => ACK3.ACLR RESET => END~reg0.PRESET RESET => SD[0].ENA RESET => SD[23].ENA RESET => SD[22].ENA RESET => SD[21].ENA RESET => SD[20].ENA RESET => SD[19].ENA RESET => SD[18].ENA RESET => SD[17].ENA RESET => SD[16].ENA RESET => SD[15].ENA RESET => SD[14].ENA RESET => SD[13].ENA RESET => SD[12].ENA RESET => SD[11].ENA RESET => SD[10].ENA RESET => SD[9].ENA RESET => SD[8].ENA RESET => SD[7].ENA RESET => SD[6].ENA RESET => SD[5].ENA RESET => SD[4].ENA RESET => SD[3].ENA RESET => SD[2].ENA RESET => SD[1].ENA SD_COUNTER[0] <= SD_COUNTER[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE SD_COUNTER[1] <= SD_COUNTER[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE SD_COUNTER[2] <= SD_COUNTER[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE SD_COUNTER[3] <= SD_COUNTER[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE SD_COUNTER[4] <= SD_COUNTER[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE SD_COUNTER[5] <= SD_COUNTER[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE SDO <= SDO~reg0.DB_MAX_OUTPUT_PORT_TYPE