{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version " "Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 30 15:40:44 2007 " "Info: Processing started: Thu Aug 30 15:40:44 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DE1_i2sound -c DE1_i2sound " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DE1_i2sound -c DE1_i2sound" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "DE1_i2sound EP2C20F484C7 " "Info: Selected device EP2C20F484C7 for design \"DE1_i2sound\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "PLL:u0\|altpll:altpll_component\|pll Cyclone II " "Info: Implemented PLL \"PLL:u0\|altpll:altpll_component\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "PLL:u0\|altpll:altpll_component\|_clk0 15 22 0 0 " "Info: Implementing clock multiplication of 15, clock division of 22, and phase shift of 0 degrees (0 ps) for PLL:u0\|altpll:altpll_component\|_clk0 port" {  } { { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0}  } { { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } }  } 0 0 "Implemented PLL \"%1!s!\" as %2!s! PLL type" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Info: Device EP2C15AF484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Info: Device EP2C35F484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Info: Device EP2C50F484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Info: Pin ~ASDO~ is reserved at location C4" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Info: Pin ~nCSO~ is reserved at location C3" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Info: Pin ~LVDS91p/nCEO~ is reserved at location W20" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "4 283 " "Warning: No exact pin location assignment(s) for 4 pins of 283 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_CLK " "Info: Pin SD_CLK not assigned to an exact location on the device" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 179 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_DAT3 " "Info: Pin SD_DAT3 not assigned to an exact location on the device" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 177 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_CMD " "Info: Pin SD_CMD not assigned to an exact location on the device" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 178 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_DAT " "Info: Pin SD_DAT not assigned to an exact location on the device" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 176 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "PLL:u0\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_3) " "Info: Automatically promoted node PLL:u0\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_3)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G11 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G11" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 504 3 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL:u0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL:u0|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "I2C_AV_Config:u1\|mI2C_CTRL_CLK " "Info: Destination node I2C_AV_Config:u1\|mI2C_CTRL_CLK" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 18 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|mI2C_CTRL_CLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|mI2C_CTRL_CLK } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 130 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "I2C_AV_Config:u1\|mI2C_CTRL_CLK  " "Info: Automatically promoted node I2C_AV_Config:u1\|mI2C_CTRL_CLK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~255 " "Info: Destination node I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~255" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 62 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "I2C_AV_Config:u1\|mI2C_CTRL_CLK~79 " "Info: Destination node I2C_AV_Config:u1\|mI2C_CTRL_CLK~79" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 18 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|mI2C_CTRL_CLK~79 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|mI2C_CTRL_CLK~79 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_AV_Config.v" 18 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|mI2C_CTRL_CLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|mI2C_CTRL_CLK } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "4 unused 3.30 0 1 3 " "Info: Number of I/O pins in group: 4 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 3 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 40 1 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 40 total pin(s) used --  1 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.30V 32 1 " "Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 32 total pin(s) used --  1 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 28 15 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 28 total pin(s) used --  15 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 38 2 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 38 total pin(s) used --  2 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.30V 36 3 " "Info: I/O bank number 5 does not use VREF pins and has 3.30V VCCIO pins. 36 total pin(s) used --  3 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.30V 31 5 " "Info: I/O bank number 6 does not use VREF pins and has 3.30V VCCIO pins. 31 total pin(s) used --  5 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 3.30V 36 4 " "Info: I/O bank number 7 does not use VREF pins and has 3.30V VCCIO pins. 36 total pin(s) used --  4 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 3.30V 41 2 " "Info: I/O bank number 8 does not use VREF pins and has 3.30V VCCIO pins. 41 total pin(s) used --  2 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0}
{ "Warning" "WCUT_PLL_NON_ZDB_COMP_CLK_FEEDING_IO" "PLL:u0\|altpll:altpll_component\|pll compensate_clock 0 " "Warning: PLL \"PLL:u0\|altpll:altpll_component\|pll\" is in normal or source synchronous mode with output clock \"compensate_clock\" set to clk\[0\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" {  } { { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/PLL.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/PLL.v" 75 0 0 } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 230 0 0 } }  } 0 0 "PLL \"%1!s!\" is in normal or source synchronous mode with output clock \"%2!s!\" set to clk\[%3!d!\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" 0 0 "" 0}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "PLL:u0\|altpll:altpll_component\|pll clk\[0\] AUD_XCK " "Warning: PLL \"PLL:u0\|altpll:altpll_component\|pll\" output port clk\[0\] feeds output pin \"AUD_XCK\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/PLL.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/PLL.v" 75 0 0 } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 230 0 0 } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 203 -1 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.782 ns register register " "Info: Estimated most critical path is register to register delay of 4.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[0\] 1 REG LAB_X21_Y5 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X21_Y5; Fanout = 20; REG Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.991 ns) + CELL(0.322 ns) 1.313 ns I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~503 2 COMB LAB_X21_Y4 1 " "Info: 2: + IC(0.991 ns) + CELL(0.322 ns) = 1.313 ns; Loc. = LAB_X21_Y4; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~503'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] I2C_AV_Config:u1|I2C_Controller:u0|Mux0~503 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.319 ns) 1.986 ns I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~504 3 COMB LAB_X21_Y4 1 " "Info: 3: + IC(0.354 ns) + CELL(0.319 ns) = 1.986 ns; Loc. = LAB_X21_Y4; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~504'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.673 ns" { I2C_AV_Config:u1|I2C_Controller:u0|Mux0~503 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~504 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.178 ns) 2.662 ns I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~505 4 COMB LAB_X21_Y4 1 " "Info: 4: + IC(0.498 ns) + CELL(0.178 ns) = 2.662 ns; Loc. = LAB_X21_Y4; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~505'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { I2C_AV_Config:u1|I2C_Controller:u0|Mux0~504 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~505 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.319 ns) 3.335 ns I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~508 5 COMB LAB_X21_Y4 1 " "Info: 5: + IC(0.354 ns) + CELL(0.319 ns) = 3.335 ns; Loc. = LAB_X21_Y4; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~508'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.673 ns" { I2C_AV_Config:u1|I2C_Controller:u0|Mux0~505 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~508 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.154 ns) + CELL(0.521 ns) 4.010 ns I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~512 6 COMB LAB_X21_Y4 1 " "Info: 6: + IC(0.154 ns) + CELL(0.521 ns) = 4.010 ns; Loc. = LAB_X21_Y4; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~512'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.675 ns" { I2C_AV_Config:u1|I2C_Controller:u0|Mux0~508 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~512 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.322 ns) 4.686 ns I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~513 7 COMB LAB_X21_Y4 1 " "Info: 7: + IC(0.354 ns) + CELL(0.322 ns) = 4.686 ns; Loc. = LAB_X21_Y4; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|Mux0~513'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { I2C_AV_Config:u1|I2C_Controller:u0|Mux0~512 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~513 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 4.782 ns I2C_AV_Config:u1\|I2C_Controller:u0\|SDO 8 REG LAB_X21_Y4 4 " "Info: 8: + IC(0.000 ns) + CELL(0.096 ns) = 4.782 ns; Loc. = LAB_X21_Y4; Fanout = 4; REG Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|SDO'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { I2C_AV_Config:u1|I2C_Controller:u0|Mux0~513 I2C_AV_Config:u1|I2C_Controller:u0|SDO } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/I2C_Controller.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.077 ns ( 43.43 % ) " "Info: Total cell delay = 2.077 ns ( 43.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.705 ns ( 56.57 % ) " "Info: Total interconnect delay = 2.705 ns ( 56.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.782 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0] I2C_AV_Config:u1|I2C_Controller:u0|Mux0~503 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~504 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~505 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~508 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~512 I2C_AV_Config:u1|I2C_Controller:u0|Mux0~513 I2C_AV_Config:u1|I2C_Controller:u0|SDO } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X12_Y0 X24_Y13 " "Info: The peak interconnect region extends from location X12_Y0 to location X24_Y13" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "256 " "Warning: Found 256 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[0\] 0 " "Info: Pin \"HEX0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[1\] 0 " "Info: Pin \"HEX0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[2\] 0 " "Info: Pin \"HEX0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[3\] 0 " "Info: Pin \"HEX0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[4\] 0 " "Info: Pin \"HEX0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[5\] 0 " "Info: Pin \"HEX0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[6\] 0 " "Info: Pin \"HEX0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[0\] 0 " "Info: Pin \"HEX1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[1\] 0 " "Info: Pin \"HEX1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[2\] 0 " "Info: Pin \"HEX1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[3\] 0 " "Info: Pin \"HEX1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[4\] 0 " "Info: Pin \"HEX1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[5\] 0 " "Info: Pin \"HEX1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[6\] 0 " "Info: Pin \"HEX1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[0\] 0 " "Info: Pin \"HEX2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[1\] 0 " "Info: Pin \"HEX2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[2\] 0 " "Info: Pin \"HEX2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[3\] 0 " "Info: Pin \"HEX2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[4\] 0 " "Info: Pin \"HEX2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[5\] 0 " "Info: Pin \"HEX2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[6\] 0 " "Info: Pin \"HEX2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[0\] 0 " "Info: Pin \"HEX3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[1\] 0 " "Info: Pin \"HEX3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[2\] 0 " "Info: Pin \"HEX3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[3\] 0 " "Info: Pin \"HEX3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[4\] 0 " "Info: Pin \"HEX3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[5\] 0 " "Info: Pin \"HEX3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[6\] 0 " "Info: Pin \"HEX3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[0\] 0 " "Info: Pin \"LEDG\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[1\] 0 " "Info: Pin \"LEDG\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[2\] 0 " "Info: Pin \"LEDG\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[3\] 0 " "Info: Pin \"LEDG\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[4\] 0 " "Info: Pin \"LEDG\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[5\] 0 " "Info: Pin \"LEDG\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[6\] 0 " "Info: Pin \"LEDG\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[7\] 0 " "Info: Pin \"LEDG\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[0\] 0 " "Info: Pin \"LEDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[1\] 0 " "Info: Pin \"LEDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[2\] 0 " "Info: Pin \"LEDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[3\] 0 " "Info: Pin \"LEDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[4\] 0 " "Info: Pin \"LEDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[5\] 0 " "Info: Pin \"LEDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[6\] 0 " "Info: Pin \"LEDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[7\] 0 " "Info: Pin \"LEDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[8\] 0 " "Info: Pin \"LEDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[9\] 0 " "Info: Pin \"LEDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "UART_TXD 0 " "Info: Pin \"UART_TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[0\] 0 " "Info: Pin \"DRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[1\] 0 " "Info: Pin \"DRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[2\] 0 " "Info: Pin \"DRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[3\] 0 " "Info: Pin \"DRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[4\] 0 " "Info: Pin \"DRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[5\] 0 " "Info: Pin \"DRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[6\] 0 " "Info: Pin \"DRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[7\] 0 " "Info: Pin \"DRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[8\] 0 " "Info: Pin \"DRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[9\] 0 " "Info: Pin \"DRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[10\] 0 " "Info: Pin \"DRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[11\] 0 " "Info: Pin \"DRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_LDQM 0 " "Info: Pin \"DRAM_LDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_UDQM 0 " "Info: Pin \"DRAM_UDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_WE_N 0 " "Info: Pin \"DRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CAS_N 0 " "Info: Pin \"DRAM_CAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_RAS_N 0 " "Info: Pin \"DRAM_RAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CS_N 0 " "Info: Pin \"DRAM_CS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_0 0 " "Info: Pin \"DRAM_BA_0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_1 0 " "Info: Pin \"DRAM_BA_1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CLK 0 " "Info: Pin \"DRAM_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CKE 0 " "Info: Pin \"DRAM_CKE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[0\] 0 " "Info: Pin \"FL_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[1\] 0 " "Info: Pin \"FL_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[2\] 0 " "Info: Pin \"FL_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[3\] 0 " "Info: Pin \"FL_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[4\] 0 " "Info: Pin \"FL_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[5\] 0 " "Info: Pin \"FL_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[6\] 0 " "Info: Pin \"FL_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[7\] 0 " "Info: Pin \"FL_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[8\] 0 " "Info: Pin \"FL_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[9\] 0 " "Info: Pin \"FL_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[10\] 0 " "Info: Pin \"FL_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[11\] 0 " "Info: Pin \"FL_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[12\] 0 " "Info: Pin \"FL_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[13\] 0 " "Info: Pin \"FL_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[14\] 0 " "Info: Pin \"FL_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[15\] 0 " "Info: Pin \"FL_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[16\] 0 " "Info: Pin \"FL_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[17\] 0 " "Info: Pin \"FL_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[18\] 0 " "Info: Pin \"FL_ADDR\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[19\] 0 " "Info: Pin \"FL_ADDR\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[20\] 0 " "Info: Pin \"FL_ADDR\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[21\] 0 " "Info: Pin \"FL_ADDR\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_WE_N 0 " "Info: Pin \"FL_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_RST_N 0 " "Info: Pin \"FL_RST_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_OE_N 0 " "Info: Pin \"FL_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_CE_N 0 " "Info: Pin \"FL_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[0\] 0 " "Info: Pin \"SRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[1\] 0 " "Info: Pin \"SRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[2\] 0 " "Info: Pin \"SRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[3\] 0 " "Info: Pin \"SRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[4\] 0 " "Info: Pin \"SRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[5\] 0 " "Info: Pin \"SRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[6\] 0 " "Info: Pin \"SRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[7\] 0 " "Info: Pin \"SRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[8\] 0 " "Info: Pin \"SRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[9\] 0 " "Info: Pin \"SRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[10\] 0 " "Info: Pin \"SRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[11\] 0 " "Info: Pin \"SRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[12\] 0 " "Info: Pin \"SRAM_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[13\] 0 " "Info: Pin \"SRAM_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[14\] 0 " "Info: Pin \"SRAM_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[15\] 0 " "Info: Pin \"SRAM_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[16\] 0 " "Info: Pin \"SRAM_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[17\] 0 " "Info: Pin \"SRAM_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_UB_N 0 " "Info: Pin \"SRAM_UB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_LB_N 0 " "Info: Pin \"SRAM_LB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_WE_N 0 " "Info: Pin \"SRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_CE_N 0 " "Info: Pin \"SRAM_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_OE_N 0 " "Info: Pin \"SRAM_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CLK 0 " "Info: Pin \"SD_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TDO 0 " "Info: Pin \"TDO\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SCLK 0 " "Info: Pin \"I2C_SCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_HS 0 " "Info: Pin \"VGA_HS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_VS 0 " "Info: Pin \"VGA_VS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[0\] 0 " "Info: Pin \"VGA_R\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[1\] 0 " "Info: Pin \"VGA_R\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[2\] 0 " "Info: Pin \"VGA_R\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[3\] 0 " "Info: Pin \"VGA_R\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[0\] 0 " "Info: Pin \"VGA_G\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[1\] 0 " "Info: Pin \"VGA_G\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[2\] 0 " "Info: Pin \"VGA_G\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[3\] 0 " "Info: Pin \"VGA_G\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[0\] 0 " "Info: Pin \"VGA_B\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[1\] 0 " "Info: Pin \"VGA_B\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[2\] 0 " "Info: Pin \"VGA_B\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[3\] 0 " "Info: Pin \"VGA_B\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACDAT 0 " "Info: Pin \"AUD_DACDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_XCK 0 " "Info: Pin \"AUD_XCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT3 0 " "Info: Pin \"SD_DAT3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CMD 0 " "Info: Pin \"SD_CMD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_ADCLRCK 0 " "Info: Pin \"AUD_ADCLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_BCLK 0 " "Info: Pin \"AUD_BCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[0\] 0 " "Info: Pin \"DRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[1\] 0 " "Info: Pin \"DRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[2\] 0 " "Info: Pin \"DRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[3\] 0 " "Info: Pin \"DRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[4\] 0 " "Info: Pin \"DRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[5\] 0 " "Info: Pin \"DRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[6\] 0 " "Info: Pin \"DRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[7\] 0 " "Info: Pin \"DRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[8\] 0 " "Info: Pin \"DRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[9\] 0 " "Info: Pin \"DRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[10\] 0 " "Info: Pin \"DRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[11\] 0 " "Info: Pin \"DRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[12\] 0 " "Info: Pin \"DRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[13\] 0 " "Info: Pin \"DRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[14\] 0 " "Info: Pin \"DRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[15\] 0 " "Info: Pin \"DRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[0\] 0 " "Info: Pin \"FL_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[1\] 0 " "Info: Pin \"FL_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[2\] 0 " "Info: Pin \"FL_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[3\] 0 " "Info: Pin \"FL_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[4\] 0 " "Info: Pin \"FL_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[5\] 0 " "Info: Pin \"FL_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[6\] 0 " "Info: Pin \"FL_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[7\] 0 " "Info: Pin \"FL_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[0\] 0 " "Info: Pin \"SRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[1\] 0 " "Info: Pin \"SRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[2\] 0 " "Info: Pin \"SRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[3\] 0 " "Info: Pin \"SRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[4\] 0 " "Info: Pin \"SRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[5\] 0 " "Info: Pin \"SRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[6\] 0 " "Info: Pin \"SRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[7\] 0 " "Info: Pin \"SRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[8\] 0 " "Info: Pin \"SRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[9\] 0 " "Info: Pin \"SRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[10\] 0 " "Info: Pin \"SRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[11\] 0 " "Info: Pin \"SRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[12\] 0 " "Info: Pin \"SRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[13\] 0 " "Info: Pin \"SRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[14\] 0 " "Info: Pin \"SRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[15\] 0 " "Info: Pin \"SRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT 0 " "Info: Pin \"SD_DAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SDAT 0 " "Info: Pin \"I2C_SDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACLRCK 0 " "Info: Pin \"AUD_DACLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[0\] 0 " "Info: Pin \"GPIO_0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[1\] 0 " "Info: Pin \"GPIO_0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[2\] 0 " "Info: Pin \"GPIO_0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[3\] 0 " "Info: Pin \"GPIO_0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[4\] 0 " "Info: Pin \"GPIO_0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[5\] 0 " "Info: Pin \"GPIO_0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[6\] 0 " "Info: Pin \"GPIO_0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[7\] 0 " "Info: Pin \"GPIO_0\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[8\] 0 " "Info: Pin \"GPIO_0\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[9\] 0 " "Info: Pin \"GPIO_0\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[10\] 0 " "Info: Pin \"GPIO_0\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[11\] 0 " "Info: Pin \"GPIO_0\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[12\] 0 " "Info: Pin \"GPIO_0\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[13\] 0 " "Info: Pin \"GPIO_0\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[14\] 0 " "Info: Pin \"GPIO_0\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[15\] 0 " "Info: Pin \"GPIO_0\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[16\] 0 " "Info: Pin \"GPIO_0\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[17\] 0 " "Info: Pin \"GPIO_0\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[18\] 0 " "Info: Pin \"GPIO_0\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[19\] 0 " "Info: Pin \"GPIO_0\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[20\] 0 " "Info: Pin \"GPIO_0\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[21\] 0 " "Info: Pin \"GPIO_0\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[22\] 0 " "Info: Pin \"GPIO_0\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[23\] 0 " "Info: Pin \"GPIO_0\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[24\] 0 " "Info: Pin \"GPIO_0\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[25\] 0 " "Info: Pin \"GPIO_0\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[26\] 0 " "Info: Pin \"GPIO_0\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[27\] 0 " "Info: Pin \"GPIO_0\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[28\] 0 " "Info: Pin \"GPIO_0\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[29\] 0 " "Info: Pin \"GPIO_0\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[30\] 0 " "Info: Pin \"GPIO_0\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[31\] 0 " "Info: Pin \"GPIO_0\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[32\] 0 " "Info: Pin \"GPIO_0\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[33\] 0 " "Info: Pin \"GPIO_0\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[34\] 0 " "Info: Pin \"GPIO_0\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[35\] 0 " "Info: Pin \"GPIO_0\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[0\] 0 " "Info: Pin \"GPIO_1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[1\] 0 " "Info: Pin \"GPIO_1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[2\] 0 " "Info: Pin \"GPIO_1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[3\] 0 " "Info: Pin \"GPIO_1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[4\] 0 " "Info: Pin \"GPIO_1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[5\] 0 " "Info: Pin \"GPIO_1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[6\] 0 " "Info: Pin \"GPIO_1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[7\] 0 " "Info: Pin \"GPIO_1\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[8\] 0 " "Info: Pin \"GPIO_1\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[9\] 0 " "Info: Pin \"GPIO_1\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[10\] 0 " "Info: Pin \"GPIO_1\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[11\] 0 " "Info: Pin \"GPIO_1\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[12\] 0 " "Info: Pin \"GPIO_1\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[13\] 0 " "Info: Pin \"GPIO_1\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[14\] 0 " "Info: Pin \"GPIO_1\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[15\] 0 " "Info: Pin \"GPIO_1\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[16\] 0 " "Info: Pin \"GPIO_1\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[17\] 0 " "Info: Pin \"GPIO_1\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[18\] 0 " "Info: Pin \"GPIO_1\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[19\] 0 " "Info: Pin \"GPIO_1\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[20\] 0 " "Info: Pin \"GPIO_1\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[21\] 0 " "Info: Pin \"GPIO_1\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[22\] 0 " "Info: Pin \"GPIO_1\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[23\] 0 " "Info: Pin \"GPIO_1\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[24\] 0 " "Info: Pin \"GPIO_1\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[25\] 0 " "Info: Pin \"GPIO_1\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[26\] 0 " "Info: Pin \"GPIO_1\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[27\] 0 " "Info: Pin \"GPIO_1\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[28\] 0 " "Info: Pin \"GPIO_1\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[29\] 0 " "Info: Pin \"GPIO_1\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[30\] 0 " "Info: Pin \"GPIO_1\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[31\] 0 " "Info: Pin \"GPIO_1\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[32\] 0 " "Info: Pin \"GPIO_1\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[33\] 0 " "Info: Pin \"GPIO_1\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[34\] 0 " "Info: Pin \"GPIO_1\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[35\] 0 " "Info: Pin \"GPIO_1\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "118 " "Warning: Following 118 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SD_DAT3 a permanently disabled " "Info: Pin SD_DAT3 has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 177 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SD_CMD a permanently disabled " "Info: Pin SD_CMD has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 178 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_ADCLRCK a permanently disabled " "Info: Pin AUD_ADCLRCK has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 198 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_BCLK a permanently disabled " "Info: Pin AUD_BCLK has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 202 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[0\] a permanently disabled " "Info: Pin DRAM_DQ\[0\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[1\] a permanently disabled " "Info: Pin DRAM_DQ\[1\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[2\] a permanently disabled " "Info: Pin DRAM_DQ\[2\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[3\] a permanently disabled " "Info: Pin DRAM_DQ\[3\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[4\] a permanently disabled " "Info: Pin DRAM_DQ\[4\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[5\] a permanently disabled " "Info: Pin DRAM_DQ\[5\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[6\] a permanently disabled " "Info: Pin DRAM_DQ\[6\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[7\] a permanently disabled " "Info: Pin DRAM_DQ\[7\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[8\] a permanently disabled " "Info: Pin DRAM_DQ\[8\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[9\] a permanently disabled " "Info: Pin DRAM_DQ\[9\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[10\] a permanently disabled " "Info: Pin DRAM_DQ\[10\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[11\] a permanently disabled " "Info: Pin DRAM_DQ\[11\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[12\] a permanently disabled " "Info: Pin DRAM_DQ\[12\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[13\] a permanently disabled " "Info: Pin DRAM_DQ\[13\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[14\] a permanently disabled " "Info: Pin DRAM_DQ\[14\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[15\] a permanently disabled " "Info: Pin DRAM_DQ\[15\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[0\] a permanently disabled " "Info: Pin FL_DQ\[0\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[1\] a permanently disabled " "Info: Pin FL_DQ\[1\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[2\] a permanently disabled " "Info: Pin FL_DQ\[2\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[3\] a permanently disabled " "Info: Pin FL_DQ\[3\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[4\] a permanently disabled " "Info: Pin FL_DQ\[4\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[5\] a permanently disabled " "Info: Pin FL_DQ\[5\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[6\] a permanently disabled " "Info: Pin FL_DQ\[6\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[7\] a permanently disabled " "Info: Pin FL_DQ\[7\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[0\] a permanently disabled " "Info: Pin SRAM_DQ\[0\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[1\] a permanently disabled " "Info: Pin SRAM_DQ\[1\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[2\] a permanently disabled " "Info: Pin SRAM_DQ\[2\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[3\] a permanently disabled " "Info: Pin SRAM_DQ\[3\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[4\] a permanently disabled " "Info: Pin SRAM_DQ\[4\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[5\] a permanently disabled " "Info: Pin SRAM_DQ\[5\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[6\] a permanently disabled " "Info: Pin SRAM_DQ\[6\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[7\] a permanently disabled " "Info: Pin SRAM_DQ\[7\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[8\] a permanently disabled " "Info: Pin SRAM_DQ\[8\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[9\] a permanently disabled " "Info: Pin SRAM_DQ\[9\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[10\] a permanently disabled " "Info: Pin SRAM_DQ\[10\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[11\] a permanently disabled " "Info: Pin SRAM_DQ\[11\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[12\] a permanently disabled " "Info: Pin SRAM_DQ\[12\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[13\] a permanently disabled " "Info: Pin SRAM_DQ\[13\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[14\] a permanently disabled " "Info: Pin SRAM_DQ\[14\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[15\] a permanently disabled " "Info: Pin SRAM_DQ\[15\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SD_DAT a permanently disabled " "Info: Pin SD_DAT has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 176 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_DACLRCK a permanently enabled " "Info: Pin AUD_DACLRCK has a permanently enabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 200 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[0\] a permanently disabled " "Info: Pin GPIO_0\[0\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[1\] a permanently disabled " "Info: Pin GPIO_0\[1\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[2\] a permanently disabled " "Info: Pin GPIO_0\[2\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[3\] a permanently disabled " "Info: Pin GPIO_0\[3\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[4\] a permanently disabled " "Info: Pin GPIO_0\[4\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[5\] a permanently disabled " "Info: Pin GPIO_0\[5\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[6\] a permanently disabled " "Info: Pin GPIO_0\[6\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[7\] a permanently disabled " "Info: Pin GPIO_0\[7\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[8\] a permanently disabled " "Info: Pin GPIO_0\[8\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[9\] a permanently disabled " "Info: Pin GPIO_0\[9\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[10\] a permanently disabled " "Info: Pin GPIO_0\[10\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[11\] a permanently disabled " "Info: Pin GPIO_0\[11\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[12\] a permanently disabled " "Info: Pin GPIO_0\[12\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[13\] a permanently disabled " "Info: Pin GPIO_0\[13\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[14\] a permanently disabled " "Info: Pin GPIO_0\[14\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[15\] a permanently disabled " "Info: Pin GPIO_0\[15\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[16\] a permanently disabled " "Info: Pin GPIO_0\[16\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[17\] a permanently disabled " "Info: Pin GPIO_0\[17\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[18\] a permanently disabled " "Info: Pin GPIO_0\[18\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[19\] a permanently disabled " "Info: Pin GPIO_0\[19\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[20\] a permanently disabled " "Info: Pin GPIO_0\[20\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[21\] a permanently disabled " "Info: Pin GPIO_0\[21\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[22\] a permanently disabled " "Info: Pin GPIO_0\[22\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[23\] a permanently disabled " "Info: Pin GPIO_0\[23\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[24\] a permanently disabled " "Info: Pin GPIO_0\[24\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[25\] a permanently disabled " "Info: Pin GPIO_0\[25\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[26\] a permanently disabled " "Info: Pin GPIO_0\[26\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[27\] a permanently disabled " "Info: Pin GPIO_0\[27\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[28\] a permanently disabled " "Info: Pin GPIO_0\[28\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[29\] a permanently disabled " "Info: Pin GPIO_0\[29\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[30\] a permanently disabled " "Info: Pin GPIO_0\[30\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[31\] a permanently disabled " "Info: Pin GPIO_0\[31\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[32\] a permanently disabled " "Info: Pin GPIO_0\[32\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[33\] a permanently disabled " "Info: Pin GPIO_0\[33\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[34\] a permanently disabled " "Info: Pin GPIO_0\[34\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[35\] a permanently disabled " "Info: Pin GPIO_0\[35\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Info: Pin GPIO_1\[0\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Info: Pin GPIO_1\[1\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Info: Pin GPIO_1\[2\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Info: Pin GPIO_1\[3\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Info: Pin GPIO_1\[4\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Info: Pin GPIO_1\[5\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Info: Pin GPIO_1\[6\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Info: Pin GPIO_1\[7\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Info: Pin GPIO_1\[8\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Info: Pin GPIO_1\[9\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Info: Pin GPIO_1\[10\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Info: Pin GPIO_1\[11\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Info: Pin GPIO_1\[12\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Info: Pin GPIO_1\[13\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Info: Pin GPIO_1\[14\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Info: Pin GPIO_1\[15\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Info: Pin GPIO_1\[16\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Info: Pin GPIO_1\[17\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Info: Pin GPIO_1\[18\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Info: Pin GPIO_1\[19\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Info: Pin GPIO_1\[20\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Info: Pin GPIO_1\[21\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Info: Pin GPIO_1\[22\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Info: Pin GPIO_1\[23\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Info: Pin GPIO_1\[24\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Info: Pin GPIO_1\[25\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Info: Pin GPIO_1\[26\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Info: Pin GPIO_1\[27\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Info: Pin GPIO_1\[28\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Info: Pin GPIO_1\[29\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Info: Pin GPIO_1\[30\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Info: Pin GPIO_1\[31\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Info: Pin GPIO_1\[32\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently disabled " "Info: Pin GPIO_1\[33\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[34\] a permanently disabled " "Info: Pin GPIO_1\[34\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[35\] a permanently disabled " "Info: Pin GPIO_1\[35\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "245 " "Warning: Following 245 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[0\] GND " "Info: Pin HEX0\[0\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 137 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[1\] GND " "Info: Pin HEX0\[1\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 137 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[2\] GND " "Info: Pin HEX0\[2\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 137 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[3\] GND " "Info: Pin HEX0\[3\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 137 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[4\] GND " "Info: Pin HEX0\[4\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 137 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[5\] GND " "Info: Pin HEX0\[5\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 137 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[6\] GND " "Info: Pin HEX0\[6\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 137 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[0\] GND " "Info: Pin HEX1\[0\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 138 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[1\] GND " "Info: Pin HEX1\[1\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 138 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[2\] GND " "Info: Pin HEX1\[2\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 138 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[3\] GND " "Info: Pin HEX1\[3\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 138 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[4\] GND " "Info: Pin HEX1\[4\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 138 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[5\] GND " "Info: Pin HEX1\[5\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 138 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[6\] GND " "Info: Pin HEX1\[6\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 138 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[0\] GND " "Info: Pin HEX2\[0\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 139 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[1\] GND " "Info: Pin HEX2\[1\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 139 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[2\] GND " "Info: Pin HEX2\[2\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 139 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[3\] GND " "Info: Pin HEX2\[3\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 139 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[4\] GND " "Info: Pin HEX2\[4\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 139 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[5\] GND " "Info: Pin HEX2\[5\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 139 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[6\] GND " "Info: Pin HEX2\[6\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 139 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[0\] GND " "Info: Pin HEX3\[0\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 140 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[1\] GND " "Info: Pin HEX3\[1\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 140 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[2\] GND " "Info: Pin HEX3\[2\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 140 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[3\] GND " "Info: Pin HEX3\[3\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 140 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[4\] GND " "Info: Pin HEX3\[4\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 140 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[5\] GND " "Info: Pin HEX3\[5\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 140 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[6\] GND " "Info: Pin HEX3\[6\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 140 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[7\] GND " "Info: Pin LEDG\[7\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 142 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[0\] VCC " "Info: Pin LEDR\[0\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 143 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[1\] VCC " "Info: Pin LEDR\[1\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 143 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[2\] VCC " "Info: Pin LEDR\[2\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 143 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[3\] VCC " "Info: Pin LEDR\[3\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 143 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[4\] VCC " "Info: Pin LEDR\[4\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 143 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[5\] VCC " "Info: Pin LEDR\[5\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 143 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[6\] VCC " "Info: Pin LEDR\[6\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 143 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[7\] VCC " "Info: Pin LEDR\[7\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 143 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[8\] VCC " "Info: Pin LEDR\[8\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 143 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[9\] VCC " "Info: Pin LEDR\[9\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 143 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "UART_TXD GND " "Info: Pin UART_TXD has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 145 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_TXD } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_TXD } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[0\] GND " "Info: Pin DRAM_ADDR\[0\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 149 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[1\] GND " "Info: Pin DRAM_ADDR\[1\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 149 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[2\] GND " "Info: Pin DRAM_ADDR\[2\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 149 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[3\] GND " "Info: Pin DRAM_ADDR\[3\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 149 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[4\] GND " "Info: Pin DRAM_ADDR\[4\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 149 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[5\] GND " "Info: Pin DRAM_ADDR\[5\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 149 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[6\] GND " "Info: Pin DRAM_ADDR\[6\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 149 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[7\] GND " "Info: Pin DRAM_ADDR\[7\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 149 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[8\] GND " "Info: Pin DRAM_ADDR\[8\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 149 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[9\] GND " "Info: Pin DRAM_ADDR\[9\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 149 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[10\] GND " "Info: Pin DRAM_ADDR\[10\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 149 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[11\] GND " "Info: Pin DRAM_ADDR\[11\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 149 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_LDQM GND " "Info: Pin DRAM_LDQM has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 150 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_LDQM" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_LDQM } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_LDQM } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_UDQM GND " "Info: Pin DRAM_UDQM has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 151 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_UDQM" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_UDQM } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_UDQM } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_WE_N GND " "Info: Pin DRAM_WE_N has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 152 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_WE_N } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_WE_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CAS_N GND " "Info: Pin DRAM_CAS_N has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 153 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CAS_N } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CAS_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_RAS_N GND " "Info: Pin DRAM_RAS_N has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 154 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_RAS_N } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_RAS_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CS_N GND " "Info: Pin DRAM_CS_N has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 155 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CS_N } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CS_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_BA_0 GND " "Info: Pin DRAM_BA_0 has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 156 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_BA_0" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_BA_0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_BA_0 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_BA_1 GND " "Info: Pin DRAM_BA_1 has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 157 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_BA_1" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_BA_1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_BA_1 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CLK GND " "Info: Pin DRAM_CLK has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 158 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CKE GND " "Info: Pin DRAM_CKE has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 159 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CKE } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CKE } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[0\] GND " "Info: Pin FL_ADDR\[0\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[1\] GND " "Info: Pin FL_ADDR\[1\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[2\] GND " "Info: Pin FL_ADDR\[2\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[3\] GND " "Info: Pin FL_ADDR\[3\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[4\] GND " "Info: Pin FL_ADDR\[4\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[5\] GND " "Info: Pin FL_ADDR\[5\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[6\] GND " "Info: Pin FL_ADDR\[6\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[7\] GND " "Info: Pin FL_ADDR\[7\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[8\] GND " "Info: Pin FL_ADDR\[8\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[9\] GND " "Info: Pin FL_ADDR\[9\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[10\] GND " "Info: Pin FL_ADDR\[10\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[11\] GND " "Info: Pin FL_ADDR\[11\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[12\] GND " "Info: Pin FL_ADDR\[12\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[13\] GND " "Info: Pin FL_ADDR\[13\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[14\] GND " "Info: Pin FL_ADDR\[14\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[15\] GND " "Info: Pin FL_ADDR\[15\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[16\] GND " "Info: Pin FL_ADDR\[16\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[16] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[17\] GND " "Info: Pin FL_ADDR\[17\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[18\] GND " "Info: Pin FL_ADDR\[18\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[18] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[19\] GND " "Info: Pin FL_ADDR\[19\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[19] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[20\] GND " "Info: Pin FL_ADDR\[20\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[20] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[21\] GND " "Info: Pin FL_ADDR\[21\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 162 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[21] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_WE_N GND " "Info: Pin FL_WE_N has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 163 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_WE_N } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_WE_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_RST_N GND " "Info: Pin FL_RST_N has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 164 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_RST_N } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_RST_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_OE_N GND " "Info: Pin FL_OE_N has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 165 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_OE_N } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_OE_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_CE_N GND " "Info: Pin FL_CE_N has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 166 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_CE_N } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_CE_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[0\] GND " "Info: Pin SRAM_ADDR\[0\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[1\] GND " "Info: Pin SRAM_ADDR\[1\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[2\] GND " "Info: Pin SRAM_ADDR\[2\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[3\] GND " "Info: Pin SRAM_ADDR\[3\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[4\] GND " "Info: Pin SRAM_ADDR\[4\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[5\] GND " "Info: Pin SRAM_ADDR\[5\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[6\] GND " "Info: Pin SRAM_ADDR\[6\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[7\] GND " "Info: Pin SRAM_ADDR\[7\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[8\] GND " "Info: Pin SRAM_ADDR\[8\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[9\] GND " "Info: Pin SRAM_ADDR\[9\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[10\] GND " "Info: Pin SRAM_ADDR\[10\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[11\] GND " "Info: Pin SRAM_ADDR\[11\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[12\] GND " "Info: Pin SRAM_ADDR\[12\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[13\] GND " "Info: Pin SRAM_ADDR\[13\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[14\] GND " "Info: Pin SRAM_ADDR\[14\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[15\] GND " "Info: Pin SRAM_ADDR\[15\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[16\] GND " "Info: Pin SRAM_ADDR\[16\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[16] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[17\] GND " "Info: Pin SRAM_ADDR\[17\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 169 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_UB_N GND " "Info: Pin SRAM_UB_N has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 170 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_UB_N } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_UB_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_LB_N GND " "Info: Pin SRAM_LB_N has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 171 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_LB_N } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_LB_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_WE_N GND " "Info: Pin SRAM_WE_N has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 172 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_WE_N } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_WE_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_CE_N GND " "Info: Pin SRAM_CE_N has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 173 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_CE_N } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_CE_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_OE_N GND " "Info: Pin SRAM_OE_N has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 174 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_OE_N } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_OE_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_CLK GND " "Info: Pin SD_CLK has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 179 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TDO GND " "Info: Pin TDO has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 190 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "TDO" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { TDO } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { TDO } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_HS GND " "Info: Pin VGA_HS has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 192 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_HS } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_HS } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_VS GND " "Info: Pin VGA_VS has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 193 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_VS } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_VS } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[0\] GND " "Info: Pin VGA_R\[0\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 194 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[1\] GND " "Info: Pin VGA_R\[1\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 194 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[2\] GND " "Info: Pin VGA_R\[2\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 194 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[3\] GND " "Info: Pin VGA_R\[3\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 194 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[0\] GND " "Info: Pin VGA_G\[0\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 195 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[1\] GND " "Info: Pin VGA_G\[1\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 195 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[2\] GND " "Info: Pin VGA_G\[2\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 195 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[3\] GND " "Info: Pin VGA_G\[3\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 195 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[0\] GND " "Info: Pin VGA_B\[0\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 196 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[1\] GND " "Info: Pin VGA_B\[1\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 196 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[2\] GND " "Info: Pin VGA_B\[2\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 196 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[3\] GND " "Info: Pin VGA_B\[3\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 196 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_DACDAT GND " "Info: Pin AUD_DACDAT has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 201 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACDAT } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACDAT } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_DAT3 VCC " "Info: Pin SD_DAT3 has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 177 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_CMD VCC " "Info: Pin SD_CMD has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 178 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_ADCLRCK VCC " "Info: Pin AUD_ADCLRCK has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 198 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_BCLK VCC " "Info: Pin AUD_BCLK has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 202 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[0\] VCC " "Info: Pin DRAM_DQ\[0\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[1\] VCC " "Info: Pin DRAM_DQ\[1\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[2\] VCC " "Info: Pin DRAM_DQ\[2\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[3\] VCC " "Info: Pin DRAM_DQ\[3\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[4\] VCC " "Info: Pin DRAM_DQ\[4\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[5\] VCC " "Info: Pin DRAM_DQ\[5\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[6\] VCC " "Info: Pin DRAM_DQ\[6\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[7\] VCC " "Info: Pin DRAM_DQ\[7\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[8\] VCC " "Info: Pin DRAM_DQ\[8\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[9\] VCC " "Info: Pin DRAM_DQ\[9\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[10\] VCC " "Info: Pin DRAM_DQ\[10\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[11\] VCC " "Info: Pin DRAM_DQ\[11\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[12\] VCC " "Info: Pin DRAM_DQ\[12\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[13\] VCC " "Info: Pin DRAM_DQ\[13\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[14\] VCC " "Info: Pin DRAM_DQ\[14\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[15\] VCC " "Info: Pin DRAM_DQ\[15\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[0\] VCC " "Info: Pin FL_DQ\[0\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[1\] VCC " "Info: Pin FL_DQ\[1\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[2\] VCC " "Info: Pin FL_DQ\[2\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[3\] VCC " "Info: Pin FL_DQ\[3\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[4\] VCC " "Info: Pin FL_DQ\[4\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[5\] VCC " "Info: Pin FL_DQ\[5\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[6\] VCC " "Info: Pin FL_DQ\[6\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[7\] VCC " "Info: Pin FL_DQ\[7\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[0\] VCC " "Info: Pin SRAM_DQ\[0\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[1\] VCC " "Info: Pin SRAM_DQ\[1\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[2\] VCC " "Info: Pin SRAM_DQ\[2\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[3\] VCC " "Info: Pin SRAM_DQ\[3\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[4\] VCC " "Info: Pin SRAM_DQ\[4\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[5\] VCC " "Info: Pin SRAM_DQ\[5\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[6\] VCC " "Info: Pin SRAM_DQ\[6\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[7\] VCC " "Info: Pin SRAM_DQ\[7\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[8\] VCC " "Info: Pin SRAM_DQ\[8\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[9\] VCC " "Info: Pin SRAM_DQ\[9\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[10\] VCC " "Info: Pin SRAM_DQ\[10\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[11\] VCC " "Info: Pin SRAM_DQ\[11\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[12\] VCC " "Info: Pin SRAM_DQ\[12\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[13\] VCC " "Info: Pin SRAM_DQ\[13\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[14\] VCC " "Info: Pin SRAM_DQ\[14\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[15\] VCC " "Info: Pin SRAM_DQ\[15\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_DAT VCC " "Info: Pin SD_DAT has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 176 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[0\] VCC " "Info: Pin GPIO_0\[0\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[1\] VCC " "Info: Pin GPIO_0\[1\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[2\] VCC " "Info: Pin GPIO_0\[2\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[3\] VCC " "Info: Pin GPIO_0\[3\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[4\] VCC " "Info: Pin GPIO_0\[4\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[5\] VCC " "Info: Pin GPIO_0\[5\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[6\] VCC " "Info: Pin GPIO_0\[6\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[7\] VCC " "Info: Pin GPIO_0\[7\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[8\] VCC " "Info: Pin GPIO_0\[8\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[9\] VCC " "Info: Pin GPIO_0\[9\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[10\] VCC " "Info: Pin GPIO_0\[10\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[11\] VCC " "Info: Pin GPIO_0\[11\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[12\] VCC " "Info: Pin GPIO_0\[12\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[13\] VCC " "Info: Pin GPIO_0\[13\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[14\] VCC " "Info: Pin GPIO_0\[14\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[15\] VCC " "Info: Pin GPIO_0\[15\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[16\] VCC " "Info: Pin GPIO_0\[16\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[17\] VCC " "Info: Pin GPIO_0\[17\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[18\] VCC " "Info: Pin GPIO_0\[18\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[19\] VCC " "Info: Pin GPIO_0\[19\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[20\] VCC " "Info: Pin GPIO_0\[20\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[21\] VCC " "Info: Pin GPIO_0\[21\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[22\] VCC " "Info: Pin GPIO_0\[22\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[23\] VCC " "Info: Pin GPIO_0\[23\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[24\] VCC " "Info: Pin GPIO_0\[24\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[25\] VCC " "Info: Pin GPIO_0\[25\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[26\] VCC " "Info: Pin GPIO_0\[26\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[27\] VCC " "Info: Pin GPIO_0\[27\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[28\] VCC " "Info: Pin GPIO_0\[28\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[29\] VCC " "Info: Pin GPIO_0\[29\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[30\] VCC " "Info: Pin GPIO_0\[30\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[31\] VCC " "Info: Pin GPIO_0\[31\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[32\] VCC " "Info: Pin GPIO_0\[32\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[33\] VCC " "Info: Pin GPIO_0\[33\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[34\] VCC " "Info: Pin GPIO_0\[34\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[35\] VCC " "Info: Pin GPIO_0\[35\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[0\] VCC " "Info: Pin GPIO_1\[0\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[1\] VCC " "Info: Pin GPIO_1\[1\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[2\] VCC " "Info: Pin GPIO_1\[2\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[3\] VCC " "Info: Pin GPIO_1\[3\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[4\] VCC " "Info: Pin GPIO_1\[4\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[5\] VCC " "Info: Pin GPIO_1\[5\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[6\] VCC " "Info: Pin GPIO_1\[6\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[7\] VCC " "Info: Pin GPIO_1\[7\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[8\] VCC " "Info: Pin GPIO_1\[8\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[9\] VCC " "Info: Pin GPIO_1\[9\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[10\] VCC " "Info: Pin GPIO_1\[10\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[11\] VCC " "Info: Pin GPIO_1\[11\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[12\] VCC " "Info: Pin GPIO_1\[12\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[13\] VCC " "Info: Pin GPIO_1\[13\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[14\] VCC " "Info: Pin GPIO_1\[14\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[15\] VCC " "Info: Pin GPIO_1\[15\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[16\] VCC " "Info: Pin GPIO_1\[16\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[17\] VCC " "Info: Pin GPIO_1\[17\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[18\] VCC " "Info: Pin GPIO_1\[18\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[19\] VCC " "Info: Pin GPIO_1\[19\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[20\] VCC " "Info: Pin GPIO_1\[20\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[21\] VCC " "Info: Pin GPIO_1\[21\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[22\] VCC " "Info: Pin GPIO_1\[22\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[23\] VCC " "Info: Pin GPIO_1\[23\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[24\] VCC " "Info: Pin GPIO_1\[24\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[25\] VCC " "Info: Pin GPIO_1\[25\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[26\] VCC " "Info: Pin GPIO_1\[26\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[27\] VCC " "Info: Pin GPIO_1\[27\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[28\] VCC " "Info: Pin GPIO_1\[28\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[29\] VCC " "Info: Pin GPIO_1\[29\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[30\] VCC " "Info: Pin GPIO_1\[30\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[31\] VCC " "Info: Pin GPIO_1\[31\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[32\] VCC " "Info: Pin GPIO_1\[32\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[33\] VCC " "Info: Pin GPIO_1\[33\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[34\] VCC " "Info: Pin GPIO_1\[34\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[35\] VCC " "Info: Pin GPIO_1\[35\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "I2C_AV_Config:u1\|I2C_Controller:u0\|SDO " "Info: Following pins have the same output enable: I2C_AV_Config:u1\|I2C_Controller:u0\|SDO" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional I2C_SDAT 3.3-V LVTTL " "Info: Type bidirectional pin I2C_SDAT uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.v" 181 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.fit.smsg " "Info: Generated suppressed messages file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_i2sound/DE1_i2sound.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "216 " "Info: Allocated 216 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 30 15:40:56 2007 " "Info: Processing ended: Thu Aug 30 15:40:56 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}