--altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone II" INIT_FILE="epcs_controller_boot_rom.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=128 OPERATION_MODE="ROM" OUTDATA_REG_A="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTHAD_A=7 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 --VERSION_BEGIN 7.1SP1 cbx_altsyncram 2007:03:22:08:29:24:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_lpm_mux 2006:11:21:10:27:10:SJ cbx_mgl 2007:06:11:08:05:04:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_stratixiii 2007:03:13:14:47:12:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ VERSION_END -- Copyright (C) 1991-2007 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. PARAMETERS ( PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_DATA_WIDTH = 1, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_DATA_WIDTH = 1 ); FUNCTION cycloneii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe) WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH, PORT_A_BYTE_ENABLE_MASK_WIDTH, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE) RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); --synthesis_resources = M4K 1 OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; SUBDESIGN altsyncram_lo31 ( address_a[6..0] : input; clock0 : input; q_a[31..0] : output; ) VARIABLE ram_block1a0 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a1 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a2 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 2, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a3 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 3, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a4 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 4, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a5 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 5, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a6 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 6, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a7 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 7, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a8 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 8, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a9 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 9, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a10 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 10, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a11 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 11, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a12 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 12, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a13 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 13, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a14 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 14, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a15 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 15, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a16 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 16, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a17 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 17, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a18 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 18, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a19 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 19, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a20 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 20, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a21 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 21, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a22 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 22, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a23 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 23, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a24 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 24, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a25 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 25, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a26 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 26, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a27 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 27, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a28 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 28, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a29 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 29, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a30 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 30, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a31 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "epcs_controller_boot_rom.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 31, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 32, RAM_BLOCK_TYPE = "AUTO" ); address_a_wire[6..0] : WIRE; BEGIN ram_block1a[31..0].clk0 = clock0; ram_block1a[31..0].portaaddr[] = ( address_a_wire[6..0]); address_a_wire[] = address_a[]; q_a[] = ( ram_block1a[31..0].portadataout[0..0]); END; --VALID FILE