--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone II" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=6 WIDTHAD_B=6 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 --VERSION_BEGIN 7.1SP1 cbx_altsyncram 2007:03:22:08:29:24:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_lpm_mux 2006:11:21:10:27:10:SJ cbx_mgl 2007:06:11:08:05:04:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_stratixiii 2007:03:13:14:47:12:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ VERSION_END -- Copyright (C) 1991-2007 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. PARAMETERS ( PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_DATA_WIDTH = 1, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_DATA_WIDTH = 1 ); FUNCTION cycloneii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe) WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH, PORT_A_BYTE_ENABLE_MASK_WIDTH, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE) RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); --synthesis_resources = M4K 1 OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; SUBDESIGN altsyncram_9tl1 ( address_a[5..0] : input; address_b[5..0] : input; clock0 : input; clock1 : input; clocken1 : input; data_a[7..0] : input; q_b[7..0] : output; wren_a : input; ) VARIABLE ram_block3a0 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 6, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 63, PORT_A_LOGICAL_RAM_DEPTH = 64, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 6, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 63, PORT_B_LOGICAL_RAM_DEPTH = 64, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "AUTO" ); ram_block3a1 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 6, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 63, PORT_A_LOGICAL_RAM_DEPTH = 64, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 6, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 1, PORT_B_LAST_ADDRESS = 63, PORT_B_LOGICAL_RAM_DEPTH = 64, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "AUTO" ); ram_block3a2 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 6, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 2, PORT_A_LAST_ADDRESS = 63, PORT_A_LOGICAL_RAM_DEPTH = 64, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 6, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 2, PORT_B_LAST_ADDRESS = 63, PORT_B_LOGICAL_RAM_DEPTH = 64, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "AUTO" ); ram_block3a3 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 6, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 3, PORT_A_LAST_ADDRESS = 63, PORT_A_LOGICAL_RAM_DEPTH = 64, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 6, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 3, PORT_B_LAST_ADDRESS = 63, PORT_B_LOGICAL_RAM_DEPTH = 64, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "AUTO" ); ram_block3a4 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 6, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 4, PORT_A_LAST_ADDRESS = 63, PORT_A_LOGICAL_RAM_DEPTH = 64, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 6, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 4, PORT_B_LAST_ADDRESS = 63, PORT_B_LOGICAL_RAM_DEPTH = 64, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "AUTO" ); ram_block3a5 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 6, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 5, PORT_A_LAST_ADDRESS = 63, PORT_A_LOGICAL_RAM_DEPTH = 64, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 6, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 5, PORT_B_LAST_ADDRESS = 63, PORT_B_LOGICAL_RAM_DEPTH = 64, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "AUTO" ); ram_block3a6 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 6, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 6, PORT_A_LAST_ADDRESS = 63, PORT_A_LOGICAL_RAM_DEPTH = 64, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 6, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 6, PORT_B_LAST_ADDRESS = 63, PORT_B_LOGICAL_RAM_DEPTH = 64, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "AUTO" ); ram_block3a7 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 6, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 7, PORT_A_LAST_ADDRESS = 63, PORT_A_LOGICAL_RAM_DEPTH = 64, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 6, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 7, PORT_B_LAST_ADDRESS = 63, PORT_B_LOGICAL_RAM_DEPTH = 64, PORT_B_LOGICAL_RAM_WIDTH = 8, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "AUTO" ); address_a_wire[5..0] : WIRE; address_b_wire[5..0] : WIRE; BEGIN ram_block3a[7..0].clk0 = clock0; ram_block3a[7..0].clk1 = clock1; ram_block3a[7..0].ena0 = wren_a; ram_block3a[7..0].ena1 = clocken1; ram_block3a[7..0].portaaddr[] = ( address_a_wire[5..0]); ram_block3a[0].portadatain[] = ( data_a[0..0]); ram_block3a[1].portadatain[] = ( data_a[1..1]); ram_block3a[2].portadatain[] = ( data_a[2..2]); ram_block3a[3].portadatain[] = ( data_a[3..3]); ram_block3a[4].portadatain[] = ( data_a[4..4]); ram_block3a[5].portadatain[] = ( data_a[5..5]); ram_block3a[6].portadatain[] = ( data_a[6..6]); ram_block3a[7].portadatain[] = ( data_a[7..7]); ram_block3a[7..0].portawe = B"11111111"; ram_block3a[7..0].portbaddr[] = ( address_b_wire[5..0]); ram_block3a[7..0].portbrewe = B"11111111"; address_a_wire[] = address_a[]; address_b_wire[] = address_b[]; q_b[] = ( ram_block3a[7..0].portbdataout[0..0]); END; --VALID FILE