{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version " "Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 30 15:48:57 2007 " "Info: Processing started: Thu Aug 30 15:48:57 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off DE1_NIOS -c DE1_NIOS --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DE1_NIOS -c DE1_NIOS --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updateir~7 " "Warning: Node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updateir~7\" is a latch" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" 139 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updatedr~8 " "Warning: Node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updatedr~8\" is a latch" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" 138 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~UPDATEUSER " "Info: Assuming node \"altera_internal_jtag~UPDATEUSER\" is an undefined clock" {  } { { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~UPDATEUSER" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk0 " "Info: No valid register-to-register data paths exist for clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk0\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 register system_0:u0\|cpu_0:the_cpu_0\|ic_fill_tag\[9\] register system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[11\] 516 ps " "Info: Slack time is 516 ps for clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" between source register \"system_0:u0\|cpu_0:the_cpu_0\|ic_fill_tag\[9\]\" and destination register \"system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[11\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "105.44 MHz 9.484 ns " "Info: Fmax is 105.44 MHz (period= 9.484 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.767 ns + Largest register register " "Info: + Largest register to register requirement is 9.767 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 7.581 ns " "Info: + Latch edge is 7.581 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 10.000 ns -2.419 ns  50 " "Info: Clock period of Destination clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" is 10.000 ns with  offset of -2.419 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.419 ns " "Info: - Launch edge is -2.419 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 10.000 ns -2.419 ns  50 " "Info: Clock period of Source clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" is 10.000 ns with  offset of -2.419 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.006 ns + Largest " "Info: + Largest clock skew is 0.006 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 destination 2.526 ns + Shortest register " "Info: + Shortest clock path from clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" to destination register is 2.526 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 877 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.000 ns) 0.929 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G3 3376 " "Info: 2: + IC(0.929 ns) + CELL(0.000 ns) = 0.929 ns; Loc. = CLKCTRL_G3; Fanout = 3376; COMB Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.929 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 877 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.602 ns) 2.526 ns system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[11\] 3 REG LCFF_X14_Y5_N23 2 " "Info: 3: + IC(0.995 ns) + CELL(0.602 ns) = 2.526 ns; Loc. = LCFF_X14_Y5_N23; Fanout = 2; REG Node = 'system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[11\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.597 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 8452 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 23.83 % ) " "Info: Total cell delay = 0.602 ns ( 23.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.924 ns ( 76.17 % ) " "Info: Total interconnect delay = 1.924 ns ( 76.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.526 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.526 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11] } { 0.000ns 0.929ns 0.995ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 source 2.520 ns - Longest register " "Info: - Longest clock path from clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" to source register is 2.520 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 877 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.000 ns) 0.929 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G3 3376 " "Info: 2: + IC(0.929 ns) + CELL(0.000 ns) = 0.929 ns; Loc. = CLKCTRL_G3; Fanout = 3376; COMB Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.929 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 877 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.989 ns) + CELL(0.602 ns) 2.520 ns system_0:u0\|cpu_0:the_cpu_0\|ic_fill_tag\[9\] 3 REG LCFF_X20_Y4_N29 4 " "Info: 3: + IC(0.989 ns) + CELL(0.602 ns) = 2.520 ns; Loc. = LCFF_X20_Y4_N29; Fanout = 4; REG Node = 'system_0:u0\|cpu_0:the_cpu_0\|ic_fill_tag\[9\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.591 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 6871 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 23.89 % ) " "Info: Total cell delay = 0.602 ns ( 23.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.918 ns ( 76.11 % ) " "Info: Total interconnect delay = 1.918 ns ( 76.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.520 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.520 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] } { 0.000ns 0.929ns 0.989ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.526 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.526 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11] } { 0.000ns 0.929ns 0.995ns } { 0.000ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.520 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.520 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] } { 0.000ns 0.929ns 0.989ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns - " "Info: - Micro clock to output delay of source is 0.277 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 6871 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns - " "Info: - Micro setup delay of destination is -0.038 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 8452 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.526 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.526 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11] } { 0.000ns 0.929ns 0.995ns } { 0.000ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.520 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.520 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] } { 0.000ns 0.929ns 0.989ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.251 ns - Longest register register " "Info: - Longest register to register delay is 9.251 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns system_0:u0\|cpu_0:the_cpu_0\|ic_fill_tag\[9\] 1 REG LCFF_X20_Y4_N29 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y4_N29; Fanout = 4; REG Node = 'system_0:u0\|cpu_0:the_cpu_0\|ic_fill_tag\[9\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 6871 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.623 ns) + CELL(0.449 ns) 1.072 ns system_0:u0\|sram_0_avalonS_arbitrator:the_sram_0_avalonS\|cpu_0_instruction_master_requests_sram_0_avalonS~55 2 COMB LCCOMB_X20_Y4_N22 3 " "Info: 2: + IC(0.623 ns) + CELL(0.449 ns) = 1.072 ns; Loc. = LCCOMB_X20_Y4_N22; Fanout = 3; COMB Node = 'system_0:u0\|sram_0_avalonS_arbitrator:the_sram_0_avalonS\|cpu_0_instruction_master_requests_sram_0_avalonS~55'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.072 ns" { system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_instruction_master_requests_sram_0_avalonS~55 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 4230 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.316 ns) + CELL(0.483 ns) 1.871 ns system_0:u0\|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port\|cpu_0_instruction_master_requests_epcs_controller_epcs_control_port~68 3 COMB LCCOMB_X20_Y4_N24 4 " "Info: 3: + IC(0.316 ns) + CELL(0.483 ns) = 1.871 ns; Loc. = LCCOMB_X20_Y4_N24; Fanout = 4; COMB Node = 'system_0:u0\|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port\|cpu_0_instruction_master_requests_epcs_controller_epcs_control_port~68'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.799 ns" { system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_instruction_master_requests_sram_0_avalonS~55 system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_0_instruction_master_requests_epcs_controller_epcs_control_port~68 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 2422 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.337 ns) + CELL(0.542 ns) 2.750 ns system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module 4 COMB LCCOMB_X20_Y4_N14 14 " "Info: 4: + IC(0.337 ns) + CELL(0.542 ns) = 2.750 ns; Loc. = LCCOMB_X20_Y4_N14; Fanout = 14; COMB Node = 'system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.879 ns" { system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_0_instruction_master_requests_epcs_controller_epcs_control_port~68 system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 1162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.904 ns) + CELL(0.322 ns) 3.976 ns system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_grant_vector\[1\]~61 5 COMB LCCOMB_X19_Y5_N18 18 " "Info: 5: + IC(0.904 ns) + CELL(0.322 ns) = 3.976 ns; Loc. = LCCOMB_X19_Y5_N18; Fanout = 18; COMB Node = 'system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_grant_vector\[1\]~61'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.226 ns" { system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_grant_vector[1]~61 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 1229 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.556 ns) + CELL(0.178 ns) 5.710 ns system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_address\[2\]~118 6 COMB LCCOMB_X15_Y8_N6 3 " "Info: 6: + IC(1.556 ns) + CELL(0.178 ns) = 5.710 ns; Loc. = LCCOMB_X15_Y8_N6; Fanout = 3; COMB Node = 'system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_address\[2\]~118'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.734 ns" { system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_grant_vector[1]~61 system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[2]~118 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 1165 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.328 ns) + CELL(0.455 ns) 6.493 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg\|Equal0~67 7 COMB LCCOMB_X15_Y8_N4 3 " "Info: 7: + IC(0.328 ns) + CELL(0.455 ns) = 6.493 ns; Loc. = LCCOMB_X15_Y8_N4; Fanout = 3; COMB Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg\|Equal0~67'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.783 ns" { system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[2]~118 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal0~67 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 1116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.316 ns) + CELL(0.322 ns) 7.131 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg\|Equal1~28 8 COMB LCCOMB_X15_Y8_N0 6 " "Info: 8: + IC(0.316 ns) + CELL(0.322 ns) = 7.131 ns; Loc. = LCCOMB_X15_Y8_N0; Fanout = 6; COMB Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg\|Equal1~28'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.638 ns" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal0~67 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal1~28 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 1117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.306 ns) + CELL(0.178 ns) 7.615 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata~2635 9 COMB LCCOMB_X15_Y8_N2 28 " "Info: 9: + IC(0.306 ns) + CELL(0.178 ns) = 7.615 ns; Loc. = LCCOMB_X15_Y8_N2; Fanout = 28; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata~2635'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.484 ns" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal1~28 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~2635 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 1631 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.218 ns) + CELL(0.322 ns) 9.155 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[11\] 10 COMB LCCOMB_X14_Y5_N22 1 " "Info: 10: + IC(1.218 ns) + CELL(0.322 ns) = 9.155 ns; Loc. = LCCOMB_X14_Y5_N22; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[11\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.540 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~2635 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[11] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 1631 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 9.251 ns system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[11\] 11 REG LCFF_X14_Y5_N23 2 " "Info: 11: + IC(0.000 ns) + CELL(0.096 ns) = 9.251 ns; Loc. = LCFF_X14_Y5_N23; Fanout = 2; REG Node = 'system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[11\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[11] system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 8452 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.347 ns ( 36.18 % ) " "Info: Total cell delay = 3.347 ns ( 36.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.904 ns ( 63.82 % ) " "Info: Total interconnect delay = 5.904 ns ( 63.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.251 ns" { system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_instruction_master_requests_sram_0_avalonS~55 system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_0_instruction_master_requests_epcs_controller_epcs_control_port~68 system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_grant_vector[1]~61 system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[2]~118 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal0~67 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal1~28 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~2635 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[11] system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.251 ns" { system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_instruction_master_requests_sram_0_avalonS~55 system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_0_instruction_master_requests_epcs_controller_epcs_control_port~68 system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_grant_vector[1]~61 system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[2]~118 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal0~67 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal1~28 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~2635 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[11] system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11] } { 0.000ns 0.623ns 0.316ns 0.337ns 0.904ns 1.556ns 0.328ns 0.316ns 0.306ns 1.218ns 0.000ns } { 0.000ns 0.449ns 0.483ns 0.542ns 0.322ns 0.178ns 0.455ns 0.322ns 0.178ns 0.322ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.526 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.526 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11] } { 0.000ns 0.929ns 0.995ns } { 0.000ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.520 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.520 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] } { 0.000ns 0.929ns 0.989ns } { 0.000ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.251 ns" { system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_instruction_master_requests_sram_0_avalonS~55 system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_0_instruction_master_requests_epcs_controller_epcs_control_port~68 system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_grant_vector[1]~61 system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[2]~118 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal0~67 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal1~28 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~2635 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[11] system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.251 ns" { system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9] system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_instruction_master_requests_sram_0_avalonS~55 system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|cpu_0_instruction_master_requests_epcs_controller_epcs_control_port~68 system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_grant_vector[1]~61 system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[2]~118 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal0~67 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal1~28 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~2635 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[11] system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11] } { 0.000ns 0.623ns 0.316ns 0.337ns 0.904ns 1.556ns 0.328ns 0.316ns 0.306ns 1.218ns 0.000ns } { 0.000ns 0.449ns 0.483ns 0.542ns 0.322ns 0.178ns 0.455ns 0.322ns 0.178ns 0.322ns 0.096ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLOCK_50 register Reset_Delay:delay1\|Cont\[15\] register Reset_Delay:delay1\|Cont\[12\] 15.086 ns " "Info: Slack time is 15.086 ns for clock \"CLOCK_50\" between source register \"Reset_Delay:delay1\|Cont\[15\]\" and destination register \"Reset_Delay:delay1\|Cont\[12\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "203.5 MHz 4.914 ns " "Info: Fmax is 203.5 MHz (period= 4.914 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.761 ns + Largest register register " "Info: + Largest register to register requirement is 19.761 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLOCK_50 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLOCK_50\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLOCK_50 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLOCK_50\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.847 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.847 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 25 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 25; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.981 ns) + CELL(0.602 ns) 2.847 ns Reset_Delay:delay1\|Cont\[12\] 3 REG LCFF_X32_Y6_N1 3 " "Info: 3: + IC(0.981 ns) + CELL(0.602 ns) = 2.847 ns; Loc. = LCFF_X32_Y6_N1; Fanout = 3; REG Node = 'Reset_Delay:delay1\|Cont\[12\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.583 ns" { CLOCK_50~clkctrl Reset_Delay:delay1|Cont[12] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.18 % ) " "Info: Total cell delay = 1.628 ns ( 57.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.219 ns ( 42.82 % ) " "Info: Total interconnect delay = 1.219 ns ( 42.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.847 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.847 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[12] } { 0.000ns 0.000ns 0.238ns 0.981ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.847 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.847 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 25 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 25; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.981 ns) + CELL(0.602 ns) 2.847 ns Reset_Delay:delay1\|Cont\[15\] 3 REG LCFF_X32_Y6_N7 3 " "Info: 3: + IC(0.981 ns) + CELL(0.602 ns) = 2.847 ns; Loc. = LCFF_X32_Y6_N7; Fanout = 3; REG Node = 'Reset_Delay:delay1\|Cont\[15\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.583 ns" { CLOCK_50~clkctrl Reset_Delay:delay1|Cont[15] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.18 % ) " "Info: Total cell delay = 1.628 ns ( 57.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.219 ns ( 42.82 % ) " "Info: Total interconnect delay = 1.219 ns ( 42.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.847 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.847 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[15] } { 0.000ns 0.000ns 0.238ns 0.981ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.847 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.847 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[12] } { 0.000ns 0.000ns 0.238ns 0.981ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.847 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.847 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[15] } { 0.000ns 0.000ns 0.238ns 0.981ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns - " "Info: - Micro clock to output delay of source is 0.277 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns - " "Info: - Micro setup delay of destination is -0.038 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.847 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.847 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[12] } { 0.000ns 0.000ns 0.238ns 0.981ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.847 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.847 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[15] } { 0.000ns 0.000ns 0.238ns 0.981ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.675 ns - Longest register register " "Info: - Longest register to register delay is 4.675 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Reset_Delay:delay1\|Cont\[15\] 1 REG LCFF_X32_Y6_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y6_N7; Fanout = 3; REG Node = 'Reset_Delay:delay1\|Cont\[15\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reset_Delay:delay1|Cont[15] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(0.512 ns) 0.910 ns Reset_Delay:delay1\|Equal0~243 2 COMB LCCOMB_X32_Y6_N28 1 " "Info: 2: + IC(0.398 ns) + CELL(0.512 ns) = 0.910 ns; Loc. = LCCOMB_X32_Y6_N28; Fanout = 1; COMB Node = 'Reset_Delay:delay1\|Equal0~243'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.910 ns" { Reset_Delay:delay1|Cont[15] Reset_Delay:delay1|Equal0~243 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.862 ns) + CELL(0.322 ns) 2.094 ns Reset_Delay:delay1\|Equal0~244 3 COMB LCCOMB_X33_Y7_N30 2 " "Info: 3: + IC(0.862 ns) + CELL(0.322 ns) = 2.094 ns; Loc. = LCCOMB_X33_Y7_N30; Fanout = 2; COMB Node = 'Reset_Delay:delay1\|Equal0~244'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.184 ns" { Reset_Delay:delay1|Equal0~243 Reset_Delay:delay1|Equal0~244 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.478 ns) + CELL(0.521 ns) 3.093 ns Reset_Delay:delay1\|Equal0~247 4 COMB LCCOMB_X32_Y7_N8 24 " "Info: 4: + IC(0.478 ns) + CELL(0.521 ns) = 3.093 ns; Loc. = LCCOMB_X32_Y7_N8; Fanout = 24; COMB Node = 'Reset_Delay:delay1\|Equal0~247'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.999 ns" { Reset_Delay:delay1|Equal0~244 Reset_Delay:delay1|Equal0~247 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.824 ns) + CELL(0.758 ns) 4.675 ns Reset_Delay:delay1\|Cont\[12\] 5 REG LCFF_X32_Y6_N1 3 " "Info: 5: + IC(0.824 ns) + CELL(0.758 ns) = 4.675 ns; Loc. = LCFF_X32_Y6_N1; Fanout = 3; REG Node = 'Reset_Delay:delay1\|Cont\[12\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.582 ns" { Reset_Delay:delay1|Equal0~247 Reset_Delay:delay1|Cont[12] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.113 ns ( 45.20 % ) " "Info: Total cell delay = 2.113 ns ( 45.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.562 ns ( 54.80 % ) " "Info: Total interconnect delay = 2.562 ns ( 54.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.675 ns" { Reset_Delay:delay1|Cont[15] Reset_Delay:delay1|Equal0~243 Reset_Delay:delay1|Equal0~244 Reset_Delay:delay1|Equal0~247 Reset_Delay:delay1|Cont[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.675 ns" { Reset_Delay:delay1|Cont[15] Reset_Delay:delay1|Equal0~243 Reset_Delay:delay1|Equal0~244 Reset_Delay:delay1|Equal0~247 Reset_Delay:delay1|Cont[12] } { 0.000ns 0.398ns 0.862ns 0.478ns 0.824ns } { 0.000ns 0.512ns 0.322ns 0.521ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.847 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.847 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[12] } { 0.000ns 0.000ns 0.238ns 0.981ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.847 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.847 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[15] } { 0.000ns 0.000ns 0.238ns 0.981ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.675 ns" { Reset_Delay:delay1|Cont[15] Reset_Delay:delay1|Equal0~243 Reset_Delay:delay1|Equal0~244 Reset_Delay:delay1|Equal0~247 Reset_Delay:delay1|Cont[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.675 ns" { Reset_Delay:delay1|Cont[15] Reset_Delay:delay1|Equal0~243 Reset_Delay:delay1|Equal0~244 Reset_Delay:delay1|Equal0~247 Reset_Delay:delay1|Cont[12] } { 0.000ns 0.398ns 0.862ns 0.478ns 0.824ns } { 0.000ns 0.512ns 0.322ns 0.521ns 0.758ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 register system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[9\] 102.24 MHz 9.781 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 102.24 MHz between source register \"sld_hub:sld_hub_inst\|jtag_debug_mode_usr1\" and destination register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[9\]\" (period= 9.781 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.542 ns + Longest register register " "Info: + Longest register to register delay is 9.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LCFF_X8_Y15_N17 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y15_N17; Fanout = 13; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 393 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.255 ns) + CELL(0.449 ns) 1.704 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[35\]~4758 2 COMB LCCOMB_X10_Y16_N20 47 " "Info: 2: + IC(1.255 ns) + CELL(0.449 ns) = 1.704 ns; Loc. = LCCOMB_X10_Y16_N20; Fanout = 47; COMB Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[35\]~4758'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.704 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4758 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" 225 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.840 ns) + CELL(0.521 ns) 4.065 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|always2~2 3 COMB LCCOMB_X13_Y14_N8 34 " "Info: 3: + IC(1.840 ns) + CELL(0.521 ns) = 4.065 ns; Loc. = LCCOMB_X13_Y14_N8; Fanout = 34; COMB Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|always2~2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.361 ns" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4758 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|always2~2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.269 ns) + CELL(0.461 ns) 5.795 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[12\]~4765 4 COMB LCCOMB_X16_Y16_N8 23 " "Info: 4: + IC(1.269 ns) + CELL(0.461 ns) = 5.795 ns; Loc. = LCCOMB_X16_Y16_N8; Fanout = 23; COMB Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[12\]~4765'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.730 ns" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|always2~2 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12]~4765 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" 225 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.965 ns) + CELL(0.521 ns) 7.281 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4822 5 COMB LCCOMB_X16_Y15_N2 1 " "Info: 5: + IC(0.965 ns) + CELL(0.521 ns) = 7.281 ns; Loc. = LCCOMB_X16_Y15_N2; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4822'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.486 ns" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12]~4765 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4822 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.292 ns) + CELL(0.516 ns) 8.089 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4823 6 COMB LCCOMB_X16_Y15_N0 1 " "Info: 6: + IC(0.292 ns) + CELL(0.516 ns) = 8.089 ns; Loc. = LCCOMB_X16_Y15_N0; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4823'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.808 ns" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4822 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4823 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.812 ns) + CELL(0.545 ns) 9.446 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4824 7 COMB LCCOMB_X14_Y16_N0 1 " "Info: 7: + IC(0.812 ns) + CELL(0.545 ns) = 9.446 ns; Loc. = LCCOMB_X14_Y16_N0; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4824'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.357 ns" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4823 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4824 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 9.542 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[9\] 8 REG LCFF_X14_Y16_N1 2 " "Info: 8: + IC(0.000 ns) + CELL(0.096 ns) = 9.542 ns; Loc. = LCFF_X14_Y16_N1; Fanout = 2; REG Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[9\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4824 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[9] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" 225 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.109 ns ( 32.58 % ) " "Info: Total cell delay = 3.109 ns ( 32.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.433 ns ( 67.42 % ) " "Info: Total interconnect delay = 6.433 ns ( 67.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.542 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4758 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|always2~2 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12]~4765 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4822 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4823 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4824 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.542 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4758 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|always2~2 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12]~4765 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4822 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4823 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4824 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[9] } { 0.000ns 1.255ns 1.840ns 1.269ns 0.965ns 0.292ns 0.812ns 0.000ns } { 0.000ns 0.449ns 0.521ns 0.461ns 0.521ns 0.516ns 0.545ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.909 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.315 ns) + CELL(0.000 ns) 3.315 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 153 " "Info: 2: + IC(3.315 ns) + CELL(0.000 ns) = 3.315 ns; Loc. = CLKCTRL_G0; Fanout = 153; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.315 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.602 ns) 4.909 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[9\] 3 REG LCFF_X14_Y16_N1 2 " "Info: 3: + IC(0.992 ns) + CELL(0.602 ns) = 4.909 ns; Loc. = LCFF_X14_Y16_N1; Fanout = 2; REG Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[9\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.594 ns" { altera_internal_jtag~TCKUTAPclkctrl system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[9] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" 225 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 12.26 % ) " "Info: Total cell delay = 0.602 ns ( 12.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.307 ns ( 87.74 % ) " "Info: Total interconnect delay = 4.307 ns ( 87.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.909 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.909 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[9] } { 0.000ns 3.315ns 0.992ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 4.909 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 4.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.315 ns) + CELL(0.000 ns) 3.315 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 153 " "Info: 2: + IC(3.315 ns) + CELL(0.000 ns) = 3.315 ns; Loc. = CLKCTRL_G0; Fanout = 153; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.315 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.602 ns) 4.909 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 3 REG LCFF_X8_Y15_N17 13 " "Info: 3: + IC(0.992 ns) + CELL(0.602 ns) = 4.909 ns; Loc. = LCFF_X8_Y15_N17; Fanout = 13; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.594 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 393 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 12.26 % ) " "Info: Total cell delay = 0.602 ns ( 12.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.307 ns ( 87.74 % ) " "Info: Total interconnect delay = 4.307 ns ( 87.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.909 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.909 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 3.315ns 0.992ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.909 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.909 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[9] } { 0.000ns 3.315ns 0.992ns } { 0.000ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.909 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.909 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 3.315ns 0.992ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 393 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" 225 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.542 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4758 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|always2~2 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12]~4765 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4822 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4823 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4824 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.542 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4758 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|always2~2 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12]~4765 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4822 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4823 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4824 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[9] } { 0.000ns 1.255ns 1.840ns 1.269ns 0.965ns 0.292ns 0.812ns 0.000ns } { 0.000ns 0.449ns 0.521ns 0.461ns 0.521ns 0.516ns 0.545ns 0.096ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.909 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.909 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[9] } { 0.000ns 3.315ns 0.992ns } { 0.000ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.909 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.909 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 3.315ns 0.992ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 register system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\] register system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\] 445 ps " "Info: Minimum slack time is 445 ps for clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" between source register \"system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\]\" and destination register \"system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.454 ns + Shortest register register " "Info: + Shortest register to register delay is 0.454 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\] 1 REG LCFF_X2_Y6_N29 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y6_N29; Fanout = 2; REG Node = 'system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 407 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.358 ns) 0.358 ns system_0:u0\|sdram_0:the_sdram_0\|Selector0~8 2 COMB LCCOMB_X2_Y6_N28 1 " "Info: 2: + IC(0.000 ns) + CELL(0.358 ns) = 0.358 ns; Loc. = LCCOMB_X2_Y6_N28; Fanout = 1; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|Selector0~8'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.358 ns" { system_0:u0|sdram_0:the_sdram_0|i_cmd[3] system_0:u0|sdram_0:the_sdram_0|Selector0~8 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 352 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 0.454 ns system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\] 3 REG LCFF_X2_Y6_N29 2 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 0.454 ns; Loc. = LCFF_X2_Y6_N29; Fanout = 2; REG Node = 'system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { system_0:u0|sdram_0:the_sdram_0|Selector0~8 system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 407 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.454 ns ( 100.00 % ) " "Info: Total cell delay = 0.454 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.454 ns" { system_0:u0|sdram_0:the_sdram_0|i_cmd[3] system_0:u0|sdram_0:the_sdram_0|Selector0~8 system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.454 ns" { system_0:u0|sdram_0:the_sdram_0|i_cmd[3] system_0:u0|sdram_0:the_sdram_0|Selector0~8 system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.358ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.009 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.009 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.419 ns " "Info: + Latch edge is -2.419 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 10.000 ns -2.419 ns  50 " "Info: Clock period of Destination clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" is 10.000 ns with  offset of -2.419 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.419 ns " "Info: - Launch edge is -2.419 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 10.000 ns -2.419 ns  50 " "Info: Clock period of Source clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" is 10.000 ns with  offset of -2.419 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 destination 2.511 ns + Longest register " "Info: + Longest clock path from clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" to destination register is 2.511 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 877 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.000 ns) 0.929 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G3 3376 " "Info: 2: + IC(0.929 ns) + CELL(0.000 ns) = 0.929 ns; Loc. = CLKCTRL_G3; Fanout = 3376; COMB Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.929 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 877 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.602 ns) 2.511 ns system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\] 3 REG LCFF_X2_Y6_N29 2 " "Info: 3: + IC(0.980 ns) + CELL(0.602 ns) = 2.511 ns; Loc. = LCFF_X2_Y6_N29; Fanout = 2; REG Node = 'system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.582 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 407 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 23.97 % ) " "Info: Total cell delay = 0.602 ns ( 23.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.909 ns ( 76.03 % ) " "Info: Total interconnect delay = 1.909 ns ( 76.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.929ns 0.980ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 source 2.511 ns - Shortest register " "Info: - Shortest clock path from clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" to source register is 2.511 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 877 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.000 ns) 0.929 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G3 3376 " "Info: 2: + IC(0.929 ns) + CELL(0.000 ns) = 0.929 ns; Loc. = CLKCTRL_G3; Fanout = 3376; COMB Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.929 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 877 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.602 ns) 2.511 ns system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\] 3 REG LCFF_X2_Y6_N29 2 " "Info: 3: + IC(0.980 ns) + CELL(0.602 ns) = 2.511 ns; Loc. = LCFF_X2_Y6_N29; Fanout = 2; REG Node = 'system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.582 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 407 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 23.97 % ) " "Info: Total cell delay = 0.602 ns ( 23.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.909 ns ( 76.03 % ) " "Info: Total interconnect delay = 1.909 ns ( 76.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.929ns 0.980ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.929ns 0.980ns } { 0.000ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.929ns 0.980ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns - " "Info: - Micro clock to output delay of source is 0.277 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 407 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 407 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.929ns 0.980ns } { 0.000ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.929ns 0.980ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.454 ns" { system_0:u0|sdram_0:the_sdram_0|i_cmd[3] system_0:u0|sdram_0:the_sdram_0|Selector0~8 system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.454 ns" { system_0:u0|sdram_0:the_sdram_0|i_cmd[3] system_0:u0|sdram_0:the_sdram_0|Selector0~8 system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.358ns 0.096ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.929ns 0.980ns } { 0.000ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.511 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.929ns 0.980ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "CLOCK_50 register Reset_Delay:delay1\|Cont\[0\] register Reset_Delay:delay1\|Cont\[0\] 445 ps " "Info: Minimum slack time is 445 ps for clock \"CLOCK_50\" between source register \"Reset_Delay:delay1\|Cont\[0\]\" and destination register \"Reset_Delay:delay1\|Cont\[0\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.454 ns + Shortest register register " "Info: + Shortest register to register delay is 0.454 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Reset_Delay:delay1\|Cont\[0\] 1 REG LCFF_X32_Y7_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y7_N1; Fanout = 4; REG Node = 'Reset_Delay:delay1\|Cont\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reset_Delay:delay1|Cont[0] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.358 ns) 0.358 ns Reset_Delay:delay1\|Cont\[0\]~997 2 COMB LCCOMB_X32_Y7_N0 1 " "Info: 2: + IC(0.000 ns) + CELL(0.358 ns) = 0.358 ns; Loc. = LCCOMB_X32_Y7_N0; Fanout = 1; COMB Node = 'Reset_Delay:delay1\|Cont\[0\]~997'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.358 ns" { Reset_Delay:delay1|Cont[0] Reset_Delay:delay1|Cont[0]~997 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 0.454 ns Reset_Delay:delay1\|Cont\[0\] 3 REG LCFF_X32_Y7_N1 4 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 0.454 ns; Loc. = LCFF_X32_Y7_N1; Fanout = 4; REG Node = 'Reset_Delay:delay1\|Cont\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { Reset_Delay:delay1|Cont[0]~997 Reset_Delay:delay1|Cont[0] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.454 ns ( 100.00 % ) " "Info: Total cell delay = 0.454 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.454 ns" { Reset_Delay:delay1|Cont[0] Reset_Delay:delay1|Cont[0]~997 Reset_Delay:delay1|Cont[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.454 ns" { Reset_Delay:delay1|Cont[0] Reset_Delay:delay1|Cont[0]~997 Reset_Delay:delay1|Cont[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.358ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.009 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.009 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLOCK_50 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLOCK_50\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLOCK_50 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLOCK_50\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.838 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 2.838 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 25 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 25; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.972 ns) + CELL(0.602 ns) 2.838 ns Reset_Delay:delay1\|Cont\[0\] 3 REG LCFF_X32_Y7_N1 4 " "Info: 3: + IC(0.972 ns) + CELL(0.602 ns) = 2.838 ns; Loc. = LCFF_X32_Y7_N1; Fanout = 4; REG Node = 'Reset_Delay:delay1\|Cont\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.574 ns" { CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.36 % ) " "Info: Total cell delay = 1.628 ns ( 57.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.210 ns ( 42.64 % ) " "Info: Total interconnect delay = 1.210 ns ( 42.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.838 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.838 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } { 0.000ns 0.000ns 0.238ns 0.972ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.838 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to source register is 2.838 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 25 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 25; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.972 ns) + CELL(0.602 ns) 2.838 ns Reset_Delay:delay1\|Cont\[0\] 3 REG LCFF_X32_Y7_N1 4 " "Info: 3: + IC(0.972 ns) + CELL(0.602 ns) = 2.838 ns; Loc. = LCFF_X32_Y7_N1; Fanout = 4; REG Node = 'Reset_Delay:delay1\|Cont\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.574 ns" { CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.36 % ) " "Info: Total cell delay = 1.628 ns ( 57.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.210 ns ( 42.64 % ) " "Info: Total interconnect delay = 1.210 ns ( 42.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.838 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.838 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } { 0.000ns 0.000ns 0.238ns 0.972ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.838 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.838 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } { 0.000ns 0.000ns 0.238ns 0.972ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.838 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.838 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } { 0.000ns 0.000ns 0.238ns 0.972ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns - " "Info: - Micro clock to output delay of source is 0.277 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v" 23 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.838 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.838 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } { 0.000ns 0.000ns 0.238ns 0.972ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.838 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.838 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } { 0.000ns 0.000ns 0.238ns 0.972ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.454 ns" { Reset_Delay:delay1|Cont[0] Reset_Delay:delay1|Cont[0]~997 Reset_Delay:delay1|Cont[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.454 ns" { Reset_Delay:delay1|Cont[0] Reset_Delay:delay1|Cont[0]~997 Reset_Delay:delay1|Cont[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.358ns 0.096ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.838 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.838 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } { 0.000ns 0.000ns 0.238ns 0.972ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.838 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.838 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:delay1|Cont[0] } { 0.000ns 0.000ns 0.238ns 0.972ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[30\] SRAM_DQ\[14\] CLOCK_50 11.184 ns register " "Info: tsu for register \"system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[30\]\" (data pin = \"SRAM_DQ\[14\]\", clock pin = \"CLOCK_50\") is 11.184 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.311 ns + Longest pin register " "Info: + Longest pin to register delay is 11.311 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SRAM_DQ\[14\] 1 PIN PIN_V8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_V8; Fanout = 1; PIN Node = 'SRAM_DQ\[14\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.843 ns) 0.843 ns SRAM_DQ\[14\]~1 2 COMB IOC_X9_Y0_N3 4 " "Info: 2: + IC(0.000 ns) + CELL(0.843 ns) = 0.843 ns; Loc. = IOC_X9_Y0_N3; Fanout = 4; COMB Node = 'SRAM_DQ\[14\]~1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.843 ns" { SRAM_DQ[14] SRAM_DQ[14]~1 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.978 ns) + CELL(0.521 ns) 8.342 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[30\]~2688 3 COMB LCCOMB_X19_Y8_N14 1 " "Info: 3: + IC(6.978 ns) + CELL(0.521 ns) = 8.342 ns; Loc. = LCCOMB_X19_Y8_N14; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[30\]~2688'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.499 ns" { SRAM_DQ[14]~1 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2688 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 1631 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.482 ns) + CELL(0.322 ns) 9.146 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[30\]~2689 4 COMB LCCOMB_X18_Y8_N4 1 " "Info: 4: + IC(0.482 ns) + CELL(0.322 ns) = 9.146 ns; Loc. = LCCOMB_X18_Y8_N4; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[30\]~2689'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.804 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2688 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2689 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 1631 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.293 ns) + CELL(0.322 ns) 9.761 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[30\]~2690 5 COMB LCCOMB_X18_Y8_N0 1 " "Info: 5: + IC(0.293 ns) + CELL(0.322 ns) = 9.761 ns; Loc. = LCCOMB_X18_Y8_N0; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[30\]~2690'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.615 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2689 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2690 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 1631 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.312 ns) + CELL(0.521 ns) 10.594 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[30\]~2691 6 COMB LCCOMB_X18_Y8_N24 1 " "Info: 6: + IC(0.312 ns) + CELL(0.521 ns) = 10.594 ns; Loc. = LCCOMB_X18_Y8_N24; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[30\]~2691'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.833 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2690 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2691 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 1631 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.299 ns) + CELL(0.322 ns) 11.215 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[30\] 7 COMB LCCOMB_X18_Y8_N8 1 " "Info: 7: + IC(0.299 ns) + CELL(0.322 ns) = 11.215 ns; Loc. = LCCOMB_X18_Y8_N8; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[30\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.621 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2691 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 1631 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 11.311 ns system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[30\] 8 REG LCFF_X18_Y8_N9 3 " "Info: 8: + IC(0.000 ns) + CELL(0.096 ns) = 11.311 ns; Loc. = LCFF_X18_Y8_N9; Fanout = 3; REG Node = 'system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[30\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30] system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[30] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 8452 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.947 ns ( 26.05 % ) " "Info: Total cell delay = 2.947 ns ( 26.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.364 ns ( 73.95 % ) " "Info: Total interconnect delay = 8.364 ns ( 73.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "11.311 ns" { SRAM_DQ[14] SRAM_DQ[14]~1 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2688 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2689 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2690 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2691 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30] system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[30] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "11.311 ns" { SRAM_DQ[14] SRAM_DQ[14]~1 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2688 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2689 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2690 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2691 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30] system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[30] } { 0.000ns 0.000ns 6.978ns 0.482ns 0.293ns 0.312ns 0.299ns 0.000ns } { 0.000ns 0.843ns 0.521ns 0.322ns 0.322ns 0.521ns 0.322ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 8452 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_PLL_OFFSET" "CLOCK_50 SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 -2.419 ns - " "Info: - Offset between input clock \"CLOCK_50\" and output clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" is -2.419 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 130 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 877 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 destination 2.508 ns - Shortest register " "Info: - Shortest clock path from clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" to destination register is 2.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 877 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.000 ns) 0.929 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G3 3376 " "Info: 2: + IC(0.929 ns) + CELL(0.000 ns) = 0.929 ns; Loc. = CLKCTRL_G3; Fanout = 3376; COMB Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.929 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 877 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.977 ns) + CELL(0.602 ns) 2.508 ns system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[30\] 3 REG LCFF_X18_Y8_N9 3 " "Info: 3: + IC(0.977 ns) + CELL(0.602 ns) = 2.508 ns; Loc. = LCFF_X18_Y8_N9; Fanout = 3; REG Node = 'system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[30\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.579 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[30] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 8452 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 24.00 % ) " "Info: Total cell delay = 0.602 ns ( 24.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.906 ns ( 76.00 % ) " "Info: Total interconnect delay = 1.906 ns ( 76.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.508 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[30] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.508 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[30] } { 0.000ns 0.929ns 0.977ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "11.311 ns" { SRAM_DQ[14] SRAM_DQ[14]~1 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2688 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2689 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2690 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2691 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30] system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[30] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "11.311 ns" { SRAM_DQ[14] SRAM_DQ[14]~1 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2688 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2689 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2690 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30]~2691 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[30] system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[30] } { 0.000ns 0.000ns 6.978ns 0.482ns 0.293ns 0.312ns 0.299ns 0.000ns } { 0.000ns 0.843ns 0.521ns 0.322ns 0.322ns 0.521ns 0.322ns 0.096ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.508 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[30] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.508 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[30] } { 0.000ns 0.929ns 0.977ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 SRAM_ADDR\[11\] system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_dbs_address\[1\] 11.580 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"SRAM_ADDR\[11\]\" through register \"system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_dbs_address\[1\]\" is 11.580 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "CLOCK_50 SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 -2.419 ns + " "Info: + Offset between input clock \"CLOCK_50\" and output clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" is -2.419 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 130 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 877 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 source 2.517 ns + Longest register " "Info: + Longest clock path from clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" to source register is 2.517 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 877 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.000 ns) 0.929 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G3 3376 " "Info: 2: + IC(0.929 ns) + CELL(0.000 ns) = 0.929 ns; Loc. = CLKCTRL_G3; Fanout = 3376; COMB Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.929 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 877 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.986 ns) + CELL(0.602 ns) 2.517 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_dbs_address\[1\] 3 REG LCFF_X22_Y5_N25 32 " "Info: 3: + IC(0.986 ns) + CELL(0.602 ns) = 2.517 ns; Loc. = LCFF_X22_Y5_N25; Fanout = 32; REG Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_dbs_address\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.588 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 1909 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 23.92 % ) " "Info: Total cell delay = 0.602 ns ( 23.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.915 ns ( 76.08 % ) " "Info: Total interconnect delay = 1.915 ns ( 76.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.517 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.517 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1] } { 0.000ns 0.929ns 0.986ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 1909 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.205 ns + Longest register pin " "Info: + Longest register to pin delay is 11.205 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_dbs_address\[1\] 1 REG LCFF_X22_Y5_N25 32 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y5_N25; Fanout = 32; REG Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_dbs_address\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 1909 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.545 ns) 0.941 ns system_0:u0\|sram_0_avalonS_arbitrator:the_sram_0_avalonS\|cpu_0_data_master_byteenable_sram_0_avalonS\[1\]~57 2 COMB LCCOMB_X22_Y5_N30 6 " "Info: 2: + IC(0.396 ns) + CELL(0.545 ns) = 0.941 ns; Loc. = LCCOMB_X22_Y5_N30; Fanout = 6; COMB Node = 'system_0:u0\|sram_0_avalonS_arbitrator:the_sram_0_avalonS\|cpu_0_data_master_byteenable_sram_0_avalonS\[1\]~57'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.941 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1] system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_byteenable_sram_0_avalonS[1]~57 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 4222 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.491 ns) + CELL(0.521 ns) 1.953 ns system_0:u0\|sram_0_avalonS_arbitrator:the_sram_0_avalonS\|cpu_0_data_master_qualified_request_sram_0_avalonS~121 3 COMB LCCOMB_X21_Y5_N16 1 " "Info: 3: + IC(0.491 ns) + CELL(0.521 ns) = 1.953 ns; Loc. = LCCOMB_X21_Y5_N16; Fanout = 1; COMB Node = 'system_0:u0\|sram_0_avalonS_arbitrator:the_sram_0_avalonS\|cpu_0_data_master_qualified_request_sram_0_avalonS~121'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.012 ns" { system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_byteenable_sram_0_avalonS[1]~57 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_qualified_request_sram_0_avalonS~121 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 4224 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.449 ns) 2.955 ns system_0:u0\|sram_0_avalonS_arbitrator:the_sram_0_avalonS\|cpu_0_data_master_qualified_request_sram_0_avalonS~122 4 COMB LCCOMB_X20_Y5_N16 10 " "Info: 4: + IC(0.553 ns) + CELL(0.449 ns) = 2.955 ns; Loc. = LCCOMB_X20_Y5_N16; Fanout = 10; COMB Node = 'system_0:u0\|sram_0_avalonS_arbitrator:the_sram_0_avalonS\|cpu_0_data_master_qualified_request_sram_0_avalonS~122'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.002 ns" { system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_qualified_request_sram_0_avalonS~121 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_qualified_request_sram_0_avalonS~122 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 4224 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.318 ns) + CELL(0.322 ns) 3.595 ns system_0:u0\|sram_0_avalonS_arbitrator:the_sram_0_avalonS\|sram_0_avalonS_grant_vector\[1\]~38 5 COMB LCCOMB_X20_Y5_N0 28 " "Info: 5: + IC(0.318 ns) + CELL(0.322 ns) = 3.595 ns; Loc. = LCCOMB_X20_Y5_N0; Fanout = 28; COMB Node = 'system_0:u0\|sram_0_avalonS_arbitrator:the_sram_0_avalonS\|sram_0_avalonS_grant_vector\[1\]~38'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.640 ns" { system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_qualified_request_sram_0_avalonS~122 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_grant_vector[1]~38 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 4303 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.467 ns) + CELL(0.521 ns) 6.583 ns system_0:u0\|sram_0_avalonS_arbitrator:the_sram_0_avalonS\|sram_0_avalonS_address\[11\]~191 6 COMB LCCOMB_X9_Y4_N18 1 " "Info: 6: + IC(2.467 ns) + CELL(0.521 ns) = 6.583 ns; Loc. = LCCOMB_X9_Y4_N18; Fanout = 1; COMB Node = 'system_0:u0\|sram_0_avalonS_arbitrator:the_sram_0_avalonS\|sram_0_avalonS_address\[11\]~191'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.988 ns" { system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_grant_vector[1]~38 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[11]~191 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 4232 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.636 ns) + CELL(2.986 ns) 11.205 ns SRAM_ADDR\[11\] 7 PIN PIN_T11 0 " "Info: 7: + IC(1.636 ns) + CELL(2.986 ns) = 11.205 ns; Loc. = PIN_T11; Fanout = 0; PIN Node = 'SRAM_ADDR\[11\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.622 ns" { system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[11]~191 SRAM_ADDR[11] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 169 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.344 ns ( 47.69 % ) " "Info: Total cell delay = 5.344 ns ( 47.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.861 ns ( 52.31 % ) " "Info: Total interconnect delay = 5.861 ns ( 52.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "11.205 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1] system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_byteenable_sram_0_avalonS[1]~57 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_qualified_request_sram_0_avalonS~121 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_qualified_request_sram_0_avalonS~122 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_grant_vector[1]~38 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[11]~191 SRAM_ADDR[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "11.205 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1] system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_byteenable_sram_0_avalonS[1]~57 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_qualified_request_sram_0_avalonS~121 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_qualified_request_sram_0_avalonS~122 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_grant_vector[1]~38 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[11]~191 SRAM_ADDR[11] } { 0.000ns 0.396ns 0.491ns 0.553ns 0.318ns 2.467ns 1.636ns } { 0.000ns 0.545ns 0.521ns 0.449ns 0.322ns 0.521ns 2.986ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.517 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.517 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1] } { 0.000ns 0.929ns 0.986ns } { 0.000ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "11.205 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1] system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_byteenable_sram_0_avalonS[1]~57 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_qualified_request_sram_0_avalonS~121 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_qualified_request_sram_0_avalonS~122 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_grant_vector[1]~38 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[11]~191 SRAM_ADDR[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "11.205 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1] system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_byteenable_sram_0_avalonS[1]~57 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_qualified_request_sram_0_avalonS~121 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|cpu_0_data_master_qualified_request_sram_0_avalonS~122 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_grant_vector[1]~38 system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_address[11]~191 SRAM_ADDR[11] } { 0.000ns 0.396ns 0.491ns 0.553ns 0.318ns 2.467ns 1.636ns } { 0.000ns 0.545ns 0.521ns 0.449ns 0.322ns 0.521ns 2.986ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.810 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.810 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.810 ns) 2.810 ns altera_reserved_tdo 2 PIN PIN_L5 0 " "Info: 2: + IC(0.000 ns) + CELL(2.810 ns) = 2.810 ns; Loc. = PIN_L5; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.810 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.810 ns ( 100.00 % ) " "Info: Total cell delay = 2.810 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.810 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.810 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 2.810ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] altera_internal_jtag altera_internal_jtag~TCKUTAP 3.311 ns register " "Info: th for register \"sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\]\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 3.311 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.907 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.907 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.315 ns) + CELL(0.000 ns) 3.315 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 153 " "Info: 2: + IC(3.315 ns) + CELL(0.000 ns) = 3.315 ns; Loc. = CLKCTRL_G0; Fanout = 153; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.315 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.602 ns) 4.907 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] 3 REG LCFF_X9_Y16_N13 5 " "Info: 3: + IC(0.990 ns) + CELL(0.602 ns) = 4.907 ns; Loc. = LCFF_X9_Y16_N13; Fanout = 5; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.592 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 12.27 % ) " "Info: Total cell delay = 0.602 ns ( 12.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.305 ns ( 87.73 % ) " "Info: Total interconnect delay = 4.305 ns ( 87.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.907 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.907 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } { 0.000ns 3.315ns 0.990ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "c:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.882 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.882 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag 1 PIN JTAG_X1_Y14_N0 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 16; PIN Node = 'altera_internal_jtag'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.464 ns) + CELL(0.322 ns) 1.786 ns sld_hub:sld_hub_inst\|Equal4~13 2 COMB LCCOMB_X9_Y16_N12 1 " "Info: 2: + IC(1.464 ns) + CELL(0.322 ns) = 1.786 ns; Loc. = LCCOMB_X9_Y16_N12; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|Equal4~13'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.786 ns" { altera_internal_jtag sld_hub:sld_hub_inst|Equal4~13 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1813 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 1.882 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] 3 REG LCFF_X9_Y16_N13 5 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 1.882 ns; Loc. = LCFF_X9_Y16_N13; Fanout = 5; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { sld_hub:sld_hub_inst|Equal4~13 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.418 ns ( 22.21 % ) " "Info: Total cell delay = 0.418 ns ( 22.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.464 ns ( 77.79 % ) " "Info: Total interconnect delay = 1.464 ns ( 77.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.882 ns" { altera_internal_jtag sld_hub:sld_hub_inst|Equal4~13 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.882 ns" { altera_internal_jtag sld_hub:sld_hub_inst|Equal4~13 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } { 0.000ns 1.464ns 0.000ns } { 0.000ns 0.322ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.907 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.907 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } { 0.000ns 3.315ns 0.990ns } { 0.000ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.882 ns" { altera_internal_jtag sld_hub:sld_hub_inst|Equal4~13 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.882 ns" { altera_internal_jtag sld_hub:sld_hub_inst|Equal4~13 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } { 0.000ns 1.464ns 0.000ns } { 0.000ns 0.322ns 0.096ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." {  } {  } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0 "" 0}
{ "Warning" "WTAN_INVALID_ASSIGNMENTS_FOUND" "" "Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details" {  } {  } 0 0 "Found invalid timing assignments -- see Ignored Timing Assignments report for details" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 6 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "155 " "Info: Allocated 155 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 30 15:49:08 2007 " "Info: Processing ended: Thu Aug 30 15:49:08 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}