|DE1_NIOS CLOCK_24[0] => ~NO_FANOUT~ CLOCK_24[1] => ~NO_FANOUT~ CLOCK_27[0] => ~NO_FANOUT~ CLOCK_27[1] => ~NO_FANOUT~ CLOCK_50 => CLOCK_50~0.IN2 EXT_CLOCK => ~NO_FANOUT~ KEY[0] => KEY[0]~3.IN1 KEY[1] => KEY[1]~2.IN1 KEY[2] => KEY[2]~1.IN1 KEY[3] => KEY[3]~0.IN1 SW[0] => SW[0]~9.IN1 SW[1] => SW[1]~8.IN1 SW[2] => SW[2]~7.IN1 SW[3] => SW[3]~6.IN1 SW[4] => SW[4]~5.IN1 SW[5] => SW[5]~4.IN1 SW[6] => SW[6]~3.IN1 SW[7] => SW[7]~2.IN1 SW[8] => SW[8]~1.IN1 SW[9] => SW[9]~0.IN1 HEX0[0] <= system_0:u0.oSEG0_from_the_SEG7 HEX0[1] <= system_0:u0.oSEG0_from_the_SEG7 HEX0[2] <= system_0:u0.oSEG0_from_the_SEG7 HEX0[3] <= system_0:u0.oSEG0_from_the_SEG7 HEX0[4] <= system_0:u0.oSEG0_from_the_SEG7 HEX0[5] <= system_0:u0.oSEG0_from_the_SEG7 HEX0[6] <= system_0:u0.oSEG0_from_the_SEG7 HEX1[0] <= system_0:u0.oSEG1_from_the_SEG7 HEX1[1] <= system_0:u0.oSEG1_from_the_SEG7 HEX1[2] <= system_0:u0.oSEG1_from_the_SEG7 HEX1[3] <= system_0:u0.oSEG1_from_the_SEG7 HEX1[4] <= system_0:u0.oSEG1_from_the_SEG7 HEX1[5] <= system_0:u0.oSEG1_from_the_SEG7 HEX1[6] <= system_0:u0.oSEG1_from_the_SEG7 HEX2[0] <= system_0:u0.oSEG2_from_the_SEG7 HEX2[1] <= system_0:u0.oSEG2_from_the_SEG7 HEX2[2] <= system_0:u0.oSEG2_from_the_SEG7 HEX2[3] <= system_0:u0.oSEG2_from_the_SEG7 HEX2[4] <= system_0:u0.oSEG2_from_the_SEG7 HEX2[5] <= system_0:u0.oSEG2_from_the_SEG7 HEX2[6] <= system_0:u0.oSEG2_from_the_SEG7 HEX3[0] <= system_0:u0.oSEG3_from_the_SEG7 HEX3[1] <= system_0:u0.oSEG3_from_the_SEG7 HEX3[2] <= system_0:u0.oSEG3_from_the_SEG7 HEX3[3] <= system_0:u0.oSEG3_from_the_SEG7 HEX3[4] <= system_0:u0.oSEG3_from_the_SEG7 HEX3[5] <= system_0:u0.oSEG3_from_the_SEG7 HEX3[6] <= system_0:u0.oSEG3_from_the_SEG7 LEDG[0] <= system_0:u0.out_port_from_the_LEDG LEDG[1] <= system_0:u0.out_port_from_the_LEDG LEDG[2] <= system_0:u0.out_port_from_the_LEDG LEDG[3] <= system_0:u0.out_port_from_the_LEDG LEDG[4] <= system_0:u0.out_port_from_the_LEDG LEDG[5] <= system_0:u0.out_port_from_the_LEDG LEDG[6] <= system_0:u0.out_port_from_the_LEDG LEDG[7] <= system_0:u0.out_port_from_the_LEDG LEDR[0] <= system_0:u0.out_port_from_the_LEDR LEDR[1] <= system_0:u0.out_port_from_the_LEDR LEDR[2] <= system_0:u0.out_port_from_the_LEDR LEDR[3] <= system_0:u0.out_port_from_the_LEDR LEDR[4] <= system_0:u0.out_port_from_the_LEDR LEDR[5] <= system_0:u0.out_port_from_the_LEDR LEDR[6] <= system_0:u0.out_port_from_the_LEDR LEDR[7] <= system_0:u0.out_port_from_the_LEDR LEDR[8] <= system_0:u0.out_port_from_the_LEDR LEDR[9] <= system_0:u0.out_port_from_the_LEDR UART_TXD <= system_0:u0.txd_from_the_uart_0 UART_RXD => UART_RXD~0.IN1 DRAM_DQ[0] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_DQ[1] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_DQ[2] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_DQ[3] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_DQ[4] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_DQ[5] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_DQ[6] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_DQ[7] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_DQ[8] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_DQ[9] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_DQ[10] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_DQ[11] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_DQ[12] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_DQ[13] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_DQ[14] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_DQ[15] <= system_0:u0.zs_dq_to_and_from_the_sdram_0 DRAM_ADDR[0] <= system_0:u0.zs_addr_from_the_sdram_0 DRAM_ADDR[1] <= system_0:u0.zs_addr_from_the_sdram_0 DRAM_ADDR[2] <= system_0:u0.zs_addr_from_the_sdram_0 DRAM_ADDR[3] <= system_0:u0.zs_addr_from_the_sdram_0 DRAM_ADDR[4] <= system_0:u0.zs_addr_from_the_sdram_0 DRAM_ADDR[5] <= system_0:u0.zs_addr_from_the_sdram_0 DRAM_ADDR[6] <= system_0:u0.zs_addr_from_the_sdram_0 DRAM_ADDR[7] <= system_0:u0.zs_addr_from_the_sdram_0 DRAM_ADDR[8] <= system_0:u0.zs_addr_from_the_sdram_0 DRAM_ADDR[9] <= system_0:u0.zs_addr_from_the_sdram_0 DRAM_ADDR[10] <= system_0:u0.zs_addr_from_the_sdram_0 DRAM_ADDR[11] <= system_0:u0.zs_addr_from_the_sdram_0 DRAM_LDQM <= system_0:u0.zs_dqm_from_the_sdram_0 DRAM_UDQM <= system_0:u0.zs_dqm_from_the_sdram_0 DRAM_WE_N <= system_0:u0.zs_we_n_from_the_sdram_0 DRAM_CAS_N <= system_0:u0.zs_cas_n_from_the_sdram_0 DRAM_RAS_N <= system_0:u0.zs_ras_n_from_the_sdram_0 DRAM_CS_N <= system_0:u0.zs_cs_n_from_the_sdram_0 DRAM_BA_0 <= system_0:u0.zs_ba_from_the_sdram_0 DRAM_BA_1 <= system_0:u0.zs_ba_from_the_sdram_0 DRAM_CLK <= SDRAM_PLL:PLL1.c0 DRAM_CKE <= system_0:u0.zs_cke_from_the_sdram_0 FL_DQ[0] <= system_0:u0.tri_state_bridge_0_data FL_DQ[1] <= system_0:u0.tri_state_bridge_0_data FL_DQ[2] <= system_0:u0.tri_state_bridge_0_data FL_DQ[3] <= system_0:u0.tri_state_bridge_0_data FL_DQ[4] <= system_0:u0.tri_state_bridge_0_data FL_DQ[5] <= system_0:u0.tri_state_bridge_0_data FL_DQ[6] <= system_0:u0.tri_state_bridge_0_data FL_DQ[7] <= system_0:u0.tri_state_bridge_0_data FL_ADDR[0] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[1] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[2] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[3] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[4] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[5] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[6] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[7] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[8] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[9] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[10] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[11] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[12] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[13] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[14] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[15] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[16] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[17] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[18] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[19] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[20] <= system_0:u0.tri_state_bridge_0_address FL_ADDR[21] <= system_0:u0.tri_state_bridge_0_address FL_WE_N <= system_0:u0.write_n_to_the_cfi_flash_0 FL_RST_N <= FL_OE_N <= system_0:u0.tri_state_bridge_0_readn FL_CE_N <= system_0:u0.select_n_to_the_cfi_flash_0 SRAM_DQ[0] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_DQ[1] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_DQ[2] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_DQ[3] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_DQ[4] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_DQ[5] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_DQ[6] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_DQ[7] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_DQ[8] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_DQ[9] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_DQ[10] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_DQ[11] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_DQ[12] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_DQ[13] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_DQ[14] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_DQ[15] <= system_0:u0.SRAM_DQ_to_and_from_the_sram_0 SRAM_ADDR[0] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[1] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[2] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[3] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[4] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[5] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[6] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[7] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[8] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[9] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[10] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[11] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[12] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[13] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[14] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[15] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[16] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_ADDR[17] <= system_0:u0.SRAM_ADDR_from_the_sram_0 SRAM_UB_N <= system_0:u0.SRAM_UB_N_from_the_sram_0 SRAM_LB_N <= system_0:u0.SRAM_LB_N_from_the_sram_0 SRAM_WE_N <= system_0:u0.SRAM_WE_N_from_the_sram_0 SRAM_CE_N <= system_0:u0.SRAM_CE_N_from_the_sram_0 SRAM_OE_N <= system_0:u0.SRAM_OE_N_from_the_sram_0 SD_DAT <= SD_DAT~1 SD_DAT3 <= SD_CMD <= SD_CLK <= TDI => ~NO_FANOUT~ TCK => ~NO_FANOUT~ TCS => ~NO_FANOUT~ TDO <= I2C_SDAT <= I2C_SDAT~0 I2C_SCLK <= PS2_DAT => ~NO_FANOUT~ PS2_CLK => ~NO_FANOUT~ VGA_HS <= VGA_VS <= VGA_R[0] <= VGA_R[1] <= VGA_R[2] <= VGA_R[3] <= VGA_G[0] <= VGA_G[1] <= VGA_G[2] <= VGA_G[3] <= VGA_B[0] <= VGA_B[1] <= VGA_B[2] <= VGA_B[3] <= AUD_ADCLRCK <= AUD_ADCLRCK~0 AUD_ADCDAT => ~NO_FANOUT~ AUD_DACLRCK <= AUD_DACLRCK~0 AUD_DACDAT <= AUD_BCLK <= AUD_BCLK~0 AUD_XCK <= GPIO_0[0] <= GPIO_0[0]~0 GPIO_0[1] <= GPIO_0[1]~1 GPIO_0[2] <= GPIO_0[2]~2 GPIO_0[3] <= GPIO_0[3]~3 GPIO_0[4] <= GPIO_0[4]~4 GPIO_0[5] <= GPIO_0[5]~5 GPIO_0[6] <= GPIO_0[6]~6 GPIO_0[7] <= GPIO_0[7]~7 GPIO_0[8] <= GPIO_0[8]~8 GPIO_0[9] <= GPIO_0[9]~9 GPIO_0[10] <= GPIO_0[10]~10 GPIO_0[11] <= GPIO_0[11]~11 GPIO_0[12] <= GPIO_0[12]~12 GPIO_0[13] <= GPIO_0[13]~13 GPIO_0[14] <= GPIO_0[14]~14 GPIO_0[15] <= GPIO_0[15]~15 GPIO_0[16] <= GPIO_0[16]~16 GPIO_0[17] <= GPIO_0[17]~17 GPIO_0[18] <= GPIO_0[18]~18 GPIO_0[19] <= GPIO_0[19]~19 GPIO_0[20] <= GPIO_0[20]~20 GPIO_0[21] <= GPIO_0[21]~21 GPIO_0[22] <= GPIO_0[22]~22 GPIO_0[23] <= GPIO_0[23]~23 GPIO_0[24] <= GPIO_0[24]~24 GPIO_0[25] <= GPIO_0[25]~25 GPIO_0[26] <= GPIO_0[26]~26 GPIO_0[27] <= GPIO_0[27]~27 GPIO_0[28] <= GPIO_0[28]~28 GPIO_0[29] <= GPIO_0[29]~29 GPIO_0[30] <= GPIO_0[30]~30 GPIO_0[31] <= GPIO_0[31]~31 GPIO_0[32] <= GPIO_0[32]~32 GPIO_0[33] <= GPIO_0[33]~33 GPIO_0[34] <= GPIO_0[34]~34 GPIO_0[35] <= GPIO_0[35]~35 GPIO_1[0] <= GPIO_1[0]~0 GPIO_1[1] <= GPIO_1[1]~1 GPIO_1[2] <= GPIO_1[2]~2 GPIO_1[3] <= GPIO_1[3]~3 GPIO_1[4] <= GPIO_1[4]~4 GPIO_1[5] <= GPIO_1[5]~5 GPIO_1[6] <= GPIO_1[6]~6 GPIO_1[7] <= GPIO_1[7]~7 GPIO_1[8] <= GPIO_1[8]~8 GPIO_1[9] <= GPIO_1[9]~9 GPIO_1[10] <= GPIO_1[10]~10 GPIO_1[11] <= GPIO_1[11]~11 GPIO_1[12] <= GPIO_1[12]~12 GPIO_1[13] <= GPIO_1[13]~13 GPIO_1[14] <= GPIO_1[14]~14 GPIO_1[15] <= GPIO_1[15]~15 GPIO_1[16] <= GPIO_1[16]~16 GPIO_1[17] <= GPIO_1[17]~17 GPIO_1[18] <= GPIO_1[18]~18 GPIO_1[19] <= GPIO_1[19]~19 GPIO_1[20] <= GPIO_1[20]~20 GPIO_1[21] <= GPIO_1[21]~21 GPIO_1[22] <= GPIO_1[22]~22 GPIO_1[23] <= GPIO_1[23]~23 GPIO_1[24] <= GPIO_1[24]~24 GPIO_1[25] <= GPIO_1[25]~25 GPIO_1[26] <= GPIO_1[26]~26 GPIO_1[27] <= GPIO_1[27]~27 GPIO_1[28] <= GPIO_1[28]~28 GPIO_1[29] <= GPIO_1[29]~29 GPIO_1[30] <= GPIO_1[30]~30 GPIO_1[31] <= GPIO_1[31]~31 GPIO_1[32] <= GPIO_1[32]~32 GPIO_1[33] <= GPIO_1[33]~33 GPIO_1[34] <= GPIO_1[34]~34 GPIO_1[35] <= GPIO_1[35]~35 |DE1_NIOS|Reset_Delay:delay1 iRST => oRESET~reg0.ACLR iRST => Cont[23].ACLR iRST => Cont[22].ACLR iRST => Cont[21].ACLR iRST => Cont[20].ACLR iRST => Cont[19].ACLR iRST => Cont[18].ACLR iRST => Cont[17].ACLR iRST => Cont[16].ACLR iRST => Cont[15].ACLR iRST => Cont[14].ACLR iRST => Cont[13].ACLR iRST => Cont[12].ACLR iRST => Cont[11].ACLR iRST => Cont[10].ACLR iRST => Cont[9].ACLR iRST => Cont[8].ACLR iRST => Cont[7].ACLR iRST => Cont[6].ACLR iRST => Cont[5].ACLR iRST => Cont[4].ACLR iRST => Cont[3].ACLR iRST => Cont[2].ACLR iRST => Cont[1].ACLR iRST => Cont[0].ACLR iCLK => oRESET~reg0.CLK iCLK => Cont[23].CLK iCLK => Cont[22].CLK iCLK => Cont[21].CLK iCLK => Cont[20].CLK iCLK => Cont[19].CLK iCLK => Cont[18].CLK iCLK => Cont[17].CLK iCLK => Cont[16].CLK iCLK => Cont[15].CLK iCLK => Cont[14].CLK iCLK => Cont[13].CLK iCLK => Cont[12].CLK iCLK => Cont[11].CLK iCLK => Cont[10].CLK iCLK => Cont[9].CLK iCLK => Cont[8].CLK iCLK => Cont[7].CLK iCLK => Cont[6].CLK iCLK => Cont[5].CLK iCLK => Cont[4].CLK iCLK => Cont[3].CLK iCLK => Cont[2].CLK iCLK => Cont[1].CLK iCLK => Cont[0].CLK oRESET <= oRESET~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|SDRAM_PLL:PLL1 inclk0 => sub_wire4[0].IN1 c0 <= altpll:altpll_component.clk c1 <= altpll:altpll_component.clk |DE1_NIOS|SDRAM_PLL:PLL1|altpll:altpll_component inclk[0] => pll.CLK inclk[1] => pll.CLK1 fbin => ~NO_FANOUT~ pllena => ~NO_FANOUT~ clkswitch => ~NO_FANOUT~ areset => ~NO_FANOUT~ pfdena => ~NO_FANOUT~ clkena[0] => ~NO_FANOUT~ clkena[1] => ~NO_FANOUT~ clkena[2] => ~NO_FANOUT~ clkena[3] => ~NO_FANOUT~ clkena[4] => ~NO_FANOUT~ clkena[5] => ~NO_FANOUT~ extclkena[0] => ~NO_FANOUT~ extclkena[1] => ~NO_FANOUT~ extclkena[2] => ~NO_FANOUT~ extclkena[3] => ~NO_FANOUT~ scanclk => ~NO_FANOUT~ scanclkena => ~NO_FANOUT~ scanaclr => ~NO_FANOUT~ scanread => ~NO_FANOUT~ scanwrite => ~NO_FANOUT~ scandata => ~NO_FANOUT~ phasecounterselect[0] => ~NO_FANOUT~ phasecounterselect[1] => ~NO_FANOUT~ phasecounterselect[2] => ~NO_FANOUT~ phasecounterselect[3] => ~NO_FANOUT~ phaseupdown => ~NO_FANOUT~ phasestep => ~NO_FANOUT~ configupdate => ~NO_FANOUT~ fbmimicbidir <= clk[0] <= clk[0]~2.DB_MAX_OUTPUT_PORT_TYPE clk[1] <= clk[1]~1.DB_MAX_OUTPUT_PORT_TYPE clk[2] <= clk[2]~0.DB_MAX_OUTPUT_PORT_TYPE clk[3] <= clk[4] <= clk[5] <= extclk[0] <= extclk[1] <= extclk[2] <= extclk[3] <= clkbad[0] <= clkbad[1] <= enable1 <= enable0 <= activeclock <= clkloss <= locked <= scandataout <= scandone <= sclkout0 <= sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE phasedone <= vcooverrange <= vcounderrange <= fbout <= |DE1_NIOS|system_0:u0 clk => clk~0.IN26 reset_n => reset_n_sources~0.IN1 in_port_to_the_KEY[0] => in_port_to_the_KEY[0]~3.IN1 in_port_to_the_KEY[1] => in_port_to_the_KEY[1]~2.IN1 in_port_to_the_KEY[2] => in_port_to_the_KEY[2]~1.IN1 in_port_to_the_KEY[3] => in_port_to_the_KEY[3]~0.IN1 out_port_from_the_LEDG[0] <= LEDG:the_LEDG.out_port out_port_from_the_LEDG[1] <= LEDG:the_LEDG.out_port out_port_from_the_LEDG[2] <= LEDG:the_LEDG.out_port out_port_from_the_LEDG[3] <= LEDG:the_LEDG.out_port out_port_from_the_LEDG[4] <= LEDG:the_LEDG.out_port out_port_from_the_LEDG[5] <= LEDG:the_LEDG.out_port out_port_from_the_LEDG[6] <= LEDG:the_LEDG.out_port out_port_from_the_LEDG[7] <= LEDG:the_LEDG.out_port out_port_from_the_LEDR[0] <= LEDR:the_LEDR.out_port out_port_from_the_LEDR[1] <= LEDR:the_LEDR.out_port out_port_from_the_LEDR[2] <= LEDR:the_LEDR.out_port out_port_from_the_LEDR[3] <= LEDR:the_LEDR.out_port out_port_from_the_LEDR[4] <= LEDR:the_LEDR.out_port out_port_from_the_LEDR[5] <= LEDR:the_LEDR.out_port out_port_from_the_LEDR[6] <= LEDR:the_LEDR.out_port out_port_from_the_LEDR[7] <= LEDR:the_LEDR.out_port out_port_from_the_LEDR[8] <= LEDR:the_LEDR.out_port out_port_from_the_LEDR[9] <= LEDR:the_LEDR.out_port oSEG0_from_the_SEG7[0] <= SEG7:the_SEG7.oSEG0 oSEG0_from_the_SEG7[1] <= SEG7:the_SEG7.oSEG0 oSEG0_from_the_SEG7[2] <= SEG7:the_SEG7.oSEG0 oSEG0_from_the_SEG7[3] <= SEG7:the_SEG7.oSEG0 oSEG0_from_the_SEG7[4] <= SEG7:the_SEG7.oSEG0 oSEG0_from_the_SEG7[5] <= SEG7:the_SEG7.oSEG0 oSEG0_from_the_SEG7[6] <= SEG7:the_SEG7.oSEG0 oSEG1_from_the_SEG7[0] <= SEG7:the_SEG7.oSEG1 oSEG1_from_the_SEG7[1] <= SEG7:the_SEG7.oSEG1 oSEG1_from_the_SEG7[2] <= SEG7:the_SEG7.oSEG1 oSEG1_from_the_SEG7[3] <= SEG7:the_SEG7.oSEG1 oSEG1_from_the_SEG7[4] <= SEG7:the_SEG7.oSEG1 oSEG1_from_the_SEG7[5] <= SEG7:the_SEG7.oSEG1 oSEG1_from_the_SEG7[6] <= SEG7:the_SEG7.oSEG1 oSEG2_from_the_SEG7[0] <= SEG7:the_SEG7.oSEG2 oSEG2_from_the_SEG7[1] <= SEG7:the_SEG7.oSEG2 oSEG2_from_the_SEG7[2] <= SEG7:the_SEG7.oSEG2 oSEG2_from_the_SEG7[3] <= SEG7:the_SEG7.oSEG2 oSEG2_from_the_SEG7[4] <= SEG7:the_SEG7.oSEG2 oSEG2_from_the_SEG7[5] <= SEG7:the_SEG7.oSEG2 oSEG2_from_the_SEG7[6] <= SEG7:the_SEG7.oSEG2 oSEG3_from_the_SEG7[0] <= SEG7:the_SEG7.oSEG3 oSEG3_from_the_SEG7[1] <= SEG7:the_SEG7.oSEG3 oSEG3_from_the_SEG7[2] <= SEG7:the_SEG7.oSEG3 oSEG3_from_the_SEG7[3] <= SEG7:the_SEG7.oSEG3 oSEG3_from_the_SEG7[4] <= SEG7:the_SEG7.oSEG3 oSEG3_from_the_SEG7[5] <= SEG7:the_SEG7.oSEG3 oSEG3_from_the_SEG7[6] <= SEG7:the_SEG7.oSEG3 in_port_to_the_Switch[0] => in_port_to_the_Switch[0]~9.IN1 in_port_to_the_Switch[1] => in_port_to_the_Switch[1]~8.IN1 in_port_to_the_Switch[2] => in_port_to_the_Switch[2]~7.IN1 in_port_to_the_Switch[3] => in_port_to_the_Switch[3]~6.IN1 in_port_to_the_Switch[4] => in_port_to_the_Switch[4]~5.IN1 in_port_to_the_Switch[5] => in_port_to_the_Switch[5]~4.IN1 in_port_to_the_Switch[6] => in_port_to_the_Switch[6]~3.IN1 in_port_to_the_Switch[7] => in_port_to_the_Switch[7]~2.IN1 in_port_to_the_Switch[8] => in_port_to_the_Switch[8]~1.IN1 in_port_to_the_Switch[9] => in_port_to_the_Switch[9]~0.IN1 zs_addr_from_the_sdram_0[0] <= sdram_0:the_sdram_0.zs_addr zs_addr_from_the_sdram_0[1] <= sdram_0:the_sdram_0.zs_addr zs_addr_from_the_sdram_0[2] <= sdram_0:the_sdram_0.zs_addr zs_addr_from_the_sdram_0[3] <= sdram_0:the_sdram_0.zs_addr zs_addr_from_the_sdram_0[4] <= sdram_0:the_sdram_0.zs_addr zs_addr_from_the_sdram_0[5] <= sdram_0:the_sdram_0.zs_addr zs_addr_from_the_sdram_0[6] <= sdram_0:the_sdram_0.zs_addr zs_addr_from_the_sdram_0[7] <= sdram_0:the_sdram_0.zs_addr zs_addr_from_the_sdram_0[8] <= sdram_0:the_sdram_0.zs_addr zs_addr_from_the_sdram_0[9] <= sdram_0:the_sdram_0.zs_addr zs_addr_from_the_sdram_0[10] <= sdram_0:the_sdram_0.zs_addr zs_addr_from_the_sdram_0[11] <= sdram_0:the_sdram_0.zs_addr zs_ba_from_the_sdram_0[0] <= sdram_0:the_sdram_0.zs_ba zs_ba_from_the_sdram_0[1] <= sdram_0:the_sdram_0.zs_ba zs_cas_n_from_the_sdram_0 <= sdram_0:the_sdram_0.zs_cas_n zs_cke_from_the_sdram_0 <= sdram_0:the_sdram_0.zs_cke zs_cs_n_from_the_sdram_0 <= sdram_0:the_sdram_0.zs_cs_n zs_dq_to_and_from_the_sdram_0[0] <= sdram_0:the_sdram_0.zs_dq zs_dq_to_and_from_the_sdram_0[1] <= sdram_0:the_sdram_0.zs_dq zs_dq_to_and_from_the_sdram_0[2] <= sdram_0:the_sdram_0.zs_dq zs_dq_to_and_from_the_sdram_0[3] <= sdram_0:the_sdram_0.zs_dq zs_dq_to_and_from_the_sdram_0[4] <= sdram_0:the_sdram_0.zs_dq zs_dq_to_and_from_the_sdram_0[5] <= sdram_0:the_sdram_0.zs_dq zs_dq_to_and_from_the_sdram_0[6] <= sdram_0:the_sdram_0.zs_dq zs_dq_to_and_from_the_sdram_0[7] <= sdram_0:the_sdram_0.zs_dq zs_dq_to_and_from_the_sdram_0[8] <= sdram_0:the_sdram_0.zs_dq zs_dq_to_and_from_the_sdram_0[9] <= sdram_0:the_sdram_0.zs_dq zs_dq_to_and_from_the_sdram_0[10] <= sdram_0:the_sdram_0.zs_dq zs_dq_to_and_from_the_sdram_0[11] <= sdram_0:the_sdram_0.zs_dq zs_dq_to_and_from_the_sdram_0[12] <= sdram_0:the_sdram_0.zs_dq zs_dq_to_and_from_the_sdram_0[13] <= sdram_0:the_sdram_0.zs_dq zs_dq_to_and_from_the_sdram_0[14] <= sdram_0:the_sdram_0.zs_dq zs_dq_to_and_from_the_sdram_0[15] <= sdram_0:the_sdram_0.zs_dq zs_dqm_from_the_sdram_0[0] <= sdram_0:the_sdram_0.zs_dqm zs_dqm_from_the_sdram_0[1] <= sdram_0:the_sdram_0.zs_dqm zs_ras_n_from_the_sdram_0 <= sdram_0:the_sdram_0.zs_ras_n zs_we_n_from_the_sdram_0 <= sdram_0:the_sdram_0.zs_we_n SRAM_ADDR_from_the_sram_0[0] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[1] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[2] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[3] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[4] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[5] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[6] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[7] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[8] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[9] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[10] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[11] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[12] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[13] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[14] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[15] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[16] <= sram_0:the_sram_0.SRAM_ADDR SRAM_ADDR_from_the_sram_0[17] <= sram_0:the_sram_0.SRAM_ADDR SRAM_CE_N_from_the_sram_0 <= sram_0:the_sram_0.SRAM_CE_N SRAM_DQ_to_and_from_the_sram_0[0] <= sram_0:the_sram_0.SRAM_DQ SRAM_DQ_to_and_from_the_sram_0[1] <= sram_0:the_sram_0.SRAM_DQ SRAM_DQ_to_and_from_the_sram_0[2] <= sram_0:the_sram_0.SRAM_DQ SRAM_DQ_to_and_from_the_sram_0[3] <= sram_0:the_sram_0.SRAM_DQ SRAM_DQ_to_and_from_the_sram_0[4] <= sram_0:the_sram_0.SRAM_DQ SRAM_DQ_to_and_from_the_sram_0[5] <= sram_0:the_sram_0.SRAM_DQ SRAM_DQ_to_and_from_the_sram_0[6] <= sram_0:the_sram_0.SRAM_DQ SRAM_DQ_to_and_from_the_sram_0[7] <= sram_0:the_sram_0.SRAM_DQ SRAM_DQ_to_and_from_the_sram_0[8] <= sram_0:the_sram_0.SRAM_DQ SRAM_DQ_to_and_from_the_sram_0[9] <= sram_0:the_sram_0.SRAM_DQ SRAM_DQ_to_and_from_the_sram_0[10] <= sram_0:the_sram_0.SRAM_DQ SRAM_DQ_to_and_from_the_sram_0[11] <= sram_0:the_sram_0.SRAM_DQ SRAM_DQ_to_and_from_the_sram_0[12] <= sram_0:the_sram_0.SRAM_DQ SRAM_DQ_to_and_from_the_sram_0[13] <= sram_0:the_sram_0.SRAM_DQ SRAM_DQ_to_and_from_the_sram_0[14] <= sram_0:the_sram_0.SRAM_DQ SRAM_DQ_to_and_from_the_sram_0[15] <= sram_0:the_sram_0.SRAM_DQ SRAM_LB_N_from_the_sram_0 <= sram_0:the_sram_0.SRAM_LB_N SRAM_OE_N_from_the_sram_0 <= sram_0:the_sram_0.SRAM_OE_N SRAM_UB_N_from_the_sram_0 <= sram_0:the_sram_0.SRAM_UB_N SRAM_WE_N_from_the_sram_0 <= sram_0:the_sram_0.SRAM_WE_N select_n_to_the_cfi_flash_0 <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.select_n_to_the_cfi_flash_0 tri_state_bridge_0_address[0] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[1] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[2] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[3] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[4] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[5] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[6] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[7] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[8] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[9] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[10] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[11] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[12] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[13] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[14] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[15] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[16] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[17] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[18] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[19] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[20] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_address[21] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address tri_state_bridge_0_data[0] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data tri_state_bridge_0_data[1] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data tri_state_bridge_0_data[2] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data tri_state_bridge_0_data[3] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data tri_state_bridge_0_data[4] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data tri_state_bridge_0_data[5] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data tri_state_bridge_0_data[6] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data tri_state_bridge_0_data[7] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data tri_state_bridge_0_readn <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_readn write_n_to_the_cfi_flash_0 <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.write_n_to_the_cfi_flash_0 rxd_to_the_uart_0 => rxd_to_the_uart_0~0.IN1 txd_from_the_uart_0 <= uart_0:the_uart_0.txd |DE1_NIOS|system_0:u0|KEY_s1_arbitrator:the_KEY_s1 KEY_s1_irq => KEY_s1_irq_from_sa.DATAIN KEY_s1_readdata[0] => KEY_s1_readdata_from_sa[0].DATAIN KEY_s1_readdata[1] => KEY_s1_readdata_from_sa[1].DATAIN KEY_s1_readdata[2] => KEY_s1_readdata_from_sa[2].DATAIN KEY_s1_readdata[3] => KEY_s1_readdata_from_sa[3].DATAIN clk => d1_reasons_to_wait.CLK clk => d1_KEY_s1_end_xfer~reg0.CLK cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[2] => KEY_s1_address[0].DATAIN cpu_0_data_master_address_to_slave[3] => KEY_s1_address[1].DATAIN cpu_0_data_master_address_to_slave[4] => Equal0.IN19 cpu_0_data_master_address_to_slave[5] => Equal0.IN18 cpu_0_data_master_address_to_slave[6] => Equal0.IN0 cpu_0_data_master_address_to_slave[7] => Equal0.IN17 cpu_0_data_master_address_to_slave[8] => Equal0.IN16 cpu_0_data_master_address_to_slave[9] => Equal0.IN15 cpu_0_data_master_address_to_slave[10] => Equal0.IN14 cpu_0_data_master_address_to_slave[11] => Equal0.IN13 cpu_0_data_master_address_to_slave[12] => Equal0.IN1 cpu_0_data_master_address_to_slave[13] => Equal0.IN12 cpu_0_data_master_address_to_slave[14] => Equal0.IN11 cpu_0_data_master_address_to_slave[15] => Equal0.IN10 cpu_0_data_master_address_to_slave[16] => Equal0.IN9 cpu_0_data_master_address_to_slave[17] => Equal0.IN8 cpu_0_data_master_address_to_slave[18] => Equal0.IN7 cpu_0_data_master_address_to_slave[19] => Equal0.IN2 cpu_0_data_master_address_to_slave[20] => Equal0.IN6 cpu_0_data_master_address_to_slave[21] => Equal0.IN5 cpu_0_data_master_address_to_slave[22] => Equal0.IN3 cpu_0_data_master_address_to_slave[23] => Equal0.IN4 cpu_0_data_master_read => KEY_s1_in_a_read_cycle.IN0 cpu_0_data_master_read => cpu_0_data_master_requests_KEY_s1~0.IN1 cpu_0_data_master_waitrequest => cpu_0_data_master_qualified_request_KEY_s1~0.IN0 cpu_0_data_master_write => KEY_s1_write_n~0.IN0 cpu_0_data_master_write => cpu_0_data_master_qualified_request_KEY_s1~0.IN1 cpu_0_data_master_write => cpu_0_data_master_requests_KEY_s1~0.IN0 cpu_0_data_master_writedata[0] => KEY_s1_writedata[0].DATAIN cpu_0_data_master_writedata[1] => KEY_s1_writedata[1].DATAIN cpu_0_data_master_writedata[2] => KEY_s1_writedata[2].DATAIN cpu_0_data_master_writedata[3] => KEY_s1_writedata[3].DATAIN cpu_0_data_master_writedata[4] => ~NO_FANOUT~ cpu_0_data_master_writedata[5] => ~NO_FANOUT~ cpu_0_data_master_writedata[6] => ~NO_FANOUT~ cpu_0_data_master_writedata[7] => ~NO_FANOUT~ cpu_0_data_master_writedata[8] => ~NO_FANOUT~ cpu_0_data_master_writedata[9] => ~NO_FANOUT~ cpu_0_data_master_writedata[10] => ~NO_FANOUT~ cpu_0_data_master_writedata[11] => ~NO_FANOUT~ cpu_0_data_master_writedata[12] => ~NO_FANOUT~ cpu_0_data_master_writedata[13] => ~NO_FANOUT~ cpu_0_data_master_writedata[14] => ~NO_FANOUT~ cpu_0_data_master_writedata[15] => ~NO_FANOUT~ cpu_0_data_master_writedata[16] => ~NO_FANOUT~ cpu_0_data_master_writedata[17] => ~NO_FANOUT~ cpu_0_data_master_writedata[18] => ~NO_FANOUT~ cpu_0_data_master_writedata[19] => ~NO_FANOUT~ cpu_0_data_master_writedata[20] => ~NO_FANOUT~ cpu_0_data_master_writedata[21] => ~NO_FANOUT~ cpu_0_data_master_writedata[22] => ~NO_FANOUT~ cpu_0_data_master_writedata[23] => ~NO_FANOUT~ cpu_0_data_master_writedata[24] => ~NO_FANOUT~ cpu_0_data_master_writedata[25] => ~NO_FANOUT~ cpu_0_data_master_writedata[26] => ~NO_FANOUT~ cpu_0_data_master_writedata[27] => ~NO_FANOUT~ cpu_0_data_master_writedata[28] => ~NO_FANOUT~ cpu_0_data_master_writedata[29] => ~NO_FANOUT~ cpu_0_data_master_writedata[30] => ~NO_FANOUT~ cpu_0_data_master_writedata[31] => ~NO_FANOUT~ reset_n => KEY_s1_reset_n.DATAIN reset_n => d1_reasons_to_wait.ACLR reset_n => d1_KEY_s1_end_xfer~reg0.PRESET KEY_s1_address[0] <= cpu_0_data_master_address_to_slave[2].DB_MAX_OUTPUT_PORT_TYPE KEY_s1_address[1] <= cpu_0_data_master_address_to_slave[3].DB_MAX_OUTPUT_PORT_TYPE KEY_s1_chipselect <= cpu_0_data_master_qualified_request_KEY_s1~1.DB_MAX_OUTPUT_PORT_TYPE KEY_s1_irq_from_sa <= KEY_s1_irq.DB_MAX_OUTPUT_PORT_TYPE KEY_s1_readdata_from_sa[0] <= KEY_s1_readdata[0].DB_MAX_OUTPUT_PORT_TYPE KEY_s1_readdata_from_sa[1] <= KEY_s1_readdata[1].DB_MAX_OUTPUT_PORT_TYPE KEY_s1_readdata_from_sa[2] <= KEY_s1_readdata[2].DB_MAX_OUTPUT_PORT_TYPE KEY_s1_readdata_from_sa[3] <= KEY_s1_readdata[3].DB_MAX_OUTPUT_PORT_TYPE KEY_s1_reset_n <= reset_n.DB_MAX_OUTPUT_PORT_TYPE KEY_s1_write_n <= KEY_s1_write_n~0.DB_MAX_OUTPUT_PORT_TYPE KEY_s1_writedata[0] <= cpu_0_data_master_writedata[0].DB_MAX_OUTPUT_PORT_TYPE KEY_s1_writedata[1] <= cpu_0_data_master_writedata[1].DB_MAX_OUTPUT_PORT_TYPE KEY_s1_writedata[2] <= cpu_0_data_master_writedata[2].DB_MAX_OUTPUT_PORT_TYPE KEY_s1_writedata[3] <= cpu_0_data_master_writedata[3].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_granted_KEY_s1 <= cpu_0_data_master_qualified_request_KEY_s1~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_qualified_request_KEY_s1 <= cpu_0_data_master_qualified_request_KEY_s1~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_read_data_valid_KEY_s1 <= cpu_0_data_master_requests_KEY_s1 <= cpu_0_data_master_requests_KEY_s1~1.DB_MAX_OUTPUT_PORT_TYPE d1_KEY_s1_end_xfer <= d1_KEY_s1_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|KEY:the_KEY address[0] => Equal0.IN30 address[0] => Equal1.IN30 address[0] => Equal2.IN61 address[1] => Equal0.IN31 address[1] => Equal1.IN61 address[1] => Equal2.IN60 chipselect => always1~0.IN1 clk => readdata[3]~reg0.CLK clk => readdata[2]~reg0.CLK clk => readdata[1]~reg0.CLK clk => readdata[0]~reg0.CLK clk => irq_mask[3].CLK clk => irq_mask[2].CLK clk => irq_mask[1].CLK clk => irq_mask[0].CLK clk => edge_capture[0].CLK clk => edge_capture[1].CLK clk => edge_capture[2].CLK clk => edge_capture[3].CLK clk => d1_data_in[3].CLK clk => d1_data_in[2].CLK clk => d1_data_in[1].CLK clk => d1_data_in[0].CLK clk => d2_data_in[3].CLK clk => d2_data_in[2].CLK clk => d2_data_in[1].CLK clk => d2_data_in[0].CLK in_port[0] => d1_data_in[0].DATAIN in_port[0] => read_mux_out~0.IN1 in_port[1] => d1_data_in[1].DATAIN in_port[1] => read_mux_out~1.IN1 in_port[2] => d1_data_in[2].DATAIN in_port[2] => read_mux_out~2.IN1 in_port[3] => d1_data_in[3].DATAIN in_port[3] => read_mux_out~3.IN1 reset_n => edge_capture[3].ACLR reset_n => edge_capture[2].ACLR reset_n => edge_capture[1].ACLR reset_n => d2_data_in[0].ACLR reset_n => d2_data_in[1].ACLR reset_n => d2_data_in[2].ACLR reset_n => d2_data_in[3].ACLR reset_n => d1_data_in[0].ACLR reset_n => d1_data_in[1].ACLR reset_n => d1_data_in[2].ACLR reset_n => d1_data_in[3].ACLR reset_n => edge_capture[0].ACLR reset_n => irq_mask[0].ACLR reset_n => irq_mask[1].ACLR reset_n => irq_mask[2].ACLR reset_n => irq_mask[3].ACLR reset_n => readdata[3]~reg0.ACLR reset_n => readdata[2]~reg0.ACLR reset_n => readdata[1]~reg0.ACLR reset_n => readdata[0]~reg0.ACLR write_n => always1~0.IN0 writedata[0] => irq_mask[0].DATAIN writedata[1] => irq_mask[1].DATAIN writedata[2] => irq_mask[2].DATAIN writedata[3] => irq_mask[3].DATAIN irq <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|LEDG_s1_arbitrator:the_LEDG_s1 clk => d1_reasons_to_wait.CLK clk => d1_LEDG_s1_end_xfer~reg0.CLK cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[2] => LEDG_s1_address[0].DATAIN cpu_0_data_master_address_to_slave[3] => LEDG_s1_address[1].DATAIN cpu_0_data_master_address_to_slave[4] => Equal0.IN19 cpu_0_data_master_address_to_slave[5] => Equal0.IN0 cpu_0_data_master_address_to_slave[6] => Equal0.IN18 cpu_0_data_master_address_to_slave[7] => Equal0.IN17 cpu_0_data_master_address_to_slave[8] => Equal0.IN16 cpu_0_data_master_address_to_slave[9] => Equal0.IN15 cpu_0_data_master_address_to_slave[10] => Equal0.IN14 cpu_0_data_master_address_to_slave[11] => Equal0.IN13 cpu_0_data_master_address_to_slave[12] => Equal0.IN1 cpu_0_data_master_address_to_slave[13] => Equal0.IN12 cpu_0_data_master_address_to_slave[14] => Equal0.IN11 cpu_0_data_master_address_to_slave[15] => Equal0.IN10 cpu_0_data_master_address_to_slave[16] => Equal0.IN9 cpu_0_data_master_address_to_slave[17] => Equal0.IN8 cpu_0_data_master_address_to_slave[18] => Equal0.IN7 cpu_0_data_master_address_to_slave[19] => Equal0.IN2 cpu_0_data_master_address_to_slave[20] => Equal0.IN6 cpu_0_data_master_address_to_slave[21] => Equal0.IN5 cpu_0_data_master_address_to_slave[22] => Equal0.IN3 cpu_0_data_master_address_to_slave[23] => Equal0.IN4 cpu_0_data_master_byteenable[0] => LEDG_s1_pretend_byte_enable.DATAB cpu_0_data_master_byteenable[1] => ~NO_FANOUT~ cpu_0_data_master_byteenable[2] => ~NO_FANOUT~ cpu_0_data_master_byteenable[3] => ~NO_FANOUT~ cpu_0_data_master_read => LEDG_s1_in_a_read_cycle.IN0 cpu_0_data_master_read => cpu_0_data_master_requests_LEDG_s1~0.IN1 cpu_0_data_master_waitrequest => cpu_0_data_master_qualified_request_LEDG_s1~0.IN0 cpu_0_data_master_write => LEDG_s1_write_n~0.IN0 cpu_0_data_master_write => cpu_0_data_master_qualified_request_LEDG_s1~0.IN1 cpu_0_data_master_write => cpu_0_data_master_requests_LEDG_s1~2.IN0 cpu_0_data_master_write => cpu_0_data_master_requests_LEDG_s1~0.IN0 cpu_0_data_master_writedata[0] => LEDG_s1_writedata[0].DATAIN cpu_0_data_master_writedata[1] => LEDG_s1_writedata[1].DATAIN cpu_0_data_master_writedata[2] => LEDG_s1_writedata[2].DATAIN cpu_0_data_master_writedata[3] => LEDG_s1_writedata[3].DATAIN cpu_0_data_master_writedata[4] => LEDG_s1_writedata[4].DATAIN cpu_0_data_master_writedata[5] => LEDG_s1_writedata[5].DATAIN cpu_0_data_master_writedata[6] => LEDG_s1_writedata[6].DATAIN cpu_0_data_master_writedata[7] => LEDG_s1_writedata[7].DATAIN cpu_0_data_master_writedata[8] => ~NO_FANOUT~ cpu_0_data_master_writedata[9] => ~NO_FANOUT~ cpu_0_data_master_writedata[10] => ~NO_FANOUT~ cpu_0_data_master_writedata[11] => ~NO_FANOUT~ cpu_0_data_master_writedata[12] => ~NO_FANOUT~ cpu_0_data_master_writedata[13] => ~NO_FANOUT~ cpu_0_data_master_writedata[14] => ~NO_FANOUT~ cpu_0_data_master_writedata[15] => ~NO_FANOUT~ cpu_0_data_master_writedata[16] => ~NO_FANOUT~ cpu_0_data_master_writedata[17] => ~NO_FANOUT~ cpu_0_data_master_writedata[18] => ~NO_FANOUT~ cpu_0_data_master_writedata[19] => ~NO_FANOUT~ cpu_0_data_master_writedata[20] => ~NO_FANOUT~ cpu_0_data_master_writedata[21] => ~NO_FANOUT~ cpu_0_data_master_writedata[22] => ~NO_FANOUT~ cpu_0_data_master_writedata[23] => ~NO_FANOUT~ cpu_0_data_master_writedata[24] => ~NO_FANOUT~ cpu_0_data_master_writedata[25] => ~NO_FANOUT~ cpu_0_data_master_writedata[26] => ~NO_FANOUT~ cpu_0_data_master_writedata[27] => ~NO_FANOUT~ cpu_0_data_master_writedata[28] => ~NO_FANOUT~ cpu_0_data_master_writedata[29] => ~NO_FANOUT~ cpu_0_data_master_writedata[30] => ~NO_FANOUT~ cpu_0_data_master_writedata[31] => ~NO_FANOUT~ reset_n => LEDG_s1_reset_n.DATAIN reset_n => d1_reasons_to_wait.ACLR reset_n => d1_LEDG_s1_end_xfer~reg0.PRESET LEDG_s1_address[0] <= cpu_0_data_master_address_to_slave[2].DB_MAX_OUTPUT_PORT_TYPE LEDG_s1_address[1] <= cpu_0_data_master_address_to_slave[3].DB_MAX_OUTPUT_PORT_TYPE LEDG_s1_chipselect <= cpu_0_data_master_qualified_request_LEDG_s1~1.DB_MAX_OUTPUT_PORT_TYPE LEDG_s1_reset_n <= reset_n.DB_MAX_OUTPUT_PORT_TYPE LEDG_s1_write_n <= LEDG_s1_write_n~1.DB_MAX_OUTPUT_PORT_TYPE LEDG_s1_writedata[0] <= cpu_0_data_master_writedata[0].DB_MAX_OUTPUT_PORT_TYPE LEDG_s1_writedata[1] <= cpu_0_data_master_writedata[1].DB_MAX_OUTPUT_PORT_TYPE LEDG_s1_writedata[2] <= cpu_0_data_master_writedata[2].DB_MAX_OUTPUT_PORT_TYPE LEDG_s1_writedata[3] <= cpu_0_data_master_writedata[3].DB_MAX_OUTPUT_PORT_TYPE LEDG_s1_writedata[4] <= cpu_0_data_master_writedata[4].DB_MAX_OUTPUT_PORT_TYPE LEDG_s1_writedata[5] <= cpu_0_data_master_writedata[5].DB_MAX_OUTPUT_PORT_TYPE LEDG_s1_writedata[6] <= cpu_0_data_master_writedata[6].DB_MAX_OUTPUT_PORT_TYPE LEDG_s1_writedata[7] <= cpu_0_data_master_writedata[7].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_granted_LEDG_s1 <= cpu_0_data_master_qualified_request_LEDG_s1~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_qualified_request_LEDG_s1 <= cpu_0_data_master_qualified_request_LEDG_s1~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_read_data_valid_LEDG_s1 <= cpu_0_data_master_requests_LEDG_s1 <= cpu_0_data_master_requests_LEDG_s1~2.DB_MAX_OUTPUT_PORT_TYPE d1_LEDG_s1_end_xfer <= d1_LEDG_s1_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|LEDG:the_LEDG address[0] => Equal0.IN30 address[1] => Equal0.IN31 chipselect => always0~0.IN1 clk => data_out[7].CLK clk => data_out[6].CLK clk => data_out[5].CLK clk => data_out[4].CLK clk => data_out[3].CLK clk => data_out[2].CLK clk => data_out[1].CLK clk => data_out[0].CLK reset_n => data_out[7].ACLR reset_n => data_out[6].ACLR reset_n => data_out[5].ACLR reset_n => data_out[4].ACLR reset_n => data_out[3].ACLR reset_n => data_out[2].ACLR reset_n => data_out[1].ACLR reset_n => data_out[0].ACLR write_n => always0~0.IN0 writedata[0] => data_out[0].DATAIN writedata[1] => data_out[1].DATAIN writedata[2] => data_out[2].DATAIN writedata[3] => data_out[3].DATAIN writedata[4] => data_out[4].DATAIN writedata[5] => data_out[5].DATAIN writedata[6] => data_out[6].DATAIN writedata[7] => data_out[7].DATAIN out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE out_port[7] <= data_out[7].DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|LEDR_s1_arbitrator:the_LEDR_s1 clk => d1_reasons_to_wait.CLK clk => d1_LEDR_s1_end_xfer~reg0.CLK cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[2] => LEDR_s1_address[0].DATAIN cpu_0_data_master_address_to_slave[3] => LEDR_s1_address[1].DATAIN cpu_0_data_master_address_to_slave[4] => Equal0.IN0 cpu_0_data_master_address_to_slave[5] => Equal0.IN1 cpu_0_data_master_address_to_slave[6] => Equal0.IN19 cpu_0_data_master_address_to_slave[7] => Equal0.IN18 cpu_0_data_master_address_to_slave[8] => Equal0.IN17 cpu_0_data_master_address_to_slave[9] => Equal0.IN16 cpu_0_data_master_address_to_slave[10] => Equal0.IN15 cpu_0_data_master_address_to_slave[11] => Equal0.IN14 cpu_0_data_master_address_to_slave[12] => Equal0.IN2 cpu_0_data_master_address_to_slave[13] => Equal0.IN13 cpu_0_data_master_address_to_slave[14] => Equal0.IN12 cpu_0_data_master_address_to_slave[15] => Equal0.IN11 cpu_0_data_master_address_to_slave[16] => Equal0.IN10 cpu_0_data_master_address_to_slave[17] => Equal0.IN9 cpu_0_data_master_address_to_slave[18] => Equal0.IN8 cpu_0_data_master_address_to_slave[19] => Equal0.IN3 cpu_0_data_master_address_to_slave[20] => Equal0.IN7 cpu_0_data_master_address_to_slave[21] => Equal0.IN6 cpu_0_data_master_address_to_slave[22] => Equal0.IN4 cpu_0_data_master_address_to_slave[23] => Equal0.IN5 cpu_0_data_master_read => LEDR_s1_in_a_read_cycle.IN0 cpu_0_data_master_read => cpu_0_data_master_requests_LEDR_s1~0.IN1 cpu_0_data_master_waitrequest => cpu_0_data_master_qualified_request_LEDR_s1~0.IN0 cpu_0_data_master_write => LEDR_s1_write_n~0.IN0 cpu_0_data_master_write => cpu_0_data_master_qualified_request_LEDR_s1~0.IN1 cpu_0_data_master_write => cpu_0_data_master_requests_LEDR_s1~2.IN0 cpu_0_data_master_write => cpu_0_data_master_requests_LEDR_s1~0.IN0 cpu_0_data_master_writedata[0] => LEDR_s1_writedata[0].DATAIN cpu_0_data_master_writedata[1] => LEDR_s1_writedata[1].DATAIN cpu_0_data_master_writedata[2] => LEDR_s1_writedata[2].DATAIN cpu_0_data_master_writedata[3] => LEDR_s1_writedata[3].DATAIN cpu_0_data_master_writedata[4] => LEDR_s1_writedata[4].DATAIN cpu_0_data_master_writedata[5] => LEDR_s1_writedata[5].DATAIN cpu_0_data_master_writedata[6] => LEDR_s1_writedata[6].DATAIN cpu_0_data_master_writedata[7] => LEDR_s1_writedata[7].DATAIN cpu_0_data_master_writedata[8] => LEDR_s1_writedata[8].DATAIN cpu_0_data_master_writedata[9] => LEDR_s1_writedata[9].DATAIN cpu_0_data_master_writedata[10] => ~NO_FANOUT~ cpu_0_data_master_writedata[11] => ~NO_FANOUT~ cpu_0_data_master_writedata[12] => ~NO_FANOUT~ cpu_0_data_master_writedata[13] => ~NO_FANOUT~ cpu_0_data_master_writedata[14] => ~NO_FANOUT~ cpu_0_data_master_writedata[15] => ~NO_FANOUT~ cpu_0_data_master_writedata[16] => ~NO_FANOUT~ cpu_0_data_master_writedata[17] => ~NO_FANOUT~ cpu_0_data_master_writedata[18] => ~NO_FANOUT~ cpu_0_data_master_writedata[19] => ~NO_FANOUT~ cpu_0_data_master_writedata[20] => ~NO_FANOUT~ cpu_0_data_master_writedata[21] => ~NO_FANOUT~ cpu_0_data_master_writedata[22] => ~NO_FANOUT~ cpu_0_data_master_writedata[23] => ~NO_FANOUT~ cpu_0_data_master_writedata[24] => ~NO_FANOUT~ cpu_0_data_master_writedata[25] => ~NO_FANOUT~ cpu_0_data_master_writedata[26] => ~NO_FANOUT~ cpu_0_data_master_writedata[27] => ~NO_FANOUT~ cpu_0_data_master_writedata[28] => ~NO_FANOUT~ cpu_0_data_master_writedata[29] => ~NO_FANOUT~ cpu_0_data_master_writedata[30] => ~NO_FANOUT~ cpu_0_data_master_writedata[31] => ~NO_FANOUT~ reset_n => LEDR_s1_reset_n.DATAIN reset_n => d1_reasons_to_wait.ACLR reset_n => d1_LEDR_s1_end_xfer~reg0.PRESET LEDR_s1_address[0] <= cpu_0_data_master_address_to_slave[2].DB_MAX_OUTPUT_PORT_TYPE LEDR_s1_address[1] <= cpu_0_data_master_address_to_slave[3].DB_MAX_OUTPUT_PORT_TYPE LEDR_s1_chipselect <= cpu_0_data_master_qualified_request_LEDR_s1~1.DB_MAX_OUTPUT_PORT_TYPE LEDR_s1_reset_n <= reset_n.DB_MAX_OUTPUT_PORT_TYPE LEDR_s1_write_n <= LEDR_s1_write_n~0.DB_MAX_OUTPUT_PORT_TYPE LEDR_s1_writedata[0] <= cpu_0_data_master_writedata[0].DB_MAX_OUTPUT_PORT_TYPE LEDR_s1_writedata[1] <= cpu_0_data_master_writedata[1].DB_MAX_OUTPUT_PORT_TYPE LEDR_s1_writedata[2] <= cpu_0_data_master_writedata[2].DB_MAX_OUTPUT_PORT_TYPE LEDR_s1_writedata[3] <= cpu_0_data_master_writedata[3].DB_MAX_OUTPUT_PORT_TYPE LEDR_s1_writedata[4] <= cpu_0_data_master_writedata[4].DB_MAX_OUTPUT_PORT_TYPE LEDR_s1_writedata[5] <= cpu_0_data_master_writedata[5].DB_MAX_OUTPUT_PORT_TYPE LEDR_s1_writedata[6] <= cpu_0_data_master_writedata[6].DB_MAX_OUTPUT_PORT_TYPE LEDR_s1_writedata[7] <= cpu_0_data_master_writedata[7].DB_MAX_OUTPUT_PORT_TYPE LEDR_s1_writedata[8] <= cpu_0_data_master_writedata[8].DB_MAX_OUTPUT_PORT_TYPE LEDR_s1_writedata[9] <= cpu_0_data_master_writedata[9].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_granted_LEDR_s1 <= cpu_0_data_master_qualified_request_LEDR_s1~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_qualified_request_LEDR_s1 <= cpu_0_data_master_qualified_request_LEDR_s1~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_read_data_valid_LEDR_s1 <= cpu_0_data_master_requests_LEDR_s1 <= cpu_0_data_master_requests_LEDR_s1~2.DB_MAX_OUTPUT_PORT_TYPE d1_LEDR_s1_end_xfer <= d1_LEDR_s1_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|LEDR:the_LEDR address[0] => Equal0.IN30 address[1] => Equal0.IN31 chipselect => always0~0.IN1 clk => data_out[9].CLK clk => data_out[8].CLK clk => data_out[7].CLK clk => data_out[6].CLK clk => data_out[5].CLK clk => data_out[4].CLK clk => data_out[3].CLK clk => data_out[2].CLK clk => data_out[1].CLK clk => data_out[0].CLK reset_n => data_out[9].ACLR reset_n => data_out[8].ACLR reset_n => data_out[7].ACLR reset_n => data_out[6].ACLR reset_n => data_out[5].ACLR reset_n => data_out[4].ACLR reset_n => data_out[3].ACLR reset_n => data_out[2].ACLR reset_n => data_out[1].ACLR reset_n => data_out[0].ACLR write_n => always0~0.IN0 writedata[0] => data_out[0].DATAIN writedata[1] => data_out[1].DATAIN writedata[2] => data_out[2].DATAIN writedata[3] => data_out[3].DATAIN writedata[4] => data_out[4].DATAIN writedata[5] => data_out[5].DATAIN writedata[6] => data_out[6].DATAIN writedata[7] => data_out[7].DATAIN writedata[8] => data_out[8].DATAIN writedata[9] => data_out[9].DATAIN out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE out_port[7] <= data_out[7].DB_MAX_OUTPUT_PORT_TYPE out_port[8] <= data_out[8].DB_MAX_OUTPUT_PORT_TYPE out_port[9] <= data_out[9].DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|SEG7_avalonS_arbitrator:the_SEG7_avalonS clk => d1_SEG7_avalonS_end_xfer~reg0.CLK cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[2] => Equal0.IN21 cpu_0_data_master_address_to_slave[3] => Equal0.IN0 cpu_0_data_master_address_to_slave[4] => Equal0.IN20 cpu_0_data_master_address_to_slave[5] => Equal0.IN1 cpu_0_data_master_address_to_slave[6] => Equal0.IN2 cpu_0_data_master_address_to_slave[7] => Equal0.IN19 cpu_0_data_master_address_to_slave[8] => Equal0.IN18 cpu_0_data_master_address_to_slave[9] => Equal0.IN17 cpu_0_data_master_address_to_slave[10] => Equal0.IN16 cpu_0_data_master_address_to_slave[11] => Equal0.IN15 cpu_0_data_master_address_to_slave[12] => Equal0.IN3 cpu_0_data_master_address_to_slave[13] => Equal0.IN14 cpu_0_data_master_address_to_slave[14] => Equal0.IN13 cpu_0_data_master_address_to_slave[15] => Equal0.IN12 cpu_0_data_master_address_to_slave[16] => Equal0.IN11 cpu_0_data_master_address_to_slave[17] => Equal0.IN10 cpu_0_data_master_address_to_slave[18] => Equal0.IN9 cpu_0_data_master_address_to_slave[19] => Equal0.IN4 cpu_0_data_master_address_to_slave[20] => Equal0.IN8 cpu_0_data_master_address_to_slave[21] => Equal0.IN7 cpu_0_data_master_address_to_slave[22] => Equal0.IN5 cpu_0_data_master_address_to_slave[23] => Equal0.IN6 cpu_0_data_master_read => cpu_0_data_master_requests_SEG7_avalonS~0.IN1 cpu_0_data_master_waitrequest => cpu_0_data_master_qualified_request_SEG7_avalonS~0.IN1 cpu_0_data_master_write => SEG7_avalonS_write~0.IN0 cpu_0_data_master_write => cpu_0_data_master_qualified_request_SEG7_avalonS~0.IN0 cpu_0_data_master_write => cpu_0_data_master_requests_SEG7_avalonS~2.IN0 cpu_0_data_master_write => cpu_0_data_master_requests_SEG7_avalonS~0.IN0 cpu_0_data_master_writedata[0] => SEG7_avalonS_writedata[0].DATAIN cpu_0_data_master_writedata[1] => SEG7_avalonS_writedata[1].DATAIN cpu_0_data_master_writedata[2] => SEG7_avalonS_writedata[2].DATAIN cpu_0_data_master_writedata[3] => SEG7_avalonS_writedata[3].DATAIN cpu_0_data_master_writedata[4] => SEG7_avalonS_writedata[4].DATAIN cpu_0_data_master_writedata[5] => SEG7_avalonS_writedata[5].DATAIN cpu_0_data_master_writedata[6] => SEG7_avalonS_writedata[6].DATAIN cpu_0_data_master_writedata[7] => SEG7_avalonS_writedata[7].DATAIN cpu_0_data_master_writedata[8] => SEG7_avalonS_writedata[8].DATAIN cpu_0_data_master_writedata[9] => SEG7_avalonS_writedata[9].DATAIN cpu_0_data_master_writedata[10] => SEG7_avalonS_writedata[10].DATAIN cpu_0_data_master_writedata[11] => SEG7_avalonS_writedata[11].DATAIN cpu_0_data_master_writedata[12] => SEG7_avalonS_writedata[12].DATAIN cpu_0_data_master_writedata[13] => SEG7_avalonS_writedata[13].DATAIN cpu_0_data_master_writedata[14] => SEG7_avalonS_writedata[14].DATAIN cpu_0_data_master_writedata[15] => SEG7_avalonS_writedata[15].DATAIN cpu_0_data_master_writedata[16] => ~NO_FANOUT~ cpu_0_data_master_writedata[17] => ~NO_FANOUT~ cpu_0_data_master_writedata[18] => ~NO_FANOUT~ cpu_0_data_master_writedata[19] => ~NO_FANOUT~ cpu_0_data_master_writedata[20] => ~NO_FANOUT~ cpu_0_data_master_writedata[21] => ~NO_FANOUT~ cpu_0_data_master_writedata[22] => ~NO_FANOUT~ cpu_0_data_master_writedata[23] => ~NO_FANOUT~ cpu_0_data_master_writedata[24] => ~NO_FANOUT~ cpu_0_data_master_writedata[25] => ~NO_FANOUT~ cpu_0_data_master_writedata[26] => ~NO_FANOUT~ cpu_0_data_master_writedata[27] => ~NO_FANOUT~ cpu_0_data_master_writedata[28] => ~NO_FANOUT~ cpu_0_data_master_writedata[29] => ~NO_FANOUT~ cpu_0_data_master_writedata[30] => ~NO_FANOUT~ cpu_0_data_master_writedata[31] => ~NO_FANOUT~ reset_n => SEG7_avalonS_reset_n.DATAIN reset_n => d1_SEG7_avalonS_end_xfer~reg0.PRESET SEG7_avalonS_reset_n <= reset_n.DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_write <= SEG7_avalonS_write~0.DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[0] <= cpu_0_data_master_writedata[0].DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[1] <= cpu_0_data_master_writedata[1].DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[2] <= cpu_0_data_master_writedata[2].DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[3] <= cpu_0_data_master_writedata[3].DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[4] <= cpu_0_data_master_writedata[4].DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[5] <= cpu_0_data_master_writedata[5].DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[6] <= cpu_0_data_master_writedata[6].DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[7] <= cpu_0_data_master_writedata[7].DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[8] <= cpu_0_data_master_writedata[8].DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[9] <= cpu_0_data_master_writedata[9].DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[10] <= cpu_0_data_master_writedata[10].DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[11] <= cpu_0_data_master_writedata[11].DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[12] <= cpu_0_data_master_writedata[12].DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[13] <= cpu_0_data_master_writedata[13].DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[14] <= cpu_0_data_master_writedata[14].DB_MAX_OUTPUT_PORT_TYPE SEG7_avalonS_writedata[15] <= cpu_0_data_master_writedata[15].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_granted_SEG7_avalonS <= cpu_0_data_master_qualified_request_SEG7_avalonS~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_qualified_request_SEG7_avalonS <= cpu_0_data_master_qualified_request_SEG7_avalonS~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_read_data_valid_SEG7_avalonS <= cpu_0_data_master_requests_SEG7_avalonS <= cpu_0_data_master_requests_SEG7_avalonS~2.DB_MAX_OUTPUT_PORT_TYPE d1_SEG7_avalonS_end_xfer <= d1_SEG7_avalonS_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|SEG7:the_SEG7 iCLK => iCLK~0.IN1 iDIG[0] => iDIG[0]~15.IN1 iDIG[1] => iDIG[1]~14.IN1 iDIG[2] => iDIG[2]~13.IN1 iDIG[3] => iDIG[3]~12.IN1 iDIG[4] => iDIG[4]~11.IN1 iDIG[5] => iDIG[5]~10.IN1 iDIG[6] => iDIG[6]~9.IN1 iDIG[7] => iDIG[7]~8.IN1 iDIG[8] => iDIG[8]~7.IN1 iDIG[9] => iDIG[9]~6.IN1 iDIG[10] => iDIG[10]~5.IN1 iDIG[11] => iDIG[11]~4.IN1 iDIG[12] => iDIG[12]~3.IN1 iDIG[13] => iDIG[13]~2.IN1 iDIG[14] => iDIG[14]~1.IN1 iDIG[15] => iDIG[15]~0.IN1 iRST_N => iRST_N~0.IN1 iWR => iWR~0.IN1 oSEG0[0] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG0 oSEG0[1] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG0 oSEG0[2] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG0 oSEG0[3] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG0 oSEG0[4] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG0 oSEG0[5] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG0 oSEG0[6] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG0 oSEG1[0] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG1 oSEG1[1] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG1 oSEG1[2] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG1 oSEG1[3] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG1 oSEG1[4] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG1 oSEG1[5] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG1 oSEG1[6] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG1 oSEG2[0] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG2 oSEG2[1] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG2 oSEG2[2] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG2 oSEG2[3] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG2 oSEG2[4] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG2 oSEG2[5] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG2 oSEG2[6] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG2 oSEG3[0] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG3 oSEG3[1] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG3 oSEG3[2] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG3 oSEG3[3] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG3 oSEG3[4] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG3 oSEG3[5] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG3 oSEG3[6] <= SEG7_LUT_4:the_SEG7_LUT_4.oSEG3 |DE1_NIOS|system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4 oSEG0[0] <= SEG7_LUT:u0.port0 oSEG0[1] <= SEG7_LUT:u0.port0 oSEG0[2] <= SEG7_LUT:u0.port0 oSEG0[3] <= SEG7_LUT:u0.port0 oSEG0[4] <= SEG7_LUT:u0.port0 oSEG0[5] <= SEG7_LUT:u0.port0 oSEG0[6] <= SEG7_LUT:u0.port0 oSEG1[0] <= SEG7_LUT:u1.port0 oSEG1[1] <= SEG7_LUT:u1.port0 oSEG1[2] <= SEG7_LUT:u1.port0 oSEG1[3] <= SEG7_LUT:u1.port0 oSEG1[4] <= SEG7_LUT:u1.port0 oSEG1[5] <= SEG7_LUT:u1.port0 oSEG1[6] <= SEG7_LUT:u1.port0 oSEG2[0] <= SEG7_LUT:u2.port0 oSEG2[1] <= SEG7_LUT:u2.port0 oSEG2[2] <= SEG7_LUT:u2.port0 oSEG2[3] <= SEG7_LUT:u2.port0 oSEG2[4] <= SEG7_LUT:u2.port0 oSEG2[5] <= SEG7_LUT:u2.port0 oSEG2[6] <= SEG7_LUT:u2.port0 oSEG3[0] <= SEG7_LUT:u3.port0 oSEG3[1] <= SEG7_LUT:u3.port0 oSEG3[2] <= SEG7_LUT:u3.port0 oSEG3[3] <= SEG7_LUT:u3.port0 oSEG3[4] <= SEG7_LUT:u3.port0 oSEG3[5] <= SEG7_LUT:u3.port0 oSEG3[6] <= SEG7_LUT:u3.port0 iDIG[0] => rDIG~31.DATAB iDIG[1] => rDIG~30.DATAB iDIG[2] => rDIG~29.DATAB iDIG[3] => rDIG~28.DATAB iDIG[4] => rDIG~27.DATAB iDIG[5] => rDIG~26.DATAB iDIG[6] => rDIG~25.DATAB iDIG[7] => rDIG~24.DATAB iDIG[8] => rDIG~23.DATAB iDIG[9] => rDIG~22.DATAB iDIG[10] => rDIG~21.DATAB iDIG[11] => rDIG~20.DATAB iDIG[12] => rDIG~19.DATAB iDIG[13] => rDIG~18.DATAB iDIG[14] => rDIG~17.DATAB iDIG[15] => rDIG~16.DATAB iWR => rDIG~31.OUTPUTSELECT iWR => rDIG~30.OUTPUTSELECT iWR => rDIG~29.OUTPUTSELECT iWR => rDIG~28.OUTPUTSELECT iWR => rDIG~27.OUTPUTSELECT iWR => rDIG~26.OUTPUTSELECT iWR => rDIG~25.OUTPUTSELECT iWR => rDIG~24.OUTPUTSELECT iWR => rDIG~23.OUTPUTSELECT iWR => rDIG~22.OUTPUTSELECT iWR => rDIG~21.OUTPUTSELECT iWR => rDIG~20.OUTPUTSELECT iWR => rDIG~19.OUTPUTSELECT iWR => rDIG~18.OUTPUTSELECT iWR => rDIG~17.OUTPUTSELECT iWR => rDIG~16.OUTPUTSELECT iCLK => rDIG[15].CLK iCLK => rDIG[14].CLK iCLK => rDIG[13].CLK iCLK => rDIG[12].CLK iCLK => rDIG[11].CLK iCLK => rDIG[10].CLK iCLK => rDIG[9].CLK iCLK => rDIG[8].CLK iCLK => rDIG[7].CLK iCLK => rDIG[6].CLK iCLK => rDIG[5].CLK iCLK => rDIG[4].CLK iCLK => rDIG[3].CLK iCLK => rDIG[2].CLK iCLK => rDIG[1].CLK iCLK => rDIG[0].CLK iRST_N => rDIG[15].ACLR iRST_N => rDIG[14].ACLR iRST_N => rDIG[13].ACLR iRST_N => rDIG[12].ACLR iRST_N => rDIG[11].ACLR iRST_N => rDIG[10].ACLR iRST_N => rDIG[9].ACLR iRST_N => rDIG[8].ACLR iRST_N => rDIG[7].ACLR iRST_N => rDIG[6].ACLR iRST_N => rDIG[5].ACLR iRST_N => rDIG[4].ACLR iRST_N => rDIG[3].ACLR iRST_N => rDIG[2].ACLR iRST_N => rDIG[1].ACLR iRST_N => rDIG[0].ACLR |DE1_NIOS|system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u0 oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE iDIG[0] => Decoder0.IN3 iDIG[1] => Decoder0.IN2 iDIG[2] => Decoder0.IN1 iDIG[3] => Decoder0.IN0 |DE1_NIOS|system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u1 oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE iDIG[0] => Decoder0.IN3 iDIG[1] => Decoder0.IN2 iDIG[2] => Decoder0.IN1 iDIG[3] => Decoder0.IN0 |DE1_NIOS|system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u2 oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE iDIG[0] => Decoder0.IN3 iDIG[1] => Decoder0.IN2 iDIG[2] => Decoder0.IN1 iDIG[3] => Decoder0.IN0 |DE1_NIOS|system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u3 oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE iDIG[0] => Decoder0.IN3 iDIG[1] => Decoder0.IN2 iDIG[2] => Decoder0.IN1 iDIG[3] => Decoder0.IN0 |DE1_NIOS|system_0:u0|Switch_s1_arbitrator:the_Switch_s1 Switch_s1_readdata[0] => Switch_s1_readdata_from_sa[0].DATAIN Switch_s1_readdata[1] => Switch_s1_readdata_from_sa[1].DATAIN Switch_s1_readdata[2] => Switch_s1_readdata_from_sa[2].DATAIN Switch_s1_readdata[3] => Switch_s1_readdata_from_sa[3].DATAIN Switch_s1_readdata[4] => Switch_s1_readdata_from_sa[4].DATAIN Switch_s1_readdata[5] => Switch_s1_readdata_from_sa[5].DATAIN Switch_s1_readdata[6] => Switch_s1_readdata_from_sa[6].DATAIN Switch_s1_readdata[7] => Switch_s1_readdata_from_sa[7].DATAIN Switch_s1_readdata[8] => Switch_s1_readdata_from_sa[8].DATAIN Switch_s1_readdata[9] => Switch_s1_readdata_from_sa[9].DATAIN clk => d1_reasons_to_wait.CLK clk => d1_Switch_s1_end_xfer~reg0.CLK cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[2] => Switch_s1_address[0].DATAIN cpu_0_data_master_address_to_slave[3] => Switch_s1_address[1].DATAIN cpu_0_data_master_address_to_slave[4] => Equal0.IN0 cpu_0_data_master_address_to_slave[5] => Equal0.IN19 cpu_0_data_master_address_to_slave[6] => Equal0.IN1 cpu_0_data_master_address_to_slave[7] => Equal0.IN18 cpu_0_data_master_address_to_slave[8] => Equal0.IN17 cpu_0_data_master_address_to_slave[9] => Equal0.IN16 cpu_0_data_master_address_to_slave[10] => Equal0.IN15 cpu_0_data_master_address_to_slave[11] => Equal0.IN14 cpu_0_data_master_address_to_slave[12] => Equal0.IN2 cpu_0_data_master_address_to_slave[13] => Equal0.IN13 cpu_0_data_master_address_to_slave[14] => Equal0.IN12 cpu_0_data_master_address_to_slave[15] => Equal0.IN11 cpu_0_data_master_address_to_slave[16] => Equal0.IN10 cpu_0_data_master_address_to_slave[17] => Equal0.IN9 cpu_0_data_master_address_to_slave[18] => Equal0.IN8 cpu_0_data_master_address_to_slave[19] => Equal0.IN3 cpu_0_data_master_address_to_slave[20] => Equal0.IN7 cpu_0_data_master_address_to_slave[21] => Equal0.IN6 cpu_0_data_master_address_to_slave[22] => Equal0.IN4 cpu_0_data_master_address_to_slave[23] => Equal0.IN5 cpu_0_data_master_read => Switch_s1_in_a_read_cycle.IN0 cpu_0_data_master_read => cpu_0_data_master_requests_Switch_s1~2.IN0 cpu_0_data_master_read => cpu_0_data_master_requests_Switch_s1~0.IN0 cpu_0_data_master_write => cpu_0_data_master_requests_Switch_s1~0.IN1 reset_n => Switch_s1_reset_n.DATAIN reset_n => d1_reasons_to_wait.ACLR reset_n => d1_Switch_s1_end_xfer~reg0.PRESET Switch_s1_address[0] <= cpu_0_data_master_address_to_slave[2].DB_MAX_OUTPUT_PORT_TYPE Switch_s1_address[1] <= cpu_0_data_master_address_to_slave[3].DB_MAX_OUTPUT_PORT_TYPE Switch_s1_readdata_from_sa[0] <= Switch_s1_readdata[0].DB_MAX_OUTPUT_PORT_TYPE Switch_s1_readdata_from_sa[1] <= Switch_s1_readdata[1].DB_MAX_OUTPUT_PORT_TYPE Switch_s1_readdata_from_sa[2] <= Switch_s1_readdata[2].DB_MAX_OUTPUT_PORT_TYPE Switch_s1_readdata_from_sa[3] <= Switch_s1_readdata[3].DB_MAX_OUTPUT_PORT_TYPE Switch_s1_readdata_from_sa[4] <= Switch_s1_readdata[4].DB_MAX_OUTPUT_PORT_TYPE Switch_s1_readdata_from_sa[5] <= Switch_s1_readdata[5].DB_MAX_OUTPUT_PORT_TYPE Switch_s1_readdata_from_sa[6] <= Switch_s1_readdata[6].DB_MAX_OUTPUT_PORT_TYPE Switch_s1_readdata_from_sa[7] <= Switch_s1_readdata[7].DB_MAX_OUTPUT_PORT_TYPE Switch_s1_readdata_from_sa[8] <= Switch_s1_readdata[8].DB_MAX_OUTPUT_PORT_TYPE Switch_s1_readdata_from_sa[9] <= Switch_s1_readdata[9].DB_MAX_OUTPUT_PORT_TYPE Switch_s1_reset_n <= reset_n.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_granted_Switch_s1 <= cpu_0_data_master_requests_Switch_s1~2.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_qualified_request_Switch_s1 <= cpu_0_data_master_requests_Switch_s1~2.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_read_data_valid_Switch_s1 <= cpu_0_data_master_requests_Switch_s1 <= cpu_0_data_master_requests_Switch_s1~2.DB_MAX_OUTPUT_PORT_TYPE d1_Switch_s1_end_xfer <= d1_Switch_s1_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|Switch:the_Switch address[0] => Equal0.IN30 address[1] => Equal0.IN31 clk => readdata[9]~reg0.CLK clk => readdata[8]~reg0.CLK clk => readdata[7]~reg0.CLK clk => readdata[6]~reg0.CLK clk => readdata[5]~reg0.CLK clk => readdata[4]~reg0.CLK clk => readdata[3]~reg0.CLK clk => readdata[2]~reg0.CLK clk => readdata[1]~reg0.CLK clk => readdata[0]~reg0.CLK in_port[0] => read_mux_out[0].IN1 in_port[1] => read_mux_out[1].IN1 in_port[2] => read_mux_out[2].IN1 in_port[3] => read_mux_out[3].IN1 in_port[4] => read_mux_out[4].IN1 in_port[5] => read_mux_out[5].IN1 in_port[6] => read_mux_out[6].IN1 in_port[7] => read_mux_out[7].IN1 in_port[8] => read_mux_out[8].IN1 in_port[9] => read_mux_out[9].IN1 reset_n => readdata[9]~reg0.ACLR reset_n => readdata[8]~reg0.ACLR reset_n => readdata[7]~reg0.ACLR reset_n => readdata[6]~reg0.ACLR reset_n => readdata[5]~reg0.ACLR reset_n => readdata[4]~reg0.ACLR reset_n => readdata[3]~reg0.ACLR reset_n => readdata[2]~reg0.ACLR reset_n => readdata[1]~reg0.ACLR reset_n => readdata[0]~reg0.ACLR readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module clk => d1_reasons_to_wait.CLK clk => cpu_0_jtag_debug_module_arb_share_counter[2].CLK clk => cpu_0_jtag_debug_module_arb_share_counter[1].CLK clk => cpu_0_jtag_debug_module_arb_share_counter[0].CLK clk => cpu_0_jtag_debug_module_slavearbiterlockenable.CLK clk => last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module.CLK clk => last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module.CLK clk => cpu_0_jtag_debug_module_saved_chosen_master_vector[1].CLK clk => cpu_0_jtag_debug_module_saved_chosen_master_vector[0].CLK clk => cpu_0_jtag_debug_module_arb_addend[1].CLK clk => cpu_0_jtag_debug_module_arb_addend[0].CLK clk => d1_cpu_0_jtag_debug_module_end_xfer~reg0.CLK cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[2] => cpu_0_jtag_debug_module_address~8.DATAB cpu_0_data_master_address_to_slave[3] => cpu_0_jtag_debug_module_address~7.DATAB cpu_0_data_master_address_to_slave[4] => cpu_0_jtag_debug_module_address~6.DATAB cpu_0_data_master_address_to_slave[5] => cpu_0_jtag_debug_module_address~5.DATAB cpu_0_data_master_address_to_slave[6] => cpu_0_jtag_debug_module_address~4.DATAB cpu_0_data_master_address_to_slave[7] => cpu_0_jtag_debug_module_address~3.DATAB cpu_0_data_master_address_to_slave[8] => cpu_0_jtag_debug_module_address~2.DATAB cpu_0_data_master_address_to_slave[9] => cpu_0_jtag_debug_module_address~1.DATAB cpu_0_data_master_address_to_slave[10] => cpu_0_jtag_debug_module_address~0.DATAB cpu_0_data_master_address_to_slave[11] => Equal0.IN10 cpu_0_data_master_address_to_slave[12] => Equal0.IN9 cpu_0_data_master_address_to_slave[13] => Equal0.IN8 cpu_0_data_master_address_to_slave[14] => Equal0.IN7 cpu_0_data_master_address_to_slave[15] => Equal0.IN6 cpu_0_data_master_address_to_slave[16] => Equal0.IN5 cpu_0_data_master_address_to_slave[17] => Equal0.IN4 cpu_0_data_master_address_to_slave[18] => Equal0.IN3 cpu_0_data_master_address_to_slave[19] => Equal0.IN34 cpu_0_data_master_address_to_slave[20] => Equal0.IN2 cpu_0_data_master_address_to_slave[21] => Equal0.IN1 cpu_0_data_master_address_to_slave[22] => Equal0.IN33 cpu_0_data_master_address_to_slave[23] => Equal0.IN0 cpu_0_data_master_byteenable[0] => cpu_0_jtag_debug_module_byteenable~3.DATAB cpu_0_data_master_byteenable[1] => cpu_0_jtag_debug_module_byteenable~2.DATAB cpu_0_data_master_byteenable[2] => cpu_0_jtag_debug_module_byteenable~1.DATAB cpu_0_data_master_byteenable[3] => cpu_0_jtag_debug_module_byteenable~0.DATAB cpu_0_data_master_debugaccess => cpu_0_jtag_debug_module_debugaccess.DATAIN cpu_0_data_master_read => cpu_0_jtag_debug_module_in_a_read_cycle~0.IN0 cpu_0_data_master_read => cpu_0_data_master_requests_cpu_0_jtag_debug_module~0.IN0 cpu_0_data_master_write => cpu_0_jtag_debug_module_in_a_write_cycle.IN0 cpu_0_data_master_write => cpu_0_jtag_debug_module_write~0.IN0 cpu_0_data_master_write => cpu_0_data_master_requests_cpu_0_jtag_debug_module~0.IN1 cpu_0_data_master_writedata[0] => cpu_0_jtag_debug_module_writedata[0].DATAIN cpu_0_data_master_writedata[1] => cpu_0_jtag_debug_module_writedata[1].DATAIN cpu_0_data_master_writedata[2] => cpu_0_jtag_debug_module_writedata[2].DATAIN cpu_0_data_master_writedata[3] => cpu_0_jtag_debug_module_writedata[3].DATAIN cpu_0_data_master_writedata[4] => cpu_0_jtag_debug_module_writedata[4].DATAIN cpu_0_data_master_writedata[5] => cpu_0_jtag_debug_module_writedata[5].DATAIN cpu_0_data_master_writedata[6] => cpu_0_jtag_debug_module_writedata[6].DATAIN cpu_0_data_master_writedata[7] => cpu_0_jtag_debug_module_writedata[7].DATAIN cpu_0_data_master_writedata[8] => cpu_0_jtag_debug_module_writedata[8].DATAIN cpu_0_data_master_writedata[9] => cpu_0_jtag_debug_module_writedata[9].DATAIN cpu_0_data_master_writedata[10] => cpu_0_jtag_debug_module_writedata[10].DATAIN cpu_0_data_master_writedata[11] => cpu_0_jtag_debug_module_writedata[11].DATAIN cpu_0_data_master_writedata[12] => cpu_0_jtag_debug_module_writedata[12].DATAIN cpu_0_data_master_writedata[13] => cpu_0_jtag_debug_module_writedata[13].DATAIN cpu_0_data_master_writedata[14] => cpu_0_jtag_debug_module_writedata[14].DATAIN cpu_0_data_master_writedata[15] => cpu_0_jtag_debug_module_writedata[15].DATAIN cpu_0_data_master_writedata[16] => cpu_0_jtag_debug_module_writedata[16].DATAIN cpu_0_data_master_writedata[17] => cpu_0_jtag_debug_module_writedata[17].DATAIN cpu_0_data_master_writedata[18] => cpu_0_jtag_debug_module_writedata[18].DATAIN cpu_0_data_master_writedata[19] => cpu_0_jtag_debug_module_writedata[19].DATAIN cpu_0_data_master_writedata[20] => cpu_0_jtag_debug_module_writedata[20].DATAIN cpu_0_data_master_writedata[21] => cpu_0_jtag_debug_module_writedata[21].DATAIN cpu_0_data_master_writedata[22] => cpu_0_jtag_debug_module_writedata[22].DATAIN cpu_0_data_master_writedata[23] => cpu_0_jtag_debug_module_writedata[23].DATAIN cpu_0_data_master_writedata[24] => cpu_0_jtag_debug_module_writedata[24].DATAIN cpu_0_data_master_writedata[25] => cpu_0_jtag_debug_module_writedata[25].DATAIN cpu_0_data_master_writedata[26] => cpu_0_jtag_debug_module_writedata[26].DATAIN cpu_0_data_master_writedata[27] => cpu_0_jtag_debug_module_writedata[27].DATAIN cpu_0_data_master_writedata[28] => cpu_0_jtag_debug_module_writedata[28].DATAIN cpu_0_data_master_writedata[29] => cpu_0_jtag_debug_module_writedata[29].DATAIN cpu_0_data_master_writedata[30] => cpu_0_jtag_debug_module_writedata[30].DATAIN cpu_0_data_master_writedata[31] => cpu_0_jtag_debug_module_writedata[31].DATAIN cpu_0_instruction_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_instruction_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_instruction_master_address_to_slave[2] => cpu_0_jtag_debug_module_address~8.DATAA cpu_0_instruction_master_address_to_slave[3] => cpu_0_jtag_debug_module_address~7.DATAA cpu_0_instruction_master_address_to_slave[4] => cpu_0_jtag_debug_module_address~6.DATAA cpu_0_instruction_master_address_to_slave[5] => cpu_0_jtag_debug_module_address~5.DATAA cpu_0_instruction_master_address_to_slave[6] => cpu_0_jtag_debug_module_address~4.DATAA cpu_0_instruction_master_address_to_slave[7] => cpu_0_jtag_debug_module_address~3.DATAA cpu_0_instruction_master_address_to_slave[8] => cpu_0_jtag_debug_module_address~2.DATAA cpu_0_instruction_master_address_to_slave[9] => cpu_0_jtag_debug_module_address~1.DATAA cpu_0_instruction_master_address_to_slave[10] => cpu_0_jtag_debug_module_address~0.DATAA cpu_0_instruction_master_address_to_slave[11] => Equal1.IN10 cpu_0_instruction_master_address_to_slave[12] => Equal1.IN9 cpu_0_instruction_master_address_to_slave[13] => Equal1.IN8 cpu_0_instruction_master_address_to_slave[14] => Equal1.IN7 cpu_0_instruction_master_address_to_slave[15] => Equal1.IN6 cpu_0_instruction_master_address_to_slave[16] => Equal1.IN5 cpu_0_instruction_master_address_to_slave[17] => Equal1.IN4 cpu_0_instruction_master_address_to_slave[18] => Equal1.IN3 cpu_0_instruction_master_address_to_slave[19] => Equal1.IN34 cpu_0_instruction_master_address_to_slave[20] => Equal1.IN2 cpu_0_instruction_master_address_to_slave[21] => Equal1.IN1 cpu_0_instruction_master_address_to_slave[22] => Equal1.IN33 cpu_0_instruction_master_address_to_slave[23] => Equal1.IN0 cpu_0_instruction_master_latency_counter[0] => Equal2.IN31 cpu_0_instruction_master_latency_counter[1] => Equal2.IN30 cpu_0_instruction_master_read => cpu_0_jtag_debug_module_in_a_read_cycle~1.IN0 cpu_0_instruction_master_read => cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module~1.IN0 cpu_0_instruction_master_read => cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~1.IN0 cpu_0_instruction_master_read => cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~0.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register => cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module~0.IN1 cpu_0_jtag_debug_module_readdata[0] => cpu_0_jtag_debug_module_readdata_from_sa[0].DATAIN cpu_0_jtag_debug_module_readdata[1] => cpu_0_jtag_debug_module_readdata_from_sa[1].DATAIN cpu_0_jtag_debug_module_readdata[2] => cpu_0_jtag_debug_module_readdata_from_sa[2].DATAIN cpu_0_jtag_debug_module_readdata[3] => cpu_0_jtag_debug_module_readdata_from_sa[3].DATAIN cpu_0_jtag_debug_module_readdata[4] => cpu_0_jtag_debug_module_readdata_from_sa[4].DATAIN cpu_0_jtag_debug_module_readdata[5] => cpu_0_jtag_debug_module_readdata_from_sa[5].DATAIN cpu_0_jtag_debug_module_readdata[6] => cpu_0_jtag_debug_module_readdata_from_sa[6].DATAIN cpu_0_jtag_debug_module_readdata[7] => cpu_0_jtag_debug_module_readdata_from_sa[7].DATAIN cpu_0_jtag_debug_module_readdata[8] => cpu_0_jtag_debug_module_readdata_from_sa[8].DATAIN cpu_0_jtag_debug_module_readdata[9] => cpu_0_jtag_debug_module_readdata_from_sa[9].DATAIN cpu_0_jtag_debug_module_readdata[10] => cpu_0_jtag_debug_module_readdata_from_sa[10].DATAIN cpu_0_jtag_debug_module_readdata[11] => cpu_0_jtag_debug_module_readdata_from_sa[11].DATAIN cpu_0_jtag_debug_module_readdata[12] => cpu_0_jtag_debug_module_readdata_from_sa[12].DATAIN cpu_0_jtag_debug_module_readdata[13] => cpu_0_jtag_debug_module_readdata_from_sa[13].DATAIN cpu_0_jtag_debug_module_readdata[14] => cpu_0_jtag_debug_module_readdata_from_sa[14].DATAIN cpu_0_jtag_debug_module_readdata[15] => cpu_0_jtag_debug_module_readdata_from_sa[15].DATAIN cpu_0_jtag_debug_module_readdata[16] => cpu_0_jtag_debug_module_readdata_from_sa[16].DATAIN cpu_0_jtag_debug_module_readdata[17] => cpu_0_jtag_debug_module_readdata_from_sa[17].DATAIN cpu_0_jtag_debug_module_readdata[18] => cpu_0_jtag_debug_module_readdata_from_sa[18].DATAIN cpu_0_jtag_debug_module_readdata[19] => cpu_0_jtag_debug_module_readdata_from_sa[19].DATAIN cpu_0_jtag_debug_module_readdata[20] => cpu_0_jtag_debug_module_readdata_from_sa[20].DATAIN cpu_0_jtag_debug_module_readdata[21] => cpu_0_jtag_debug_module_readdata_from_sa[21].DATAIN cpu_0_jtag_debug_module_readdata[22] => cpu_0_jtag_debug_module_readdata_from_sa[22].DATAIN cpu_0_jtag_debug_module_readdata[23] => cpu_0_jtag_debug_module_readdata_from_sa[23].DATAIN cpu_0_jtag_debug_module_readdata[24] => cpu_0_jtag_debug_module_readdata_from_sa[24].DATAIN cpu_0_jtag_debug_module_readdata[25] => cpu_0_jtag_debug_module_readdata_from_sa[25].DATAIN cpu_0_jtag_debug_module_readdata[26] => cpu_0_jtag_debug_module_readdata_from_sa[26].DATAIN cpu_0_jtag_debug_module_readdata[27] => cpu_0_jtag_debug_module_readdata_from_sa[27].DATAIN cpu_0_jtag_debug_module_readdata[28] => cpu_0_jtag_debug_module_readdata_from_sa[28].DATAIN cpu_0_jtag_debug_module_readdata[29] => cpu_0_jtag_debug_module_readdata_from_sa[29].DATAIN cpu_0_jtag_debug_module_readdata[30] => cpu_0_jtag_debug_module_readdata_from_sa[30].DATAIN cpu_0_jtag_debug_module_readdata[31] => cpu_0_jtag_debug_module_readdata_from_sa[31].DATAIN cpu_0_jtag_debug_module_resetrequest => cpu_0_jtag_debug_module_resetrequest_from_sa.DATAIN reset_n => cpu_0_jtag_debug_module_reset_n.DATAIN reset_n => cpu_0_jtag_debug_module_arb_addend[0].PRESET reset_n => cpu_0_jtag_debug_module_arb_addend[1].ACLR reset_n => cpu_0_jtag_debug_module_saved_chosen_master_vector[0].ACLR reset_n => cpu_0_jtag_debug_module_saved_chosen_master_vector[1].ACLR reset_n => last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module.ACLR reset_n => last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module.ACLR reset_n => cpu_0_jtag_debug_module_slavearbiterlockenable.ACLR reset_n => cpu_0_jtag_debug_module_arb_share_counter[0].ACLR reset_n => cpu_0_jtag_debug_module_arb_share_counter[1].ACLR reset_n => cpu_0_jtag_debug_module_arb_share_counter[2].ACLR reset_n => d1_reasons_to_wait.ACLR reset_n => d1_cpu_0_jtag_debug_module_end_xfer~reg0.PRESET reset_n => cpu_0_jtag_debug_module_reset.DATAIN cpu_0_data_master_granted_cpu_0_jtag_debug_module <= cpu_0_jtag_debug_module_grant_vector[1].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module <= cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module <= cpu_0_data_master_requests_cpu_0_jtag_debug_module <= cpu_0_data_master_requests_cpu_0_jtag_debug_module~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_granted_cpu_0_jtag_debug_module <= cpu_0_jtag_debug_module_grant_vector~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module <= cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module~3.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module <= cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_requests_cpu_0_jtag_debug_module <= cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_address[0] <= cpu_0_jtag_debug_module_address~8.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_address[1] <= cpu_0_jtag_debug_module_address~7.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_address[2] <= cpu_0_jtag_debug_module_address~6.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_address[3] <= cpu_0_jtag_debug_module_address~5.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_address[4] <= cpu_0_jtag_debug_module_address~4.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_address[5] <= cpu_0_jtag_debug_module_address~3.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_address[6] <= cpu_0_jtag_debug_module_address~2.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_address[7] <= cpu_0_jtag_debug_module_address~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_address[8] <= cpu_0_jtag_debug_module_address~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_begintransfer <= cpu_0_jtag_debug_module_begins_xfer~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_byteenable[0] <= cpu_0_jtag_debug_module_byteenable~3.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_byteenable[1] <= cpu_0_jtag_debug_module_byteenable~2.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_byteenable[2] <= cpu_0_jtag_debug_module_byteenable~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_byteenable[3] <= cpu_0_jtag_debug_module_byteenable~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_chipselect <= cpu_0_jtag_debug_module_chipselect~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_debugaccess <= cpu_0_data_master_debugaccess.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[0] <= cpu_0_jtag_debug_module_readdata[0].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[1] <= cpu_0_jtag_debug_module_readdata[1].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[2] <= cpu_0_jtag_debug_module_readdata[2].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[3] <= cpu_0_jtag_debug_module_readdata[3].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[4] <= cpu_0_jtag_debug_module_readdata[4].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[5] <= cpu_0_jtag_debug_module_readdata[5].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[6] <= cpu_0_jtag_debug_module_readdata[6].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[7] <= cpu_0_jtag_debug_module_readdata[7].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[8] <= cpu_0_jtag_debug_module_readdata[8].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[9] <= cpu_0_jtag_debug_module_readdata[9].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[10] <= cpu_0_jtag_debug_module_readdata[10].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[11] <= cpu_0_jtag_debug_module_readdata[11].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[12] <= cpu_0_jtag_debug_module_readdata[12].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[13] <= cpu_0_jtag_debug_module_readdata[13].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[14] <= cpu_0_jtag_debug_module_readdata[14].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[15] <= cpu_0_jtag_debug_module_readdata[15].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[16] <= cpu_0_jtag_debug_module_readdata[16].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[17] <= cpu_0_jtag_debug_module_readdata[17].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[18] <= cpu_0_jtag_debug_module_readdata[18].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[19] <= cpu_0_jtag_debug_module_readdata[19].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[20] <= cpu_0_jtag_debug_module_readdata[20].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[21] <= cpu_0_jtag_debug_module_readdata[21].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[22] <= cpu_0_jtag_debug_module_readdata[22].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[23] <= cpu_0_jtag_debug_module_readdata[23].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[24] <= cpu_0_jtag_debug_module_readdata[24].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[25] <= cpu_0_jtag_debug_module_readdata[25].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[26] <= cpu_0_jtag_debug_module_readdata[26].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[27] <= cpu_0_jtag_debug_module_readdata[27].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[28] <= cpu_0_jtag_debug_module_readdata[28].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[29] <= cpu_0_jtag_debug_module_readdata[29].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[30] <= cpu_0_jtag_debug_module_readdata[30].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_readdata_from_sa[31] <= cpu_0_jtag_debug_module_readdata[31].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_reset <= reset_n.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_reset_n <= reset_n.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_resetrequest_from_sa <= cpu_0_jtag_debug_module_resetrequest.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_write <= cpu_0_jtag_debug_module_write~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[0] <= cpu_0_data_master_writedata[0].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[1] <= cpu_0_data_master_writedata[1].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[2] <= cpu_0_data_master_writedata[2].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[3] <= cpu_0_data_master_writedata[3].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[4] <= cpu_0_data_master_writedata[4].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[5] <= cpu_0_data_master_writedata[5].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[6] <= cpu_0_data_master_writedata[6].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[7] <= cpu_0_data_master_writedata[7].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[8] <= cpu_0_data_master_writedata[8].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[9] <= cpu_0_data_master_writedata[9].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[10] <= cpu_0_data_master_writedata[10].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[11] <= cpu_0_data_master_writedata[11].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[12] <= cpu_0_data_master_writedata[12].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[13] <= cpu_0_data_master_writedata[13].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[14] <= cpu_0_data_master_writedata[14].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[15] <= cpu_0_data_master_writedata[15].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[16] <= cpu_0_data_master_writedata[16].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[17] <= cpu_0_data_master_writedata[17].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[18] <= cpu_0_data_master_writedata[18].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[19] <= cpu_0_data_master_writedata[19].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[20] <= cpu_0_data_master_writedata[20].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[21] <= cpu_0_data_master_writedata[21].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[22] <= cpu_0_data_master_writedata[22].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[23] <= cpu_0_data_master_writedata[23].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[24] <= cpu_0_data_master_writedata[24].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[25] <= cpu_0_data_master_writedata[25].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[26] <= cpu_0_data_master_writedata[26].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[27] <= cpu_0_data_master_writedata[27].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[28] <= cpu_0_data_master_writedata[28].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[29] <= cpu_0_data_master_writedata[29].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[30] <= cpu_0_data_master_writedata[30].DB_MAX_OUTPUT_PORT_TYPE cpu_0_jtag_debug_module_writedata[31] <= cpu_0_data_master_writedata[31].DB_MAX_OUTPUT_PORT_TYPE d1_cpu_0_jtag_debug_module_end_xfer <= d1_cpu_0_jtag_debug_module_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master KEY_s1_irq_from_sa => cpu_0_data_master_irq[3].DATAIN KEY_s1_readdata_from_sa[0] => cpu_0_data_master_readdata~0.IN1 KEY_s1_readdata_from_sa[1] => cpu_0_data_master_readdata~1.IN1 KEY_s1_readdata_from_sa[2] => cpu_0_data_master_readdata~2.IN1 KEY_s1_readdata_from_sa[3] => cpu_0_data_master_readdata~3.IN1 Switch_s1_readdata_from_sa[0] => cpu_0_data_master_readdata~4.IN1 Switch_s1_readdata_from_sa[1] => cpu_0_data_master_readdata~5.IN1 Switch_s1_readdata_from_sa[2] => cpu_0_data_master_readdata~6.IN1 Switch_s1_readdata_from_sa[3] => cpu_0_data_master_readdata~7.IN1 Switch_s1_readdata_from_sa[4] => cpu_0_data_master_readdata~8.IN1 Switch_s1_readdata_from_sa[5] => cpu_0_data_master_readdata~9.IN1 Switch_s1_readdata_from_sa[6] => cpu_0_data_master_readdata~10.IN1 Switch_s1_readdata_from_sa[7] => cpu_0_data_master_readdata~11.IN1 Switch_s1_readdata_from_sa[8] => cpu_0_data_master_readdata~12.IN1 Switch_s1_readdata_from_sa[9] => cpu_0_data_master_readdata~13.IN1 cfi_flash_0_s1_wait_counter_eq_0 => pre_dbs_count_enable~24.IN1 cfi_flash_0_s1_wait_counter_eq_1 => r_2~28.IN1 clk => cpu_0_data_master_waitrequest~reg0.CLK clk => registered_cpu_0_data_master_readdata[31].CLK clk => registered_cpu_0_data_master_readdata[30].CLK clk => registered_cpu_0_data_master_readdata[29].CLK clk => registered_cpu_0_data_master_readdata[28].CLK clk => registered_cpu_0_data_master_readdata[27].CLK clk => registered_cpu_0_data_master_readdata[26].CLK clk => registered_cpu_0_data_master_readdata[25].CLK clk => registered_cpu_0_data_master_readdata[24].CLK clk => registered_cpu_0_data_master_readdata[23].CLK clk => registered_cpu_0_data_master_readdata[22].CLK clk => registered_cpu_0_data_master_readdata[21].CLK clk => registered_cpu_0_data_master_readdata[20].CLK clk => registered_cpu_0_data_master_readdata[19].CLK clk => registered_cpu_0_data_master_readdata[18].CLK clk => registered_cpu_0_data_master_readdata[17].CLK clk => registered_cpu_0_data_master_readdata[16].CLK clk => registered_cpu_0_data_master_readdata[15].CLK clk => registered_cpu_0_data_master_readdata[14].CLK clk => registered_cpu_0_data_master_readdata[13].CLK clk => registered_cpu_0_data_master_readdata[12].CLK clk => registered_cpu_0_data_master_readdata[11].CLK clk => registered_cpu_0_data_master_readdata[10].CLK clk => registered_cpu_0_data_master_readdata[9].CLK clk => registered_cpu_0_data_master_readdata[8].CLK clk => registered_cpu_0_data_master_readdata[7].CLK clk => registered_cpu_0_data_master_readdata[6].CLK clk => registered_cpu_0_data_master_readdata[5].CLK clk => registered_cpu_0_data_master_readdata[4].CLK clk => registered_cpu_0_data_master_readdata[3].CLK clk => registered_cpu_0_data_master_readdata[2].CLK clk => registered_cpu_0_data_master_readdata[1].CLK clk => registered_cpu_0_data_master_readdata[0].CLK clk => cpu_0_data_master_no_byte_enables_and_last_term~reg0.CLK clk => dbs_16_reg_segment_0[15].CLK clk => dbs_16_reg_segment_0[14].CLK clk => dbs_16_reg_segment_0[13].CLK clk => dbs_16_reg_segment_0[12].CLK clk => dbs_16_reg_segment_0[11].CLK clk => dbs_16_reg_segment_0[10].CLK clk => dbs_16_reg_segment_0[9].CLK clk => dbs_16_reg_segment_0[8].CLK clk => dbs_16_reg_segment_0[7].CLK clk => dbs_16_reg_segment_0[6].CLK clk => dbs_16_reg_segment_0[5].CLK clk => dbs_16_reg_segment_0[4].CLK clk => dbs_16_reg_segment_0[3].CLK clk => dbs_16_reg_segment_0[2].CLK clk => dbs_16_reg_segment_0[1].CLK clk => dbs_16_reg_segment_0[0].CLK clk => cpu_0_data_master_dbs_address[1]~reg0.CLK clk => cpu_0_data_master_dbs_address[0]~reg0.CLK clk => dbs_8_reg_segment_0[7].CLK clk => dbs_8_reg_segment_0[6].CLK clk => dbs_8_reg_segment_0[5].CLK clk => dbs_8_reg_segment_0[4].CLK clk => dbs_8_reg_segment_0[3].CLK clk => dbs_8_reg_segment_0[2].CLK clk => dbs_8_reg_segment_0[1].CLK clk => dbs_8_reg_segment_0[0].CLK clk => dbs_8_reg_segment_1[7].CLK clk => dbs_8_reg_segment_1[6].CLK clk => dbs_8_reg_segment_1[5].CLK clk => dbs_8_reg_segment_1[4].CLK clk => dbs_8_reg_segment_1[3].CLK clk => dbs_8_reg_segment_1[2].CLK clk => dbs_8_reg_segment_1[1].CLK clk => dbs_8_reg_segment_1[0].CLK clk => dbs_8_reg_segment_2[7].CLK clk => dbs_8_reg_segment_2[6].CLK clk => dbs_8_reg_segment_2[5].CLK clk => dbs_8_reg_segment_2[4].CLK clk => dbs_8_reg_segment_2[3].CLK clk => dbs_8_reg_segment_2[2].CLK clk => dbs_8_reg_segment_2[1].CLK clk => dbs_8_reg_segment_2[0].CLK cpu_0_data_master_address[0] => cpu_0_data_master_address_to_slave[0].DATAIN cpu_0_data_master_address[1] => cpu_0_data_master_address_to_slave[1].DATAIN cpu_0_data_master_address[2] => cpu_0_data_master_address_to_slave[2].DATAIN cpu_0_data_master_address[3] => cpu_0_data_master_address_to_slave[3].DATAIN cpu_0_data_master_address[4] => cpu_0_data_master_address_to_slave[4].DATAIN cpu_0_data_master_address[5] => cpu_0_data_master_address_to_slave[5].DATAIN cpu_0_data_master_address[6] => cpu_0_data_master_address_to_slave[6].DATAIN cpu_0_data_master_address[7] => cpu_0_data_master_address_to_slave[7].DATAIN cpu_0_data_master_address[8] => cpu_0_data_master_address_to_slave[8].DATAIN cpu_0_data_master_address[9] => cpu_0_data_master_address_to_slave[9].DATAIN cpu_0_data_master_address[10] => cpu_0_data_master_address_to_slave[10].DATAIN cpu_0_data_master_address[11] => cpu_0_data_master_address_to_slave[11].DATAIN cpu_0_data_master_address[12] => cpu_0_data_master_address_to_slave[12].DATAIN cpu_0_data_master_address[13] => cpu_0_data_master_address_to_slave[13].DATAIN cpu_0_data_master_address[14] => cpu_0_data_master_address_to_slave[14].DATAIN cpu_0_data_master_address[15] => cpu_0_data_master_address_to_slave[15].DATAIN cpu_0_data_master_address[16] => cpu_0_data_master_address_to_slave[16].DATAIN cpu_0_data_master_address[17] => cpu_0_data_master_address_to_slave[17].DATAIN cpu_0_data_master_address[18] => cpu_0_data_master_address_to_slave[18].DATAIN cpu_0_data_master_address[19] => cpu_0_data_master_address_to_slave[19].DATAIN cpu_0_data_master_address[20] => cpu_0_data_master_address_to_slave[20].DATAIN cpu_0_data_master_address[21] => cpu_0_data_master_address_to_slave[21].DATAIN cpu_0_data_master_address[22] => cpu_0_data_master_address_to_slave[22].DATAIN cpu_0_data_master_address[23] => cpu_0_data_master_address_to_slave[23].DATAIN cpu_0_data_master_byteenable_cfi_flash_0_s1 => r_2~13.IN1 cpu_0_data_master_byteenable_cfi_flash_0_s1 => last_dbs_term_and_run~4.IN0 cpu_0_data_master_byteenable_cfi_flash_0_s1 => pre_dbs_count_enable~20.IN0 cpu_0_data_master_byteenable_sdram_0_s1[0] => WideNor0.IN1 cpu_0_data_master_byteenable_sdram_0_s1[1] => WideNor0.IN0 cpu_0_data_master_byteenable_sram_0_avalonS[0] => WideNor1.IN1 cpu_0_data_master_byteenable_sram_0_avalonS[1] => WideNor1.IN0 cpu_0_data_master_debugaccess => ~NO_FANOUT~ cpu_0_data_master_granted_KEY_s1 => ~NO_FANOUT~ cpu_0_data_master_granted_LEDG_s1 => ~NO_FANOUT~ cpu_0_data_master_granted_LEDR_s1 => ~NO_FANOUT~ cpu_0_data_master_granted_SEG7_avalonS => ~NO_FANOUT~ cpu_0_data_master_granted_Switch_s1 => ~NO_FANOUT~ cpu_0_data_master_granted_cfi_flash_0_s1 => pre_dbs_count_enable~23.IN1 cpu_0_data_master_granted_cfi_flash_0_s1 => r_2~19.IN1 cpu_0_data_master_granted_cpu_0_jtag_debug_module => r_1~1.IN1 cpu_0_data_master_granted_epcs_controller_epcs_control_port => r_1~9.IN1 cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave => ~NO_FANOUT~ cpu_0_data_master_granted_sdram_0_s1 => pre_dbs_count_enable~4.IN1 cpu_0_data_master_granted_sdram_0_s1 => r_1~28.IN1 cpu_0_data_master_granted_sram_0_avalonS => pre_dbs_count_enable~14.IN1 cpu_0_data_master_granted_sram_0_avalonS => pre_dbs_count_enable~11.IN1 cpu_0_data_master_granted_sram_0_avalonS => r_2~0.IN1 cpu_0_data_master_granted_uart_0_s1 => ~NO_FANOUT~ cpu_0_data_master_qualified_request_KEY_s1 => r_0~0.IN1 cpu_0_data_master_qualified_request_KEY_s1 => r_0~1.IN1 cpu_0_data_master_qualified_request_KEY_s1 => r_0~4.IN1 cpu_0_data_master_qualified_request_LEDG_s1 => r_0~7.IN1 cpu_0_data_master_qualified_request_LEDG_s1 => r_0~9.IN1 cpu_0_data_master_qualified_request_LEDG_s1 => r_0~12.IN1 cpu_0_data_master_qualified_request_LEDR_s1 => r_0~15.IN1 cpu_0_data_master_qualified_request_LEDR_s1 => r_0~17.IN1 cpu_0_data_master_qualified_request_LEDR_s1 => r_0~20.IN1 cpu_0_data_master_qualified_request_SEG7_avalonS => r_0~23.IN0 cpu_0_data_master_qualified_request_SEG7_avalonS => r_0~26.IN1 cpu_0_data_master_qualified_request_Switch_s1 => r_0~29.IN1 cpu_0_data_master_qualified_request_Switch_s1 => r_0~32.IN1 cpu_0_data_master_qualified_request_cfi_flash_0_s1 => r_2~12.IN1 cpu_0_data_master_qualified_request_cfi_flash_0_s1 => r_2~19.IN0 cpu_0_data_master_qualified_request_cfi_flash_0_s1 => r_2~21.IN1 cpu_0_data_master_qualified_request_cfi_flash_0_s1 => r_2~26.IN1 cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module => r_1~0.IN0 cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module => r_1~1.IN0 cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module => r_1~4.IN1 cpu_0_data_master_qualified_request_epcs_controller_epcs_control_port => r_1~7.IN0 cpu_0_data_master_qualified_request_epcs_controller_epcs_control_port => r_1~9.IN0 cpu_0_data_master_qualified_request_epcs_controller_epcs_control_port => r_1~12.IN1 cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave => r_1~15.IN0 cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave => r_1~18.IN1 cpu_0_data_master_qualified_request_sdram_0_s1 => r_1~22.IN1 cpu_0_data_master_qualified_request_sdram_0_s1 => r_1~28.IN0 cpu_0_data_master_qualified_request_sdram_0_s1 => r_1~30.IN1 cpu_0_data_master_qualified_request_sdram_0_s1 => r_1~35.IN1 cpu_0_data_master_qualified_request_sram_0_avalonS => r_1~42.IN1 cpu_0_data_master_qualified_request_sram_0_avalonS => r_2~0.IN0 cpu_0_data_master_qualified_request_sram_0_avalonS => r_2~1.IN1 cpu_0_data_master_qualified_request_sram_0_avalonS => r_2~5.IN1 cpu_0_data_master_qualified_request_uart_0_s1 => r_2~33.IN1 cpu_0_data_master_read => pre_dbs_count_enable~11.IN0 cpu_0_data_master_read => r_2~34.IN0 cpu_0_data_master_read => r_2~23.IN0 cpu_0_data_master_read => r_2~2.IN0 cpu_0_data_master_read => r_1~32.IN0 cpu_0_data_master_read => r_0~30.IN0 cpu_0_data_master_read => r_0~18.IN0 cpu_0_data_master_read => r_0~10.IN0 cpu_0_data_master_read => r_0~2.IN0 cpu_0_data_master_read => r_0~1.IN0 cpu_0_data_master_read => r_0~9.IN0 cpu_0_data_master_read => r_0~17.IN0 cpu_0_data_master_read => r_0~29.IN0 cpu_0_data_master_read => r_1~30.IN0 cpu_0_data_master_read => r_2~1.IN0 cpu_0_data_master_read => r_2~21.IN0 cpu_0_data_master_read_data_valid_KEY_s1 => ~NO_FANOUT~ cpu_0_data_master_read_data_valid_LEDG_s1 => ~NO_FANOUT~ cpu_0_data_master_read_data_valid_LEDR_s1 => ~NO_FANOUT~ cpu_0_data_master_read_data_valid_SEG7_avalonS => ~NO_FANOUT~ cpu_0_data_master_read_data_valid_Switch_s1 => ~NO_FANOUT~ cpu_0_data_master_read_data_valid_cfi_flash_0_s1 => pre_dbs_count_enable~22.IN1 cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module => ~NO_FANOUT~ cpu_0_data_master_read_data_valid_epcs_controller_epcs_control_port => ~NO_FANOUT~ cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave => ~NO_FANOUT~ cpu_0_data_master_read_data_valid_sdram_0_s1 => pre_dbs_count_enable~3.IN0 cpu_0_data_master_read_data_valid_sdram_0_s1 => r_1~31.IN1 cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register => ~NO_FANOUT~ cpu_0_data_master_read_data_valid_sram_0_avalonS => ~NO_FANOUT~ cpu_0_data_master_read_data_valid_uart_0_s1 => ~NO_FANOUT~ cpu_0_data_master_requests_KEY_s1 => r_0~0.IN0 cpu_0_data_master_requests_KEY_s1 => cpu_0_data_master_readdata~24.IN0 cpu_0_data_master_requests_KEY_s1 => cpu_0_data_master_readdata~23.IN0 cpu_0_data_master_requests_KEY_s1 => cpu_0_data_master_readdata~22.IN0 cpu_0_data_master_requests_KEY_s1 => cpu_0_data_master_readdata~21.IN0 cpu_0_data_master_requests_KEY_s1 => cpu_0_data_master_readdata~20.IN0 cpu_0_data_master_requests_KEY_s1 => cpu_0_data_master_readdata~19.IN0 cpu_0_data_master_requests_KEY_s1 => cpu_0_data_master_readdata~18.IN0 cpu_0_data_master_requests_KEY_s1 => cpu_0_data_master_readdata~3.IN0 cpu_0_data_master_requests_KEY_s1 => cpu_0_data_master_readdata~2.IN0 cpu_0_data_master_requests_KEY_s1 => cpu_0_data_master_readdata~1.IN0 cpu_0_data_master_requests_KEY_s1 => cpu_0_data_master_readdata~0.IN0 cpu_0_data_master_requests_LEDG_s1 => r_0~7.IN0 cpu_0_data_master_requests_LEDR_s1 => r_0~15.IN0 cpu_0_data_master_requests_SEG7_avalonS => r_0~23.IN1 cpu_0_data_master_requests_Switch_s1 => cpu_0_data_master_readdata~24.IN1 cpu_0_data_master_requests_Switch_s1 => cpu_0_data_master_readdata~13.IN0 cpu_0_data_master_requests_Switch_s1 => cpu_0_data_master_readdata~12.IN0 cpu_0_data_master_requests_Switch_s1 => cpu_0_data_master_readdata~11.IN0 cpu_0_data_master_requests_Switch_s1 => cpu_0_data_master_readdata~10.IN0 cpu_0_data_master_requests_Switch_s1 => cpu_0_data_master_readdata~9.IN0 cpu_0_data_master_requests_Switch_s1 => cpu_0_data_master_readdata~8.IN0 cpu_0_data_master_requests_Switch_s1 => cpu_0_data_master_readdata~7.IN0 cpu_0_data_master_requests_Switch_s1 => cpu_0_data_master_readdata~6.IN0 cpu_0_data_master_requests_Switch_s1 => cpu_0_data_master_readdata~5.IN0 cpu_0_data_master_requests_Switch_s1 => cpu_0_data_master_readdata~4.IN0 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_dbs_increment~0.DATAA cpu_0_data_master_requests_cfi_flash_0_s1 => pre_dbs_count_enable~18.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => r_2~17.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~376.IN0 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~375.IN0 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~374.IN0 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~373.IN0 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~372.IN0 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~371.IN0 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~370.IN0 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~369.IN0 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~368.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~367.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~366.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~365.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~364.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~363.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~362.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~361.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~360.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~359.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~358.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~357.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~356.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~355.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~354.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~353.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~352.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~351.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~350.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~349.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~348.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~347.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~346.IN1 cpu_0_data_master_requests_cfi_flash_0_s1 => cpu_0_data_master_readdata~345.IN1 cpu_0_data_master_requests_cpu_0_jtag_debug_module => r_1~0.IN1 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~56.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~55.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~54.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~53.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~52.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~51.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~50.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~49.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~48.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~47.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~46.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~45.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~44.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~43.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~42.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~41.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~40.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~39.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~38.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~37.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~36.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~35.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~34.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~33.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~32.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~31.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~30.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~29.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~28.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~27.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~26.IN0 cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~25.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => r_1~7.IN1 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~120.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~119.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~118.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~117.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~116.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~115.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~114.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~113.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~112.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~111.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~110.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~109.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~108.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~107.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~106.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~105.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~104.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~103.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~102.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~101.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~100.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~99.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~98.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~97.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~96.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~95.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~94.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~93.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~92.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~91.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~90.IN0 cpu_0_data_master_requests_epcs_controller_epcs_control_port => cpu_0_data_master_readdata~89.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~0.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~1.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~2.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~3.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~4.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~5.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~6.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~7.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~8.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~9.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~10.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~11.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~12.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~13.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~14.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~15.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~16.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~17.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~18.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~19.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~20.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~21.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~22.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~23.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~24.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~25.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~26.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~27.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~28.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~29.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~30.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => p1_registered_cpu_0_data_master_readdata~31.IN0 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => r_1~15.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~184.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~183.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~182.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~181.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~180.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~179.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~178.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~177.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~176.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~175.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~174.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~173.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~172.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~171.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~170.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~169.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~168.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~167.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~166.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~165.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~164.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~163.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~162.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~161.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~160.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~159.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~158.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~157.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~156.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~155.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~154.IN1 cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_readdata~153.IN1 cpu_0_data_master_requests_sdram_0_s1 => dbs_count_enable~0.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_dbs_increment[0].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_dbs_increment[1].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[0].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[1].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[2].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[3].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[4].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[5].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[6].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[7].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[8].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[9].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[10].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[11].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[12].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[13].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[14].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_dbs_16_reg_segment_0[15].OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => pre_dbs_count_enable~0.IN1 cpu_0_data_master_requests_sdram_0_s1 => last_dbs_term_and_run.OUTPUTSELECT cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~32.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~33.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~34.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~35.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~36.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~37.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~38.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~39.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~40.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~41.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~42.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~43.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~44.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~45.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~46.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~47.IN1 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~48.IN0 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~49.IN0 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~50.IN0 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~51.IN0 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~52.IN0 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~53.IN0 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~54.IN0 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~55.IN0 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~56.IN0 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~57.IN0 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~58.IN0 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~59.IN0 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~60.IN0 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~61.IN0 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~62.IN0 cpu_0_data_master_requests_sdram_0_s1 => p1_registered_cpu_0_data_master_readdata~63.IN0 cpu_0_data_master_requests_sdram_0_s1 => r_1~26.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~248.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~247.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~246.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~245.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~244.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~243.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~242.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~241.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~240.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~239.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~238.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~237.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~236.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~235.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~234.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~233.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~232.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~231.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~230.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~229.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~228.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~227.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~226.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~225.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~224.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~223.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~222.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~221.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~220.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~219.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~218.IN1 cpu_0_data_master_requests_sdram_0_s1 => cpu_0_data_master_readdata~217.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_dbs_increment[1].DATAA cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_dbs_increment~0.OUTPUTSELECT cpu_0_data_master_requests_sram_0_avalonS => pre_dbs_count_enable~7.IN1 cpu_0_data_master_requests_sram_0_avalonS => last_dbs_term_and_run~5.OUTPUTSELECT cpu_0_data_master_requests_sram_0_avalonS => r_1~43.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~312.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~311.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~310.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~309.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~308.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~307.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~306.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~305.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~304.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~303.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~302.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~301.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~300.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~299.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~298.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~297.IN0 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~296.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~295.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~294.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~293.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~292.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~291.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~290.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~289.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~288.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~287.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~286.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~285.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~284.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~283.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~282.IN1 cpu_0_data_master_requests_sram_0_avalonS => cpu_0_data_master_readdata~281.IN1 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~456.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~455.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~454.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~453.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~452.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~451.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~450.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~449.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~448.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~447.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~446.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~445.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~444.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~443.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~442.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~441.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~424.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~423.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~422.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~421.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~420.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~419.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~418.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~417.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~416.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~415.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~414.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~413.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~412.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~411.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~410.IN0 cpu_0_data_master_requests_uart_0_s1 => cpu_0_data_master_readdata~409.IN0 cpu_0_data_master_write => pre_dbs_count_enable~23.IN0 cpu_0_data_master_write => pre_dbs_count_enable~19.IN0 cpu_0_data_master_write => pre_dbs_count_enable~14.IN0 cpu_0_data_master_write => pre_dbs_count_enable~8.IN0 cpu_0_data_master_write => pre_dbs_count_enable~4.IN0 cpu_0_data_master_write => pre_dbs_count_enable~1.IN0 cpu_0_data_master_write => last_dbs_term_and_run~3.IN0 cpu_0_data_master_write => last_dbs_term_and_run~1.IN0 cpu_0_data_master_write => r_2~34.IN1 cpu_0_data_master_write => r_2~29.IN0 cpu_0_data_master_write => r_2~13.IN0 cpu_0_data_master_write => r_2~7.IN0 cpu_0_data_master_write => r_1~40.IN0 cpu_0_data_master_write => r_1~37.IN0 cpu_0_data_master_write => r_1~23.IN0 cpu_0_data_master_write => r_0~33.IN0 cpu_0_data_master_write => r_0~21.IN0 cpu_0_data_master_write => r_0~13.IN0 cpu_0_data_master_write => r_0~5.IN0 cpu_0_data_master_write => r_0~4.IN0 cpu_0_data_master_write => r_0~12.IN0 cpu_0_data_master_write => r_0~20.IN0 cpu_0_data_master_write => r_0~32.IN0 cpu_0_data_master_write => r_1~35.IN0 cpu_0_data_master_write => r_2~5.IN0 cpu_0_data_master_write => r_2~26.IN0 cpu_0_data_master_writedata[0] => cpu_0_data_master_dbs_write_8~23.DATAB cpu_0_data_master_writedata[0] => cpu_0_data_master_dbs_write_16~31.DATAB cpu_0_data_master_writedata[0] => cpu_0_data_master_dbs_write_16~15.DATAA cpu_0_data_master_writedata[1] => cpu_0_data_master_dbs_write_8~22.DATAB cpu_0_data_master_writedata[1] => cpu_0_data_master_dbs_write_16~30.DATAB cpu_0_data_master_writedata[1] => cpu_0_data_master_dbs_write_16~14.DATAA cpu_0_data_master_writedata[2] => cpu_0_data_master_dbs_write_8~21.DATAB cpu_0_data_master_writedata[2] => cpu_0_data_master_dbs_write_16~29.DATAB cpu_0_data_master_writedata[2] => cpu_0_data_master_dbs_write_16~13.DATAA cpu_0_data_master_writedata[3] => cpu_0_data_master_dbs_write_8~20.DATAB cpu_0_data_master_writedata[3] => cpu_0_data_master_dbs_write_16~28.DATAB cpu_0_data_master_writedata[3] => cpu_0_data_master_dbs_write_16~12.DATAA cpu_0_data_master_writedata[4] => cpu_0_data_master_dbs_write_8~19.DATAB cpu_0_data_master_writedata[4] => cpu_0_data_master_dbs_write_16~27.DATAB cpu_0_data_master_writedata[4] => cpu_0_data_master_dbs_write_16~11.DATAA cpu_0_data_master_writedata[5] => cpu_0_data_master_dbs_write_8~18.DATAB cpu_0_data_master_writedata[5] => cpu_0_data_master_dbs_write_16~26.DATAB cpu_0_data_master_writedata[5] => cpu_0_data_master_dbs_write_16~10.DATAA cpu_0_data_master_writedata[6] => cpu_0_data_master_dbs_write_8~17.DATAB cpu_0_data_master_writedata[6] => cpu_0_data_master_dbs_write_16~25.DATAB cpu_0_data_master_writedata[6] => cpu_0_data_master_dbs_write_16~9.DATAA cpu_0_data_master_writedata[7] => cpu_0_data_master_dbs_write_8~16.DATAB cpu_0_data_master_writedata[7] => cpu_0_data_master_dbs_write_16~24.DATAB cpu_0_data_master_writedata[7] => cpu_0_data_master_dbs_write_16~8.DATAA cpu_0_data_master_writedata[8] => cpu_0_data_master_dbs_write_8~15.DATAB cpu_0_data_master_writedata[8] => cpu_0_data_master_dbs_write_16~23.DATAB cpu_0_data_master_writedata[8] => cpu_0_data_master_dbs_write_16~7.DATAA cpu_0_data_master_writedata[9] => cpu_0_data_master_dbs_write_8~14.DATAB cpu_0_data_master_writedata[9] => cpu_0_data_master_dbs_write_16~22.DATAB cpu_0_data_master_writedata[9] => cpu_0_data_master_dbs_write_16~6.DATAA cpu_0_data_master_writedata[10] => cpu_0_data_master_dbs_write_8~13.DATAB cpu_0_data_master_writedata[10] => cpu_0_data_master_dbs_write_16~21.DATAB cpu_0_data_master_writedata[10] => cpu_0_data_master_dbs_write_16~5.DATAA cpu_0_data_master_writedata[11] => cpu_0_data_master_dbs_write_8~12.DATAB cpu_0_data_master_writedata[11] => cpu_0_data_master_dbs_write_16~20.DATAB cpu_0_data_master_writedata[11] => cpu_0_data_master_dbs_write_16~4.DATAA cpu_0_data_master_writedata[12] => cpu_0_data_master_dbs_write_8~11.DATAB cpu_0_data_master_writedata[12] => cpu_0_data_master_dbs_write_16~19.DATAB cpu_0_data_master_writedata[12] => cpu_0_data_master_dbs_write_16~3.DATAA cpu_0_data_master_writedata[13] => cpu_0_data_master_dbs_write_8~10.DATAB cpu_0_data_master_writedata[13] => cpu_0_data_master_dbs_write_16~18.DATAB cpu_0_data_master_writedata[13] => cpu_0_data_master_dbs_write_16~2.DATAA cpu_0_data_master_writedata[14] => cpu_0_data_master_dbs_write_8~9.DATAB cpu_0_data_master_writedata[14] => cpu_0_data_master_dbs_write_16~17.DATAB cpu_0_data_master_writedata[14] => cpu_0_data_master_dbs_write_16~1.DATAA cpu_0_data_master_writedata[15] => cpu_0_data_master_dbs_write_8~8.DATAB cpu_0_data_master_writedata[15] => cpu_0_data_master_dbs_write_16~16.DATAB cpu_0_data_master_writedata[15] => cpu_0_data_master_dbs_write_16~0.DATAA cpu_0_data_master_writedata[16] => cpu_0_data_master_dbs_write_8~7.DATAB cpu_0_data_master_writedata[16] => cpu_0_data_master_dbs_write_16~47.DATAB cpu_0_data_master_writedata[16] => cpu_0_data_master_dbs_write_16~15.DATAB cpu_0_data_master_writedata[17] => cpu_0_data_master_dbs_write_8~6.DATAB cpu_0_data_master_writedata[17] => cpu_0_data_master_dbs_write_16~46.DATAB cpu_0_data_master_writedata[17] => cpu_0_data_master_dbs_write_16~14.DATAB cpu_0_data_master_writedata[18] => cpu_0_data_master_dbs_write_8~5.DATAB cpu_0_data_master_writedata[18] => cpu_0_data_master_dbs_write_16~45.DATAB cpu_0_data_master_writedata[18] => cpu_0_data_master_dbs_write_16~13.DATAB cpu_0_data_master_writedata[19] => cpu_0_data_master_dbs_write_8~4.DATAB cpu_0_data_master_writedata[19] => cpu_0_data_master_dbs_write_16~44.DATAB cpu_0_data_master_writedata[19] => cpu_0_data_master_dbs_write_16~12.DATAB cpu_0_data_master_writedata[20] => cpu_0_data_master_dbs_write_8~3.DATAB cpu_0_data_master_writedata[20] => cpu_0_data_master_dbs_write_16~43.DATAB cpu_0_data_master_writedata[20] => cpu_0_data_master_dbs_write_16~11.DATAB cpu_0_data_master_writedata[21] => cpu_0_data_master_dbs_write_8~2.DATAB cpu_0_data_master_writedata[21] => cpu_0_data_master_dbs_write_16~42.DATAB cpu_0_data_master_writedata[21] => cpu_0_data_master_dbs_write_16~10.DATAB cpu_0_data_master_writedata[22] => cpu_0_data_master_dbs_write_8~1.DATAB cpu_0_data_master_writedata[22] => cpu_0_data_master_dbs_write_16~41.DATAB cpu_0_data_master_writedata[22] => cpu_0_data_master_dbs_write_16~9.DATAB cpu_0_data_master_writedata[23] => cpu_0_data_master_dbs_write_8~0.DATAB cpu_0_data_master_writedata[23] => cpu_0_data_master_dbs_write_16~40.DATAB cpu_0_data_master_writedata[23] => cpu_0_data_master_dbs_write_16~8.DATAB cpu_0_data_master_writedata[24] => cpu_0_data_master_dbs_write_8~7.DATAA cpu_0_data_master_writedata[24] => cpu_0_data_master_dbs_write_16~39.DATAB cpu_0_data_master_writedata[24] => cpu_0_data_master_dbs_write_16~7.DATAB cpu_0_data_master_writedata[25] => cpu_0_data_master_dbs_write_8~6.DATAA cpu_0_data_master_writedata[25] => cpu_0_data_master_dbs_write_16~38.DATAB cpu_0_data_master_writedata[25] => cpu_0_data_master_dbs_write_16~6.DATAB cpu_0_data_master_writedata[26] => cpu_0_data_master_dbs_write_8~5.DATAA cpu_0_data_master_writedata[26] => cpu_0_data_master_dbs_write_16~37.DATAB cpu_0_data_master_writedata[26] => cpu_0_data_master_dbs_write_16~5.DATAB cpu_0_data_master_writedata[27] => cpu_0_data_master_dbs_write_8~4.DATAA cpu_0_data_master_writedata[27] => cpu_0_data_master_dbs_write_16~36.DATAB cpu_0_data_master_writedata[27] => cpu_0_data_master_dbs_write_16~4.DATAB cpu_0_data_master_writedata[28] => cpu_0_data_master_dbs_write_8~3.DATAA cpu_0_data_master_writedata[28] => cpu_0_data_master_dbs_write_16~35.DATAB cpu_0_data_master_writedata[28] => cpu_0_data_master_dbs_write_16~3.DATAB cpu_0_data_master_writedata[29] => cpu_0_data_master_dbs_write_8~2.DATAA cpu_0_data_master_writedata[29] => cpu_0_data_master_dbs_write_16~34.DATAB cpu_0_data_master_writedata[29] => cpu_0_data_master_dbs_write_16~2.DATAB cpu_0_data_master_writedata[30] => cpu_0_data_master_dbs_write_8~1.DATAA cpu_0_data_master_writedata[30] => cpu_0_data_master_dbs_write_16~33.DATAB cpu_0_data_master_writedata[30] => cpu_0_data_master_dbs_write_16~1.DATAB cpu_0_data_master_writedata[31] => cpu_0_data_master_dbs_write_8~0.DATAA cpu_0_data_master_writedata[31] => cpu_0_data_master_dbs_write_16~32.DATAB cpu_0_data_master_writedata[31] => cpu_0_data_master_dbs_write_16~0.DATAB cpu_0_jtag_debug_module_readdata_from_sa[0] => cpu_0_data_master_readdata~25.IN1 cpu_0_jtag_debug_module_readdata_from_sa[1] => cpu_0_data_master_readdata~26.IN1 cpu_0_jtag_debug_module_readdata_from_sa[2] => cpu_0_data_master_readdata~27.IN1 cpu_0_jtag_debug_module_readdata_from_sa[3] => cpu_0_data_master_readdata~28.IN1 cpu_0_jtag_debug_module_readdata_from_sa[4] => cpu_0_data_master_readdata~29.IN1 cpu_0_jtag_debug_module_readdata_from_sa[5] => cpu_0_data_master_readdata~30.IN1 cpu_0_jtag_debug_module_readdata_from_sa[6] => cpu_0_data_master_readdata~31.IN1 cpu_0_jtag_debug_module_readdata_from_sa[7] => cpu_0_data_master_readdata~32.IN1 cpu_0_jtag_debug_module_readdata_from_sa[8] => cpu_0_data_master_readdata~33.IN1 cpu_0_jtag_debug_module_readdata_from_sa[9] => cpu_0_data_master_readdata~34.IN1 cpu_0_jtag_debug_module_readdata_from_sa[10] => cpu_0_data_master_readdata~35.IN1 cpu_0_jtag_debug_module_readdata_from_sa[11] => cpu_0_data_master_readdata~36.IN1 cpu_0_jtag_debug_module_readdata_from_sa[12] => cpu_0_data_master_readdata~37.IN1 cpu_0_jtag_debug_module_readdata_from_sa[13] => cpu_0_data_master_readdata~38.IN1 cpu_0_jtag_debug_module_readdata_from_sa[14] => cpu_0_data_master_readdata~39.IN1 cpu_0_jtag_debug_module_readdata_from_sa[15] => cpu_0_data_master_readdata~40.IN1 cpu_0_jtag_debug_module_readdata_from_sa[16] => cpu_0_data_master_readdata~41.IN1 cpu_0_jtag_debug_module_readdata_from_sa[17] => cpu_0_data_master_readdata~42.IN1 cpu_0_jtag_debug_module_readdata_from_sa[18] => cpu_0_data_master_readdata~43.IN1 cpu_0_jtag_debug_module_readdata_from_sa[19] => cpu_0_data_master_readdata~44.IN1 cpu_0_jtag_debug_module_readdata_from_sa[20] => cpu_0_data_master_readdata~45.IN1 cpu_0_jtag_debug_module_readdata_from_sa[21] => cpu_0_data_master_readdata~46.IN1 cpu_0_jtag_debug_module_readdata_from_sa[22] => cpu_0_data_master_readdata~47.IN1 cpu_0_jtag_debug_module_readdata_from_sa[23] => cpu_0_data_master_readdata~48.IN1 cpu_0_jtag_debug_module_readdata_from_sa[24] => cpu_0_data_master_readdata~49.IN1 cpu_0_jtag_debug_module_readdata_from_sa[25] => cpu_0_data_master_readdata~50.IN1 cpu_0_jtag_debug_module_readdata_from_sa[26] => cpu_0_data_master_readdata~51.IN1 cpu_0_jtag_debug_module_readdata_from_sa[27] => cpu_0_data_master_readdata~52.IN1 cpu_0_jtag_debug_module_readdata_from_sa[28] => cpu_0_data_master_readdata~53.IN1 cpu_0_jtag_debug_module_readdata_from_sa[29] => cpu_0_data_master_readdata~54.IN1 cpu_0_jtag_debug_module_readdata_from_sa[30] => cpu_0_data_master_readdata~55.IN1 cpu_0_jtag_debug_module_readdata_from_sa[31] => cpu_0_data_master_readdata~56.IN1 d1_KEY_s1_end_xfer => ~NO_FANOUT~ d1_LEDG_s1_end_xfer => ~NO_FANOUT~ d1_LEDR_s1_end_xfer => ~NO_FANOUT~ d1_SEG7_avalonS_end_xfer => ~NO_FANOUT~ d1_Switch_s1_end_xfer => ~NO_FANOUT~ d1_cpu_0_jtag_debug_module_end_xfer => ~NO_FANOUT~ d1_epcs_controller_epcs_control_port_end_xfer => ~NO_FANOUT~ d1_jtag_uart_0_avalon_jtag_slave_end_xfer => ~NO_FANOUT~ d1_sdram_0_s1_end_xfer => ~NO_FANOUT~ d1_sram_0_avalonS_end_xfer => pre_dbs_count_enable~15.IN0 d1_tri_state_bridge_0_avalon_slave_end_xfer => pre_dbs_count_enable~24.IN0 d1_uart_0_s1_end_xfer => ~NO_FANOUT~ epcs_controller_epcs_control_port_irq_from_sa => cpu_0_data_master_irq[2].DATAIN epcs_controller_epcs_control_port_readdata_from_sa[0] => cpu_0_data_master_readdata~89.IN1 epcs_controller_epcs_control_port_readdata_from_sa[1] => cpu_0_data_master_readdata~90.IN1 epcs_controller_epcs_control_port_readdata_from_sa[2] => cpu_0_data_master_readdata~91.IN1 epcs_controller_epcs_control_port_readdata_from_sa[3] => cpu_0_data_master_readdata~92.IN1 epcs_controller_epcs_control_port_readdata_from_sa[4] => cpu_0_data_master_readdata~93.IN1 epcs_controller_epcs_control_port_readdata_from_sa[5] => cpu_0_data_master_readdata~94.IN1 epcs_controller_epcs_control_port_readdata_from_sa[6] => cpu_0_data_master_readdata~95.IN1 epcs_controller_epcs_control_port_readdata_from_sa[7] => cpu_0_data_master_readdata~96.IN1 epcs_controller_epcs_control_port_readdata_from_sa[8] => cpu_0_data_master_readdata~97.IN1 epcs_controller_epcs_control_port_readdata_from_sa[9] => cpu_0_data_master_readdata~98.IN1 epcs_controller_epcs_control_port_readdata_from_sa[10] => cpu_0_data_master_readdata~99.IN1 epcs_controller_epcs_control_port_readdata_from_sa[11] => cpu_0_data_master_readdata~100.IN1 epcs_controller_epcs_control_port_readdata_from_sa[12] => cpu_0_data_master_readdata~101.IN1 epcs_controller_epcs_control_port_readdata_from_sa[13] => cpu_0_data_master_readdata~102.IN1 epcs_controller_epcs_control_port_readdata_from_sa[14] => cpu_0_data_master_readdata~103.IN1 epcs_controller_epcs_control_port_readdata_from_sa[15] => cpu_0_data_master_readdata~104.IN1 epcs_controller_epcs_control_port_readdata_from_sa[16] => cpu_0_data_master_readdata~105.IN1 epcs_controller_epcs_control_port_readdata_from_sa[17] => cpu_0_data_master_readdata~106.IN1 epcs_controller_epcs_control_port_readdata_from_sa[18] => cpu_0_data_master_readdata~107.IN1 epcs_controller_epcs_control_port_readdata_from_sa[19] => cpu_0_data_master_readdata~108.IN1 epcs_controller_epcs_control_port_readdata_from_sa[20] => cpu_0_data_master_readdata~109.IN1 epcs_controller_epcs_control_port_readdata_from_sa[21] => cpu_0_data_master_readdata~110.IN1 epcs_controller_epcs_control_port_readdata_from_sa[22] => cpu_0_data_master_readdata~111.IN1 epcs_controller_epcs_control_port_readdata_from_sa[23] => cpu_0_data_master_readdata~112.IN1 epcs_controller_epcs_control_port_readdata_from_sa[24] => cpu_0_data_master_readdata~113.IN1 epcs_controller_epcs_control_port_readdata_from_sa[25] => cpu_0_data_master_readdata~114.IN1 epcs_controller_epcs_control_port_readdata_from_sa[26] => cpu_0_data_master_readdata~115.IN1 epcs_controller_epcs_control_port_readdata_from_sa[27] => cpu_0_data_master_readdata~116.IN1 epcs_controller_epcs_control_port_readdata_from_sa[28] => cpu_0_data_master_readdata~117.IN1 epcs_controller_epcs_control_port_readdata_from_sa[29] => cpu_0_data_master_readdata~118.IN1 epcs_controller_epcs_control_port_readdata_from_sa[30] => cpu_0_data_master_readdata~119.IN1 epcs_controller_epcs_control_port_readdata_from_sa[31] => cpu_0_data_master_readdata~120.IN1 incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[0] => cpu_0_data_master_readdata~369.IN1 incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[0] => dbs_8_reg_segment_0[0].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[0] => dbs_8_reg_segment_2[0].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[0] => dbs_8_reg_segment_1[0].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[1] => cpu_0_data_master_readdata~370.IN1 incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[1] => dbs_8_reg_segment_0[1].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[1] => dbs_8_reg_segment_1[1].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[1] => dbs_8_reg_segment_2[1].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[2] => cpu_0_data_master_readdata~371.IN1 incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[2] => dbs_8_reg_segment_0[2].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[2] => dbs_8_reg_segment_1[2].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[2] => dbs_8_reg_segment_2[2].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[3] => cpu_0_data_master_readdata~372.IN1 incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[3] => dbs_8_reg_segment_0[3].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[3] => dbs_8_reg_segment_1[3].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[3] => dbs_8_reg_segment_2[3].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[4] => cpu_0_data_master_readdata~373.IN1 incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[4] => dbs_8_reg_segment_0[4].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[4] => dbs_8_reg_segment_1[4].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[4] => dbs_8_reg_segment_2[4].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[5] => cpu_0_data_master_readdata~374.IN1 incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[5] => dbs_8_reg_segment_0[5].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[5] => dbs_8_reg_segment_1[5].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[5] => dbs_8_reg_segment_2[5].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[6] => cpu_0_data_master_readdata~375.IN1 incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[6] => dbs_8_reg_segment_0[6].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[6] => dbs_8_reg_segment_1[6].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[6] => dbs_8_reg_segment_2[6].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[7] => cpu_0_data_master_readdata~376.IN1 incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[7] => dbs_8_reg_segment_0[7].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[7] => dbs_8_reg_segment_1[7].DATAIN incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[7] => dbs_8_reg_segment_2[7].DATAIN jtag_uart_0_avalon_jtag_slave_irq_from_sa => cpu_0_data_master_irq[0].DATAIN jtag_uart_0_avalon_jtag_slave_readdata_from_sa[0] => p1_registered_cpu_0_data_master_readdata~0.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[1] => p1_registered_cpu_0_data_master_readdata~1.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[2] => p1_registered_cpu_0_data_master_readdata~2.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[3] => p1_registered_cpu_0_data_master_readdata~3.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[4] => p1_registered_cpu_0_data_master_readdata~4.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[5] => p1_registered_cpu_0_data_master_readdata~5.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[6] => p1_registered_cpu_0_data_master_readdata~6.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[7] => p1_registered_cpu_0_data_master_readdata~7.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[8] => p1_registered_cpu_0_data_master_readdata~8.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[9] => p1_registered_cpu_0_data_master_readdata~9.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[10] => p1_registered_cpu_0_data_master_readdata~10.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[11] => p1_registered_cpu_0_data_master_readdata~11.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[12] => p1_registered_cpu_0_data_master_readdata~12.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[13] => p1_registered_cpu_0_data_master_readdata~13.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[14] => p1_registered_cpu_0_data_master_readdata~14.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[15] => p1_registered_cpu_0_data_master_readdata~15.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[16] => p1_registered_cpu_0_data_master_readdata~16.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[17] => p1_registered_cpu_0_data_master_readdata~17.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[18] => p1_registered_cpu_0_data_master_readdata~18.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[19] => p1_registered_cpu_0_data_master_readdata~19.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[20] => p1_registered_cpu_0_data_master_readdata~20.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[21] => p1_registered_cpu_0_data_master_readdata~21.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[22] => p1_registered_cpu_0_data_master_readdata~22.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[23] => p1_registered_cpu_0_data_master_readdata~23.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[24] => p1_registered_cpu_0_data_master_readdata~24.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[25] => p1_registered_cpu_0_data_master_readdata~25.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[26] => p1_registered_cpu_0_data_master_readdata~26.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[27] => p1_registered_cpu_0_data_master_readdata~27.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[28] => p1_registered_cpu_0_data_master_readdata~28.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[29] => p1_registered_cpu_0_data_master_readdata~29.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[30] => p1_registered_cpu_0_data_master_readdata~30.IN1 jtag_uart_0_avalon_jtag_slave_readdata_from_sa[31] => p1_registered_cpu_0_data_master_readdata~31.IN1 jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa => r_1~19.IN1 registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1 => r_2~22.IN0 registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1 => r_2~10.IN1 reset_n => dbs_8_reg_segment_2[0].ACLR reset_n => dbs_8_reg_segment_2[1].ACLR reset_n => dbs_8_reg_segment_2[2].ACLR reset_n => dbs_8_reg_segment_2[3].ACLR reset_n => dbs_8_reg_segment_2[4].ACLR reset_n => dbs_8_reg_segment_2[5].ACLR reset_n => dbs_8_reg_segment_2[6].ACLR reset_n => dbs_8_reg_segment_2[7].ACLR reset_n => dbs_8_reg_segment_1[0].ACLR reset_n => dbs_8_reg_segment_1[1].ACLR reset_n => dbs_8_reg_segment_1[2].ACLR reset_n => dbs_8_reg_segment_1[3].ACLR reset_n => dbs_8_reg_segment_1[4].ACLR reset_n => dbs_8_reg_segment_1[5].ACLR reset_n => dbs_8_reg_segment_1[6].ACLR reset_n => dbs_8_reg_segment_1[7].ACLR reset_n => dbs_8_reg_segment_0[0].ACLR reset_n => dbs_8_reg_segment_0[1].ACLR reset_n => dbs_8_reg_segment_0[2].ACLR reset_n => dbs_8_reg_segment_0[3].ACLR reset_n => dbs_8_reg_segment_0[4].ACLR reset_n => dbs_8_reg_segment_0[5].ACLR reset_n => dbs_8_reg_segment_0[6].ACLR reset_n => dbs_8_reg_segment_0[7].ACLR reset_n => dbs_16_reg_segment_0[0].ACLR reset_n => dbs_16_reg_segment_0[1].ACLR reset_n => dbs_16_reg_segment_0[2].ACLR reset_n => dbs_16_reg_segment_0[3].ACLR reset_n => dbs_16_reg_segment_0[4].ACLR reset_n => dbs_16_reg_segment_0[5].ACLR reset_n => dbs_16_reg_segment_0[6].ACLR reset_n => dbs_16_reg_segment_0[7].ACLR reset_n => dbs_16_reg_segment_0[8].ACLR reset_n => dbs_16_reg_segment_0[9].ACLR reset_n => dbs_16_reg_segment_0[10].ACLR reset_n => dbs_16_reg_segment_0[11].ACLR reset_n => dbs_16_reg_segment_0[12].ACLR reset_n => dbs_16_reg_segment_0[13].ACLR reset_n => dbs_16_reg_segment_0[14].ACLR reset_n => dbs_16_reg_segment_0[15].ACLR reset_n => cpu_0_data_master_dbs_address[0]~reg0.ACLR reset_n => cpu_0_data_master_dbs_address[1]~reg0.ACLR reset_n => cpu_0_data_master_no_byte_enables_and_last_term~reg0.ACLR reset_n => cpu_0_data_master_waitrequest~reg0.PRESET reset_n => registered_cpu_0_data_master_readdata[31].ACLR reset_n => registered_cpu_0_data_master_readdata[30].ACLR reset_n => registered_cpu_0_data_master_readdata[29].ACLR reset_n => registered_cpu_0_data_master_readdata[28].ACLR reset_n => registered_cpu_0_data_master_readdata[27].ACLR reset_n => registered_cpu_0_data_master_readdata[26].ACLR reset_n => registered_cpu_0_data_master_readdata[25].ACLR reset_n => registered_cpu_0_data_master_readdata[24].ACLR reset_n => registered_cpu_0_data_master_readdata[23].ACLR reset_n => registered_cpu_0_data_master_readdata[22].ACLR reset_n => registered_cpu_0_data_master_readdata[21].ACLR reset_n => registered_cpu_0_data_master_readdata[20].ACLR reset_n => registered_cpu_0_data_master_readdata[19].ACLR reset_n => registered_cpu_0_data_master_readdata[18].ACLR reset_n => registered_cpu_0_data_master_readdata[17].ACLR reset_n => registered_cpu_0_data_master_readdata[16].ACLR reset_n => registered_cpu_0_data_master_readdata[15].ACLR reset_n => registered_cpu_0_data_master_readdata[14].ACLR reset_n => registered_cpu_0_data_master_readdata[13].ACLR reset_n => registered_cpu_0_data_master_readdata[12].ACLR reset_n => registered_cpu_0_data_master_readdata[11].ACLR reset_n => registered_cpu_0_data_master_readdata[10].ACLR reset_n => registered_cpu_0_data_master_readdata[9].ACLR reset_n => registered_cpu_0_data_master_readdata[8].ACLR reset_n => registered_cpu_0_data_master_readdata[7].ACLR reset_n => registered_cpu_0_data_master_readdata[6].ACLR reset_n => registered_cpu_0_data_master_readdata[5].ACLR reset_n => registered_cpu_0_data_master_readdata[4].ACLR reset_n => registered_cpu_0_data_master_readdata[3].ACLR reset_n => registered_cpu_0_data_master_readdata[2].ACLR reset_n => registered_cpu_0_data_master_readdata[1].ACLR reset_n => registered_cpu_0_data_master_readdata[0].ACLR sdram_0_s1_readdata_from_sa[0] => p1_dbs_16_reg_segment_0[0].DATAB sdram_0_s1_readdata_from_sa[0] => p1_registered_cpu_0_data_master_readdata~48.IN1 sdram_0_s1_readdata_from_sa[1] => p1_dbs_16_reg_segment_0[1].DATAB sdram_0_s1_readdata_from_sa[1] => p1_registered_cpu_0_data_master_readdata~49.IN1 sdram_0_s1_readdata_from_sa[2] => p1_dbs_16_reg_segment_0[2].DATAB sdram_0_s1_readdata_from_sa[2] => p1_registered_cpu_0_data_master_readdata~50.IN1 sdram_0_s1_readdata_from_sa[3] => p1_dbs_16_reg_segment_0[3].DATAB sdram_0_s1_readdata_from_sa[3] => p1_registered_cpu_0_data_master_readdata~51.IN1 sdram_0_s1_readdata_from_sa[4] => p1_dbs_16_reg_segment_0[4].DATAB sdram_0_s1_readdata_from_sa[4] => p1_registered_cpu_0_data_master_readdata~52.IN1 sdram_0_s1_readdata_from_sa[5] => p1_dbs_16_reg_segment_0[5].DATAB sdram_0_s1_readdata_from_sa[5] => p1_registered_cpu_0_data_master_readdata~53.IN1 sdram_0_s1_readdata_from_sa[6] => p1_dbs_16_reg_segment_0[6].DATAB sdram_0_s1_readdata_from_sa[6] => p1_registered_cpu_0_data_master_readdata~54.IN1 sdram_0_s1_readdata_from_sa[7] => p1_dbs_16_reg_segment_0[7].DATAB sdram_0_s1_readdata_from_sa[7] => p1_registered_cpu_0_data_master_readdata~55.IN1 sdram_0_s1_readdata_from_sa[8] => p1_dbs_16_reg_segment_0[8].DATAB sdram_0_s1_readdata_from_sa[8] => p1_registered_cpu_0_data_master_readdata~56.IN1 sdram_0_s1_readdata_from_sa[9] => p1_dbs_16_reg_segment_0[9].DATAB sdram_0_s1_readdata_from_sa[9] => p1_registered_cpu_0_data_master_readdata~57.IN1 sdram_0_s1_readdata_from_sa[10] => p1_dbs_16_reg_segment_0[10].DATAB sdram_0_s1_readdata_from_sa[10] => p1_registered_cpu_0_data_master_readdata~58.IN1 sdram_0_s1_readdata_from_sa[11] => p1_dbs_16_reg_segment_0[11].DATAB sdram_0_s1_readdata_from_sa[11] => p1_registered_cpu_0_data_master_readdata~59.IN1 sdram_0_s1_readdata_from_sa[12] => p1_dbs_16_reg_segment_0[12].DATAB sdram_0_s1_readdata_from_sa[12] => p1_registered_cpu_0_data_master_readdata~60.IN1 sdram_0_s1_readdata_from_sa[13] => p1_dbs_16_reg_segment_0[13].DATAB sdram_0_s1_readdata_from_sa[13] => p1_registered_cpu_0_data_master_readdata~61.IN1 sdram_0_s1_readdata_from_sa[14] => p1_dbs_16_reg_segment_0[14].DATAB sdram_0_s1_readdata_from_sa[14] => p1_registered_cpu_0_data_master_readdata~62.IN1 sdram_0_s1_readdata_from_sa[15] => p1_dbs_16_reg_segment_0[15].DATAB sdram_0_s1_readdata_from_sa[15] => p1_registered_cpu_0_data_master_readdata~63.IN1 sdram_0_s1_waitrequest_from_sa => r_1~36.IN1 sdram_0_s1_waitrequest_from_sa => pre_dbs_count_enable~5.IN0 sram_0_avalonS_readdata_from_sa[0] => p1_dbs_16_reg_segment_0[0].DATAA sram_0_avalonS_readdata_from_sa[0] => cpu_0_data_master_readdata~297.IN1 sram_0_avalonS_readdata_from_sa[1] => p1_dbs_16_reg_segment_0[1].DATAA sram_0_avalonS_readdata_from_sa[1] => cpu_0_data_master_readdata~298.IN1 sram_0_avalonS_readdata_from_sa[2] => p1_dbs_16_reg_segment_0[2].DATAA sram_0_avalonS_readdata_from_sa[2] => cpu_0_data_master_readdata~299.IN1 sram_0_avalonS_readdata_from_sa[3] => p1_dbs_16_reg_segment_0[3].DATAA sram_0_avalonS_readdata_from_sa[3] => cpu_0_data_master_readdata~300.IN1 sram_0_avalonS_readdata_from_sa[4] => p1_dbs_16_reg_segment_0[4].DATAA sram_0_avalonS_readdata_from_sa[4] => cpu_0_data_master_readdata~301.IN1 sram_0_avalonS_readdata_from_sa[5] => p1_dbs_16_reg_segment_0[5].DATAA sram_0_avalonS_readdata_from_sa[5] => cpu_0_data_master_readdata~302.IN1 sram_0_avalonS_readdata_from_sa[6] => p1_dbs_16_reg_segment_0[6].DATAA sram_0_avalonS_readdata_from_sa[6] => cpu_0_data_master_readdata~303.IN1 sram_0_avalonS_readdata_from_sa[7] => p1_dbs_16_reg_segment_0[7].DATAA sram_0_avalonS_readdata_from_sa[7] => cpu_0_data_master_readdata~304.IN1 sram_0_avalonS_readdata_from_sa[8] => p1_dbs_16_reg_segment_0[8].DATAA sram_0_avalonS_readdata_from_sa[8] => cpu_0_data_master_readdata~305.IN1 sram_0_avalonS_readdata_from_sa[9] => p1_dbs_16_reg_segment_0[9].DATAA sram_0_avalonS_readdata_from_sa[9] => cpu_0_data_master_readdata~306.IN1 sram_0_avalonS_readdata_from_sa[10] => p1_dbs_16_reg_segment_0[10].DATAA sram_0_avalonS_readdata_from_sa[10] => cpu_0_data_master_readdata~307.IN1 sram_0_avalonS_readdata_from_sa[11] => p1_dbs_16_reg_segment_0[11].DATAA sram_0_avalonS_readdata_from_sa[11] => cpu_0_data_master_readdata~308.IN1 sram_0_avalonS_readdata_from_sa[12] => p1_dbs_16_reg_segment_0[12].DATAA sram_0_avalonS_readdata_from_sa[12] => cpu_0_data_master_readdata~309.IN1 sram_0_avalonS_readdata_from_sa[13] => p1_dbs_16_reg_segment_0[13].DATAA sram_0_avalonS_readdata_from_sa[13] => cpu_0_data_master_readdata~310.IN1 sram_0_avalonS_readdata_from_sa[14] => p1_dbs_16_reg_segment_0[14].DATAA sram_0_avalonS_readdata_from_sa[14] => cpu_0_data_master_readdata~311.IN1 sram_0_avalonS_readdata_from_sa[15] => p1_dbs_16_reg_segment_0[15].DATAA sram_0_avalonS_readdata_from_sa[15] => cpu_0_data_master_readdata~312.IN1 sram_0_avalonS_wait_counter_eq_0 => pre_dbs_count_enable~15.IN1 sram_0_avalonS_wait_counter_eq_1 => r_2~6.IN1 uart_0_s1_irq_from_sa => cpu_0_data_master_irq[1].DATAIN uart_0_s1_readdata_from_sa[0] => cpu_0_data_master_readdata~409.IN1 uart_0_s1_readdata_from_sa[1] => cpu_0_data_master_readdata~410.IN1 uart_0_s1_readdata_from_sa[2] => cpu_0_data_master_readdata~411.IN1 uart_0_s1_readdata_from_sa[3] => cpu_0_data_master_readdata~412.IN1 uart_0_s1_readdata_from_sa[4] => cpu_0_data_master_readdata~413.IN1 uart_0_s1_readdata_from_sa[5] => cpu_0_data_master_readdata~414.IN1 uart_0_s1_readdata_from_sa[6] => cpu_0_data_master_readdata~415.IN1 uart_0_s1_readdata_from_sa[7] => cpu_0_data_master_readdata~416.IN1 uart_0_s1_readdata_from_sa[8] => cpu_0_data_master_readdata~417.IN1 uart_0_s1_readdata_from_sa[9] => cpu_0_data_master_readdata~418.IN1 uart_0_s1_readdata_from_sa[10] => cpu_0_data_master_readdata~419.IN1 uart_0_s1_readdata_from_sa[11] => cpu_0_data_master_readdata~420.IN1 uart_0_s1_readdata_from_sa[12] => cpu_0_data_master_readdata~421.IN1 uart_0_s1_readdata_from_sa[13] => cpu_0_data_master_readdata~422.IN1 uart_0_s1_readdata_from_sa[14] => cpu_0_data_master_readdata~423.IN1 uart_0_s1_readdata_from_sa[15] => cpu_0_data_master_readdata~424.IN1 cpu_0_data_master_address_to_slave[0] <= cpu_0_data_master_address[0].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[1] <= cpu_0_data_master_address[1].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[2] <= cpu_0_data_master_address[2].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[3] <= cpu_0_data_master_address[3].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[4] <= cpu_0_data_master_address[4].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[5] <= cpu_0_data_master_address[5].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[6] <= cpu_0_data_master_address[6].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[7] <= cpu_0_data_master_address[7].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[8] <= cpu_0_data_master_address[8].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[9] <= cpu_0_data_master_address[9].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[10] <= cpu_0_data_master_address[10].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[11] <= cpu_0_data_master_address[11].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[12] <= cpu_0_data_master_address[12].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[13] <= cpu_0_data_master_address[13].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[14] <= cpu_0_data_master_address[14].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[15] <= cpu_0_data_master_address[15].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[16] <= cpu_0_data_master_address[16].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[17] <= cpu_0_data_master_address[17].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[18] <= cpu_0_data_master_address[18].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[19] <= cpu_0_data_master_address[19].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[20] <= cpu_0_data_master_address[20].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[21] <= cpu_0_data_master_address[21].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[22] <= cpu_0_data_master_address[22].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_address_to_slave[23] <= cpu_0_data_master_address[23].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_address[0] <= cpu_0_data_master_dbs_address[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_address[1] <= cpu_0_data_master_dbs_address[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[0] <= cpu_0_data_master_dbs_write_16~47.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[1] <= cpu_0_data_master_dbs_write_16~46.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[2] <= cpu_0_data_master_dbs_write_16~45.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[3] <= cpu_0_data_master_dbs_write_16~44.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[4] <= cpu_0_data_master_dbs_write_16~43.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[5] <= cpu_0_data_master_dbs_write_16~42.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[6] <= cpu_0_data_master_dbs_write_16~41.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[7] <= cpu_0_data_master_dbs_write_16~40.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[8] <= cpu_0_data_master_dbs_write_16~39.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[9] <= cpu_0_data_master_dbs_write_16~38.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[10] <= cpu_0_data_master_dbs_write_16~37.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[11] <= cpu_0_data_master_dbs_write_16~36.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[12] <= cpu_0_data_master_dbs_write_16~35.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[13] <= cpu_0_data_master_dbs_write_16~34.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[14] <= cpu_0_data_master_dbs_write_16~33.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_16[15] <= cpu_0_data_master_dbs_write_16~32.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_8[0] <= cpu_0_data_master_dbs_write_8~23.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_8[1] <= cpu_0_data_master_dbs_write_8~22.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_8[2] <= cpu_0_data_master_dbs_write_8~21.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_8[3] <= cpu_0_data_master_dbs_write_8~20.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_8[4] <= cpu_0_data_master_dbs_write_8~19.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_8[5] <= cpu_0_data_master_dbs_write_8~18.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_8[6] <= cpu_0_data_master_dbs_write_8~17.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_dbs_write_8[7] <= cpu_0_data_master_dbs_write_8~16.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_irq[0] <= jtag_uart_0_avalon_jtag_slave_irq_from_sa.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_irq[1] <= uart_0_s1_irq_from_sa.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_irq[2] <= epcs_controller_epcs_control_port_irq_from_sa.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_irq[3] <= KEY_s1_irq_from_sa.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_irq[4] <= cpu_0_data_master_irq[5] <= cpu_0_data_master_irq[6] <= cpu_0_data_master_irq[7] <= cpu_0_data_master_irq[8] <= cpu_0_data_master_irq[9] <= cpu_0_data_master_irq[10] <= cpu_0_data_master_irq[11] <= cpu_0_data_master_irq[12] <= cpu_0_data_master_irq[13] <= cpu_0_data_master_irq[14] <= cpu_0_data_master_irq[15] <= cpu_0_data_master_irq[16] <= cpu_0_data_master_irq[17] <= cpu_0_data_master_irq[18] <= cpu_0_data_master_irq[19] <= cpu_0_data_master_irq[20] <= cpu_0_data_master_irq[21] <= cpu_0_data_master_irq[22] <= cpu_0_data_master_irq[23] <= cpu_0_data_master_irq[24] <= cpu_0_data_master_irq[25] <= cpu_0_data_master_irq[26] <= cpu_0_data_master_irq[27] <= cpu_0_data_master_irq[28] <= cpu_0_data_master_irq[29] <= cpu_0_data_master_irq[30] <= cpu_0_data_master_irq[31] <= cpu_0_data_master_no_byte_enables_and_last_term <= cpu_0_data_master_no_byte_enables_and_last_term~reg0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[0] <= cpu_0_data_master_readdata~425.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[1] <= cpu_0_data_master_readdata~426.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[2] <= cpu_0_data_master_readdata~427.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[3] <= cpu_0_data_master_readdata~428.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[4] <= cpu_0_data_master_readdata~429.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[5] <= cpu_0_data_master_readdata~430.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[6] <= cpu_0_data_master_readdata~431.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[7] <= cpu_0_data_master_readdata~432.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[8] <= cpu_0_data_master_readdata~433.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[9] <= cpu_0_data_master_readdata~434.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[10] <= cpu_0_data_master_readdata~435.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[11] <= cpu_0_data_master_readdata~436.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[12] <= cpu_0_data_master_readdata~437.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[13] <= cpu_0_data_master_readdata~438.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[14] <= cpu_0_data_master_readdata~439.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[15] <= cpu_0_data_master_readdata~440.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[16] <= cpu_0_data_master_readdata~441.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[17] <= cpu_0_data_master_readdata~442.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[18] <= cpu_0_data_master_readdata~443.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[19] <= cpu_0_data_master_readdata~444.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[20] <= cpu_0_data_master_readdata~445.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[21] <= cpu_0_data_master_readdata~446.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[22] <= cpu_0_data_master_readdata~447.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[23] <= cpu_0_data_master_readdata~448.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[24] <= cpu_0_data_master_readdata~449.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[25] <= cpu_0_data_master_readdata~450.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[26] <= cpu_0_data_master_readdata~451.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[27] <= cpu_0_data_master_readdata~452.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[28] <= cpu_0_data_master_readdata~453.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[29] <= cpu_0_data_master_readdata~454.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[30] <= cpu_0_data_master_readdata~455.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_readdata[31] <= cpu_0_data_master_readdata~456.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_waitrequest <= cpu_0_data_master_waitrequest~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master cfi_flash_0_s1_wait_counter_eq_0 => pre_dbs_count_enable~7.IN1 cfi_flash_0_s1_wait_counter_eq_1 => ~NO_FANOUT~ clk => cpu_0_instruction_master_read_but_no_slave_selected.CLK clk => cpu_0_instruction_master_latency_counter[1]~reg0.CLK clk => cpu_0_instruction_master_latency_counter[0]~reg0.CLK clk => dbs_latent_16_reg_segment_0[15].CLK clk => dbs_latent_16_reg_segment_0[14].CLK clk => dbs_latent_16_reg_segment_0[13].CLK clk => dbs_latent_16_reg_segment_0[12].CLK clk => dbs_latent_16_reg_segment_0[11].CLK clk => dbs_latent_16_reg_segment_0[10].CLK clk => dbs_latent_16_reg_segment_0[9].CLK clk => dbs_latent_16_reg_segment_0[8].CLK clk => dbs_latent_16_reg_segment_0[7].CLK clk => dbs_latent_16_reg_segment_0[6].CLK clk => dbs_latent_16_reg_segment_0[5].CLK clk => dbs_latent_16_reg_segment_0[4].CLK clk => dbs_latent_16_reg_segment_0[3].CLK clk => dbs_latent_16_reg_segment_0[2].CLK clk => dbs_latent_16_reg_segment_0[1].CLK clk => dbs_latent_16_reg_segment_0[0].CLK clk => cpu_0_instruction_master_dbs_address[1]~reg0.CLK clk => cpu_0_instruction_master_dbs_address[0]~reg0.CLK clk => cpu_0_instruction_master_dbs_rdv_counter[1].CLK clk => cpu_0_instruction_master_dbs_rdv_counter[0].CLK clk => dbs_16_reg_segment_0[15].CLK clk => dbs_16_reg_segment_0[14].CLK clk => dbs_16_reg_segment_0[13].CLK clk => dbs_16_reg_segment_0[12].CLK clk => dbs_16_reg_segment_0[11].CLK clk => dbs_16_reg_segment_0[10].CLK clk => dbs_16_reg_segment_0[9].CLK clk => dbs_16_reg_segment_0[8].CLK clk => dbs_16_reg_segment_0[7].CLK clk => dbs_16_reg_segment_0[6].CLK clk => dbs_16_reg_segment_0[5].CLK clk => dbs_16_reg_segment_0[4].CLK clk => dbs_16_reg_segment_0[3].CLK clk => dbs_16_reg_segment_0[2].CLK clk => dbs_16_reg_segment_0[1].CLK clk => dbs_16_reg_segment_0[0].CLK clk => dbs_latent_8_reg_segment_0[7].CLK clk => dbs_latent_8_reg_segment_0[6].CLK clk => dbs_latent_8_reg_segment_0[5].CLK clk => dbs_latent_8_reg_segment_0[4].CLK clk => dbs_latent_8_reg_segment_0[3].CLK clk => dbs_latent_8_reg_segment_0[2].CLK clk => dbs_latent_8_reg_segment_0[1].CLK clk => dbs_latent_8_reg_segment_0[0].CLK clk => dbs_latent_8_reg_segment_1[7].CLK clk => dbs_latent_8_reg_segment_1[6].CLK clk => dbs_latent_8_reg_segment_1[5].CLK clk => dbs_latent_8_reg_segment_1[4].CLK clk => dbs_latent_8_reg_segment_1[3].CLK clk => dbs_latent_8_reg_segment_1[2].CLK clk => dbs_latent_8_reg_segment_1[1].CLK clk => dbs_latent_8_reg_segment_1[0].CLK clk => dbs_latent_8_reg_segment_2[7].CLK clk => dbs_latent_8_reg_segment_2[6].CLK clk => dbs_latent_8_reg_segment_2[5].CLK clk => dbs_latent_8_reg_segment_2[4].CLK clk => dbs_latent_8_reg_segment_2[3].CLK clk => dbs_latent_8_reg_segment_2[2].CLK clk => dbs_latent_8_reg_segment_2[1].CLK clk => dbs_latent_8_reg_segment_2[0].CLK cpu_0_instruction_master_address[0] => cpu_0_instruction_master_address_to_slave[0].DATAIN cpu_0_instruction_master_address[1] => cpu_0_instruction_master_address_to_slave[1].DATAIN cpu_0_instruction_master_address[2] => cpu_0_instruction_master_address_to_slave[2].DATAIN cpu_0_instruction_master_address[3] => cpu_0_instruction_master_address_to_slave[3].DATAIN cpu_0_instruction_master_address[4] => cpu_0_instruction_master_address_to_slave[4].DATAIN cpu_0_instruction_master_address[5] => cpu_0_instruction_master_address_to_slave[5].DATAIN cpu_0_instruction_master_address[6] => cpu_0_instruction_master_address_to_slave[6].DATAIN cpu_0_instruction_master_address[7] => cpu_0_instruction_master_address_to_slave[7].DATAIN cpu_0_instruction_master_address[8] => cpu_0_instruction_master_address_to_slave[8].DATAIN cpu_0_instruction_master_address[9] => cpu_0_instruction_master_address_to_slave[9].DATAIN cpu_0_instruction_master_address[10] => cpu_0_instruction_master_address_to_slave[10].DATAIN cpu_0_instruction_master_address[11] => cpu_0_instruction_master_address_to_slave[11].DATAIN cpu_0_instruction_master_address[12] => cpu_0_instruction_master_address_to_slave[12].DATAIN cpu_0_instruction_master_address[13] => cpu_0_instruction_master_address_to_slave[13].DATAIN cpu_0_instruction_master_address[14] => cpu_0_instruction_master_address_to_slave[14].DATAIN cpu_0_instruction_master_address[15] => cpu_0_instruction_master_address_to_slave[15].DATAIN cpu_0_instruction_master_address[16] => cpu_0_instruction_master_address_to_slave[16].DATAIN cpu_0_instruction_master_address[17] => cpu_0_instruction_master_address_to_slave[17].DATAIN cpu_0_instruction_master_address[18] => cpu_0_instruction_master_address_to_slave[18].DATAIN cpu_0_instruction_master_address[19] => cpu_0_instruction_master_address_to_slave[19].DATAIN cpu_0_instruction_master_address[20] => cpu_0_instruction_master_address_to_slave[20].DATAIN cpu_0_instruction_master_address[21] => cpu_0_instruction_master_address_to_slave[21].DATAIN cpu_0_instruction_master_address[22] => cpu_0_instruction_master_address_to_slave[22].DATAIN cpu_0_instruction_master_address[23] => cpu_0_instruction_master_address_to_slave[23].DATAIN cpu_0_instruction_master_granted_cfi_flash_0_s1 => pre_dbs_count_enable~6.IN0 cpu_0_instruction_master_granted_cfi_flash_0_s1 => cpu_0_instruction_master_is_granted_some_slave.IN1 cpu_0_instruction_master_granted_cfi_flash_0_s1 => r_2~10.IN0 cpu_0_instruction_master_granted_cpu_0_jtag_debug_module => cpu_0_instruction_master_is_granted_some_slave~0.IN0 cpu_0_instruction_master_granted_cpu_0_jtag_debug_module => r_1~1.IN0 cpu_0_instruction_master_granted_epcs_controller_epcs_control_port => cpu_0_instruction_master_is_granted_some_slave~0.IN1 cpu_0_instruction_master_granted_epcs_controller_epcs_control_port => r_1~9.IN0 cpu_0_instruction_master_granted_sdram_0_s1 => pre_dbs_count_enable~0.IN0 cpu_0_instruction_master_granted_sdram_0_s1 => cpu_0_instruction_master_is_granted_some_slave~1.IN1 cpu_0_instruction_master_granted_sdram_0_s1 => r_1~17.IN0 cpu_0_instruction_master_granted_sram_0_avalonS => pre_dbs_count_enable~2.IN0 cpu_0_instruction_master_granted_sram_0_avalonS => cpu_0_instruction_master_is_granted_some_slave~2.IN1 cpu_0_instruction_master_granted_sram_0_avalonS => r_2~1.IN0 cpu_0_instruction_master_qualified_request_cfi_flash_0_s1 => r_2~8.IN1 cpu_0_instruction_master_qualified_request_cfi_flash_0_s1 => r_2~10.IN1 cpu_0_instruction_master_qualified_request_cfi_flash_0_s1 => r_2~12.IN1 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => r_1~0.IN1 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => r_1~3.IN1 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => r_1~1.IN1 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~31.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~30.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~29.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~28.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~27.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~26.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~25.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~24.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~23.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~22.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~21.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~20.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~19.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~18.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~17.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~16.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~15.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~14.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~13.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~12.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~11.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~10.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~9.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~8.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~7.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~6.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~5.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~4.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~3.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~2.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~1.IN0 cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~0.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => r_1~7.IN1 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => r_1~11.IN1 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => r_1~9.IN1 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~63.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~62.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~61.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~60.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~59.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~58.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~57.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~56.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~55.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~54.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~53.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~52.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~51.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~50.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~49.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~48.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~47.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~46.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~45.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~44.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~43.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~42.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~41.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~40.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~39.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~38.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~37.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~36.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~35.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~34.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~33.IN0 cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdata~32.IN0 cpu_0_instruction_master_qualified_request_sdram_0_s1 => r_1~15.IN1 cpu_0_instruction_master_qualified_request_sdram_0_s1 => r_1~17.IN1 cpu_0_instruction_master_qualified_request_sdram_0_s1 => r_1~19.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => r_2~0.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => r_2~3.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => r_2~1.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~191.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~190.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~189.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~188.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~187.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~186.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~185.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~184.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~183.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~182.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~181.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~180.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~179.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~178.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~177.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~176.IN0 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~175.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~174.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~173.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~172.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~171.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~170.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~169.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~168.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~167.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~166.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~165.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~164.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~163.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~162.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~161.IN1 cpu_0_instruction_master_qualified_request_sram_0_avalonS => cpu_0_instruction_master_readdata~160.IN1 cpu_0_instruction_master_read => pre_dbs_count_enable~6.IN1 cpu_0_instruction_master_read => pre_dbs_count_enable~2.IN1 cpu_0_instruction_master_read => pre_dbs_count_enable~0.IN1 cpu_0_instruction_master_read => p1_cpu_0_instruction_master_latency_counter~0.IN0 cpu_0_instruction_master_read => r_2~15.IN0 cpu_0_instruction_master_read => r_2~5.IN0 cpu_0_instruction_master_read => r_1~21.IN0 cpu_0_instruction_master_read => r_1~12.IN0 cpu_0_instruction_master_read => r_1~4.IN0 cpu_0_instruction_master_read => r_1~3.IN0 cpu_0_instruction_master_read => r_1~11.IN0 cpu_0_instruction_master_read => r_1~19.IN0 cpu_0_instruction_master_read => r_2~3.IN0 cpu_0_instruction_master_read => r_2~12.IN0 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => dbs_rdv_count_enable.IN0 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => pre_flush_cpu_0_instruction_master_readdatavalid~1.IN0 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~255.IN0 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~254.IN0 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~253.IN0 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~252.IN0 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~251.IN0 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~250.IN0 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~249.IN0 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~248.IN0 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~247.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~246.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~245.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~244.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~243.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~242.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~241.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~240.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~239.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~238.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~237.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~236.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~235.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~234.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~233.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~232.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~231.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~230.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~229.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~228.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~227.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~226.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~225.IN1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 => cpu_0_instruction_master_readdata~224.IN1 cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdatavalid~1.IN1 cpu_0_instruction_master_read_data_valid_epcs_controller_epcs_control_port => cpu_0_instruction_master_readdatavalid~4.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => dbs_rdv_count_enable.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => pre_flush_cpu_0_instruction_master_readdatavalid~0.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~127.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~126.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~125.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~124.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~123.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~122.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~121.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~120.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~119.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~118.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~117.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~116.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~115.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~114.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~113.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~112.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~111.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~110.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~109.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~108.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~107.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~106.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~105.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~104.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~103.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~102.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~101.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~100.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~99.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~98.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~97.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => cpu_0_instruction_master_readdata~96.IN1 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => Add2.IN3 cpu_0_instruction_master_read_data_valid_sdram_0_s1 => Add2.IN4 cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register => ~NO_FANOUT~ cpu_0_instruction_master_read_data_valid_sram_0_avalonS => cpu_0_instruction_master_readdatavalid~9.IN0 cpu_0_instruction_master_requests_cfi_flash_0_s1 => cpu_0_instruction_master_dbs_increment~0.DATAA cpu_0_instruction_master_requests_cfi_flash_0_s1 => p1_cpu_0_instruction_master_latency_counter[1].DATAB cpu_0_instruction_master_requests_cfi_flash_0_s1 => r_2~8.IN0 cpu_0_instruction_master_requests_cpu_0_jtag_debug_module => r_1~0.IN0 cpu_0_instruction_master_requests_epcs_controller_epcs_control_port => r_1~7.IN0 cpu_0_instruction_master_requests_sdram_0_s1 => cpu_0_instruction_master_dbs_increment[0].OUTPUTSELECT cpu_0_instruction_master_requests_sdram_0_s1 => cpu_0_instruction_master_dbs_increment[1].OUTPUTSELECT cpu_0_instruction_master_requests_sdram_0_s1 => r_1~15.IN0 cpu_0_instruction_master_requests_sram_0_avalonS => cpu_0_instruction_master_dbs_increment[1].DATAA cpu_0_instruction_master_requests_sram_0_avalonS => cpu_0_instruction_master_dbs_increment~0.OUTPUTSELECT cpu_0_instruction_master_requests_sram_0_avalonS => r_2~0.IN0 cpu_0_jtag_debug_module_readdata_from_sa[0] => cpu_0_instruction_master_readdata~0.IN1 cpu_0_jtag_debug_module_readdata_from_sa[1] => cpu_0_instruction_master_readdata~1.IN1 cpu_0_jtag_debug_module_readdata_from_sa[2] => cpu_0_instruction_master_readdata~2.IN1 cpu_0_jtag_debug_module_readdata_from_sa[3] => cpu_0_instruction_master_readdata~3.IN1 cpu_0_jtag_debug_module_readdata_from_sa[4] => cpu_0_instruction_master_readdata~4.IN1 cpu_0_jtag_debug_module_readdata_from_sa[5] => cpu_0_instruction_master_readdata~5.IN1 cpu_0_jtag_debug_module_readdata_from_sa[6] => cpu_0_instruction_master_readdata~6.IN1 cpu_0_jtag_debug_module_readdata_from_sa[7] => cpu_0_instruction_master_readdata~7.IN1 cpu_0_jtag_debug_module_readdata_from_sa[8] => cpu_0_instruction_master_readdata~8.IN1 cpu_0_jtag_debug_module_readdata_from_sa[9] => cpu_0_instruction_master_readdata~9.IN1 cpu_0_jtag_debug_module_readdata_from_sa[10] => cpu_0_instruction_master_readdata~10.IN1 cpu_0_jtag_debug_module_readdata_from_sa[11] => cpu_0_instruction_master_readdata~11.IN1 cpu_0_jtag_debug_module_readdata_from_sa[12] => cpu_0_instruction_master_readdata~12.IN1 cpu_0_jtag_debug_module_readdata_from_sa[13] => cpu_0_instruction_master_readdata~13.IN1 cpu_0_jtag_debug_module_readdata_from_sa[14] => cpu_0_instruction_master_readdata~14.IN1 cpu_0_jtag_debug_module_readdata_from_sa[15] => cpu_0_instruction_master_readdata~15.IN1 cpu_0_jtag_debug_module_readdata_from_sa[16] => cpu_0_instruction_master_readdata~16.IN1 cpu_0_jtag_debug_module_readdata_from_sa[17] => cpu_0_instruction_master_readdata~17.IN1 cpu_0_jtag_debug_module_readdata_from_sa[18] => cpu_0_instruction_master_readdata~18.IN1 cpu_0_jtag_debug_module_readdata_from_sa[19] => cpu_0_instruction_master_readdata~19.IN1 cpu_0_jtag_debug_module_readdata_from_sa[20] => cpu_0_instruction_master_readdata~20.IN1 cpu_0_jtag_debug_module_readdata_from_sa[21] => cpu_0_instruction_master_readdata~21.IN1 cpu_0_jtag_debug_module_readdata_from_sa[22] => cpu_0_instruction_master_readdata~22.IN1 cpu_0_jtag_debug_module_readdata_from_sa[23] => cpu_0_instruction_master_readdata~23.IN1 cpu_0_jtag_debug_module_readdata_from_sa[24] => cpu_0_instruction_master_readdata~24.IN1 cpu_0_jtag_debug_module_readdata_from_sa[25] => cpu_0_instruction_master_readdata~25.IN1 cpu_0_jtag_debug_module_readdata_from_sa[26] => cpu_0_instruction_master_readdata~26.IN1 cpu_0_jtag_debug_module_readdata_from_sa[27] => cpu_0_instruction_master_readdata~27.IN1 cpu_0_jtag_debug_module_readdata_from_sa[28] => cpu_0_instruction_master_readdata~28.IN1 cpu_0_jtag_debug_module_readdata_from_sa[29] => cpu_0_instruction_master_readdata~29.IN1 cpu_0_jtag_debug_module_readdata_from_sa[30] => cpu_0_instruction_master_readdata~30.IN1 cpu_0_jtag_debug_module_readdata_from_sa[31] => cpu_0_instruction_master_readdata~31.IN1 d1_cpu_0_jtag_debug_module_end_xfer => r_1~4.IN1 d1_epcs_controller_epcs_control_port_end_xfer => r_1~12.IN1 d1_sdram_0_s1_end_xfer => ~NO_FANOUT~ d1_sram_0_avalonS_end_xfer => pre_dbs_count_enable~3.IN0 d1_tri_state_bridge_0_avalon_slave_end_xfer => pre_dbs_count_enable~7.IN0 epcs_controller_epcs_control_port_readdata_from_sa[0] => cpu_0_instruction_master_readdata~32.IN1 epcs_controller_epcs_control_port_readdata_from_sa[1] => cpu_0_instruction_master_readdata~33.IN1 epcs_controller_epcs_control_port_readdata_from_sa[2] => cpu_0_instruction_master_readdata~34.IN1 epcs_controller_epcs_control_port_readdata_from_sa[3] => cpu_0_instruction_master_readdata~35.IN1 epcs_controller_epcs_control_port_readdata_from_sa[4] => cpu_0_instruction_master_readdata~36.IN1 epcs_controller_epcs_control_port_readdata_from_sa[5] => cpu_0_instruction_master_readdata~37.IN1 epcs_controller_epcs_control_port_readdata_from_sa[6] => cpu_0_instruction_master_readdata~38.IN1 epcs_controller_epcs_control_port_readdata_from_sa[7] => cpu_0_instruction_master_readdata~39.IN1 epcs_controller_epcs_control_port_readdata_from_sa[8] => cpu_0_instruction_master_readdata~40.IN1 epcs_controller_epcs_control_port_readdata_from_sa[9] => cpu_0_instruction_master_readdata~41.IN1 epcs_controller_epcs_control_port_readdata_from_sa[10] => cpu_0_instruction_master_readdata~42.IN1 epcs_controller_epcs_control_port_readdata_from_sa[11] => cpu_0_instruction_master_readdata~43.IN1 epcs_controller_epcs_control_port_readdata_from_sa[12] => cpu_0_instruction_master_readdata~44.IN1 epcs_controller_epcs_control_port_readdata_from_sa[13] => cpu_0_instruction_master_readdata~45.IN1 epcs_controller_epcs_control_port_readdata_from_sa[14] => cpu_0_instruction_master_readdata~46.IN1 epcs_controller_epcs_control_port_readdata_from_sa[15] => cpu_0_instruction_master_readdata~47.IN1 epcs_controller_epcs_control_port_readdata_from_sa[16] => cpu_0_instruction_master_readdata~48.IN1 epcs_controller_epcs_control_port_readdata_from_sa[17] => cpu_0_instruction_master_readdata~49.IN1 epcs_controller_epcs_control_port_readdata_from_sa[18] => cpu_0_instruction_master_readdata~50.IN1 epcs_controller_epcs_control_port_readdata_from_sa[19] => cpu_0_instruction_master_readdata~51.IN1 epcs_controller_epcs_control_port_readdata_from_sa[20] => cpu_0_instruction_master_readdata~52.IN1 epcs_controller_epcs_control_port_readdata_from_sa[21] => cpu_0_instruction_master_readdata~53.IN1 epcs_controller_epcs_control_port_readdata_from_sa[22] => cpu_0_instruction_master_readdata~54.IN1 epcs_controller_epcs_control_port_readdata_from_sa[23] => cpu_0_instruction_master_readdata~55.IN1 epcs_controller_epcs_control_port_readdata_from_sa[24] => cpu_0_instruction_master_readdata~56.IN1 epcs_controller_epcs_control_port_readdata_from_sa[25] => cpu_0_instruction_master_readdata~57.IN1 epcs_controller_epcs_control_port_readdata_from_sa[26] => cpu_0_instruction_master_readdata~58.IN1 epcs_controller_epcs_control_port_readdata_from_sa[27] => cpu_0_instruction_master_readdata~59.IN1 epcs_controller_epcs_control_port_readdata_from_sa[28] => cpu_0_instruction_master_readdata~60.IN1 epcs_controller_epcs_control_port_readdata_from_sa[29] => cpu_0_instruction_master_readdata~61.IN1 epcs_controller_epcs_control_port_readdata_from_sa[30] => cpu_0_instruction_master_readdata~62.IN1 epcs_controller_epcs_control_port_readdata_from_sa[31] => cpu_0_instruction_master_readdata~63.IN1 incoming_tri_state_bridge_0_data[0] => cpu_0_instruction_master_readdata~248.IN1 incoming_tri_state_bridge_0_data[0] => dbs_latent_8_reg_segment_2[0].DATAIN incoming_tri_state_bridge_0_data[0] => dbs_latent_8_reg_segment_0[0].DATAIN incoming_tri_state_bridge_0_data[0] => dbs_latent_8_reg_segment_1[0].DATAIN incoming_tri_state_bridge_0_data[1] => cpu_0_instruction_master_readdata~249.IN1 incoming_tri_state_bridge_0_data[1] => dbs_latent_8_reg_segment_0[1].DATAIN incoming_tri_state_bridge_0_data[1] => dbs_latent_8_reg_segment_1[1].DATAIN incoming_tri_state_bridge_0_data[1] => dbs_latent_8_reg_segment_2[1].DATAIN incoming_tri_state_bridge_0_data[2] => cpu_0_instruction_master_readdata~250.IN1 incoming_tri_state_bridge_0_data[2] => dbs_latent_8_reg_segment_0[2].DATAIN incoming_tri_state_bridge_0_data[2] => dbs_latent_8_reg_segment_1[2].DATAIN incoming_tri_state_bridge_0_data[2] => dbs_latent_8_reg_segment_2[2].DATAIN incoming_tri_state_bridge_0_data[3] => cpu_0_instruction_master_readdata~251.IN1 incoming_tri_state_bridge_0_data[3] => dbs_latent_8_reg_segment_0[3].DATAIN incoming_tri_state_bridge_0_data[3] => dbs_latent_8_reg_segment_1[3].DATAIN incoming_tri_state_bridge_0_data[3] => dbs_latent_8_reg_segment_2[3].DATAIN incoming_tri_state_bridge_0_data[4] => cpu_0_instruction_master_readdata~252.IN1 incoming_tri_state_bridge_0_data[4] => dbs_latent_8_reg_segment_0[4].DATAIN incoming_tri_state_bridge_0_data[4] => dbs_latent_8_reg_segment_1[4].DATAIN incoming_tri_state_bridge_0_data[4] => dbs_latent_8_reg_segment_2[4].DATAIN incoming_tri_state_bridge_0_data[5] => cpu_0_instruction_master_readdata~253.IN1 incoming_tri_state_bridge_0_data[5] => dbs_latent_8_reg_segment_0[5].DATAIN incoming_tri_state_bridge_0_data[5] => dbs_latent_8_reg_segment_1[5].DATAIN incoming_tri_state_bridge_0_data[5] => dbs_latent_8_reg_segment_2[5].DATAIN incoming_tri_state_bridge_0_data[6] => cpu_0_instruction_master_readdata~254.IN1 incoming_tri_state_bridge_0_data[6] => dbs_latent_8_reg_segment_0[6].DATAIN incoming_tri_state_bridge_0_data[6] => dbs_latent_8_reg_segment_1[6].DATAIN incoming_tri_state_bridge_0_data[6] => dbs_latent_8_reg_segment_2[6].DATAIN incoming_tri_state_bridge_0_data[7] => cpu_0_instruction_master_readdata~255.IN1 incoming_tri_state_bridge_0_data[7] => dbs_latent_8_reg_segment_0[7].DATAIN incoming_tri_state_bridge_0_data[7] => dbs_latent_8_reg_segment_1[7].DATAIN incoming_tri_state_bridge_0_data[7] => dbs_latent_8_reg_segment_2[7].DATAIN reset_n => dbs_latent_8_reg_segment_1[0].ACLR reset_n => dbs_latent_8_reg_segment_1[1].ACLR reset_n => dbs_latent_8_reg_segment_1[2].ACLR reset_n => dbs_latent_8_reg_segment_1[3].ACLR reset_n => dbs_latent_8_reg_segment_1[4].ACLR reset_n => dbs_latent_8_reg_segment_1[5].ACLR reset_n => dbs_latent_8_reg_segment_1[6].ACLR reset_n => dbs_latent_8_reg_segment_1[7].ACLR reset_n => dbs_latent_8_reg_segment_2[0].ACLR reset_n => dbs_latent_8_reg_segment_2[1].ACLR reset_n => dbs_latent_8_reg_segment_2[2].ACLR reset_n => dbs_latent_8_reg_segment_2[3].ACLR reset_n => dbs_latent_8_reg_segment_2[4].ACLR reset_n => dbs_latent_8_reg_segment_2[5].ACLR reset_n => dbs_latent_8_reg_segment_2[6].ACLR reset_n => dbs_latent_8_reg_segment_2[7].ACLR reset_n => dbs_latent_8_reg_segment_0[0].ACLR reset_n => dbs_latent_8_reg_segment_0[1].ACLR reset_n => dbs_latent_8_reg_segment_0[2].ACLR reset_n => dbs_latent_8_reg_segment_0[3].ACLR reset_n => dbs_latent_8_reg_segment_0[4].ACLR reset_n => dbs_latent_8_reg_segment_0[5].ACLR reset_n => dbs_latent_8_reg_segment_0[6].ACLR reset_n => dbs_latent_8_reg_segment_0[7].ACLR reset_n => dbs_16_reg_segment_0[0].ACLR reset_n => dbs_16_reg_segment_0[1].ACLR reset_n => dbs_16_reg_segment_0[2].ACLR reset_n => dbs_16_reg_segment_0[3].ACLR reset_n => dbs_16_reg_segment_0[4].ACLR reset_n => dbs_16_reg_segment_0[5].ACLR reset_n => dbs_16_reg_segment_0[6].ACLR reset_n => dbs_16_reg_segment_0[7].ACLR reset_n => dbs_16_reg_segment_0[8].ACLR reset_n => dbs_16_reg_segment_0[9].ACLR reset_n => dbs_16_reg_segment_0[10].ACLR reset_n => dbs_16_reg_segment_0[11].ACLR reset_n => dbs_16_reg_segment_0[12].ACLR reset_n => dbs_16_reg_segment_0[13].ACLR reset_n => dbs_16_reg_segment_0[14].ACLR reset_n => dbs_16_reg_segment_0[15].ACLR reset_n => cpu_0_instruction_master_dbs_rdv_counter[0].ACLR reset_n => cpu_0_instruction_master_dbs_rdv_counter[1].ACLR reset_n => cpu_0_instruction_master_dbs_address[0]~reg0.ACLR reset_n => cpu_0_instruction_master_dbs_address[1]~reg0.ACLR reset_n => cpu_0_instruction_master_latency_counter[1]~reg0.ACLR reset_n => cpu_0_instruction_master_latency_counter[0]~reg0.ACLR reset_n => cpu_0_instruction_master_read_but_no_slave_selected.ACLR reset_n => dbs_latent_16_reg_segment_0[15].ACLR reset_n => dbs_latent_16_reg_segment_0[14].ACLR reset_n => dbs_latent_16_reg_segment_0[13].ACLR reset_n => dbs_latent_16_reg_segment_0[12].ACLR reset_n => dbs_latent_16_reg_segment_0[11].ACLR reset_n => dbs_latent_16_reg_segment_0[10].ACLR reset_n => dbs_latent_16_reg_segment_0[9].ACLR reset_n => dbs_latent_16_reg_segment_0[8].ACLR reset_n => dbs_latent_16_reg_segment_0[7].ACLR reset_n => dbs_latent_16_reg_segment_0[6].ACLR reset_n => dbs_latent_16_reg_segment_0[5].ACLR reset_n => dbs_latent_16_reg_segment_0[4].ACLR reset_n => dbs_latent_16_reg_segment_0[3].ACLR reset_n => dbs_latent_16_reg_segment_0[2].ACLR reset_n => dbs_latent_16_reg_segment_0[1].ACLR reset_n => dbs_latent_16_reg_segment_0[0].ACLR sdram_0_s1_readdata_from_sa[0] => cpu_0_instruction_master_readdata~112.IN1 sdram_0_s1_readdata_from_sa[0] => dbs_latent_16_reg_segment_0[0].DATAIN sdram_0_s1_readdata_from_sa[1] => cpu_0_instruction_master_readdata~113.IN1 sdram_0_s1_readdata_from_sa[1] => dbs_latent_16_reg_segment_0[1].DATAIN sdram_0_s1_readdata_from_sa[2] => cpu_0_instruction_master_readdata~114.IN1 sdram_0_s1_readdata_from_sa[2] => dbs_latent_16_reg_segment_0[2].DATAIN sdram_0_s1_readdata_from_sa[3] => cpu_0_instruction_master_readdata~115.IN1 sdram_0_s1_readdata_from_sa[3] => dbs_latent_16_reg_segment_0[3].DATAIN sdram_0_s1_readdata_from_sa[4] => cpu_0_instruction_master_readdata~116.IN1 sdram_0_s1_readdata_from_sa[4] => dbs_latent_16_reg_segment_0[4].DATAIN sdram_0_s1_readdata_from_sa[5] => cpu_0_instruction_master_readdata~117.IN1 sdram_0_s1_readdata_from_sa[5] => dbs_latent_16_reg_segment_0[5].DATAIN sdram_0_s1_readdata_from_sa[6] => cpu_0_instruction_master_readdata~118.IN1 sdram_0_s1_readdata_from_sa[6] => dbs_latent_16_reg_segment_0[6].DATAIN sdram_0_s1_readdata_from_sa[7] => cpu_0_instruction_master_readdata~119.IN1 sdram_0_s1_readdata_from_sa[7] => dbs_latent_16_reg_segment_0[7].DATAIN sdram_0_s1_readdata_from_sa[8] => cpu_0_instruction_master_readdata~120.IN1 sdram_0_s1_readdata_from_sa[8] => dbs_latent_16_reg_segment_0[8].DATAIN sdram_0_s1_readdata_from_sa[9] => cpu_0_instruction_master_readdata~121.IN1 sdram_0_s1_readdata_from_sa[9] => dbs_latent_16_reg_segment_0[9].DATAIN sdram_0_s1_readdata_from_sa[10] => cpu_0_instruction_master_readdata~122.IN1 sdram_0_s1_readdata_from_sa[10] => dbs_latent_16_reg_segment_0[10].DATAIN sdram_0_s1_readdata_from_sa[11] => cpu_0_instruction_master_readdata~123.IN1 sdram_0_s1_readdata_from_sa[11] => dbs_latent_16_reg_segment_0[11].DATAIN sdram_0_s1_readdata_from_sa[12] => cpu_0_instruction_master_readdata~124.IN1 sdram_0_s1_readdata_from_sa[12] => dbs_latent_16_reg_segment_0[12].DATAIN sdram_0_s1_readdata_from_sa[13] => cpu_0_instruction_master_readdata~125.IN1 sdram_0_s1_readdata_from_sa[13] => dbs_latent_16_reg_segment_0[13].DATAIN sdram_0_s1_readdata_from_sa[14] => cpu_0_instruction_master_readdata~126.IN1 sdram_0_s1_readdata_from_sa[14] => dbs_latent_16_reg_segment_0[14].DATAIN sdram_0_s1_readdata_from_sa[15] => cpu_0_instruction_master_readdata~127.IN0 sdram_0_s1_readdata_from_sa[15] => dbs_latent_16_reg_segment_0[15].DATAIN sdram_0_s1_waitrequest_from_sa => r_1~20.IN1 sdram_0_s1_waitrequest_from_sa => pre_dbs_count_enable~1.IN0 sram_0_avalonS_readdata_from_sa[0] => cpu_0_instruction_master_readdata~176.IN1 sram_0_avalonS_readdata_from_sa[0] => dbs_16_reg_segment_0[0].DATAIN sram_0_avalonS_readdata_from_sa[1] => cpu_0_instruction_master_readdata~177.IN1 sram_0_avalonS_readdata_from_sa[1] => dbs_16_reg_segment_0[1].DATAIN sram_0_avalonS_readdata_from_sa[2] => cpu_0_instruction_master_readdata~178.IN1 sram_0_avalonS_readdata_from_sa[2] => dbs_16_reg_segment_0[2].DATAIN sram_0_avalonS_readdata_from_sa[3] => cpu_0_instruction_master_readdata~179.IN1 sram_0_avalonS_readdata_from_sa[3] => dbs_16_reg_segment_0[3].DATAIN sram_0_avalonS_readdata_from_sa[4] => cpu_0_instruction_master_readdata~180.IN1 sram_0_avalonS_readdata_from_sa[4] => dbs_16_reg_segment_0[4].DATAIN sram_0_avalonS_readdata_from_sa[5] => cpu_0_instruction_master_readdata~181.IN1 sram_0_avalonS_readdata_from_sa[5] => dbs_16_reg_segment_0[5].DATAIN sram_0_avalonS_readdata_from_sa[6] => cpu_0_instruction_master_readdata~182.IN1 sram_0_avalonS_readdata_from_sa[6] => dbs_16_reg_segment_0[6].DATAIN sram_0_avalonS_readdata_from_sa[7] => cpu_0_instruction_master_readdata~183.IN1 sram_0_avalonS_readdata_from_sa[7] => dbs_16_reg_segment_0[7].DATAIN sram_0_avalonS_readdata_from_sa[8] => cpu_0_instruction_master_readdata~184.IN1 sram_0_avalonS_readdata_from_sa[8] => dbs_16_reg_segment_0[8].DATAIN sram_0_avalonS_readdata_from_sa[9] => cpu_0_instruction_master_readdata~185.IN1 sram_0_avalonS_readdata_from_sa[9] => dbs_16_reg_segment_0[9].DATAIN sram_0_avalonS_readdata_from_sa[10] => cpu_0_instruction_master_readdata~186.IN1 sram_0_avalonS_readdata_from_sa[10] => dbs_16_reg_segment_0[10].DATAIN sram_0_avalonS_readdata_from_sa[11] => cpu_0_instruction_master_readdata~187.IN1 sram_0_avalonS_readdata_from_sa[11] => dbs_16_reg_segment_0[11].DATAIN sram_0_avalonS_readdata_from_sa[12] => cpu_0_instruction_master_readdata~188.IN1 sram_0_avalonS_readdata_from_sa[12] => dbs_16_reg_segment_0[12].DATAIN sram_0_avalonS_readdata_from_sa[13] => cpu_0_instruction_master_readdata~189.IN1 sram_0_avalonS_readdata_from_sa[13] => dbs_16_reg_segment_0[13].DATAIN sram_0_avalonS_readdata_from_sa[14] => cpu_0_instruction_master_readdata~190.IN1 sram_0_avalonS_readdata_from_sa[14] => dbs_16_reg_segment_0[14].DATAIN sram_0_avalonS_readdata_from_sa[15] => cpu_0_instruction_master_readdata~191.IN1 sram_0_avalonS_readdata_from_sa[15] => dbs_16_reg_segment_0[15].DATAIN sram_0_avalonS_wait_counter_eq_0 => pre_dbs_count_enable~3.IN1 sram_0_avalonS_wait_counter_eq_1 => ~NO_FANOUT~ cpu_0_instruction_master_address_to_slave[0] <= cpu_0_instruction_master_address[0].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[1] <= cpu_0_instruction_master_address[1].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[2] <= cpu_0_instruction_master_address[2].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[3] <= cpu_0_instruction_master_address[3].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[4] <= cpu_0_instruction_master_address[4].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[5] <= cpu_0_instruction_master_address[5].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[6] <= cpu_0_instruction_master_address[6].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[7] <= cpu_0_instruction_master_address[7].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[8] <= cpu_0_instruction_master_address[8].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[9] <= cpu_0_instruction_master_address[9].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[10] <= cpu_0_instruction_master_address[10].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[11] <= cpu_0_instruction_master_address[11].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[12] <= cpu_0_instruction_master_address[12].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[13] <= cpu_0_instruction_master_address[13].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[14] <= cpu_0_instruction_master_address[14].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[15] <= cpu_0_instruction_master_address[15].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[16] <= cpu_0_instruction_master_address[16].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[17] <= cpu_0_instruction_master_address[17].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[18] <= cpu_0_instruction_master_address[18].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[19] <= cpu_0_instruction_master_address[19].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[20] <= cpu_0_instruction_master_address[20].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[21] <= cpu_0_instruction_master_address[21].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[22] <= cpu_0_instruction_master_address[22].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_address_to_slave[23] <= cpu_0_instruction_master_address[23].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_dbs_address[0] <= cpu_0_instruction_master_dbs_address[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_dbs_address[1] <= cpu_0_instruction_master_dbs_address[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_latency_counter[0] <= cpu_0_instruction_master_latency_counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_latency_counter[1] <= cpu_0_instruction_master_latency_counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[0] <= cpu_0_instruction_master_readdata~256.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[1] <= cpu_0_instruction_master_readdata~257.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[2] <= cpu_0_instruction_master_readdata~258.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[3] <= cpu_0_instruction_master_readdata~259.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[4] <= cpu_0_instruction_master_readdata~260.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[5] <= cpu_0_instruction_master_readdata~261.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[6] <= cpu_0_instruction_master_readdata~262.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[7] <= cpu_0_instruction_master_readdata~263.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[8] <= cpu_0_instruction_master_readdata~264.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[9] <= cpu_0_instruction_master_readdata~265.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[10] <= cpu_0_instruction_master_readdata~266.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[11] <= cpu_0_instruction_master_readdata~267.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[12] <= cpu_0_instruction_master_readdata~268.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[13] <= cpu_0_instruction_master_readdata~269.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[14] <= cpu_0_instruction_master_readdata~270.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[15] <= cpu_0_instruction_master_readdata~271.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[16] <= cpu_0_instruction_master_readdata~272.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[17] <= cpu_0_instruction_master_readdata~273.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[18] <= cpu_0_instruction_master_readdata~274.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[19] <= cpu_0_instruction_master_readdata~275.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[20] <= cpu_0_instruction_master_readdata~276.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[21] <= cpu_0_instruction_master_readdata~277.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[22] <= cpu_0_instruction_master_readdata~278.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[23] <= cpu_0_instruction_master_readdata~279.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[24] <= cpu_0_instruction_master_readdata~280.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[25] <= cpu_0_instruction_master_readdata~281.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[26] <= cpu_0_instruction_master_readdata~282.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[27] <= cpu_0_instruction_master_readdata~283.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[28] <= cpu_0_instruction_master_readdata~284.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[29] <= cpu_0_instruction_master_readdata~285.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[30] <= cpu_0_instruction_master_readdata~286.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdata[31] <= cpu_0_instruction_master_readdata~287.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_readdatavalid <= cpu_0_instruction_master_readdatavalid~12.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_waitrequest <= cpu_0_instruction_master_run.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0 clk => clk~0.IN16 d_irq[0] => A_ipending_reg_nxt~0.IN1 d_irq[1] => A_ipending_reg_nxt~1.IN1 d_irq[2] => A_ipending_reg_nxt~2.IN1 d_irq[3] => A_ipending_reg_nxt~3.IN1 d_irq[4] => ~NO_FANOUT~ d_irq[5] => ~NO_FANOUT~ d_irq[6] => ~NO_FANOUT~ d_irq[7] => ~NO_FANOUT~ d_irq[8] => ~NO_FANOUT~ d_irq[9] => ~NO_FANOUT~ d_irq[10] => ~NO_FANOUT~ d_irq[11] => ~NO_FANOUT~ d_irq[12] => ~NO_FANOUT~ d_irq[13] => ~NO_FANOUT~ d_irq[14] => ~NO_FANOUT~ d_irq[15] => ~NO_FANOUT~ d_irq[16] => ~NO_FANOUT~ d_irq[17] => ~NO_FANOUT~ d_irq[18] => ~NO_FANOUT~ d_irq[19] => ~NO_FANOUT~ d_irq[20] => ~NO_FANOUT~ d_irq[21] => ~NO_FANOUT~ d_irq[22] => ~NO_FANOUT~ d_irq[23] => ~NO_FANOUT~ d_irq[24] => ~NO_FANOUT~ d_irq[25] => ~NO_FANOUT~ d_irq[26] => ~NO_FANOUT~ d_irq[27] => ~NO_FANOUT~ d_irq[28] => ~NO_FANOUT~ d_irq[29] => ~NO_FANOUT~ d_irq[30] => ~NO_FANOUT~ d_irq[31] => ~NO_FANOUT~ d_readdata[0] => d_readdata_d1[0].DATAIN d_readdata[1] => d_readdata_d1[1].DATAIN d_readdata[2] => d_readdata_d1[2].DATAIN d_readdata[3] => d_readdata_d1[3].DATAIN d_readdata[4] => d_readdata_d1[4].DATAIN d_readdata[5] => d_readdata_d1[5].DATAIN d_readdata[6] => d_readdata_d1[6].DATAIN d_readdata[7] => d_readdata_d1[7].DATAIN d_readdata[8] => d_readdata_d1[8].DATAIN d_readdata[9] => d_readdata_d1[9].DATAIN d_readdata[10] => d_readdata_d1[10].DATAIN d_readdata[11] => d_readdata_d1[11].DATAIN d_readdata[12] => d_readdata_d1[12].DATAIN d_readdata[13] => d_readdata_d1[13].DATAIN d_readdata[14] => d_readdata_d1[14].DATAIN d_readdata[15] => d_readdata_d1[15].DATAIN d_readdata[16] => d_readdata_d1[16].DATAIN d_readdata[17] => d_readdata_d1[17].DATAIN d_readdata[18] => d_readdata_d1[18].DATAIN d_readdata[19] => d_readdata_d1[19].DATAIN d_readdata[20] => d_readdata_d1[20].DATAIN d_readdata[21] => d_readdata_d1[21].DATAIN d_readdata[22] => d_readdata_d1[22].DATAIN d_readdata[23] => d_readdata_d1[23].DATAIN d_readdata[24] => d_readdata_d1[24].DATAIN d_readdata[25] => d_readdata_d1[25].DATAIN d_readdata[26] => d_readdata_d1[26].DATAIN d_readdata[27] => d_readdata_d1[27].DATAIN d_readdata[28] => d_readdata_d1[28].DATAIN d_readdata[29] => d_readdata_d1[29].DATAIN d_readdata[30] => d_readdata_d1[30].DATAIN d_readdata[31] => d_readdata_d1[31].DATAIN d_waitrequest => d_read_nxt~0.IN1 d_waitrequest => A_wr_stall.IN0 d_waitrequest => av_rd_data_transfer.IN1 d_waitrequest => av_wr_data_transfer.IN1 i_readdata[0] => i_readdata_d1[0].DATAIN i_readdata[1] => i_readdata_d1[1].DATAIN i_readdata[2] => i_readdata_d1[2].DATAIN i_readdata[3] => i_readdata_d1[3].DATAIN i_readdata[4] => i_readdata_d1[4].DATAIN i_readdata[5] => i_readdata_d1[5].DATAIN i_readdata[6] => i_readdata_d1[6].DATAIN i_readdata[7] => i_readdata_d1[7].DATAIN i_readdata[8] => i_readdata_d1[8].DATAIN i_readdata[9] => i_readdata_d1[9].DATAIN i_readdata[10] => i_readdata_d1[10].DATAIN i_readdata[11] => i_readdata_d1[11].DATAIN i_readdata[12] => i_readdata_d1[12].DATAIN i_readdata[13] => i_readdata_d1[13].DATAIN i_readdata[14] => i_readdata_d1[14].DATAIN i_readdata[15] => i_readdata_d1[15].DATAIN i_readdata[16] => i_readdata_d1[16].DATAIN i_readdata[17] => i_readdata_d1[17].DATAIN i_readdata[18] => i_readdata_d1[18].DATAIN i_readdata[19] => i_readdata_d1[19].DATAIN i_readdata[20] => i_readdata_d1[20].DATAIN i_readdata[21] => i_readdata_d1[21].DATAIN i_readdata[22] => i_readdata_d1[22].DATAIN i_readdata[23] => i_readdata_d1[23].DATAIN i_readdata[24] => i_readdata_d1[24].DATAIN i_readdata[25] => i_readdata_d1[25].DATAIN i_readdata[26] => i_readdata_d1[26].DATAIN i_readdata[27] => i_readdata_d1[27].DATAIN i_readdata[28] => i_readdata_d1[28].DATAIN i_readdata[29] => i_readdata_d1[29].DATAIN i_readdata[30] => i_readdata_d1[30].DATAIN i_readdata[31] => i_readdata_d1[31].DATAIN i_readdatavalid => i_readdatavalid~0.IN1 i_waitrequest => i_read_nxt~0.IN1 i_waitrequest => ic_fill_req_accepted.IN1 jtag_debug_module_address[0] => jtag_debug_module_address[0]~8.IN1 jtag_debug_module_address[1] => jtag_debug_module_address[1]~7.IN1 jtag_debug_module_address[2] => jtag_debug_module_address[2]~6.IN1 jtag_debug_module_address[3] => jtag_debug_module_address[3]~5.IN1 jtag_debug_module_address[4] => jtag_debug_module_address[4]~4.IN1 jtag_debug_module_address[5] => jtag_debug_module_address[5]~3.IN1 jtag_debug_module_address[6] => jtag_debug_module_address[6]~2.IN1 jtag_debug_module_address[7] => jtag_debug_module_address[7]~1.IN1 jtag_debug_module_address[8] => jtag_debug_module_address[8]~0.IN1 jtag_debug_module_begintransfer => jtag_debug_module_begintransfer~0.IN1 jtag_debug_module_byteenable[0] => jtag_debug_module_byteenable[0]~3.IN1 jtag_debug_module_byteenable[1] => jtag_debug_module_byteenable[1]~2.IN1 jtag_debug_module_byteenable[2] => jtag_debug_module_byteenable[2]~1.IN1 jtag_debug_module_byteenable[3] => jtag_debug_module_byteenable[3]~0.IN1 jtag_debug_module_clk => jtag_debug_module_clk~0.IN1 jtag_debug_module_debugaccess => jtag_debug_module_debugaccess~0.IN1 jtag_debug_module_reset => jtag_debug_module_reset~0.IN1 jtag_debug_module_select => jtag_debug_module_select~0.IN1 jtag_debug_module_write => jtag_debug_module_write~0.IN1 jtag_debug_module_writedata[0] => jtag_debug_module_writedata[0]~31.IN1 jtag_debug_module_writedata[1] => jtag_debug_module_writedata[1]~30.IN1 jtag_debug_module_writedata[2] => jtag_debug_module_writedata[2]~29.IN1 jtag_debug_module_writedata[3] => jtag_debug_module_writedata[3]~28.IN1 jtag_debug_module_writedata[4] => jtag_debug_module_writedata[4]~27.IN1 jtag_debug_module_writedata[5] => jtag_debug_module_writedata[5]~26.IN1 jtag_debug_module_writedata[6] => jtag_debug_module_writedata[6]~25.IN1 jtag_debug_module_writedata[7] => jtag_debug_module_writedata[7]~24.IN1 jtag_debug_module_writedata[8] => jtag_debug_module_writedata[8]~23.IN1 jtag_debug_module_writedata[9] => jtag_debug_module_writedata[9]~22.IN1 jtag_debug_module_writedata[10] => jtag_debug_module_writedata[10]~21.IN1 jtag_debug_module_writedata[11] => jtag_debug_module_writedata[11]~20.IN1 jtag_debug_module_writedata[12] => jtag_debug_module_writedata[12]~19.IN1 jtag_debug_module_writedata[13] => jtag_debug_module_writedata[13]~18.IN1 jtag_debug_module_writedata[14] => jtag_debug_module_writedata[14]~17.IN1 jtag_debug_module_writedata[15] => jtag_debug_module_writedata[15]~16.IN1 jtag_debug_module_writedata[16] => jtag_debug_module_writedata[16]~15.IN1 jtag_debug_module_writedata[17] => jtag_debug_module_writedata[17]~14.IN1 jtag_debug_module_writedata[18] => jtag_debug_module_writedata[18]~13.IN1 jtag_debug_module_writedata[19] => jtag_debug_module_writedata[19]~12.IN1 jtag_debug_module_writedata[20] => jtag_debug_module_writedata[20]~11.IN1 jtag_debug_module_writedata[21] => jtag_debug_module_writedata[21]~10.IN1 jtag_debug_module_writedata[22] => jtag_debug_module_writedata[22]~9.IN1 jtag_debug_module_writedata[23] => jtag_debug_module_writedata[23]~8.IN1 jtag_debug_module_writedata[24] => jtag_debug_module_writedata[24]~7.IN1 jtag_debug_module_writedata[25] => jtag_debug_module_writedata[25]~6.IN1 jtag_debug_module_writedata[26] => jtag_debug_module_writedata[26]~5.IN1 jtag_debug_module_writedata[27] => jtag_debug_module_writedata[27]~4.IN1 jtag_debug_module_writedata[28] => jtag_debug_module_writedata[28]~3.IN1 jtag_debug_module_writedata[29] => jtag_debug_module_writedata[29]~2.IN1 jtag_debug_module_writedata[30] => jtag_debug_module_writedata[30]~1.IN1 jtag_debug_module_writedata[31] => jtag_debug_module_writedata[31]~0.IN1 reset_n => reset_n~0.IN3 d_address[0] <= d_address[0]~23.DB_MAX_OUTPUT_PORT_TYPE d_address[1] <= d_address[1]~22.DB_MAX_OUTPUT_PORT_TYPE d_address[2] <= d_address[2]~21.DB_MAX_OUTPUT_PORT_TYPE d_address[3] <= d_address[3]~20.DB_MAX_OUTPUT_PORT_TYPE d_address[4] <= d_address[4]~19.DB_MAX_OUTPUT_PORT_TYPE d_address[5] <= d_address[5]~18.DB_MAX_OUTPUT_PORT_TYPE d_address[6] <= d_address[6]~17.DB_MAX_OUTPUT_PORT_TYPE d_address[7] <= d_address[7]~16.DB_MAX_OUTPUT_PORT_TYPE d_address[8] <= d_address[8]~15.DB_MAX_OUTPUT_PORT_TYPE d_address[9] <= d_address[9]~14.DB_MAX_OUTPUT_PORT_TYPE d_address[10] <= d_address[10]~13.DB_MAX_OUTPUT_PORT_TYPE d_address[11] <= d_address[11]~12.DB_MAX_OUTPUT_PORT_TYPE d_address[12] <= d_address[12]~11.DB_MAX_OUTPUT_PORT_TYPE d_address[13] <= d_address[13]~10.DB_MAX_OUTPUT_PORT_TYPE d_address[14] <= d_address[14]~9.DB_MAX_OUTPUT_PORT_TYPE d_address[15] <= d_address[15]~8.DB_MAX_OUTPUT_PORT_TYPE d_address[16] <= d_address[16]~7.DB_MAX_OUTPUT_PORT_TYPE d_address[17] <= d_address[17]~6.DB_MAX_OUTPUT_PORT_TYPE d_address[18] <= d_address[18]~5.DB_MAX_OUTPUT_PORT_TYPE d_address[19] <= d_address[19]~4.DB_MAX_OUTPUT_PORT_TYPE d_address[20] <= d_address[20]~3.DB_MAX_OUTPUT_PORT_TYPE d_address[21] <= d_address[21]~2.DB_MAX_OUTPUT_PORT_TYPE d_address[22] <= d_address[22]~1.DB_MAX_OUTPUT_PORT_TYPE d_address[23] <= d_address[23]~0.DB_MAX_OUTPUT_PORT_TYPE d_byteenable[0] <= d_byteenable[0]~3.DB_MAX_OUTPUT_PORT_TYPE d_byteenable[1] <= d_byteenable[1]~2.DB_MAX_OUTPUT_PORT_TYPE d_byteenable[2] <= d_byteenable[2]~1.DB_MAX_OUTPUT_PORT_TYPE d_byteenable[3] <= d_byteenable[3]~0.DB_MAX_OUTPUT_PORT_TYPE d_read <= d_read~0.DB_MAX_OUTPUT_PORT_TYPE d_write <= d_write~0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[0] <= d_writedata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[1] <= d_writedata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[2] <= d_writedata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[3] <= d_writedata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[4] <= d_writedata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[5] <= d_writedata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[6] <= d_writedata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[7] <= d_writedata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[8] <= d_writedata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[9] <= d_writedata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[10] <= d_writedata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[11] <= d_writedata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[12] <= d_writedata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[13] <= d_writedata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[14] <= d_writedata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[15] <= d_writedata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[16] <= d_writedata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[17] <= d_writedata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[18] <= d_writedata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[19] <= d_writedata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[20] <= d_writedata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[21] <= d_writedata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[22] <= d_writedata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[23] <= d_writedata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[24] <= d_writedata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[25] <= d_writedata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[26] <= d_writedata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[27] <= d_writedata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[28] <= d_writedata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[29] <= d_writedata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[30] <= d_writedata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE d_writedata[31] <= d_writedata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE i_address[0] <= i_address[0]~1.DB_MAX_OUTPUT_PORT_TYPE i_address[1] <= i_address[1]~0.DB_MAX_OUTPUT_PORT_TYPE i_address[2] <= i_address[2]~4.DB_MAX_OUTPUT_PORT_TYPE i_address[3] <= i_address[3]~3.DB_MAX_OUTPUT_PORT_TYPE i_address[4] <= i_address[4]~2.DB_MAX_OUTPUT_PORT_TYPE i_address[5] <= ic_fill_line[0]~6.DB_MAX_OUTPUT_PORT_TYPE i_address[6] <= ic_fill_line[1]~5.DB_MAX_OUTPUT_PORT_TYPE i_address[7] <= ic_fill_line[2]~4.DB_MAX_OUTPUT_PORT_TYPE i_address[8] <= ic_fill_line[3]~3.DB_MAX_OUTPUT_PORT_TYPE i_address[9] <= ic_fill_line[4]~2.DB_MAX_OUTPUT_PORT_TYPE i_address[10] <= ic_fill_line[5]~1.DB_MAX_OUTPUT_PORT_TYPE i_address[11] <= ic_fill_line[6]~0.DB_MAX_OUTPUT_PORT_TYPE i_address[12] <= i_address[12]~16.DB_MAX_OUTPUT_PORT_TYPE i_address[13] <= i_address[13]~15.DB_MAX_OUTPUT_PORT_TYPE i_address[14] <= i_address[14]~14.DB_MAX_OUTPUT_PORT_TYPE i_address[15] <= i_address[15]~13.DB_MAX_OUTPUT_PORT_TYPE i_address[16] <= i_address[16]~12.DB_MAX_OUTPUT_PORT_TYPE i_address[17] <= i_address[17]~11.DB_MAX_OUTPUT_PORT_TYPE i_address[18] <= i_address[18]~10.DB_MAX_OUTPUT_PORT_TYPE i_address[19] <= i_address[19]~9.DB_MAX_OUTPUT_PORT_TYPE i_address[20] <= i_address[20]~8.DB_MAX_OUTPUT_PORT_TYPE i_address[21] <= i_address[21]~7.DB_MAX_OUTPUT_PORT_TYPE i_address[22] <= i_address[22]~6.DB_MAX_OUTPUT_PORT_TYPE i_address[23] <= i_address[23]~5.DB_MAX_OUTPUT_PORT_TYPE i_read <= i_read~0.DB_MAX_OUTPUT_PORT_TYPE jtag_debug_module_debugaccess_to_roms <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.jtag_debug_module_debugaccess_to_roms jtag_debug_module_readdata[0] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[1] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[2] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[3] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[4] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[5] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[6] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[7] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[8] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[9] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[10] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[11] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[12] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[13] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[14] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[15] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[16] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[17] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[18] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[19] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[20] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[21] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[22] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[23] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[24] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[25] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[26] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[27] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[28] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[29] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[30] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_readdata[31] <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.readdata jtag_debug_module_resetrequest <= cpu_0_nios2_oci:the_cpu_0_nios2_oci.resetrequest |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench A_bstatus_reg => ~NO_FANOUT~ A_cmp_result => ~NO_FANOUT~ A_ctrl_ld_non_bypass => ~NO_FANOUT~ A_dst_regnum[0] => ~NO_FANOUT~ A_dst_regnum[1] => ~NO_FANOUT~ A_dst_regnum[2] => ~NO_FANOUT~ A_dst_regnum[3] => ~NO_FANOUT~ A_dst_regnum[4] => ~NO_FANOUT~ A_en => ~NO_FANOUT~ A_estatus_reg => ~NO_FANOUT~ A_ienable_reg[0] => ~NO_FANOUT~ A_ienable_reg[1] => ~NO_FANOUT~ A_ienable_reg[2] => ~NO_FANOUT~ A_ienable_reg[3] => ~NO_FANOUT~ A_ienable_reg[4] => ~NO_FANOUT~ A_ienable_reg[5] => ~NO_FANOUT~ A_ienable_reg[6] => ~NO_FANOUT~ A_ienable_reg[7] => ~NO_FANOUT~ A_ienable_reg[8] => ~NO_FANOUT~ A_ienable_reg[9] => ~NO_FANOUT~ A_ienable_reg[10] => ~NO_FANOUT~ A_ienable_reg[11] => ~NO_FANOUT~ A_ienable_reg[12] => ~NO_FANOUT~ A_ienable_reg[13] => ~NO_FANOUT~ A_ienable_reg[14] => ~NO_FANOUT~ A_ienable_reg[15] => ~NO_FANOUT~ A_ienable_reg[16] => ~NO_FANOUT~ A_ienable_reg[17] => ~NO_FANOUT~ A_ienable_reg[18] => ~NO_FANOUT~ A_ienable_reg[19] => ~NO_FANOUT~ A_ienable_reg[20] => ~NO_FANOUT~ A_ienable_reg[21] => ~NO_FANOUT~ A_ienable_reg[22] => ~NO_FANOUT~ A_ienable_reg[23] => ~NO_FANOUT~ A_ienable_reg[24] => ~NO_FANOUT~ A_ienable_reg[25] => ~NO_FANOUT~ A_ienable_reg[26] => ~NO_FANOUT~ A_ienable_reg[27] => ~NO_FANOUT~ A_ienable_reg[28] => ~NO_FANOUT~ A_ienable_reg[29] => ~NO_FANOUT~ A_ienable_reg[30] => ~NO_FANOUT~ A_ienable_reg[31] => ~NO_FANOUT~ A_ipending_reg[0] => ~NO_FANOUT~ A_ipending_reg[1] => ~NO_FANOUT~ A_ipending_reg[2] => ~NO_FANOUT~ A_ipending_reg[3] => ~NO_FANOUT~ A_ipending_reg[4] => ~NO_FANOUT~ A_ipending_reg[5] => ~NO_FANOUT~ A_ipending_reg[6] => ~NO_FANOUT~ A_ipending_reg[7] => ~NO_FANOUT~ A_ipending_reg[8] => ~NO_FANOUT~ A_ipending_reg[9] => ~NO_FANOUT~ A_ipending_reg[10] => ~NO_FANOUT~ A_ipending_reg[11] => ~NO_FANOUT~ A_ipending_reg[12] => ~NO_FANOUT~ A_ipending_reg[13] => ~NO_FANOUT~ A_ipending_reg[14] => ~NO_FANOUT~ A_ipending_reg[15] => ~NO_FANOUT~ A_ipending_reg[16] => ~NO_FANOUT~ A_ipending_reg[17] => ~NO_FANOUT~ A_ipending_reg[18] => ~NO_FANOUT~ A_ipending_reg[19] => ~NO_FANOUT~ A_ipending_reg[20] => ~NO_FANOUT~ A_ipending_reg[21] => ~NO_FANOUT~ A_ipending_reg[22] => ~NO_FANOUT~ A_ipending_reg[23] => ~NO_FANOUT~ A_ipending_reg[24] => ~NO_FANOUT~ A_ipending_reg[25] => ~NO_FANOUT~ A_ipending_reg[26] => ~NO_FANOUT~ A_ipending_reg[27] => ~NO_FANOUT~ A_ipending_reg[28] => ~NO_FANOUT~ A_ipending_reg[29] => ~NO_FANOUT~ A_ipending_reg[30] => ~NO_FANOUT~ A_ipending_reg[31] => ~NO_FANOUT~ A_iw[0] => ~NO_FANOUT~ A_iw[1] => ~NO_FANOUT~ A_iw[2] => ~NO_FANOUT~ A_iw[3] => ~NO_FANOUT~ A_iw[4] => ~NO_FANOUT~ A_iw[5] => ~NO_FANOUT~ A_iw[6] => ~NO_FANOUT~ A_iw[7] => ~NO_FANOUT~ A_iw[8] => ~NO_FANOUT~ A_iw[9] => ~NO_FANOUT~ A_iw[10] => ~NO_FANOUT~ A_iw[11] => ~NO_FANOUT~ A_iw[12] => ~NO_FANOUT~ A_iw[13] => ~NO_FANOUT~ A_iw[14] => ~NO_FANOUT~ A_iw[15] => ~NO_FANOUT~ A_iw[16] => ~NO_FANOUT~ A_iw[17] => ~NO_FANOUT~ A_iw[18] => ~NO_FANOUT~ A_iw[19] => ~NO_FANOUT~ A_iw[20] => ~NO_FANOUT~ A_iw[21] => ~NO_FANOUT~ A_iw[22] => ~NO_FANOUT~ A_iw[23] => ~NO_FANOUT~ A_iw[24] => ~NO_FANOUT~ A_iw[25] => ~NO_FANOUT~ A_iw[26] => ~NO_FANOUT~ A_iw[27] => ~NO_FANOUT~ A_iw[28] => ~NO_FANOUT~ A_iw[29] => ~NO_FANOUT~ A_iw[30] => ~NO_FANOUT~ A_iw[31] => ~NO_FANOUT~ A_mem_byte_en[0] => ~NO_FANOUT~ A_mem_byte_en[1] => ~NO_FANOUT~ A_mem_byte_en[2] => ~NO_FANOUT~ A_mem_byte_en[3] => ~NO_FANOUT~ A_op_hbreak => ~NO_FANOUT~ A_op_intr => ~NO_FANOUT~ A_pcb[0] => ~NO_FANOUT~ A_pcb[1] => ~NO_FANOUT~ A_pcb[2] => ~NO_FANOUT~ A_pcb[3] => ~NO_FANOUT~ A_pcb[4] => ~NO_FANOUT~ A_pcb[5] => ~NO_FANOUT~ A_pcb[6] => ~NO_FANOUT~ A_pcb[7] => ~NO_FANOUT~ A_pcb[8] => ~NO_FANOUT~ A_pcb[9] => ~NO_FANOUT~ A_pcb[10] => ~NO_FANOUT~ A_pcb[11] => ~NO_FANOUT~ A_pcb[12] => ~NO_FANOUT~ A_pcb[13] => ~NO_FANOUT~ A_pcb[14] => ~NO_FANOUT~ A_pcb[15] => ~NO_FANOUT~ A_pcb[16] => ~NO_FANOUT~ A_pcb[17] => ~NO_FANOUT~ A_pcb[18] => ~NO_FANOUT~ A_pcb[19] => ~NO_FANOUT~ A_pcb[20] => ~NO_FANOUT~ A_pcb[21] => ~NO_FANOUT~ A_pcb[22] => ~NO_FANOUT~ A_pcb[23] => ~NO_FANOUT~ A_st_data[0] => ~NO_FANOUT~ A_st_data[1] => ~NO_FANOUT~ A_st_data[2] => ~NO_FANOUT~ A_st_data[3] => ~NO_FANOUT~ A_st_data[4] => ~NO_FANOUT~ A_st_data[5] => ~NO_FANOUT~ A_st_data[6] => ~NO_FANOUT~ A_st_data[7] => ~NO_FANOUT~ A_st_data[8] => ~NO_FANOUT~ A_st_data[9] => ~NO_FANOUT~ A_st_data[10] => ~NO_FANOUT~ A_st_data[11] => ~NO_FANOUT~ A_st_data[12] => ~NO_FANOUT~ A_st_data[13] => ~NO_FANOUT~ A_st_data[14] => ~NO_FANOUT~ A_st_data[15] => ~NO_FANOUT~ A_st_data[16] => ~NO_FANOUT~ A_st_data[17] => ~NO_FANOUT~ A_st_data[18] => ~NO_FANOUT~ A_st_data[19] => ~NO_FANOUT~ A_st_data[20] => ~NO_FANOUT~ A_st_data[21] => ~NO_FANOUT~ A_st_data[22] => ~NO_FANOUT~ A_st_data[23] => ~NO_FANOUT~ A_st_data[24] => ~NO_FANOUT~ A_st_data[25] => ~NO_FANOUT~ A_st_data[26] => ~NO_FANOUT~ A_st_data[27] => ~NO_FANOUT~ A_st_data[28] => ~NO_FANOUT~ A_st_data[29] => ~NO_FANOUT~ A_st_data[30] => ~NO_FANOUT~ A_st_data[31] => ~NO_FANOUT~ A_status_reg => ~NO_FANOUT~ A_valid => ~NO_FANOUT~ A_wr_data_unfiltered[0] => A_wr_data_filtered[0].DATAIN A_wr_data_unfiltered[1] => A_wr_data_filtered[1].DATAIN A_wr_data_unfiltered[2] => A_wr_data_filtered[2].DATAIN A_wr_data_unfiltered[3] => A_wr_data_filtered[3].DATAIN A_wr_data_unfiltered[4] => A_wr_data_filtered[4].DATAIN A_wr_data_unfiltered[5] => A_wr_data_filtered[5].DATAIN A_wr_data_unfiltered[6] => A_wr_data_filtered[6].DATAIN A_wr_data_unfiltered[7] => A_wr_data_filtered[7].DATAIN A_wr_data_unfiltered[8] => A_wr_data_filtered[8].DATAIN A_wr_data_unfiltered[9] => A_wr_data_filtered[9].DATAIN A_wr_data_unfiltered[10] => A_wr_data_filtered[10].DATAIN A_wr_data_unfiltered[11] => A_wr_data_filtered[11].DATAIN A_wr_data_unfiltered[12] => A_wr_data_filtered[12].DATAIN A_wr_data_unfiltered[13] => A_wr_data_filtered[13].DATAIN A_wr_data_unfiltered[14] => A_wr_data_filtered[14].DATAIN A_wr_data_unfiltered[15] => A_wr_data_filtered[15].DATAIN A_wr_data_unfiltered[16] => A_wr_data_filtered[16].DATAIN A_wr_data_unfiltered[17] => A_wr_data_filtered[17].DATAIN A_wr_data_unfiltered[18] => A_wr_data_filtered[18].DATAIN A_wr_data_unfiltered[19] => A_wr_data_filtered[19].DATAIN A_wr_data_unfiltered[20] => A_wr_data_filtered[20].DATAIN A_wr_data_unfiltered[21] => A_wr_data_filtered[21].DATAIN A_wr_data_unfiltered[22] => A_wr_data_filtered[22].DATAIN A_wr_data_unfiltered[23] => A_wr_data_filtered[23].DATAIN A_wr_data_unfiltered[24] => A_wr_data_filtered[24].DATAIN A_wr_data_unfiltered[25] => A_wr_data_filtered[25].DATAIN A_wr_data_unfiltered[26] => A_wr_data_filtered[26].DATAIN A_wr_data_unfiltered[27] => A_wr_data_filtered[27].DATAIN A_wr_data_unfiltered[28] => A_wr_data_filtered[28].DATAIN A_wr_data_unfiltered[29] => A_wr_data_filtered[29].DATAIN A_wr_data_unfiltered[30] => A_wr_data_filtered[30].DATAIN A_wr_data_unfiltered[31] => A_wr_data_filtered[31].DATAIN A_wr_dst_reg => ~NO_FANOUT~ E_logic_result[0] => Equal0.IN0 E_logic_result[1] => Equal0.IN1 E_logic_result[2] => Equal0.IN2 E_logic_result[3] => Equal0.IN3 E_logic_result[4] => Equal0.IN4 E_logic_result[5] => Equal0.IN5 E_logic_result[6] => Equal0.IN6 E_logic_result[7] => Equal0.IN7 E_logic_result[8] => Equal0.IN8 E_logic_result[9] => Equal0.IN9 E_logic_result[10] => Equal0.IN10 E_logic_result[11] => Equal0.IN11 E_logic_result[12] => Equal0.IN12 E_logic_result[13] => Equal0.IN13 E_logic_result[14] => Equal0.IN14 E_logic_result[15] => Equal0.IN15 E_logic_result[16] => Equal0.IN16 E_logic_result[17] => Equal0.IN17 E_logic_result[18] => Equal0.IN18 E_logic_result[19] => Equal0.IN19 E_logic_result[20] => Equal0.IN20 E_logic_result[21] => Equal0.IN21 E_logic_result[22] => Equal0.IN22 E_logic_result[23] => Equal0.IN23 E_logic_result[24] => Equal0.IN24 E_logic_result[25] => Equal0.IN25 E_logic_result[26] => Equal0.IN26 E_logic_result[27] => Equal0.IN27 E_logic_result[28] => Equal0.IN28 E_logic_result[29] => Equal0.IN29 E_logic_result[30] => Equal0.IN30 E_logic_result[31] => Equal0.IN31 E_src1[0] => ~NO_FANOUT~ E_src1[1] => ~NO_FANOUT~ E_src1[2] => ~NO_FANOUT~ E_src1[3] => ~NO_FANOUT~ E_src1[4] => ~NO_FANOUT~ E_src1[5] => ~NO_FANOUT~ E_src1[6] => ~NO_FANOUT~ E_src1[7] => ~NO_FANOUT~ E_src1[8] => ~NO_FANOUT~ E_src1[9] => ~NO_FANOUT~ E_src1[10] => ~NO_FANOUT~ E_src1[11] => ~NO_FANOUT~ E_src1[12] => ~NO_FANOUT~ E_src1[13] => ~NO_FANOUT~ E_src1[14] => ~NO_FANOUT~ E_src1[15] => ~NO_FANOUT~ E_src1[16] => ~NO_FANOUT~ E_src1[17] => ~NO_FANOUT~ E_src1[18] => ~NO_FANOUT~ E_src1[19] => ~NO_FANOUT~ E_src1[20] => ~NO_FANOUT~ E_src1[21] => ~NO_FANOUT~ E_src1[22] => ~NO_FANOUT~ E_src1[23] => ~NO_FANOUT~ E_src1[24] => ~NO_FANOUT~ E_src1[25] => ~NO_FANOUT~ E_src1[26] => ~NO_FANOUT~ E_src1[27] => ~NO_FANOUT~ E_src1[28] => ~NO_FANOUT~ E_src1[29] => ~NO_FANOUT~ E_src1[30] => ~NO_FANOUT~ E_src1[31] => ~NO_FANOUT~ E_valid => ~NO_FANOUT~ M_alu_result[0] => ~NO_FANOUT~ M_alu_result[1] => ~NO_FANOUT~ M_alu_result[2] => ~NO_FANOUT~ M_alu_result[3] => ~NO_FANOUT~ M_alu_result[4] => ~NO_FANOUT~ M_alu_result[5] => ~NO_FANOUT~ M_alu_result[6] => ~NO_FANOUT~ M_alu_result[7] => ~NO_FANOUT~ M_alu_result[8] => ~NO_FANOUT~ M_alu_result[9] => ~NO_FANOUT~ M_alu_result[10] => ~NO_FANOUT~ M_alu_result[11] => ~NO_FANOUT~ M_alu_result[12] => ~NO_FANOUT~ M_alu_result[13] => ~NO_FANOUT~ M_alu_result[14] => ~NO_FANOUT~ M_alu_result[15] => ~NO_FANOUT~ M_alu_result[16] => ~NO_FANOUT~ M_alu_result[17] => ~NO_FANOUT~ M_alu_result[18] => ~NO_FANOUT~ M_alu_result[19] => ~NO_FANOUT~ M_alu_result[20] => ~NO_FANOUT~ M_alu_result[21] => ~NO_FANOUT~ M_alu_result[22] => ~NO_FANOUT~ M_alu_result[23] => ~NO_FANOUT~ M_alu_result[24] => ~NO_FANOUT~ M_alu_result[25] => ~NO_FANOUT~ M_alu_result[26] => ~NO_FANOUT~ M_alu_result[27] => ~NO_FANOUT~ M_alu_result[28] => ~NO_FANOUT~ M_alu_result[29] => ~NO_FANOUT~ M_alu_result[30] => ~NO_FANOUT~ M_alu_result[31] => ~NO_FANOUT~ M_en => ~NO_FANOUT~ M_valid => ~NO_FANOUT~ W_dst_regnum[0] => ~NO_FANOUT~ W_dst_regnum[1] => ~NO_FANOUT~ W_dst_regnum[2] => ~NO_FANOUT~ W_dst_regnum[3] => ~NO_FANOUT~ W_dst_regnum[4] => ~NO_FANOUT~ W_iw[0] => ~NO_FANOUT~ W_iw[1] => ~NO_FANOUT~ W_iw[2] => ~NO_FANOUT~ W_iw[3] => ~NO_FANOUT~ W_iw[4] => ~NO_FANOUT~ W_iw[5] => ~NO_FANOUT~ W_iw[6] => ~NO_FANOUT~ W_iw[7] => ~NO_FANOUT~ W_iw[8] => ~NO_FANOUT~ W_iw[9] => ~NO_FANOUT~ W_iw[10] => ~NO_FANOUT~ W_iw[11] => ~NO_FANOUT~ W_iw[12] => ~NO_FANOUT~ W_iw[13] => ~NO_FANOUT~ W_iw[14] => ~NO_FANOUT~ W_iw[15] => ~NO_FANOUT~ W_iw[16] => ~NO_FANOUT~ W_iw[17] => ~NO_FANOUT~ W_iw[18] => ~NO_FANOUT~ W_iw[19] => ~NO_FANOUT~ W_iw[20] => ~NO_FANOUT~ W_iw[21] => ~NO_FANOUT~ W_iw[22] => ~NO_FANOUT~ W_iw[23] => ~NO_FANOUT~ W_iw[24] => ~NO_FANOUT~ W_iw[25] => ~NO_FANOUT~ W_iw[26] => ~NO_FANOUT~ W_iw[27] => ~NO_FANOUT~ W_iw[28] => ~NO_FANOUT~ W_iw[29] => ~NO_FANOUT~ W_iw[30] => ~NO_FANOUT~ W_iw[31] => ~NO_FANOUT~ W_iw_op[0] => ~NO_FANOUT~ W_iw_op[1] => ~NO_FANOUT~ W_iw_op[2] => ~NO_FANOUT~ W_iw_op[3] => ~NO_FANOUT~ W_iw_op[4] => ~NO_FANOUT~ W_iw_op[5] => ~NO_FANOUT~ W_iw_opx[0] => ~NO_FANOUT~ W_iw_opx[1] => ~NO_FANOUT~ W_iw_opx[2] => ~NO_FANOUT~ W_iw_opx[3] => ~NO_FANOUT~ W_iw_opx[4] => ~NO_FANOUT~ W_iw_opx[5] => ~NO_FANOUT~ W_pcb[0] => ~NO_FANOUT~ W_pcb[1] => ~NO_FANOUT~ W_pcb[2] => ~NO_FANOUT~ W_pcb[3] => ~NO_FANOUT~ W_pcb[4] => ~NO_FANOUT~ W_pcb[5] => ~NO_FANOUT~ W_pcb[6] => ~NO_FANOUT~ W_pcb[7] => ~NO_FANOUT~ W_pcb[8] => ~NO_FANOUT~ W_pcb[9] => ~NO_FANOUT~ W_pcb[10] => ~NO_FANOUT~ W_pcb[11] => ~NO_FANOUT~ W_pcb[12] => ~NO_FANOUT~ W_pcb[13] => ~NO_FANOUT~ W_pcb[14] => ~NO_FANOUT~ W_pcb[15] => ~NO_FANOUT~ W_pcb[16] => ~NO_FANOUT~ W_pcb[17] => ~NO_FANOUT~ W_pcb[18] => ~NO_FANOUT~ W_pcb[19] => ~NO_FANOUT~ W_pcb[20] => ~NO_FANOUT~ W_pcb[21] => ~NO_FANOUT~ W_pcb[22] => ~NO_FANOUT~ W_pcb[23] => ~NO_FANOUT~ W_valid => ~NO_FANOUT~ W_wr_dst_reg => ~NO_FANOUT~ clk => ~NO_FANOUT~ d_address[0] => ~NO_FANOUT~ d_address[1] => ~NO_FANOUT~ d_address[2] => ~NO_FANOUT~ d_address[3] => ~NO_FANOUT~ d_address[4] => ~NO_FANOUT~ d_address[5] => ~NO_FANOUT~ d_address[6] => ~NO_FANOUT~ d_address[7] => ~NO_FANOUT~ d_address[8] => ~NO_FANOUT~ d_address[9] => ~NO_FANOUT~ d_address[10] => ~NO_FANOUT~ d_address[11] => ~NO_FANOUT~ d_address[12] => ~NO_FANOUT~ d_address[13] => ~NO_FANOUT~ d_address[14] => ~NO_FANOUT~ d_address[15] => ~NO_FANOUT~ d_address[16] => ~NO_FANOUT~ d_address[17] => ~NO_FANOUT~ d_address[18] => ~NO_FANOUT~ d_address[19] => ~NO_FANOUT~ d_address[20] => ~NO_FANOUT~ d_address[21] => ~NO_FANOUT~ d_address[22] => ~NO_FANOUT~ d_address[23] => ~NO_FANOUT~ d_byteenable[0] => ~NO_FANOUT~ d_byteenable[1] => ~NO_FANOUT~ d_byteenable[2] => ~NO_FANOUT~ d_byteenable[3] => ~NO_FANOUT~ d_read => ~NO_FANOUT~ d_write => ~NO_FANOUT~ i_address[0] => ~NO_FANOUT~ i_address[1] => ~NO_FANOUT~ i_address[2] => ~NO_FANOUT~ i_address[3] => ~NO_FANOUT~ i_address[4] => ~NO_FANOUT~ i_address[5] => ~NO_FANOUT~ i_address[6] => ~NO_FANOUT~ i_address[7] => ~NO_FANOUT~ i_address[8] => ~NO_FANOUT~ i_address[9] => ~NO_FANOUT~ i_address[10] => ~NO_FANOUT~ i_address[11] => ~NO_FANOUT~ i_address[12] => ~NO_FANOUT~ i_address[13] => ~NO_FANOUT~ i_address[14] => ~NO_FANOUT~ i_address[15] => ~NO_FANOUT~ i_address[16] => ~NO_FANOUT~ i_address[17] => ~NO_FANOUT~ i_address[18] => ~NO_FANOUT~ i_address[19] => ~NO_FANOUT~ i_address[20] => ~NO_FANOUT~ i_address[21] => ~NO_FANOUT~ i_address[22] => ~NO_FANOUT~ i_address[23] => ~NO_FANOUT~ i_read => ~NO_FANOUT~ i_readdatavalid => ~NO_FANOUT~ reset_n => ~NO_FANOUT~ A_wr_data_filtered[0] <= A_wr_data_unfiltered[0].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[1] <= A_wr_data_unfiltered[1].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[2] <= A_wr_data_unfiltered[2].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[3] <= A_wr_data_unfiltered[3].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[4] <= A_wr_data_unfiltered[4].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[5] <= A_wr_data_unfiltered[5].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[6] <= A_wr_data_unfiltered[6].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[7] <= A_wr_data_unfiltered[7].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[8] <= A_wr_data_unfiltered[8].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[9] <= A_wr_data_unfiltered[9].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[10] <= A_wr_data_unfiltered[10].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[11] <= A_wr_data_unfiltered[11].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[12] <= A_wr_data_unfiltered[12].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[13] <= A_wr_data_unfiltered[13].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[14] <= A_wr_data_unfiltered[14].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[15] <= A_wr_data_unfiltered[15].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[16] <= A_wr_data_unfiltered[16].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[17] <= A_wr_data_unfiltered[17].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[18] <= A_wr_data_unfiltered[18].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[19] <= A_wr_data_unfiltered[19].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[20] <= A_wr_data_unfiltered[20].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[21] <= A_wr_data_unfiltered[21].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[22] <= A_wr_data_unfiltered[22].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[23] <= A_wr_data_unfiltered[23].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[24] <= A_wr_data_unfiltered[24].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[25] <= A_wr_data_unfiltered[25].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[26] <= A_wr_data_unfiltered[26].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[27] <= A_wr_data_unfiltered[27].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[28] <= A_wr_data_unfiltered[28].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[29] <= A_wr_data_unfiltered[29].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[30] <= A_wr_data_unfiltered[30].DB_MAX_OUTPUT_PORT_TYPE A_wr_data_filtered[31] <= A_wr_data_unfiltered[31].DB_MAX_OUTPUT_PORT_TYPE E_src1_eq_src2 <= Equal0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data data[0] => data[0]~31.IN1 data[1] => data[1]~30.IN1 data[2] => data[2]~29.IN1 data[3] => data[3]~28.IN1 data[4] => data[4]~27.IN1 data[5] => data[5]~26.IN1 data[6] => data[6]~25.IN1 data[7] => data[7]~24.IN1 data[8] => data[8]~23.IN1 data[9] => data[9]~22.IN1 data[10] => data[10]~21.IN1 data[11] => data[11]~20.IN1 data[12] => data[12]~19.IN1 data[13] => data[13]~18.IN1 data[14] => data[14]~17.IN1 data[15] => data[15]~16.IN1 data[16] => data[16]~15.IN1 data[17] => data[17]~14.IN1 data[18] => data[18]~13.IN1 data[19] => data[19]~12.IN1 data[20] => data[20]~11.IN1 data[21] => data[21]~10.IN1 data[22] => data[22]~9.IN1 data[23] => data[23]~8.IN1 data[24] => data[24]~7.IN1 data[25] => data[25]~6.IN1 data[26] => data[26]~5.IN1 data[27] => data[27]~4.IN1 data[28] => data[28]~3.IN1 data[29] => data[29]~2.IN1 data[30] => data[30]~1.IN1 data[31] => data[31]~0.IN1 rdaddress[0] => rdaddress[0]~9.IN1 rdaddress[1] => rdaddress[1]~8.IN1 rdaddress[2] => rdaddress[2]~7.IN1 rdaddress[3] => rdaddress[3]~6.IN1 rdaddress[4] => rdaddress[4]~5.IN1 rdaddress[5] => rdaddress[5]~4.IN1 rdaddress[6] => rdaddress[6]~3.IN1 rdaddress[7] => rdaddress[7]~2.IN1 rdaddress[8] => rdaddress[8]~1.IN1 rdaddress[9] => rdaddress[9]~0.IN1 rdclken => rdclken~0.IN1 rdclock => rdclock~0.IN1 wraddress[0] => wraddress[0]~9.IN1 wraddress[1] => wraddress[1]~8.IN1 wraddress[2] => wraddress[2]~7.IN1 wraddress[3] => wraddress[3]~6.IN1 wraddress[4] => wraddress[4]~5.IN1 wraddress[5] => wraddress[5]~4.IN1 wraddress[6] => wraddress[6]~3.IN1 wraddress[7] => wraddress[7]~2.IN1 wraddress[8] => wraddress[8]~1.IN1 wraddress[9] => wraddress[9]~0.IN1 wrclock => wrclock~0.IN1 wren => wren~0.IN1 q[0] <= altsyncram:the_altsyncram.q_b q[1] <= altsyncram:the_altsyncram.q_b q[2] <= altsyncram:the_altsyncram.q_b q[3] <= altsyncram:the_altsyncram.q_b q[4] <= altsyncram:the_altsyncram.q_b q[5] <= altsyncram:the_altsyncram.q_b q[6] <= altsyncram:the_altsyncram.q_b q[7] <= altsyncram:the_altsyncram.q_b q[8] <= altsyncram:the_altsyncram.q_b q[9] <= altsyncram:the_altsyncram.q_b q[10] <= altsyncram:the_altsyncram.q_b q[11] <= altsyncram:the_altsyncram.q_b q[12] <= altsyncram:the_altsyncram.q_b q[13] <= altsyncram:the_altsyncram.q_b q[14] <= altsyncram:the_altsyncram.q_b q[15] <= altsyncram:the_altsyncram.q_b q[16] <= altsyncram:the_altsyncram.q_b q[17] <= altsyncram:the_altsyncram.q_b q[18] <= altsyncram:the_altsyncram.q_b q[19] <= altsyncram:the_altsyncram.q_b q[20] <= altsyncram:the_altsyncram.q_b q[21] <= altsyncram:the_altsyncram.q_b q[22] <= altsyncram:the_altsyncram.q_b q[23] <= altsyncram:the_altsyncram.q_b q[24] <= altsyncram:the_altsyncram.q_b q[25] <= altsyncram:the_altsyncram.q_b q[26] <= altsyncram:the_altsyncram.q_b q[27] <= altsyncram:the_altsyncram.q_b q[28] <= altsyncram:the_altsyncram.q_b q[29] <= altsyncram:the_altsyncram.q_b q[30] <= altsyncram:the_altsyncram.q_b q[31] <= altsyncram:the_altsyncram.q_b |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram wren_a => altsyncram_cub1:auto_generated.wren_a rden_a => ~NO_FANOUT~ wren_b => ~NO_FANOUT~ rden_b => ~NO_FANOUT~ data_a[0] => altsyncram_cub1:auto_generated.data_a[0] data_a[1] => altsyncram_cub1:auto_generated.data_a[1] data_a[2] => altsyncram_cub1:auto_generated.data_a[2] data_a[3] => altsyncram_cub1:auto_generated.data_a[3] data_a[4] => altsyncram_cub1:auto_generated.data_a[4] data_a[5] => altsyncram_cub1:auto_generated.data_a[5] data_a[6] => altsyncram_cub1:auto_generated.data_a[6] data_a[7] => altsyncram_cub1:auto_generated.data_a[7] data_a[8] => altsyncram_cub1:auto_generated.data_a[8] data_a[9] => altsyncram_cub1:auto_generated.data_a[9] data_a[10] => altsyncram_cub1:auto_generated.data_a[10] data_a[11] => altsyncram_cub1:auto_generated.data_a[11] data_a[12] => altsyncram_cub1:auto_generated.data_a[12] data_a[13] => altsyncram_cub1:auto_generated.data_a[13] data_a[14] => altsyncram_cub1:auto_generated.data_a[14] data_a[15] => altsyncram_cub1:auto_generated.data_a[15] data_a[16] => altsyncram_cub1:auto_generated.data_a[16] data_a[17] => altsyncram_cub1:auto_generated.data_a[17] data_a[18] => altsyncram_cub1:auto_generated.data_a[18] data_a[19] => altsyncram_cub1:auto_generated.data_a[19] data_a[20] => altsyncram_cub1:auto_generated.data_a[20] data_a[21] => altsyncram_cub1:auto_generated.data_a[21] data_a[22] => altsyncram_cub1:auto_generated.data_a[22] data_a[23] => altsyncram_cub1:auto_generated.data_a[23] data_a[24] => altsyncram_cub1:auto_generated.data_a[24] data_a[25] => altsyncram_cub1:auto_generated.data_a[25] data_a[26] => altsyncram_cub1:auto_generated.data_a[26] data_a[27] => altsyncram_cub1:auto_generated.data_a[27] data_a[28] => altsyncram_cub1:auto_generated.data_a[28] data_a[29] => altsyncram_cub1:auto_generated.data_a[29] data_a[30] => altsyncram_cub1:auto_generated.data_a[30] data_a[31] => altsyncram_cub1:auto_generated.data_a[31] data_b[0] => ~NO_FANOUT~ data_b[1] => ~NO_FANOUT~ data_b[2] => ~NO_FANOUT~ data_b[3] => ~NO_FANOUT~ data_b[4] => ~NO_FANOUT~ data_b[5] => ~NO_FANOUT~ data_b[6] => ~NO_FANOUT~ data_b[7] => ~NO_FANOUT~ data_b[8] => ~NO_FANOUT~ data_b[9] => ~NO_FANOUT~ data_b[10] => ~NO_FANOUT~ data_b[11] => ~NO_FANOUT~ data_b[12] => ~NO_FANOUT~ data_b[13] => ~NO_FANOUT~ data_b[14] => ~NO_FANOUT~ data_b[15] => ~NO_FANOUT~ data_b[16] => ~NO_FANOUT~ data_b[17] => ~NO_FANOUT~ data_b[18] => ~NO_FANOUT~ data_b[19] => ~NO_FANOUT~ data_b[20] => ~NO_FANOUT~ data_b[21] => ~NO_FANOUT~ data_b[22] => ~NO_FANOUT~ data_b[23] => ~NO_FANOUT~ data_b[24] => ~NO_FANOUT~ data_b[25] => ~NO_FANOUT~ data_b[26] => ~NO_FANOUT~ data_b[27] => ~NO_FANOUT~ data_b[28] => ~NO_FANOUT~ data_b[29] => ~NO_FANOUT~ data_b[30] => ~NO_FANOUT~ data_b[31] => ~NO_FANOUT~ address_a[0] => altsyncram_cub1:auto_generated.address_a[0] address_a[1] => altsyncram_cub1:auto_generated.address_a[1] address_a[2] => altsyncram_cub1:auto_generated.address_a[2] address_a[3] => altsyncram_cub1:auto_generated.address_a[3] address_a[4] => altsyncram_cub1:auto_generated.address_a[4] address_a[5] => altsyncram_cub1:auto_generated.address_a[5] address_a[6] => altsyncram_cub1:auto_generated.address_a[6] address_a[7] => altsyncram_cub1:auto_generated.address_a[7] address_a[8] => altsyncram_cub1:auto_generated.address_a[8] address_a[9] => altsyncram_cub1:auto_generated.address_a[9] address_b[0] => altsyncram_cub1:auto_generated.address_b[0] address_b[1] => altsyncram_cub1:auto_generated.address_b[1] address_b[2] => altsyncram_cub1:auto_generated.address_b[2] address_b[3] => altsyncram_cub1:auto_generated.address_b[3] address_b[4] => altsyncram_cub1:auto_generated.address_b[4] address_b[5] => altsyncram_cub1:auto_generated.address_b[5] address_b[6] => altsyncram_cub1:auto_generated.address_b[6] address_b[7] => altsyncram_cub1:auto_generated.address_b[7] address_b[8] => altsyncram_cub1:auto_generated.address_b[8] address_b[9] => altsyncram_cub1:auto_generated.address_b[9] addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_cub1:auto_generated.clock0 clock1 => altsyncram_cub1:auto_generated.clock1 clocken0 => ~NO_FANOUT~ clocken1 => altsyncram_cub1:auto_generated.clocken1 clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= q_a[1] <= q_a[2] <= q_a[3] <= q_a[4] <= q_a[5] <= q_a[6] <= q_a[7] <= q_a[8] <= q_a[9] <= q_a[10] <= q_a[11] <= q_a[12] <= q_a[13] <= q_a[14] <= q_a[15] <= q_a[16] <= q_a[17] <= q_a[18] <= q_a[19] <= q_a[20] <= q_a[21] <= q_a[22] <= q_a[23] <= q_a[24] <= q_a[25] <= q_a[26] <= q_a[27] <= q_a[28] <= q_a[29] <= q_a[30] <= q_a[31] <= q_b[0] <= altsyncram_cub1:auto_generated.q_b[0] q_b[1] <= altsyncram_cub1:auto_generated.q_b[1] q_b[2] <= altsyncram_cub1:auto_generated.q_b[2] q_b[3] <= altsyncram_cub1:auto_generated.q_b[3] q_b[4] <= altsyncram_cub1:auto_generated.q_b[4] q_b[5] <= altsyncram_cub1:auto_generated.q_b[5] q_b[6] <= altsyncram_cub1:auto_generated.q_b[6] q_b[7] <= altsyncram_cub1:auto_generated.q_b[7] q_b[8] <= altsyncram_cub1:auto_generated.q_b[8] q_b[9] <= altsyncram_cub1:auto_generated.q_b[9] q_b[10] <= altsyncram_cub1:auto_generated.q_b[10] q_b[11] <= altsyncram_cub1:auto_generated.q_b[11] q_b[12] <= altsyncram_cub1:auto_generated.q_b[12] q_b[13] <= altsyncram_cub1:auto_generated.q_b[13] q_b[14] <= altsyncram_cub1:auto_generated.q_b[14] q_b[15] <= altsyncram_cub1:auto_generated.q_b[15] q_b[16] <= altsyncram_cub1:auto_generated.q_b[16] q_b[17] <= altsyncram_cub1:auto_generated.q_b[17] q_b[18] <= altsyncram_cub1:auto_generated.q_b[18] q_b[19] <= altsyncram_cub1:auto_generated.q_b[19] q_b[20] <= altsyncram_cub1:auto_generated.q_b[20] q_b[21] <= altsyncram_cub1:auto_generated.q_b[21] q_b[22] <= altsyncram_cub1:auto_generated.q_b[22] q_b[23] <= altsyncram_cub1:auto_generated.q_b[23] q_b[24] <= altsyncram_cub1:auto_generated.q_b[24] q_b[25] <= altsyncram_cub1:auto_generated.q_b[25] q_b[26] <= altsyncram_cub1:auto_generated.q_b[26] q_b[27] <= altsyncram_cub1:auto_generated.q_b[27] q_b[28] <= altsyncram_cub1:auto_generated.q_b[28] q_b[29] <= altsyncram_cub1:auto_generated.q_b[29] q_b[30] <= altsyncram_cub1:auto_generated.q_b[30] q_b[31] <= altsyncram_cub1:auto_generated.q_b[31] eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated address_a[0] => altsyncram_k1l1:altsyncram1.address_b[0] address_a[1] => altsyncram_k1l1:altsyncram1.address_b[1] address_a[2] => altsyncram_k1l1:altsyncram1.address_b[2] address_a[3] => altsyncram_k1l1:altsyncram1.address_b[3] address_a[4] => altsyncram_k1l1:altsyncram1.address_b[4] address_a[5] => altsyncram_k1l1:altsyncram1.address_b[5] address_a[6] => altsyncram_k1l1:altsyncram1.address_b[6] address_a[7] => altsyncram_k1l1:altsyncram1.address_b[7] address_a[8] => altsyncram_k1l1:altsyncram1.address_b[8] address_a[9] => altsyncram_k1l1:altsyncram1.address_b[9] address_b[0] => altsyncram_k1l1:altsyncram1.address_a[0] address_b[1] => altsyncram_k1l1:altsyncram1.address_a[1] address_b[2] => altsyncram_k1l1:altsyncram1.address_a[2] address_b[3] => altsyncram_k1l1:altsyncram1.address_a[3] address_b[4] => altsyncram_k1l1:altsyncram1.address_a[4] address_b[5] => altsyncram_k1l1:altsyncram1.address_a[5] address_b[6] => altsyncram_k1l1:altsyncram1.address_a[6] address_b[7] => altsyncram_k1l1:altsyncram1.address_a[7] address_b[8] => altsyncram_k1l1:altsyncram1.address_a[8] address_b[9] => altsyncram_k1l1:altsyncram1.address_a[9] clock0 => altsyncram_k1l1:altsyncram1.clock1 clock1 => altsyncram_k1l1:altsyncram1.clock0 clocken1 => altsyncram_k1l1:altsyncram1.clocken0 data_a[0] => altsyncram_k1l1:altsyncram1.data_b[0] data_a[1] => altsyncram_k1l1:altsyncram1.data_b[1] data_a[2] => altsyncram_k1l1:altsyncram1.data_b[2] data_a[3] => altsyncram_k1l1:altsyncram1.data_b[3] data_a[4] => altsyncram_k1l1:altsyncram1.data_b[4] data_a[5] => altsyncram_k1l1:altsyncram1.data_b[5] data_a[6] => altsyncram_k1l1:altsyncram1.data_b[6] data_a[7] => altsyncram_k1l1:altsyncram1.data_b[7] data_a[8] => altsyncram_k1l1:altsyncram1.data_b[8] data_a[9] => altsyncram_k1l1:altsyncram1.data_b[9] data_a[10] => altsyncram_k1l1:altsyncram1.data_b[10] data_a[11] => altsyncram_k1l1:altsyncram1.data_b[11] data_a[12] => altsyncram_k1l1:altsyncram1.data_b[12] data_a[13] => altsyncram_k1l1:altsyncram1.data_b[13] data_a[14] => altsyncram_k1l1:altsyncram1.data_b[14] data_a[15] => altsyncram_k1l1:altsyncram1.data_b[15] data_a[16] => altsyncram_k1l1:altsyncram1.data_b[16] data_a[17] => altsyncram_k1l1:altsyncram1.data_b[17] data_a[18] => altsyncram_k1l1:altsyncram1.data_b[18] data_a[19] => altsyncram_k1l1:altsyncram1.data_b[19] data_a[20] => altsyncram_k1l1:altsyncram1.data_b[20] data_a[21] => altsyncram_k1l1:altsyncram1.data_b[21] data_a[22] => altsyncram_k1l1:altsyncram1.data_b[22] data_a[23] => altsyncram_k1l1:altsyncram1.data_b[23] data_a[24] => altsyncram_k1l1:altsyncram1.data_b[24] data_a[25] => altsyncram_k1l1:altsyncram1.data_b[25] data_a[26] => altsyncram_k1l1:altsyncram1.data_b[26] data_a[27] => altsyncram_k1l1:altsyncram1.data_b[27] data_a[28] => altsyncram_k1l1:altsyncram1.data_b[28] data_a[29] => altsyncram_k1l1:altsyncram1.data_b[29] data_a[30] => altsyncram_k1l1:altsyncram1.data_b[30] data_a[31] => altsyncram_k1l1:altsyncram1.data_b[31] q_b[0] <= altsyncram_k1l1:altsyncram1.q_a[0] q_b[1] <= altsyncram_k1l1:altsyncram1.q_a[1] q_b[2] <= altsyncram_k1l1:altsyncram1.q_a[2] q_b[3] <= altsyncram_k1l1:altsyncram1.q_a[3] q_b[4] <= altsyncram_k1l1:altsyncram1.q_a[4] q_b[5] <= altsyncram_k1l1:altsyncram1.q_a[5] q_b[6] <= altsyncram_k1l1:altsyncram1.q_a[6] q_b[7] <= altsyncram_k1l1:altsyncram1.q_a[7] q_b[8] <= altsyncram_k1l1:altsyncram1.q_a[8] q_b[9] <= altsyncram_k1l1:altsyncram1.q_a[9] q_b[10] <= altsyncram_k1l1:altsyncram1.q_a[10] q_b[11] <= altsyncram_k1l1:altsyncram1.q_a[11] q_b[12] <= altsyncram_k1l1:altsyncram1.q_a[12] q_b[13] <= altsyncram_k1l1:altsyncram1.q_a[13] q_b[14] <= altsyncram_k1l1:altsyncram1.q_a[14] q_b[15] <= altsyncram_k1l1:altsyncram1.q_a[15] q_b[16] <= altsyncram_k1l1:altsyncram1.q_a[16] q_b[17] <= altsyncram_k1l1:altsyncram1.q_a[17] q_b[18] <= altsyncram_k1l1:altsyncram1.q_a[18] q_b[19] <= altsyncram_k1l1:altsyncram1.q_a[19] q_b[20] <= altsyncram_k1l1:altsyncram1.q_a[20] q_b[21] <= altsyncram_k1l1:altsyncram1.q_a[21] q_b[22] <= altsyncram_k1l1:altsyncram1.q_a[22] q_b[23] <= altsyncram_k1l1:altsyncram1.q_a[23] q_b[24] <= altsyncram_k1l1:altsyncram1.q_a[24] q_b[25] <= altsyncram_k1l1:altsyncram1.q_a[25] q_b[26] <= altsyncram_k1l1:altsyncram1.q_a[26] q_b[27] <= altsyncram_k1l1:altsyncram1.q_a[27] q_b[28] <= altsyncram_k1l1:altsyncram1.q_a[28] q_b[29] <= altsyncram_k1l1:altsyncram1.q_a[29] q_b[30] <= altsyncram_k1l1:altsyncram1.q_a[30] q_b[31] <= altsyncram_k1l1:altsyncram1.q_a[31] wren_a => altsyncram_k1l1:altsyncram1.clocken1 wren_a => altsyncram_k1l1:altsyncram1.wren_b |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1 address_a[0] => ram_block2a0.PORTAADDR address_a[0] => ram_block2a1.PORTAADDR address_a[0] => ram_block2a2.PORTAADDR address_a[0] => ram_block2a3.PORTAADDR address_a[0] => ram_block2a4.PORTAADDR address_a[0] => ram_block2a5.PORTAADDR address_a[0] => ram_block2a6.PORTAADDR address_a[0] => ram_block2a7.PORTAADDR address_a[0] => ram_block2a8.PORTAADDR address_a[0] => ram_block2a9.PORTAADDR address_a[0] => ram_block2a10.PORTAADDR address_a[0] => ram_block2a11.PORTAADDR address_a[0] => ram_block2a12.PORTAADDR address_a[0] => ram_block2a13.PORTAADDR address_a[0] => ram_block2a14.PORTAADDR address_a[0] => ram_block2a15.PORTAADDR address_a[0] => ram_block2a16.PORTAADDR address_a[0] => ram_block2a17.PORTAADDR address_a[0] => ram_block2a18.PORTAADDR address_a[0] => ram_block2a19.PORTAADDR address_a[0] => ram_block2a20.PORTAADDR address_a[0] => ram_block2a21.PORTAADDR address_a[0] => ram_block2a22.PORTAADDR address_a[0] => ram_block2a23.PORTAADDR address_a[0] => ram_block2a24.PORTAADDR address_a[0] => ram_block2a25.PORTAADDR address_a[0] => ram_block2a26.PORTAADDR address_a[0] => ram_block2a27.PORTAADDR address_a[0] => ram_block2a28.PORTAADDR address_a[0] => ram_block2a29.PORTAADDR address_a[0] => ram_block2a30.PORTAADDR address_a[0] => ram_block2a31.PORTAADDR address_a[1] => ram_block2a0.PORTAADDR1 address_a[1] => ram_block2a1.PORTAADDR1 address_a[1] => ram_block2a2.PORTAADDR1 address_a[1] => ram_block2a3.PORTAADDR1 address_a[1] => ram_block2a4.PORTAADDR1 address_a[1] => ram_block2a5.PORTAADDR1 address_a[1] => ram_block2a6.PORTAADDR1 address_a[1] => ram_block2a7.PORTAADDR1 address_a[1] => ram_block2a8.PORTAADDR1 address_a[1] => ram_block2a9.PORTAADDR1 address_a[1] => ram_block2a10.PORTAADDR1 address_a[1] => ram_block2a11.PORTAADDR1 address_a[1] => ram_block2a12.PORTAADDR1 address_a[1] => ram_block2a13.PORTAADDR1 address_a[1] => ram_block2a14.PORTAADDR1 address_a[1] => ram_block2a15.PORTAADDR1 address_a[1] => ram_block2a16.PORTAADDR1 address_a[1] => ram_block2a17.PORTAADDR1 address_a[1] => ram_block2a18.PORTAADDR1 address_a[1] => ram_block2a19.PORTAADDR1 address_a[1] => ram_block2a20.PORTAADDR1 address_a[1] => ram_block2a21.PORTAADDR1 address_a[1] => ram_block2a22.PORTAADDR1 address_a[1] => ram_block2a23.PORTAADDR1 address_a[1] => ram_block2a24.PORTAADDR1 address_a[1] => ram_block2a25.PORTAADDR1 address_a[1] => ram_block2a26.PORTAADDR1 address_a[1] => ram_block2a27.PORTAADDR1 address_a[1] => ram_block2a28.PORTAADDR1 address_a[1] => ram_block2a29.PORTAADDR1 address_a[1] => ram_block2a30.PORTAADDR1 address_a[1] => ram_block2a31.PORTAADDR1 address_a[2] => ram_block2a0.PORTAADDR2 address_a[2] => ram_block2a1.PORTAADDR2 address_a[2] => ram_block2a2.PORTAADDR2 address_a[2] => ram_block2a3.PORTAADDR2 address_a[2] => ram_block2a4.PORTAADDR2 address_a[2] => ram_block2a5.PORTAADDR2 address_a[2] => ram_block2a6.PORTAADDR2 address_a[2] => ram_block2a7.PORTAADDR2 address_a[2] => ram_block2a8.PORTAADDR2 address_a[2] => ram_block2a9.PORTAADDR2 address_a[2] => ram_block2a10.PORTAADDR2 address_a[2] => ram_block2a11.PORTAADDR2 address_a[2] => ram_block2a12.PORTAADDR2 address_a[2] => ram_block2a13.PORTAADDR2 address_a[2] => ram_block2a14.PORTAADDR2 address_a[2] => ram_block2a15.PORTAADDR2 address_a[2] => ram_block2a16.PORTAADDR2 address_a[2] => ram_block2a17.PORTAADDR2 address_a[2] => ram_block2a18.PORTAADDR2 address_a[2] => ram_block2a19.PORTAADDR2 address_a[2] => ram_block2a20.PORTAADDR2 address_a[2] => ram_block2a21.PORTAADDR2 address_a[2] => ram_block2a22.PORTAADDR2 address_a[2] => ram_block2a23.PORTAADDR2 address_a[2] => ram_block2a24.PORTAADDR2 address_a[2] => ram_block2a25.PORTAADDR2 address_a[2] => ram_block2a26.PORTAADDR2 address_a[2] => ram_block2a27.PORTAADDR2 address_a[2] => ram_block2a28.PORTAADDR2 address_a[2] => ram_block2a29.PORTAADDR2 address_a[2] => ram_block2a30.PORTAADDR2 address_a[2] => ram_block2a31.PORTAADDR2 address_a[3] => ram_block2a0.PORTAADDR3 address_a[3] => ram_block2a1.PORTAADDR3 address_a[3] => ram_block2a2.PORTAADDR3 address_a[3] => ram_block2a3.PORTAADDR3 address_a[3] => ram_block2a4.PORTAADDR3 address_a[3] => ram_block2a5.PORTAADDR3 address_a[3] => ram_block2a6.PORTAADDR3 address_a[3] => ram_block2a7.PORTAADDR3 address_a[3] => ram_block2a8.PORTAADDR3 address_a[3] => ram_block2a9.PORTAADDR3 address_a[3] => ram_block2a10.PORTAADDR3 address_a[3] => ram_block2a11.PORTAADDR3 address_a[3] => ram_block2a12.PORTAADDR3 address_a[3] => ram_block2a13.PORTAADDR3 address_a[3] => ram_block2a14.PORTAADDR3 address_a[3] => ram_block2a15.PORTAADDR3 address_a[3] => ram_block2a16.PORTAADDR3 address_a[3] => ram_block2a17.PORTAADDR3 address_a[3] => ram_block2a18.PORTAADDR3 address_a[3] => ram_block2a19.PORTAADDR3 address_a[3] => ram_block2a20.PORTAADDR3 address_a[3] => ram_block2a21.PORTAADDR3 address_a[3] => ram_block2a22.PORTAADDR3 address_a[3] => ram_block2a23.PORTAADDR3 address_a[3] => ram_block2a24.PORTAADDR3 address_a[3] => ram_block2a25.PORTAADDR3 address_a[3] => ram_block2a26.PORTAADDR3 address_a[3] => ram_block2a27.PORTAADDR3 address_a[3] => ram_block2a28.PORTAADDR3 address_a[3] => ram_block2a29.PORTAADDR3 address_a[3] => ram_block2a30.PORTAADDR3 address_a[3] => ram_block2a31.PORTAADDR3 address_a[4] => ram_block2a0.PORTAADDR4 address_a[4] => ram_block2a1.PORTAADDR4 address_a[4] => ram_block2a2.PORTAADDR4 address_a[4] => ram_block2a3.PORTAADDR4 address_a[4] => ram_block2a4.PORTAADDR4 address_a[4] => ram_block2a5.PORTAADDR4 address_a[4] => ram_block2a6.PORTAADDR4 address_a[4] => ram_block2a7.PORTAADDR4 address_a[4] => ram_block2a8.PORTAADDR4 address_a[4] => ram_block2a9.PORTAADDR4 address_a[4] => ram_block2a10.PORTAADDR4 address_a[4] => ram_block2a11.PORTAADDR4 address_a[4] => ram_block2a12.PORTAADDR4 address_a[4] => ram_block2a13.PORTAADDR4 address_a[4] => ram_block2a14.PORTAADDR4 address_a[4] => ram_block2a15.PORTAADDR4 address_a[4] => ram_block2a16.PORTAADDR4 address_a[4] => ram_block2a17.PORTAADDR4 address_a[4] => ram_block2a18.PORTAADDR4 address_a[4] => ram_block2a19.PORTAADDR4 address_a[4] => ram_block2a20.PORTAADDR4 address_a[4] => ram_block2a21.PORTAADDR4 address_a[4] => ram_block2a22.PORTAADDR4 address_a[4] => ram_block2a23.PORTAADDR4 address_a[4] => ram_block2a24.PORTAADDR4 address_a[4] => ram_block2a25.PORTAADDR4 address_a[4] => ram_block2a26.PORTAADDR4 address_a[4] => ram_block2a27.PORTAADDR4 address_a[4] => ram_block2a28.PORTAADDR4 address_a[4] => ram_block2a29.PORTAADDR4 address_a[4] => ram_block2a30.PORTAADDR4 address_a[4] => ram_block2a31.PORTAADDR4 address_a[5] => ram_block2a0.PORTAADDR5 address_a[5] => ram_block2a1.PORTAADDR5 address_a[5] => ram_block2a2.PORTAADDR5 address_a[5] => ram_block2a3.PORTAADDR5 address_a[5] => ram_block2a4.PORTAADDR5 address_a[5] => ram_block2a5.PORTAADDR5 address_a[5] => ram_block2a6.PORTAADDR5 address_a[5] => ram_block2a7.PORTAADDR5 address_a[5] => ram_block2a8.PORTAADDR5 address_a[5] => ram_block2a9.PORTAADDR5 address_a[5] => ram_block2a10.PORTAADDR5 address_a[5] => ram_block2a11.PORTAADDR5 address_a[5] => ram_block2a12.PORTAADDR5 address_a[5] => ram_block2a13.PORTAADDR5 address_a[5] => ram_block2a14.PORTAADDR5 address_a[5] => ram_block2a15.PORTAADDR5 address_a[5] => ram_block2a16.PORTAADDR5 address_a[5] => ram_block2a17.PORTAADDR5 address_a[5] => ram_block2a18.PORTAADDR5 address_a[5] => ram_block2a19.PORTAADDR5 address_a[5] => ram_block2a20.PORTAADDR5 address_a[5] => ram_block2a21.PORTAADDR5 address_a[5] => ram_block2a22.PORTAADDR5 address_a[5] => ram_block2a23.PORTAADDR5 address_a[5] => ram_block2a24.PORTAADDR5 address_a[5] => ram_block2a25.PORTAADDR5 address_a[5] => ram_block2a26.PORTAADDR5 address_a[5] => ram_block2a27.PORTAADDR5 address_a[5] => ram_block2a28.PORTAADDR5 address_a[5] => ram_block2a29.PORTAADDR5 address_a[5] => ram_block2a30.PORTAADDR5 address_a[5] => ram_block2a31.PORTAADDR5 address_a[6] => ram_block2a0.PORTAADDR6 address_a[6] => ram_block2a1.PORTAADDR6 address_a[6] => ram_block2a2.PORTAADDR6 address_a[6] => ram_block2a3.PORTAADDR6 address_a[6] => ram_block2a4.PORTAADDR6 address_a[6] => ram_block2a5.PORTAADDR6 address_a[6] => ram_block2a6.PORTAADDR6 address_a[6] => ram_block2a7.PORTAADDR6 address_a[6] => ram_block2a8.PORTAADDR6 address_a[6] => ram_block2a9.PORTAADDR6 address_a[6] => ram_block2a10.PORTAADDR6 address_a[6] => ram_block2a11.PORTAADDR6 address_a[6] => ram_block2a12.PORTAADDR6 address_a[6] => ram_block2a13.PORTAADDR6 address_a[6] => ram_block2a14.PORTAADDR6 address_a[6] => ram_block2a15.PORTAADDR6 address_a[6] => ram_block2a16.PORTAADDR6 address_a[6] => ram_block2a17.PORTAADDR6 address_a[6] => ram_block2a18.PORTAADDR6 address_a[6] => ram_block2a19.PORTAADDR6 address_a[6] => ram_block2a20.PORTAADDR6 address_a[6] => ram_block2a21.PORTAADDR6 address_a[6] => ram_block2a22.PORTAADDR6 address_a[6] => ram_block2a23.PORTAADDR6 address_a[6] => ram_block2a24.PORTAADDR6 address_a[6] => ram_block2a25.PORTAADDR6 address_a[6] => ram_block2a26.PORTAADDR6 address_a[6] => ram_block2a27.PORTAADDR6 address_a[6] => ram_block2a28.PORTAADDR6 address_a[6] => ram_block2a29.PORTAADDR6 address_a[6] => ram_block2a30.PORTAADDR6 address_a[6] => ram_block2a31.PORTAADDR6 address_a[7] => ram_block2a0.PORTAADDR7 address_a[7] => ram_block2a1.PORTAADDR7 address_a[7] => ram_block2a2.PORTAADDR7 address_a[7] => ram_block2a3.PORTAADDR7 address_a[7] => ram_block2a4.PORTAADDR7 address_a[7] => ram_block2a5.PORTAADDR7 address_a[7] => ram_block2a6.PORTAADDR7 address_a[7] => ram_block2a7.PORTAADDR7 address_a[7] => ram_block2a8.PORTAADDR7 address_a[7] => ram_block2a9.PORTAADDR7 address_a[7] => ram_block2a10.PORTAADDR7 address_a[7] => ram_block2a11.PORTAADDR7 address_a[7] => ram_block2a12.PORTAADDR7 address_a[7] => ram_block2a13.PORTAADDR7 address_a[7] => ram_block2a14.PORTAADDR7 address_a[7] => ram_block2a15.PORTAADDR7 address_a[7] => ram_block2a16.PORTAADDR7 address_a[7] => ram_block2a17.PORTAADDR7 address_a[7] => ram_block2a18.PORTAADDR7 address_a[7] => ram_block2a19.PORTAADDR7 address_a[7] => ram_block2a20.PORTAADDR7 address_a[7] => ram_block2a21.PORTAADDR7 address_a[7] => ram_block2a22.PORTAADDR7 address_a[7] => ram_block2a23.PORTAADDR7 address_a[7] => ram_block2a24.PORTAADDR7 address_a[7] => ram_block2a25.PORTAADDR7 address_a[7] => ram_block2a26.PORTAADDR7 address_a[7] => ram_block2a27.PORTAADDR7 address_a[7] => ram_block2a28.PORTAADDR7 address_a[7] => ram_block2a29.PORTAADDR7 address_a[7] => ram_block2a30.PORTAADDR7 address_a[7] => ram_block2a31.PORTAADDR7 address_a[8] => ram_block2a0.PORTAADDR8 address_a[8] => ram_block2a1.PORTAADDR8 address_a[8] => ram_block2a2.PORTAADDR8 address_a[8] => ram_block2a3.PORTAADDR8 address_a[8] => ram_block2a4.PORTAADDR8 address_a[8] => ram_block2a5.PORTAADDR8 address_a[8] => ram_block2a6.PORTAADDR8 address_a[8] => ram_block2a7.PORTAADDR8 address_a[8] => ram_block2a8.PORTAADDR8 address_a[8] => ram_block2a9.PORTAADDR8 address_a[8] => ram_block2a10.PORTAADDR8 address_a[8] => ram_block2a11.PORTAADDR8 address_a[8] => ram_block2a12.PORTAADDR8 address_a[8] => ram_block2a13.PORTAADDR8 address_a[8] => ram_block2a14.PORTAADDR8 address_a[8] => ram_block2a15.PORTAADDR8 address_a[8] => ram_block2a16.PORTAADDR8 address_a[8] => ram_block2a17.PORTAADDR8 address_a[8] => ram_block2a18.PORTAADDR8 address_a[8] => ram_block2a19.PORTAADDR8 address_a[8] => ram_block2a20.PORTAADDR8 address_a[8] => ram_block2a21.PORTAADDR8 address_a[8] => ram_block2a22.PORTAADDR8 address_a[8] => ram_block2a23.PORTAADDR8 address_a[8] => ram_block2a24.PORTAADDR8 address_a[8] => ram_block2a25.PORTAADDR8 address_a[8] => ram_block2a26.PORTAADDR8 address_a[8] => ram_block2a27.PORTAADDR8 address_a[8] => ram_block2a28.PORTAADDR8 address_a[8] => ram_block2a29.PORTAADDR8 address_a[8] => ram_block2a30.PORTAADDR8 address_a[8] => ram_block2a31.PORTAADDR8 address_a[9] => ram_block2a0.PORTAADDR9 address_a[9] => ram_block2a1.PORTAADDR9 address_a[9] => ram_block2a2.PORTAADDR9 address_a[9] => ram_block2a3.PORTAADDR9 address_a[9] => ram_block2a4.PORTAADDR9 address_a[9] => ram_block2a5.PORTAADDR9 address_a[9] => ram_block2a6.PORTAADDR9 address_a[9] => ram_block2a7.PORTAADDR9 address_a[9] => ram_block2a8.PORTAADDR9 address_a[9] => ram_block2a9.PORTAADDR9 address_a[9] => ram_block2a10.PORTAADDR9 address_a[9] => ram_block2a11.PORTAADDR9 address_a[9] => ram_block2a12.PORTAADDR9 address_a[9] => ram_block2a13.PORTAADDR9 address_a[9] => ram_block2a14.PORTAADDR9 address_a[9] => ram_block2a15.PORTAADDR9 address_a[9] => ram_block2a16.PORTAADDR9 address_a[9] => ram_block2a17.PORTAADDR9 address_a[9] => ram_block2a18.PORTAADDR9 address_a[9] => ram_block2a19.PORTAADDR9 address_a[9] => ram_block2a20.PORTAADDR9 address_a[9] => ram_block2a21.PORTAADDR9 address_a[9] => ram_block2a22.PORTAADDR9 address_a[9] => ram_block2a23.PORTAADDR9 address_a[9] => ram_block2a24.PORTAADDR9 address_a[9] => ram_block2a25.PORTAADDR9 address_a[9] => ram_block2a26.PORTAADDR9 address_a[9] => ram_block2a27.PORTAADDR9 address_a[9] => ram_block2a28.PORTAADDR9 address_a[9] => ram_block2a29.PORTAADDR9 address_a[9] => ram_block2a30.PORTAADDR9 address_a[9] => ram_block2a31.PORTAADDR9 address_b[0] => ram_block2a0.PORTBADDR address_b[0] => ram_block2a1.PORTBADDR address_b[0] => ram_block2a2.PORTBADDR address_b[0] => ram_block2a3.PORTBADDR address_b[0] => ram_block2a4.PORTBADDR address_b[0] => ram_block2a5.PORTBADDR address_b[0] => ram_block2a6.PORTBADDR address_b[0] => ram_block2a7.PORTBADDR address_b[0] => ram_block2a8.PORTBADDR address_b[0] => ram_block2a9.PORTBADDR address_b[0] => ram_block2a10.PORTBADDR address_b[0] => ram_block2a11.PORTBADDR address_b[0] => ram_block2a12.PORTBADDR address_b[0] => ram_block2a13.PORTBADDR address_b[0] => ram_block2a14.PORTBADDR address_b[0] => ram_block2a15.PORTBADDR address_b[0] => ram_block2a16.PORTBADDR address_b[0] => ram_block2a17.PORTBADDR address_b[0] => ram_block2a18.PORTBADDR address_b[0] => ram_block2a19.PORTBADDR address_b[0] => ram_block2a20.PORTBADDR address_b[0] => ram_block2a21.PORTBADDR address_b[0] => ram_block2a22.PORTBADDR address_b[0] => ram_block2a23.PORTBADDR address_b[0] => ram_block2a24.PORTBADDR address_b[0] => ram_block2a25.PORTBADDR address_b[0] => ram_block2a26.PORTBADDR address_b[0] => ram_block2a27.PORTBADDR address_b[0] => ram_block2a28.PORTBADDR address_b[0] => ram_block2a29.PORTBADDR address_b[0] => ram_block2a30.PORTBADDR address_b[0] => ram_block2a31.PORTBADDR address_b[1] => ram_block2a0.PORTBADDR1 address_b[1] => ram_block2a1.PORTBADDR1 address_b[1] => ram_block2a2.PORTBADDR1 address_b[1] => ram_block2a3.PORTBADDR1 address_b[1] => ram_block2a4.PORTBADDR1 address_b[1] => ram_block2a5.PORTBADDR1 address_b[1] => ram_block2a6.PORTBADDR1 address_b[1] => ram_block2a7.PORTBADDR1 address_b[1] => ram_block2a8.PORTBADDR1 address_b[1] => ram_block2a9.PORTBADDR1 address_b[1] => ram_block2a10.PORTBADDR1 address_b[1] => ram_block2a11.PORTBADDR1 address_b[1] => ram_block2a12.PORTBADDR1 address_b[1] => ram_block2a13.PORTBADDR1 address_b[1] => ram_block2a14.PORTBADDR1 address_b[1] => ram_block2a15.PORTBADDR1 address_b[1] => ram_block2a16.PORTBADDR1 address_b[1] => ram_block2a17.PORTBADDR1 address_b[1] => ram_block2a18.PORTBADDR1 address_b[1] => ram_block2a19.PORTBADDR1 address_b[1] => ram_block2a20.PORTBADDR1 address_b[1] => ram_block2a21.PORTBADDR1 address_b[1] => ram_block2a22.PORTBADDR1 address_b[1] => ram_block2a23.PORTBADDR1 address_b[1] => ram_block2a24.PORTBADDR1 address_b[1] => ram_block2a25.PORTBADDR1 address_b[1] => ram_block2a26.PORTBADDR1 address_b[1] => ram_block2a27.PORTBADDR1 address_b[1] => ram_block2a28.PORTBADDR1 address_b[1] => ram_block2a29.PORTBADDR1 address_b[1] => ram_block2a30.PORTBADDR1 address_b[1] => ram_block2a31.PORTBADDR1 address_b[2] => ram_block2a0.PORTBADDR2 address_b[2] => ram_block2a1.PORTBADDR2 address_b[2] => ram_block2a2.PORTBADDR2 address_b[2] => ram_block2a3.PORTBADDR2 address_b[2] => ram_block2a4.PORTBADDR2 address_b[2] => ram_block2a5.PORTBADDR2 address_b[2] => ram_block2a6.PORTBADDR2 address_b[2] => ram_block2a7.PORTBADDR2 address_b[2] => ram_block2a8.PORTBADDR2 address_b[2] => ram_block2a9.PORTBADDR2 address_b[2] => ram_block2a10.PORTBADDR2 address_b[2] => ram_block2a11.PORTBADDR2 address_b[2] => ram_block2a12.PORTBADDR2 address_b[2] => ram_block2a13.PORTBADDR2 address_b[2] => ram_block2a14.PORTBADDR2 address_b[2] => ram_block2a15.PORTBADDR2 address_b[2] => ram_block2a16.PORTBADDR2 address_b[2] => ram_block2a17.PORTBADDR2 address_b[2] => ram_block2a18.PORTBADDR2 address_b[2] => ram_block2a19.PORTBADDR2 address_b[2] => ram_block2a20.PORTBADDR2 address_b[2] => ram_block2a21.PORTBADDR2 address_b[2] => ram_block2a22.PORTBADDR2 address_b[2] => ram_block2a23.PORTBADDR2 address_b[2] => ram_block2a24.PORTBADDR2 address_b[2] => ram_block2a25.PORTBADDR2 address_b[2] => ram_block2a26.PORTBADDR2 address_b[2] => ram_block2a27.PORTBADDR2 address_b[2] => ram_block2a28.PORTBADDR2 address_b[2] => ram_block2a29.PORTBADDR2 address_b[2] => ram_block2a30.PORTBADDR2 address_b[2] => ram_block2a31.PORTBADDR2 address_b[3] => ram_block2a0.PORTBADDR3 address_b[3] => ram_block2a1.PORTBADDR3 address_b[3] => ram_block2a2.PORTBADDR3 address_b[3] => ram_block2a3.PORTBADDR3 address_b[3] => ram_block2a4.PORTBADDR3 address_b[3] => ram_block2a5.PORTBADDR3 address_b[3] => ram_block2a6.PORTBADDR3 address_b[3] => ram_block2a7.PORTBADDR3 address_b[3] => ram_block2a8.PORTBADDR3 address_b[3] => ram_block2a9.PORTBADDR3 address_b[3] => ram_block2a10.PORTBADDR3 address_b[3] => ram_block2a11.PORTBADDR3 address_b[3] => ram_block2a12.PORTBADDR3 address_b[3] => ram_block2a13.PORTBADDR3 address_b[3] => ram_block2a14.PORTBADDR3 address_b[3] => ram_block2a15.PORTBADDR3 address_b[3] => ram_block2a16.PORTBADDR3 address_b[3] => ram_block2a17.PORTBADDR3 address_b[3] => ram_block2a18.PORTBADDR3 address_b[3] => ram_block2a19.PORTBADDR3 address_b[3] => ram_block2a20.PORTBADDR3 address_b[3] => ram_block2a21.PORTBADDR3 address_b[3] => ram_block2a22.PORTBADDR3 address_b[3] => ram_block2a23.PORTBADDR3 address_b[3] => ram_block2a24.PORTBADDR3 address_b[3] => ram_block2a25.PORTBADDR3 address_b[3] => ram_block2a26.PORTBADDR3 address_b[3] => ram_block2a27.PORTBADDR3 address_b[3] => ram_block2a28.PORTBADDR3 address_b[3] => ram_block2a29.PORTBADDR3 address_b[3] => ram_block2a30.PORTBADDR3 address_b[3] => ram_block2a31.PORTBADDR3 address_b[4] => ram_block2a0.PORTBADDR4 address_b[4] => ram_block2a1.PORTBADDR4 address_b[4] => ram_block2a2.PORTBADDR4 address_b[4] => ram_block2a3.PORTBADDR4 address_b[4] => ram_block2a4.PORTBADDR4 address_b[4] => ram_block2a5.PORTBADDR4 address_b[4] => ram_block2a6.PORTBADDR4 address_b[4] => ram_block2a7.PORTBADDR4 address_b[4] => ram_block2a8.PORTBADDR4 address_b[4] => ram_block2a9.PORTBADDR4 address_b[4] => ram_block2a10.PORTBADDR4 address_b[4] => ram_block2a11.PORTBADDR4 address_b[4] => ram_block2a12.PORTBADDR4 address_b[4] => ram_block2a13.PORTBADDR4 address_b[4] => ram_block2a14.PORTBADDR4 address_b[4] => ram_block2a15.PORTBADDR4 address_b[4] => ram_block2a16.PORTBADDR4 address_b[4] => ram_block2a17.PORTBADDR4 address_b[4] => ram_block2a18.PORTBADDR4 address_b[4] => ram_block2a19.PORTBADDR4 address_b[4] => ram_block2a20.PORTBADDR4 address_b[4] => ram_block2a21.PORTBADDR4 address_b[4] => ram_block2a22.PORTBADDR4 address_b[4] => ram_block2a23.PORTBADDR4 address_b[4] => ram_block2a24.PORTBADDR4 address_b[4] => ram_block2a25.PORTBADDR4 address_b[4] => ram_block2a26.PORTBADDR4 address_b[4] => ram_block2a27.PORTBADDR4 address_b[4] => ram_block2a28.PORTBADDR4 address_b[4] => ram_block2a29.PORTBADDR4 address_b[4] => ram_block2a30.PORTBADDR4 address_b[4] => ram_block2a31.PORTBADDR4 address_b[5] => ram_block2a0.PORTBADDR5 address_b[5] => ram_block2a1.PORTBADDR5 address_b[5] => ram_block2a2.PORTBADDR5 address_b[5] => ram_block2a3.PORTBADDR5 address_b[5] => ram_block2a4.PORTBADDR5 address_b[5] => ram_block2a5.PORTBADDR5 address_b[5] => ram_block2a6.PORTBADDR5 address_b[5] => ram_block2a7.PORTBADDR5 address_b[5] => ram_block2a8.PORTBADDR5 address_b[5] => ram_block2a9.PORTBADDR5 address_b[5] => ram_block2a10.PORTBADDR5 address_b[5] => ram_block2a11.PORTBADDR5 address_b[5] => ram_block2a12.PORTBADDR5 address_b[5] => ram_block2a13.PORTBADDR5 address_b[5] => ram_block2a14.PORTBADDR5 address_b[5] => ram_block2a15.PORTBADDR5 address_b[5] => ram_block2a16.PORTBADDR5 address_b[5] => ram_block2a17.PORTBADDR5 address_b[5] => ram_block2a18.PORTBADDR5 address_b[5] => ram_block2a19.PORTBADDR5 address_b[5] => ram_block2a20.PORTBADDR5 address_b[5] => ram_block2a21.PORTBADDR5 address_b[5] => ram_block2a22.PORTBADDR5 address_b[5] => ram_block2a23.PORTBADDR5 address_b[5] => ram_block2a24.PORTBADDR5 address_b[5] => ram_block2a25.PORTBADDR5 address_b[5] => ram_block2a26.PORTBADDR5 address_b[5] => ram_block2a27.PORTBADDR5 address_b[5] => ram_block2a28.PORTBADDR5 address_b[5] => ram_block2a29.PORTBADDR5 address_b[5] => ram_block2a30.PORTBADDR5 address_b[5] => ram_block2a31.PORTBADDR5 address_b[6] => ram_block2a0.PORTBADDR6 address_b[6] => ram_block2a1.PORTBADDR6 address_b[6] => ram_block2a2.PORTBADDR6 address_b[6] => ram_block2a3.PORTBADDR6 address_b[6] => ram_block2a4.PORTBADDR6 address_b[6] => ram_block2a5.PORTBADDR6 address_b[6] => ram_block2a6.PORTBADDR6 address_b[6] => ram_block2a7.PORTBADDR6 address_b[6] => ram_block2a8.PORTBADDR6 address_b[6] => ram_block2a9.PORTBADDR6 address_b[6] => ram_block2a10.PORTBADDR6 address_b[6] => ram_block2a11.PORTBADDR6 address_b[6] => ram_block2a12.PORTBADDR6 address_b[6] => ram_block2a13.PORTBADDR6 address_b[6] => ram_block2a14.PORTBADDR6 address_b[6] => ram_block2a15.PORTBADDR6 address_b[6] => ram_block2a16.PORTBADDR6 address_b[6] => ram_block2a17.PORTBADDR6 address_b[6] => ram_block2a18.PORTBADDR6 address_b[6] => ram_block2a19.PORTBADDR6 address_b[6] => ram_block2a20.PORTBADDR6 address_b[6] => ram_block2a21.PORTBADDR6 address_b[6] => ram_block2a22.PORTBADDR6 address_b[6] => ram_block2a23.PORTBADDR6 address_b[6] => ram_block2a24.PORTBADDR6 address_b[6] => ram_block2a25.PORTBADDR6 address_b[6] => ram_block2a26.PORTBADDR6 address_b[6] => ram_block2a27.PORTBADDR6 address_b[6] => ram_block2a28.PORTBADDR6 address_b[6] => ram_block2a29.PORTBADDR6 address_b[6] => ram_block2a30.PORTBADDR6 address_b[6] => ram_block2a31.PORTBADDR6 address_b[7] => ram_block2a0.PORTBADDR7 address_b[7] => ram_block2a1.PORTBADDR7 address_b[7] => ram_block2a2.PORTBADDR7 address_b[7] => ram_block2a3.PORTBADDR7 address_b[7] => ram_block2a4.PORTBADDR7 address_b[7] => ram_block2a5.PORTBADDR7 address_b[7] => ram_block2a6.PORTBADDR7 address_b[7] => ram_block2a7.PORTBADDR7 address_b[7] => ram_block2a8.PORTBADDR7 address_b[7] => ram_block2a9.PORTBADDR7 address_b[7] => ram_block2a10.PORTBADDR7 address_b[7] => ram_block2a11.PORTBADDR7 address_b[7] => ram_block2a12.PORTBADDR7 address_b[7] => ram_block2a13.PORTBADDR7 address_b[7] => ram_block2a14.PORTBADDR7 address_b[7] => ram_block2a15.PORTBADDR7 address_b[7] => ram_block2a16.PORTBADDR7 address_b[7] => ram_block2a17.PORTBADDR7 address_b[7] => ram_block2a18.PORTBADDR7 address_b[7] => ram_block2a19.PORTBADDR7 address_b[7] => ram_block2a20.PORTBADDR7 address_b[7] => ram_block2a21.PORTBADDR7 address_b[7] => ram_block2a22.PORTBADDR7 address_b[7] => ram_block2a23.PORTBADDR7 address_b[7] => ram_block2a24.PORTBADDR7 address_b[7] => ram_block2a25.PORTBADDR7 address_b[7] => ram_block2a26.PORTBADDR7 address_b[7] => ram_block2a27.PORTBADDR7 address_b[7] => ram_block2a28.PORTBADDR7 address_b[7] => ram_block2a29.PORTBADDR7 address_b[7] => ram_block2a30.PORTBADDR7 address_b[7] => ram_block2a31.PORTBADDR7 address_b[8] => ram_block2a0.PORTBADDR8 address_b[8] => ram_block2a1.PORTBADDR8 address_b[8] => ram_block2a2.PORTBADDR8 address_b[8] => ram_block2a3.PORTBADDR8 address_b[8] => ram_block2a4.PORTBADDR8 address_b[8] => ram_block2a5.PORTBADDR8 address_b[8] => ram_block2a6.PORTBADDR8 address_b[8] => ram_block2a7.PORTBADDR8 address_b[8] => ram_block2a8.PORTBADDR8 address_b[8] => ram_block2a9.PORTBADDR8 address_b[8] => ram_block2a10.PORTBADDR8 address_b[8] => ram_block2a11.PORTBADDR8 address_b[8] => ram_block2a12.PORTBADDR8 address_b[8] => ram_block2a13.PORTBADDR8 address_b[8] => ram_block2a14.PORTBADDR8 address_b[8] => ram_block2a15.PORTBADDR8 address_b[8] => ram_block2a16.PORTBADDR8 address_b[8] => ram_block2a17.PORTBADDR8 address_b[8] => ram_block2a18.PORTBADDR8 address_b[8] => ram_block2a19.PORTBADDR8 address_b[8] => ram_block2a20.PORTBADDR8 address_b[8] => ram_block2a21.PORTBADDR8 address_b[8] => ram_block2a22.PORTBADDR8 address_b[8] => ram_block2a23.PORTBADDR8 address_b[8] => ram_block2a24.PORTBADDR8 address_b[8] => ram_block2a25.PORTBADDR8 address_b[8] => ram_block2a26.PORTBADDR8 address_b[8] => ram_block2a27.PORTBADDR8 address_b[8] => ram_block2a28.PORTBADDR8 address_b[8] => ram_block2a29.PORTBADDR8 address_b[8] => ram_block2a30.PORTBADDR8 address_b[8] => ram_block2a31.PORTBADDR8 address_b[9] => ram_block2a0.PORTBADDR9 address_b[9] => ram_block2a1.PORTBADDR9 address_b[9] => ram_block2a2.PORTBADDR9 address_b[9] => ram_block2a3.PORTBADDR9 address_b[9] => ram_block2a4.PORTBADDR9 address_b[9] => ram_block2a5.PORTBADDR9 address_b[9] => ram_block2a6.PORTBADDR9 address_b[9] => ram_block2a7.PORTBADDR9 address_b[9] => ram_block2a8.PORTBADDR9 address_b[9] => ram_block2a9.PORTBADDR9 address_b[9] => ram_block2a10.PORTBADDR9 address_b[9] => ram_block2a11.PORTBADDR9 address_b[9] => ram_block2a12.PORTBADDR9 address_b[9] => ram_block2a13.PORTBADDR9 address_b[9] => ram_block2a14.PORTBADDR9 address_b[9] => ram_block2a15.PORTBADDR9 address_b[9] => ram_block2a16.PORTBADDR9 address_b[9] => ram_block2a17.PORTBADDR9 address_b[9] => ram_block2a18.PORTBADDR9 address_b[9] => ram_block2a19.PORTBADDR9 address_b[9] => ram_block2a20.PORTBADDR9 address_b[9] => ram_block2a21.PORTBADDR9 address_b[9] => ram_block2a22.PORTBADDR9 address_b[9] => ram_block2a23.PORTBADDR9 address_b[9] => ram_block2a24.PORTBADDR9 address_b[9] => ram_block2a25.PORTBADDR9 address_b[9] => ram_block2a26.PORTBADDR9 address_b[9] => ram_block2a27.PORTBADDR9 address_b[9] => ram_block2a28.PORTBADDR9 address_b[9] => ram_block2a29.PORTBADDR9 address_b[9] => ram_block2a30.PORTBADDR9 address_b[9] => ram_block2a31.PORTBADDR9 clock0 => ram_block2a0.CLK0 clock0 => ram_block2a1.CLK0 clock0 => ram_block2a2.CLK0 clock0 => ram_block2a3.CLK0 clock0 => ram_block2a4.CLK0 clock0 => ram_block2a5.CLK0 clock0 => ram_block2a6.CLK0 clock0 => ram_block2a7.CLK0 clock0 => ram_block2a8.CLK0 clock0 => ram_block2a9.CLK0 clock0 => ram_block2a10.CLK0 clock0 => ram_block2a11.CLK0 clock0 => ram_block2a12.CLK0 clock0 => ram_block2a13.CLK0 clock0 => ram_block2a14.CLK0 clock0 => ram_block2a15.CLK0 clock0 => ram_block2a16.CLK0 clock0 => ram_block2a17.CLK0 clock0 => ram_block2a18.CLK0 clock0 => ram_block2a19.CLK0 clock0 => ram_block2a20.CLK0 clock0 => ram_block2a21.CLK0 clock0 => ram_block2a22.CLK0 clock0 => ram_block2a23.CLK0 clock0 => ram_block2a24.CLK0 clock0 => ram_block2a25.CLK0 clock0 => ram_block2a26.CLK0 clock0 => ram_block2a27.CLK0 clock0 => ram_block2a28.CLK0 clock0 => ram_block2a29.CLK0 clock0 => ram_block2a30.CLK0 clock0 => ram_block2a31.CLK0 clock1 => ram_block2a0.CLK1 clock1 => ram_block2a1.CLK1 clock1 => ram_block2a2.CLK1 clock1 => ram_block2a3.CLK1 clock1 => ram_block2a4.CLK1 clock1 => ram_block2a5.CLK1 clock1 => ram_block2a6.CLK1 clock1 => ram_block2a7.CLK1 clock1 => ram_block2a8.CLK1 clock1 => ram_block2a9.CLK1 clock1 => ram_block2a10.CLK1 clock1 => ram_block2a11.CLK1 clock1 => ram_block2a12.CLK1 clock1 => ram_block2a13.CLK1 clock1 => ram_block2a14.CLK1 clock1 => ram_block2a15.CLK1 clock1 => ram_block2a16.CLK1 clock1 => ram_block2a17.CLK1 clock1 => ram_block2a18.CLK1 clock1 => ram_block2a19.CLK1 clock1 => ram_block2a20.CLK1 clock1 => ram_block2a21.CLK1 clock1 => ram_block2a22.CLK1 clock1 => ram_block2a23.CLK1 clock1 => ram_block2a24.CLK1 clock1 => ram_block2a25.CLK1 clock1 => ram_block2a26.CLK1 clock1 => ram_block2a27.CLK1 clock1 => ram_block2a28.CLK1 clock1 => ram_block2a29.CLK1 clock1 => ram_block2a30.CLK1 clock1 => ram_block2a31.CLK1 clocken0 => ram_block2a0.ENA0 clocken0 => ram_block2a1.ENA0 clocken0 => ram_block2a2.ENA0 clocken0 => ram_block2a3.ENA0 clocken0 => ram_block2a4.ENA0 clocken0 => ram_block2a5.ENA0 clocken0 => ram_block2a6.ENA0 clocken0 => ram_block2a7.ENA0 clocken0 => ram_block2a8.ENA0 clocken0 => ram_block2a9.ENA0 clocken0 => ram_block2a10.ENA0 clocken0 => ram_block2a11.ENA0 clocken0 => ram_block2a12.ENA0 clocken0 => ram_block2a13.ENA0 clocken0 => ram_block2a14.ENA0 clocken0 => ram_block2a15.ENA0 clocken0 => ram_block2a16.ENA0 clocken0 => ram_block2a17.ENA0 clocken0 => ram_block2a18.ENA0 clocken0 => ram_block2a19.ENA0 clocken0 => ram_block2a20.ENA0 clocken0 => ram_block2a21.ENA0 clocken0 => ram_block2a22.ENA0 clocken0 => ram_block2a23.ENA0 clocken0 => ram_block2a24.ENA0 clocken0 => ram_block2a25.ENA0 clocken0 => ram_block2a26.ENA0 clocken0 => ram_block2a27.ENA0 clocken0 => ram_block2a28.ENA0 clocken0 => ram_block2a29.ENA0 clocken0 => ram_block2a30.ENA0 clocken0 => ram_block2a31.ENA0 clocken1 => ram_block2a0.ENA1 clocken1 => ram_block2a1.ENA1 clocken1 => ram_block2a2.ENA1 clocken1 => ram_block2a3.ENA1 clocken1 => ram_block2a4.ENA1 clocken1 => ram_block2a5.ENA1 clocken1 => ram_block2a6.ENA1 clocken1 => ram_block2a7.ENA1 clocken1 => ram_block2a8.ENA1 clocken1 => ram_block2a9.ENA1 clocken1 => ram_block2a10.ENA1 clocken1 => ram_block2a11.ENA1 clocken1 => ram_block2a12.ENA1 clocken1 => ram_block2a13.ENA1 clocken1 => ram_block2a14.ENA1 clocken1 => ram_block2a15.ENA1 clocken1 => ram_block2a16.ENA1 clocken1 => ram_block2a17.ENA1 clocken1 => ram_block2a18.ENA1 clocken1 => ram_block2a19.ENA1 clocken1 => ram_block2a20.ENA1 clocken1 => ram_block2a21.ENA1 clocken1 => ram_block2a22.ENA1 clocken1 => ram_block2a23.ENA1 clocken1 => ram_block2a24.ENA1 clocken1 => ram_block2a25.ENA1 clocken1 => ram_block2a26.ENA1 clocken1 => ram_block2a27.ENA1 clocken1 => ram_block2a28.ENA1 clocken1 => ram_block2a29.ENA1 clocken1 => ram_block2a30.ENA1 clocken1 => ram_block2a31.ENA1 data_a[0] => ram_block2a0.PORTADATAIN data_a[1] => ram_block2a1.PORTADATAIN data_a[2] => ram_block2a2.PORTADATAIN data_a[3] => ram_block2a3.PORTADATAIN data_a[4] => ram_block2a4.PORTADATAIN data_a[5] => ram_block2a5.PORTADATAIN data_a[6] => ram_block2a6.PORTADATAIN data_a[7] => ram_block2a7.PORTADATAIN data_a[8] => ram_block2a8.PORTADATAIN data_a[9] => ram_block2a9.PORTADATAIN data_a[10] => ram_block2a10.PORTADATAIN data_a[11] => ram_block2a11.PORTADATAIN data_a[12] => ram_block2a12.PORTADATAIN data_a[13] => ram_block2a13.PORTADATAIN data_a[14] => ram_block2a14.PORTADATAIN data_a[15] => ram_block2a15.PORTADATAIN data_a[16] => ram_block2a16.PORTADATAIN data_a[17] => ram_block2a17.PORTADATAIN data_a[18] => ram_block2a18.PORTADATAIN data_a[19] => ram_block2a19.PORTADATAIN data_a[20] => ram_block2a20.PORTADATAIN data_a[21] => ram_block2a21.PORTADATAIN data_a[22] => ram_block2a22.PORTADATAIN data_a[23] => ram_block2a23.PORTADATAIN data_a[24] => ram_block2a24.PORTADATAIN data_a[25] => ram_block2a25.PORTADATAIN data_a[26] => ram_block2a26.PORTADATAIN data_a[27] => ram_block2a27.PORTADATAIN data_a[28] => ram_block2a28.PORTADATAIN data_a[29] => ram_block2a29.PORTADATAIN data_a[30] => ram_block2a30.PORTADATAIN data_a[31] => ram_block2a31.PORTADATAIN data_b[0] => ram_block2a0.PORTBDATAIN data_b[1] => ram_block2a1.PORTBDATAIN data_b[2] => ram_block2a2.PORTBDATAIN data_b[3] => ram_block2a3.PORTBDATAIN data_b[4] => ram_block2a4.PORTBDATAIN data_b[5] => ram_block2a5.PORTBDATAIN data_b[6] => ram_block2a6.PORTBDATAIN data_b[7] => ram_block2a7.PORTBDATAIN data_b[8] => ram_block2a8.PORTBDATAIN data_b[9] => ram_block2a9.PORTBDATAIN data_b[10] => ram_block2a10.PORTBDATAIN data_b[11] => ram_block2a11.PORTBDATAIN data_b[12] => ram_block2a12.PORTBDATAIN data_b[13] => ram_block2a13.PORTBDATAIN data_b[14] => ram_block2a14.PORTBDATAIN data_b[15] => ram_block2a15.PORTBDATAIN data_b[16] => ram_block2a16.PORTBDATAIN data_b[17] => ram_block2a17.PORTBDATAIN data_b[18] => ram_block2a18.PORTBDATAIN data_b[19] => ram_block2a19.PORTBDATAIN data_b[20] => ram_block2a20.PORTBDATAIN data_b[21] => ram_block2a21.PORTBDATAIN data_b[22] => ram_block2a22.PORTBDATAIN data_b[23] => ram_block2a23.PORTBDATAIN data_b[24] => ram_block2a24.PORTBDATAIN data_b[25] => ram_block2a25.PORTBDATAIN data_b[26] => ram_block2a26.PORTBDATAIN data_b[27] => ram_block2a27.PORTBDATAIN data_b[28] => ram_block2a28.PORTBDATAIN data_b[29] => ram_block2a29.PORTBDATAIN data_b[30] => ram_block2a30.PORTBDATAIN data_b[31] => ram_block2a31.PORTBDATAIN q_a[0] <= ram_block2a0.PORTADATAOUT q_a[1] <= ram_block2a1.PORTADATAOUT q_a[2] <= ram_block2a2.PORTADATAOUT q_a[3] <= ram_block2a3.PORTADATAOUT q_a[4] <= ram_block2a4.PORTADATAOUT q_a[5] <= ram_block2a5.PORTADATAOUT q_a[6] <= ram_block2a6.PORTADATAOUT q_a[7] <= ram_block2a7.PORTADATAOUT q_a[8] <= ram_block2a8.PORTADATAOUT q_a[9] <= ram_block2a9.PORTADATAOUT q_a[10] <= ram_block2a10.PORTADATAOUT q_a[11] <= ram_block2a11.PORTADATAOUT q_a[12] <= ram_block2a12.PORTADATAOUT q_a[13] <= ram_block2a13.PORTADATAOUT q_a[14] <= ram_block2a14.PORTADATAOUT q_a[15] <= ram_block2a15.PORTADATAOUT q_a[16] <= ram_block2a16.PORTADATAOUT q_a[17] <= ram_block2a17.PORTADATAOUT q_a[18] <= ram_block2a18.PORTADATAOUT q_a[19] <= ram_block2a19.PORTADATAOUT q_a[20] <= ram_block2a20.PORTADATAOUT q_a[21] <= ram_block2a21.PORTADATAOUT q_a[22] <= ram_block2a22.PORTADATAOUT q_a[23] <= ram_block2a23.PORTADATAOUT q_a[24] <= ram_block2a24.PORTADATAOUT q_a[25] <= ram_block2a25.PORTADATAOUT q_a[26] <= ram_block2a26.PORTADATAOUT q_a[27] <= ram_block2a27.PORTADATAOUT q_a[28] <= ram_block2a28.PORTADATAOUT q_a[29] <= ram_block2a29.PORTADATAOUT q_a[30] <= ram_block2a30.PORTADATAOUT q_a[31] <= ram_block2a31.PORTADATAOUT q_b[0] <= ram_block2a0.PORTBDATAOUT q_b[1] <= ram_block2a1.PORTBDATAOUT q_b[2] <= ram_block2a2.PORTBDATAOUT q_b[3] <= ram_block2a3.PORTBDATAOUT q_b[4] <= ram_block2a4.PORTBDATAOUT q_b[5] <= ram_block2a5.PORTBDATAOUT q_b[6] <= ram_block2a6.PORTBDATAOUT q_b[7] <= ram_block2a7.PORTBDATAOUT q_b[8] <= ram_block2a8.PORTBDATAOUT q_b[9] <= ram_block2a9.PORTBDATAOUT q_b[10] <= ram_block2a10.PORTBDATAOUT q_b[11] <= ram_block2a11.PORTBDATAOUT q_b[12] <= ram_block2a12.PORTBDATAOUT q_b[13] <= ram_block2a13.PORTBDATAOUT q_b[14] <= ram_block2a14.PORTBDATAOUT q_b[15] <= ram_block2a15.PORTBDATAOUT q_b[16] <= ram_block2a16.PORTBDATAOUT q_b[17] <= ram_block2a17.PORTBDATAOUT q_b[18] <= ram_block2a18.PORTBDATAOUT q_b[19] <= ram_block2a19.PORTBDATAOUT q_b[20] <= ram_block2a20.PORTBDATAOUT q_b[21] <= ram_block2a21.PORTBDATAOUT q_b[22] <= ram_block2a22.PORTBDATAOUT q_b[23] <= ram_block2a23.PORTBDATAOUT q_b[24] <= ram_block2a24.PORTBDATAOUT q_b[25] <= ram_block2a25.PORTBDATAOUT q_b[26] <= ram_block2a26.PORTBDATAOUT q_b[27] <= ram_block2a27.PORTBDATAOUT q_b[28] <= ram_block2a28.PORTBDATAOUT q_b[29] <= ram_block2a29.PORTBDATAOUT q_b[30] <= ram_block2a30.PORTBDATAOUT q_b[31] <= ram_block2a31.PORTBDATAOUT wren_a => ram_block2a0.PORTAWE wren_a => ram_block2a1.PORTAWE wren_a => ram_block2a2.PORTAWE wren_a => ram_block2a3.PORTAWE wren_a => ram_block2a4.PORTAWE wren_a => ram_block2a5.PORTAWE wren_a => ram_block2a6.PORTAWE wren_a => ram_block2a7.PORTAWE wren_a => ram_block2a8.PORTAWE wren_a => ram_block2a9.PORTAWE wren_a => ram_block2a10.PORTAWE wren_a => ram_block2a11.PORTAWE wren_a => ram_block2a12.PORTAWE wren_a => ram_block2a13.PORTAWE wren_a => ram_block2a14.PORTAWE wren_a => ram_block2a15.PORTAWE wren_a => ram_block2a16.PORTAWE wren_a => ram_block2a17.PORTAWE wren_a => ram_block2a18.PORTAWE wren_a => ram_block2a19.PORTAWE wren_a => ram_block2a20.PORTAWE wren_a => ram_block2a21.PORTAWE wren_a => ram_block2a22.PORTAWE wren_a => ram_block2a23.PORTAWE wren_a => ram_block2a24.PORTAWE wren_a => ram_block2a25.PORTAWE wren_a => ram_block2a26.PORTAWE wren_a => ram_block2a27.PORTAWE wren_a => ram_block2a28.PORTAWE wren_a => ram_block2a29.PORTAWE wren_a => ram_block2a30.PORTAWE wren_a => ram_block2a31.PORTAWE wren_b => ram_block2a0.PORTBRE wren_b => ram_block2a1.PORTBRE wren_b => ram_block2a2.PORTBRE wren_b => ram_block2a3.PORTBRE wren_b => ram_block2a4.PORTBRE wren_b => ram_block2a5.PORTBRE wren_b => ram_block2a6.PORTBRE wren_b => ram_block2a7.PORTBRE wren_b => ram_block2a8.PORTBRE wren_b => ram_block2a9.PORTBRE wren_b => ram_block2a10.PORTBRE wren_b => ram_block2a11.PORTBRE wren_b => ram_block2a12.PORTBRE wren_b => ram_block2a13.PORTBRE wren_b => ram_block2a14.PORTBRE wren_b => ram_block2a15.PORTBRE wren_b => ram_block2a16.PORTBRE wren_b => ram_block2a17.PORTBRE wren_b => ram_block2a18.PORTBRE wren_b => ram_block2a19.PORTBRE wren_b => ram_block2a20.PORTBRE wren_b => ram_block2a21.PORTBRE wren_b => ram_block2a22.PORTBRE wren_b => ram_block2a23.PORTBRE wren_b => ram_block2a24.PORTBRE wren_b => ram_block2a25.PORTBRE wren_b => ram_block2a26.PORTBRE wren_b => ram_block2a27.PORTBRE wren_b => ram_block2a28.PORTBRE wren_b => ram_block2a29.PORTBRE wren_b => ram_block2a30.PORTBRE wren_b => ram_block2a31.PORTBRE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag data[0] => data[0]~19.IN1 data[1] => data[1]~18.IN1 data[2] => data[2]~17.IN1 data[3] => data[3]~16.IN1 data[4] => data[4]~15.IN1 data[5] => data[5]~14.IN1 data[6] => data[6]~13.IN1 data[7] => data[7]~12.IN1 data[8] => data[8]~11.IN1 data[9] => data[9]~10.IN1 data[10] => data[10]~9.IN1 data[11] => data[11]~8.IN1 data[12] => data[12]~7.IN1 data[13] => data[13]~6.IN1 data[14] => data[14]~5.IN1 data[15] => data[15]~4.IN1 data[16] => data[16]~3.IN1 data[17] => data[17]~2.IN1 data[18] => data[18]~1.IN1 data[19] => data[19]~0.IN1 rdaddress[0] => rdaddress[0]~6.IN1 rdaddress[1] => rdaddress[1]~5.IN1 rdaddress[2] => rdaddress[2]~4.IN1 rdaddress[3] => rdaddress[3]~3.IN1 rdaddress[4] => rdaddress[4]~2.IN1 rdaddress[5] => rdaddress[5]~1.IN1 rdaddress[6] => rdaddress[6]~0.IN1 rdclken => rdclken~0.IN1 rdclock => rdclock~0.IN1 wraddress[0] => wraddress[0]~6.IN1 wraddress[1] => wraddress[1]~5.IN1 wraddress[2] => wraddress[2]~4.IN1 wraddress[3] => wraddress[3]~3.IN1 wraddress[4] => wraddress[4]~2.IN1 wraddress[5] => wraddress[5]~1.IN1 wraddress[6] => wraddress[6]~0.IN1 wrclock => wrclock~0.IN1 wren => wren~0.IN1 q[0] <= altsyncram:the_altsyncram.q_b q[1] <= altsyncram:the_altsyncram.q_b q[2] <= altsyncram:the_altsyncram.q_b q[3] <= altsyncram:the_altsyncram.q_b q[4] <= altsyncram:the_altsyncram.q_b q[5] <= altsyncram:the_altsyncram.q_b q[6] <= altsyncram:the_altsyncram.q_b q[7] <= altsyncram:the_altsyncram.q_b q[8] <= altsyncram:the_altsyncram.q_b q[9] <= altsyncram:the_altsyncram.q_b q[10] <= altsyncram:the_altsyncram.q_b q[11] <= altsyncram:the_altsyncram.q_b q[12] <= altsyncram:the_altsyncram.q_b q[13] <= altsyncram:the_altsyncram.q_b q[14] <= altsyncram:the_altsyncram.q_b q[15] <= altsyncram:the_altsyncram.q_b q[16] <= altsyncram:the_altsyncram.q_b q[17] <= altsyncram:the_altsyncram.q_b q[18] <= altsyncram:the_altsyncram.q_b q[19] <= altsyncram:the_altsyncram.q_b |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram wren_a => altsyncram_73e1:auto_generated.wren_a rden_a => ~NO_FANOUT~ wren_b => ~NO_FANOUT~ rden_b => ~NO_FANOUT~ data_a[0] => altsyncram_73e1:auto_generated.data_a[0] data_a[1] => altsyncram_73e1:auto_generated.data_a[1] data_a[2] => altsyncram_73e1:auto_generated.data_a[2] data_a[3] => altsyncram_73e1:auto_generated.data_a[3] data_a[4] => altsyncram_73e1:auto_generated.data_a[4] data_a[5] => altsyncram_73e1:auto_generated.data_a[5] data_a[6] => altsyncram_73e1:auto_generated.data_a[6] data_a[7] => altsyncram_73e1:auto_generated.data_a[7] data_a[8] => altsyncram_73e1:auto_generated.data_a[8] data_a[9] => altsyncram_73e1:auto_generated.data_a[9] data_a[10] => altsyncram_73e1:auto_generated.data_a[10] data_a[11] => altsyncram_73e1:auto_generated.data_a[11] data_a[12] => altsyncram_73e1:auto_generated.data_a[12] data_a[13] => altsyncram_73e1:auto_generated.data_a[13] data_a[14] => altsyncram_73e1:auto_generated.data_a[14] data_a[15] => altsyncram_73e1:auto_generated.data_a[15] data_a[16] => altsyncram_73e1:auto_generated.data_a[16] data_a[17] => altsyncram_73e1:auto_generated.data_a[17] data_a[18] => altsyncram_73e1:auto_generated.data_a[18] data_a[19] => altsyncram_73e1:auto_generated.data_a[19] data_b[0] => ~NO_FANOUT~ data_b[1] => ~NO_FANOUT~ data_b[2] => ~NO_FANOUT~ data_b[3] => ~NO_FANOUT~ data_b[4] => ~NO_FANOUT~ data_b[5] => ~NO_FANOUT~ data_b[6] => ~NO_FANOUT~ data_b[7] => ~NO_FANOUT~ data_b[8] => ~NO_FANOUT~ data_b[9] => ~NO_FANOUT~ data_b[10] => ~NO_FANOUT~ data_b[11] => ~NO_FANOUT~ data_b[12] => ~NO_FANOUT~ data_b[13] => ~NO_FANOUT~ data_b[14] => ~NO_FANOUT~ data_b[15] => ~NO_FANOUT~ data_b[16] => ~NO_FANOUT~ data_b[17] => ~NO_FANOUT~ data_b[18] => ~NO_FANOUT~ data_b[19] => ~NO_FANOUT~ address_a[0] => altsyncram_73e1:auto_generated.address_a[0] address_a[1] => altsyncram_73e1:auto_generated.address_a[1] address_a[2] => altsyncram_73e1:auto_generated.address_a[2] address_a[3] => altsyncram_73e1:auto_generated.address_a[3] address_a[4] => altsyncram_73e1:auto_generated.address_a[4] address_a[5] => altsyncram_73e1:auto_generated.address_a[5] address_a[6] => altsyncram_73e1:auto_generated.address_a[6] address_b[0] => altsyncram_73e1:auto_generated.address_b[0] address_b[1] => altsyncram_73e1:auto_generated.address_b[1] address_b[2] => altsyncram_73e1:auto_generated.address_b[2] address_b[3] => altsyncram_73e1:auto_generated.address_b[3] address_b[4] => altsyncram_73e1:auto_generated.address_b[4] address_b[5] => altsyncram_73e1:auto_generated.address_b[5] address_b[6] => altsyncram_73e1:auto_generated.address_b[6] addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_73e1:auto_generated.clock0 clock1 => altsyncram_73e1:auto_generated.clock1 clocken0 => ~NO_FANOUT~ clocken1 => altsyncram_73e1:auto_generated.clocken1 clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= q_a[1] <= q_a[2] <= q_a[3] <= q_a[4] <= q_a[5] <= q_a[6] <= q_a[7] <= q_a[8] <= q_a[9] <= q_a[10] <= q_a[11] <= q_a[12] <= q_a[13] <= q_a[14] <= q_a[15] <= q_a[16] <= q_a[17] <= q_a[18] <= q_a[19] <= q_b[0] <= altsyncram_73e1:auto_generated.q_b[0] q_b[1] <= altsyncram_73e1:auto_generated.q_b[1] q_b[2] <= altsyncram_73e1:auto_generated.q_b[2] q_b[3] <= altsyncram_73e1:auto_generated.q_b[3] q_b[4] <= altsyncram_73e1:auto_generated.q_b[4] q_b[5] <= altsyncram_73e1:auto_generated.q_b[5] q_b[6] <= altsyncram_73e1:auto_generated.q_b[6] q_b[7] <= altsyncram_73e1:auto_generated.q_b[7] q_b[8] <= altsyncram_73e1:auto_generated.q_b[8] q_b[9] <= altsyncram_73e1:auto_generated.q_b[9] q_b[10] <= altsyncram_73e1:auto_generated.q_b[10] q_b[11] <= altsyncram_73e1:auto_generated.q_b[11] q_b[12] <= altsyncram_73e1:auto_generated.q_b[12] q_b[13] <= altsyncram_73e1:auto_generated.q_b[13] q_b[14] <= altsyncram_73e1:auto_generated.q_b[14] q_b[15] <= altsyncram_73e1:auto_generated.q_b[15] q_b[16] <= altsyncram_73e1:auto_generated.q_b[16] q_b[17] <= altsyncram_73e1:auto_generated.q_b[17] q_b[18] <= altsyncram_73e1:auto_generated.q_b[18] q_b[19] <= altsyncram_73e1:auto_generated.q_b[19] eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_73e1:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[0] => ram_block1a8.PORTAADDR address_a[0] => ram_block1a9.PORTAADDR address_a[0] => ram_block1a10.PORTAADDR address_a[0] => ram_block1a11.PORTAADDR address_a[0] => ram_block1a12.PORTAADDR address_a[0] => ram_block1a13.PORTAADDR address_a[0] => ram_block1a14.PORTAADDR address_a[0] => ram_block1a15.PORTAADDR address_a[0] => ram_block1a16.PORTAADDR address_a[0] => ram_block1a17.PORTAADDR address_a[0] => ram_block1a18.PORTAADDR address_a[0] => ram_block1a19.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[1] => ram_block1a8.PORTAADDR1 address_a[1] => ram_block1a9.PORTAADDR1 address_a[1] => ram_block1a10.PORTAADDR1 address_a[1] => ram_block1a11.PORTAADDR1 address_a[1] => ram_block1a12.PORTAADDR1 address_a[1] => ram_block1a13.PORTAADDR1 address_a[1] => ram_block1a14.PORTAADDR1 address_a[1] => ram_block1a15.PORTAADDR1 address_a[1] => ram_block1a16.PORTAADDR1 address_a[1] => ram_block1a17.PORTAADDR1 address_a[1] => ram_block1a18.PORTAADDR1 address_a[1] => ram_block1a19.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[2] => ram_block1a8.PORTAADDR2 address_a[2] => ram_block1a9.PORTAADDR2 address_a[2] => ram_block1a10.PORTAADDR2 address_a[2] => ram_block1a11.PORTAADDR2 address_a[2] => ram_block1a12.PORTAADDR2 address_a[2] => ram_block1a13.PORTAADDR2 address_a[2] => ram_block1a14.PORTAADDR2 address_a[2] => ram_block1a15.PORTAADDR2 address_a[2] => ram_block1a16.PORTAADDR2 address_a[2] => ram_block1a17.PORTAADDR2 address_a[2] => ram_block1a18.PORTAADDR2 address_a[2] => ram_block1a19.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[3] => ram_block1a8.PORTAADDR3 address_a[3] => ram_block1a9.PORTAADDR3 address_a[3] => ram_block1a10.PORTAADDR3 address_a[3] => ram_block1a11.PORTAADDR3 address_a[3] => ram_block1a12.PORTAADDR3 address_a[3] => ram_block1a13.PORTAADDR3 address_a[3] => ram_block1a14.PORTAADDR3 address_a[3] => ram_block1a15.PORTAADDR3 address_a[3] => ram_block1a16.PORTAADDR3 address_a[3] => ram_block1a17.PORTAADDR3 address_a[3] => ram_block1a18.PORTAADDR3 address_a[3] => ram_block1a19.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[4] => ram_block1a8.PORTAADDR4 address_a[4] => ram_block1a9.PORTAADDR4 address_a[4] => ram_block1a10.PORTAADDR4 address_a[4] => ram_block1a11.PORTAADDR4 address_a[4] => ram_block1a12.PORTAADDR4 address_a[4] => ram_block1a13.PORTAADDR4 address_a[4] => ram_block1a14.PORTAADDR4 address_a[4] => ram_block1a15.PORTAADDR4 address_a[4] => ram_block1a16.PORTAADDR4 address_a[4] => ram_block1a17.PORTAADDR4 address_a[4] => ram_block1a18.PORTAADDR4 address_a[4] => ram_block1a19.PORTAADDR4 address_a[5] => ram_block1a0.PORTAADDR5 address_a[5] => ram_block1a1.PORTAADDR5 address_a[5] => ram_block1a2.PORTAADDR5 address_a[5] => ram_block1a3.PORTAADDR5 address_a[5] => ram_block1a4.PORTAADDR5 address_a[5] => ram_block1a5.PORTAADDR5 address_a[5] => ram_block1a6.PORTAADDR5 address_a[5] => ram_block1a7.PORTAADDR5 address_a[5] => ram_block1a8.PORTAADDR5 address_a[5] => ram_block1a9.PORTAADDR5 address_a[5] => ram_block1a10.PORTAADDR5 address_a[5] => ram_block1a11.PORTAADDR5 address_a[5] => ram_block1a12.PORTAADDR5 address_a[5] => ram_block1a13.PORTAADDR5 address_a[5] => ram_block1a14.PORTAADDR5 address_a[5] => ram_block1a15.PORTAADDR5 address_a[5] => ram_block1a16.PORTAADDR5 address_a[5] => ram_block1a17.PORTAADDR5 address_a[5] => ram_block1a18.PORTAADDR5 address_a[5] => ram_block1a19.PORTAADDR5 address_a[6] => ram_block1a0.PORTAADDR6 address_a[6] => ram_block1a1.PORTAADDR6 address_a[6] => ram_block1a2.PORTAADDR6 address_a[6] => ram_block1a3.PORTAADDR6 address_a[6] => ram_block1a4.PORTAADDR6 address_a[6] => ram_block1a5.PORTAADDR6 address_a[6] => ram_block1a6.PORTAADDR6 address_a[6] => ram_block1a7.PORTAADDR6 address_a[6] => ram_block1a8.PORTAADDR6 address_a[6] => ram_block1a9.PORTAADDR6 address_a[6] => ram_block1a10.PORTAADDR6 address_a[6] => ram_block1a11.PORTAADDR6 address_a[6] => ram_block1a12.PORTAADDR6 address_a[6] => ram_block1a13.PORTAADDR6 address_a[6] => ram_block1a14.PORTAADDR6 address_a[6] => ram_block1a15.PORTAADDR6 address_a[6] => ram_block1a16.PORTAADDR6 address_a[6] => ram_block1a17.PORTAADDR6 address_a[6] => ram_block1a18.PORTAADDR6 address_a[6] => ram_block1a19.PORTAADDR6 address_b[0] => ram_block1a0.PORTBADDR address_b[0] => ram_block1a1.PORTBADDR address_b[0] => ram_block1a2.PORTBADDR address_b[0] => ram_block1a3.PORTBADDR address_b[0] => ram_block1a4.PORTBADDR address_b[0] => ram_block1a5.PORTBADDR address_b[0] => ram_block1a6.PORTBADDR address_b[0] => ram_block1a7.PORTBADDR address_b[0] => ram_block1a8.PORTBADDR address_b[0] => ram_block1a9.PORTBADDR address_b[0] => ram_block1a10.PORTBADDR address_b[0] => ram_block1a11.PORTBADDR address_b[0] => ram_block1a12.PORTBADDR address_b[0] => ram_block1a13.PORTBADDR address_b[0] => ram_block1a14.PORTBADDR address_b[0] => ram_block1a15.PORTBADDR address_b[0] => ram_block1a16.PORTBADDR address_b[0] => ram_block1a17.PORTBADDR address_b[0] => ram_block1a18.PORTBADDR address_b[0] => ram_block1a19.PORTBADDR address_b[1] => ram_block1a0.PORTBADDR1 address_b[1] => ram_block1a1.PORTBADDR1 address_b[1] => ram_block1a2.PORTBADDR1 address_b[1] => ram_block1a3.PORTBADDR1 address_b[1] => ram_block1a4.PORTBADDR1 address_b[1] => ram_block1a5.PORTBADDR1 address_b[1] => ram_block1a6.PORTBADDR1 address_b[1] => ram_block1a7.PORTBADDR1 address_b[1] => ram_block1a8.PORTBADDR1 address_b[1] => ram_block1a9.PORTBADDR1 address_b[1] => ram_block1a10.PORTBADDR1 address_b[1] => ram_block1a11.PORTBADDR1 address_b[1] => ram_block1a12.PORTBADDR1 address_b[1] => ram_block1a13.PORTBADDR1 address_b[1] => ram_block1a14.PORTBADDR1 address_b[1] => ram_block1a15.PORTBADDR1 address_b[1] => ram_block1a16.PORTBADDR1 address_b[1] => ram_block1a17.PORTBADDR1 address_b[1] => ram_block1a18.PORTBADDR1 address_b[1] => ram_block1a19.PORTBADDR1 address_b[2] => ram_block1a0.PORTBADDR2 address_b[2] => ram_block1a1.PORTBADDR2 address_b[2] => ram_block1a2.PORTBADDR2 address_b[2] => ram_block1a3.PORTBADDR2 address_b[2] => ram_block1a4.PORTBADDR2 address_b[2] => ram_block1a5.PORTBADDR2 address_b[2] => ram_block1a6.PORTBADDR2 address_b[2] => ram_block1a7.PORTBADDR2 address_b[2] => ram_block1a8.PORTBADDR2 address_b[2] => ram_block1a9.PORTBADDR2 address_b[2] => ram_block1a10.PORTBADDR2 address_b[2] => ram_block1a11.PORTBADDR2 address_b[2] => ram_block1a12.PORTBADDR2 address_b[2] => ram_block1a13.PORTBADDR2 address_b[2] => ram_block1a14.PORTBADDR2 address_b[2] => ram_block1a15.PORTBADDR2 address_b[2] => ram_block1a16.PORTBADDR2 address_b[2] => ram_block1a17.PORTBADDR2 address_b[2] => ram_block1a18.PORTBADDR2 address_b[2] => ram_block1a19.PORTBADDR2 address_b[3] => ram_block1a0.PORTBADDR3 address_b[3] => ram_block1a1.PORTBADDR3 address_b[3] => ram_block1a2.PORTBADDR3 address_b[3] => ram_block1a3.PORTBADDR3 address_b[3] => ram_block1a4.PORTBADDR3 address_b[3] => ram_block1a5.PORTBADDR3 address_b[3] => ram_block1a6.PORTBADDR3 address_b[3] => ram_block1a7.PORTBADDR3 address_b[3] => ram_block1a8.PORTBADDR3 address_b[3] => ram_block1a9.PORTBADDR3 address_b[3] => ram_block1a10.PORTBADDR3 address_b[3] => ram_block1a11.PORTBADDR3 address_b[3] => ram_block1a12.PORTBADDR3 address_b[3] => ram_block1a13.PORTBADDR3 address_b[3] => ram_block1a14.PORTBADDR3 address_b[3] => ram_block1a15.PORTBADDR3 address_b[3] => ram_block1a16.PORTBADDR3 address_b[3] => ram_block1a17.PORTBADDR3 address_b[3] => ram_block1a18.PORTBADDR3 address_b[3] => ram_block1a19.PORTBADDR3 address_b[4] => ram_block1a0.PORTBADDR4 address_b[4] => ram_block1a1.PORTBADDR4 address_b[4] => ram_block1a2.PORTBADDR4 address_b[4] => ram_block1a3.PORTBADDR4 address_b[4] => ram_block1a4.PORTBADDR4 address_b[4] => ram_block1a5.PORTBADDR4 address_b[4] => ram_block1a6.PORTBADDR4 address_b[4] => ram_block1a7.PORTBADDR4 address_b[4] => ram_block1a8.PORTBADDR4 address_b[4] => ram_block1a9.PORTBADDR4 address_b[4] => ram_block1a10.PORTBADDR4 address_b[4] => ram_block1a11.PORTBADDR4 address_b[4] => ram_block1a12.PORTBADDR4 address_b[4] => ram_block1a13.PORTBADDR4 address_b[4] => ram_block1a14.PORTBADDR4 address_b[4] => ram_block1a15.PORTBADDR4 address_b[4] => ram_block1a16.PORTBADDR4 address_b[4] => ram_block1a17.PORTBADDR4 address_b[4] => ram_block1a18.PORTBADDR4 address_b[4] => ram_block1a19.PORTBADDR4 address_b[5] => ram_block1a0.PORTBADDR5 address_b[5] => ram_block1a1.PORTBADDR5 address_b[5] => ram_block1a2.PORTBADDR5 address_b[5] => ram_block1a3.PORTBADDR5 address_b[5] => ram_block1a4.PORTBADDR5 address_b[5] => ram_block1a5.PORTBADDR5 address_b[5] => ram_block1a6.PORTBADDR5 address_b[5] => ram_block1a7.PORTBADDR5 address_b[5] => ram_block1a8.PORTBADDR5 address_b[5] => ram_block1a9.PORTBADDR5 address_b[5] => ram_block1a10.PORTBADDR5 address_b[5] => ram_block1a11.PORTBADDR5 address_b[5] => ram_block1a12.PORTBADDR5 address_b[5] => ram_block1a13.PORTBADDR5 address_b[5] => ram_block1a14.PORTBADDR5 address_b[5] => ram_block1a15.PORTBADDR5 address_b[5] => ram_block1a16.PORTBADDR5 address_b[5] => ram_block1a17.PORTBADDR5 address_b[5] => ram_block1a18.PORTBADDR5 address_b[5] => ram_block1a19.PORTBADDR5 address_b[6] => ram_block1a0.PORTBADDR6 address_b[6] => ram_block1a1.PORTBADDR6 address_b[6] => ram_block1a2.PORTBADDR6 address_b[6] => ram_block1a3.PORTBADDR6 address_b[6] => ram_block1a4.PORTBADDR6 address_b[6] => ram_block1a5.PORTBADDR6 address_b[6] => ram_block1a6.PORTBADDR6 address_b[6] => ram_block1a7.PORTBADDR6 address_b[6] => ram_block1a8.PORTBADDR6 address_b[6] => ram_block1a9.PORTBADDR6 address_b[6] => ram_block1a10.PORTBADDR6 address_b[6] => ram_block1a11.PORTBADDR6 address_b[6] => ram_block1a12.PORTBADDR6 address_b[6] => ram_block1a13.PORTBADDR6 address_b[6] => ram_block1a14.PORTBADDR6 address_b[6] => ram_block1a15.PORTBADDR6 address_b[6] => ram_block1a16.PORTBADDR6 address_b[6] => ram_block1a17.PORTBADDR6 address_b[6] => ram_block1a18.PORTBADDR6 address_b[6] => ram_block1a19.PORTBADDR6 clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 clock0 => ram_block1a8.CLK0 clock0 => ram_block1a9.CLK0 clock0 => ram_block1a10.CLK0 clock0 => ram_block1a11.CLK0 clock0 => ram_block1a12.CLK0 clock0 => ram_block1a13.CLK0 clock0 => ram_block1a14.CLK0 clock0 => ram_block1a15.CLK0 clock0 => ram_block1a16.CLK0 clock0 => ram_block1a17.CLK0 clock0 => ram_block1a18.CLK0 clock0 => ram_block1a19.CLK0 clock1 => ram_block1a0.CLK1 clock1 => ram_block1a1.CLK1 clock1 => ram_block1a2.CLK1 clock1 => ram_block1a3.CLK1 clock1 => ram_block1a4.CLK1 clock1 => ram_block1a5.CLK1 clock1 => ram_block1a6.CLK1 clock1 => ram_block1a7.CLK1 clock1 => ram_block1a8.CLK1 clock1 => ram_block1a9.CLK1 clock1 => ram_block1a10.CLK1 clock1 => ram_block1a11.CLK1 clock1 => ram_block1a12.CLK1 clock1 => ram_block1a13.CLK1 clock1 => ram_block1a14.CLK1 clock1 => ram_block1a15.CLK1 clock1 => ram_block1a16.CLK1 clock1 => ram_block1a17.CLK1 clock1 => ram_block1a18.CLK1 clock1 => ram_block1a19.CLK1 clocken1 => ram_block1a0.ENA1 clocken1 => ram_block1a1.ENA1 clocken1 => ram_block1a2.ENA1 clocken1 => ram_block1a3.ENA1 clocken1 => ram_block1a4.ENA1 clocken1 => ram_block1a5.ENA1 clocken1 => ram_block1a6.ENA1 clocken1 => ram_block1a7.ENA1 clocken1 => ram_block1a8.ENA1 clocken1 => ram_block1a9.ENA1 clocken1 => ram_block1a10.ENA1 clocken1 => ram_block1a11.ENA1 clocken1 => ram_block1a12.ENA1 clocken1 => ram_block1a13.ENA1 clocken1 => ram_block1a14.ENA1 clocken1 => ram_block1a15.ENA1 clocken1 => ram_block1a16.ENA1 clocken1 => ram_block1a17.ENA1 clocken1 => ram_block1a18.ENA1 clocken1 => ram_block1a19.ENA1 data_a[0] => ram_block1a0.PORTADATAIN data_a[1] => ram_block1a1.PORTADATAIN data_a[2] => ram_block1a2.PORTADATAIN data_a[3] => ram_block1a3.PORTADATAIN data_a[4] => ram_block1a4.PORTADATAIN data_a[5] => ram_block1a5.PORTADATAIN data_a[6] => ram_block1a6.PORTADATAIN data_a[7] => ram_block1a7.PORTADATAIN data_a[8] => ram_block1a8.PORTADATAIN data_a[9] => ram_block1a9.PORTADATAIN data_a[10] => ram_block1a10.PORTADATAIN data_a[11] => ram_block1a11.PORTADATAIN data_a[12] => ram_block1a12.PORTADATAIN data_a[13] => ram_block1a13.PORTADATAIN data_a[14] => ram_block1a14.PORTADATAIN data_a[15] => ram_block1a15.PORTADATAIN data_a[16] => ram_block1a16.PORTADATAIN data_a[17] => ram_block1a17.PORTADATAIN data_a[18] => ram_block1a18.PORTADATAIN data_a[19] => ram_block1a19.PORTADATAIN q_b[0] <= ram_block1a0.PORTBDATAOUT q_b[1] <= ram_block1a1.PORTBDATAOUT q_b[2] <= ram_block1a2.PORTBDATAOUT q_b[3] <= ram_block1a3.PORTBDATAOUT q_b[4] <= ram_block1a4.PORTBDATAOUT q_b[5] <= ram_block1a5.PORTBDATAOUT q_b[6] <= ram_block1a6.PORTBDATAOUT q_b[7] <= ram_block1a7.PORTBDATAOUT q_b[8] <= ram_block1a8.PORTBDATAOUT q_b[9] <= ram_block1a9.PORTBDATAOUT q_b[10] <= ram_block1a10.PORTBDATAOUT q_b[11] <= ram_block1a11.PORTBDATAOUT q_b[12] <= ram_block1a12.PORTBDATAOUT q_b[13] <= ram_block1a13.PORTBDATAOUT q_b[14] <= ram_block1a14.PORTBDATAOUT q_b[15] <= ram_block1a15.PORTBDATAOUT q_b[16] <= ram_block1a16.PORTBDATAOUT q_b[17] <= ram_block1a17.PORTBDATAOUT q_b[18] <= ram_block1a18.PORTBDATAOUT q_b[19] <= ram_block1a19.PORTBDATAOUT wren_a => ram_block1a0.ENA0 wren_a => ram_block1a1.ENA0 wren_a => ram_block1a2.ENA0 wren_a => ram_block1a3.ENA0 wren_a => ram_block1a4.ENA0 wren_a => ram_block1a5.ENA0 wren_a => ram_block1a6.ENA0 wren_a => ram_block1a7.ENA0 wren_a => ram_block1a8.ENA0 wren_a => ram_block1a9.ENA0 wren_a => ram_block1a10.ENA0 wren_a => ram_block1a11.ENA0 wren_a => ram_block1a12.ENA0 wren_a => ram_block1a13.ENA0 wren_a => ram_block1a14.ENA0 wren_a => ram_block1a15.ENA0 wren_a => ram_block1a16.ENA0 wren_a => ram_block1a17.ENA0 wren_a => ram_block1a18.ENA0 wren_a => ram_block1a19.ENA0 |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht data[0] => data[0]~1.IN1 data[1] => data[1]~0.IN1 rdaddress[0] => rdaddress[0]~7.IN1 rdaddress[1] => rdaddress[1]~6.IN1 rdaddress[2] => rdaddress[2]~5.IN1 rdaddress[3] => rdaddress[3]~4.IN1 rdaddress[4] => rdaddress[4]~3.IN1 rdaddress[5] => rdaddress[5]~2.IN1 rdaddress[6] => rdaddress[6]~1.IN1 rdaddress[7] => rdaddress[7]~0.IN1 rdclken => rdclken~0.IN1 rdclock => rdclock~0.IN1 wraddress[0] => wraddress[0]~7.IN1 wraddress[1] => wraddress[1]~6.IN1 wraddress[2] => wraddress[2]~5.IN1 wraddress[3] => wraddress[3]~4.IN1 wraddress[4] => wraddress[4]~3.IN1 wraddress[5] => wraddress[5]~2.IN1 wraddress[6] => wraddress[6]~1.IN1 wraddress[7] => wraddress[7]~0.IN1 wrclock => wrclock~0.IN1 wren => wren~0.IN1 q[0] <= altsyncram:the_altsyncram.q_b q[1] <= altsyncram:the_altsyncram.q_b |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram wren_a => altsyncram_4nd1:auto_generated.wren_a rden_a => ~NO_FANOUT~ wren_b => ~NO_FANOUT~ rden_b => ~NO_FANOUT~ data_a[0] => altsyncram_4nd1:auto_generated.data_a[0] data_a[1] => altsyncram_4nd1:auto_generated.data_a[1] data_b[0] => ~NO_FANOUT~ data_b[1] => ~NO_FANOUT~ address_a[0] => altsyncram_4nd1:auto_generated.address_a[0] address_a[1] => altsyncram_4nd1:auto_generated.address_a[1] address_a[2] => altsyncram_4nd1:auto_generated.address_a[2] address_a[3] => altsyncram_4nd1:auto_generated.address_a[3] address_a[4] => altsyncram_4nd1:auto_generated.address_a[4] address_a[5] => altsyncram_4nd1:auto_generated.address_a[5] address_a[6] => altsyncram_4nd1:auto_generated.address_a[6] address_a[7] => altsyncram_4nd1:auto_generated.address_a[7] address_b[0] => altsyncram_4nd1:auto_generated.address_b[0] address_b[1] => altsyncram_4nd1:auto_generated.address_b[1] address_b[2] => altsyncram_4nd1:auto_generated.address_b[2] address_b[3] => altsyncram_4nd1:auto_generated.address_b[3] address_b[4] => altsyncram_4nd1:auto_generated.address_b[4] address_b[5] => altsyncram_4nd1:auto_generated.address_b[5] address_b[6] => altsyncram_4nd1:auto_generated.address_b[6] address_b[7] => altsyncram_4nd1:auto_generated.address_b[7] addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_4nd1:auto_generated.clock0 clock1 => altsyncram_4nd1:auto_generated.clock1 clocken0 => ~NO_FANOUT~ clocken1 => altsyncram_4nd1:auto_generated.clocken1 clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= q_a[1] <= q_b[0] <= altsyncram_4nd1:auto_generated.q_b[0] q_b[1] <= altsyncram_4nd1:auto_generated.q_b[1] eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_4nd1:auto_generated address_a[0] => altsyncram_3um1:altsyncram1.address_b[0] address_a[1] => altsyncram_3um1:altsyncram1.address_b[1] address_a[2] => altsyncram_3um1:altsyncram1.address_b[2] address_a[3] => altsyncram_3um1:altsyncram1.address_b[3] address_a[4] => altsyncram_3um1:altsyncram1.address_b[4] address_a[5] => altsyncram_3um1:altsyncram1.address_b[5] address_a[6] => altsyncram_3um1:altsyncram1.address_b[6] address_a[7] => altsyncram_3um1:altsyncram1.address_b[7] address_b[0] => altsyncram_3um1:altsyncram1.address_a[0] address_b[1] => altsyncram_3um1:altsyncram1.address_a[1] address_b[2] => altsyncram_3um1:altsyncram1.address_a[2] address_b[3] => altsyncram_3um1:altsyncram1.address_a[3] address_b[4] => altsyncram_3um1:altsyncram1.address_a[4] address_b[5] => altsyncram_3um1:altsyncram1.address_a[5] address_b[6] => altsyncram_3um1:altsyncram1.address_a[6] address_b[7] => altsyncram_3um1:altsyncram1.address_a[7] clock0 => altsyncram_3um1:altsyncram1.clock1 clock1 => altsyncram_3um1:altsyncram1.clock0 clocken1 => altsyncram_3um1:altsyncram1.clocken0 data_a[0] => altsyncram_3um1:altsyncram1.data_b[0] data_a[1] => altsyncram_3um1:altsyncram1.data_b[1] q_b[0] <= altsyncram_3um1:altsyncram1.q_a[0] q_b[1] <= altsyncram_3um1:altsyncram1.q_a[1] wren_a => altsyncram_3um1:altsyncram1.clocken1 wren_a => altsyncram_3um1:altsyncram1.wren_b |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_4nd1:auto_generated|altsyncram_3um1:altsyncram1 address_a[0] => ram_block2a0.PORTAADDR address_a[0] => ram_block2a1.PORTAADDR address_a[1] => ram_block2a0.PORTAADDR1 address_a[1] => ram_block2a1.PORTAADDR1 address_a[2] => ram_block2a0.PORTAADDR2 address_a[2] => ram_block2a1.PORTAADDR2 address_a[3] => ram_block2a0.PORTAADDR3 address_a[3] => ram_block2a1.PORTAADDR3 address_a[4] => ram_block2a0.PORTAADDR4 address_a[4] => ram_block2a1.PORTAADDR4 address_a[5] => ram_block2a0.PORTAADDR5 address_a[5] => ram_block2a1.PORTAADDR5 address_a[6] => ram_block2a0.PORTAADDR6 address_a[6] => ram_block2a1.PORTAADDR6 address_a[7] => ram_block2a0.PORTAADDR7 address_a[7] => ram_block2a1.PORTAADDR7 address_b[0] => ram_block2a0.PORTBADDR address_b[0] => ram_block2a1.PORTBADDR address_b[1] => ram_block2a0.PORTBADDR1 address_b[1] => ram_block2a1.PORTBADDR1 address_b[2] => ram_block2a0.PORTBADDR2 address_b[2] => ram_block2a1.PORTBADDR2 address_b[3] => ram_block2a0.PORTBADDR3 address_b[3] => ram_block2a1.PORTBADDR3 address_b[4] => ram_block2a0.PORTBADDR4 address_b[4] => ram_block2a1.PORTBADDR4 address_b[5] => ram_block2a0.PORTBADDR5 address_b[5] => ram_block2a1.PORTBADDR5 address_b[6] => ram_block2a0.PORTBADDR6 address_b[6] => ram_block2a1.PORTBADDR6 address_b[7] => ram_block2a0.PORTBADDR7 address_b[7] => ram_block2a1.PORTBADDR7 clock0 => ram_block2a0.CLK0 clock0 => ram_block2a1.CLK0 clock1 => ram_block2a0.CLK1 clock1 => ram_block2a1.CLK1 clocken0 => ram_block2a0.ENA0 clocken0 => ram_block2a1.ENA0 clocken1 => ram_block2a0.ENA1 clocken1 => ram_block2a1.ENA1 data_a[0] => ram_block2a0.PORTADATAIN data_a[1] => ram_block2a1.PORTADATAIN data_b[0] => ram_block2a0.PORTBDATAIN data_b[1] => ram_block2a1.PORTBDATAIN q_a[0] <= ram_block2a0.PORTADATAOUT q_a[1] <= ram_block2a1.PORTADATAOUT q_b[0] <= ram_block2a0.PORTBDATAOUT q_b[1] <= ram_block2a1.PORTBDATAOUT wren_a => ram_block2a0.PORTAWE wren_a => ram_block2a1.PORTAWE wren_b => ram_block2a0.PORTBRE wren_b => ram_block2a1.PORTBRE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a data[0] => data[0]~31.IN1 data[1] => data[1]~30.IN1 data[2] => data[2]~29.IN1 data[3] => data[3]~28.IN1 data[4] => data[4]~27.IN1 data[5] => data[5]~26.IN1 data[6] => data[6]~25.IN1 data[7] => data[7]~24.IN1 data[8] => data[8]~23.IN1 data[9] => data[9]~22.IN1 data[10] => data[10]~21.IN1 data[11] => data[11]~20.IN1 data[12] => data[12]~19.IN1 data[13] => data[13]~18.IN1 data[14] => data[14]~17.IN1 data[15] => data[15]~16.IN1 data[16] => data[16]~15.IN1 data[17] => data[17]~14.IN1 data[18] => data[18]~13.IN1 data[19] => data[19]~12.IN1 data[20] => data[20]~11.IN1 data[21] => data[21]~10.IN1 data[22] => data[22]~9.IN1 data[23] => data[23]~8.IN1 data[24] => data[24]~7.IN1 data[25] => data[25]~6.IN1 data[26] => data[26]~5.IN1 data[27] => data[27]~4.IN1 data[28] => data[28]~3.IN1 data[29] => data[29]~2.IN1 data[30] => data[30]~1.IN1 data[31] => data[31]~0.IN1 rdaddress[0] => rdaddress[0]~4.IN1 rdaddress[1] => rdaddress[1]~3.IN1 rdaddress[2] => rdaddress[2]~2.IN1 rdaddress[3] => rdaddress[3]~1.IN1 rdaddress[4] => rdaddress[4]~0.IN1 rdclken => rdclken~0.IN1 rdclock => rdclock~0.IN1 wraddress[0] => wraddress[0]~4.IN1 wraddress[1] => wraddress[1]~3.IN1 wraddress[2] => wraddress[2]~2.IN1 wraddress[3] => wraddress[3]~1.IN1 wraddress[4] => wraddress[4]~0.IN1 wrclock => wrclock~0.IN1 wren => wren~0.IN1 q[0] <= altsyncram:the_altsyncram.q_b q[1] <= altsyncram:the_altsyncram.q_b q[2] <= altsyncram:the_altsyncram.q_b q[3] <= altsyncram:the_altsyncram.q_b q[4] <= altsyncram:the_altsyncram.q_b q[5] <= altsyncram:the_altsyncram.q_b q[6] <= altsyncram:the_altsyncram.q_b q[7] <= altsyncram:the_altsyncram.q_b q[8] <= altsyncram:the_altsyncram.q_b q[9] <= altsyncram:the_altsyncram.q_b q[10] <= altsyncram:the_altsyncram.q_b q[11] <= altsyncram:the_altsyncram.q_b q[12] <= altsyncram:the_altsyncram.q_b q[13] <= altsyncram:the_altsyncram.q_b q[14] <= altsyncram:the_altsyncram.q_b q[15] <= altsyncram:the_altsyncram.q_b q[16] <= altsyncram:the_altsyncram.q_b q[17] <= altsyncram:the_altsyncram.q_b q[18] <= altsyncram:the_altsyncram.q_b q[19] <= altsyncram:the_altsyncram.q_b q[20] <= altsyncram:the_altsyncram.q_b q[21] <= altsyncram:the_altsyncram.q_b q[22] <= altsyncram:the_altsyncram.q_b q[23] <= altsyncram:the_altsyncram.q_b q[24] <= altsyncram:the_altsyncram.q_b q[25] <= altsyncram:the_altsyncram.q_b q[26] <= altsyncram:the_altsyncram.q_b q[27] <= altsyncram:the_altsyncram.q_b q[28] <= altsyncram:the_altsyncram.q_b q[29] <= altsyncram:the_altsyncram.q_b q[30] <= altsyncram:the_altsyncram.q_b q[31] <= altsyncram:the_altsyncram.q_b |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram wren_a => altsyncram_epd1:auto_generated.wren_a rden_a => ~NO_FANOUT~ wren_b => ~NO_FANOUT~ rden_b => ~NO_FANOUT~ data_a[0] => altsyncram_epd1:auto_generated.data_a[0] data_a[1] => altsyncram_epd1:auto_generated.data_a[1] data_a[2] => altsyncram_epd1:auto_generated.data_a[2] data_a[3] => altsyncram_epd1:auto_generated.data_a[3] data_a[4] => altsyncram_epd1:auto_generated.data_a[4] data_a[5] => altsyncram_epd1:auto_generated.data_a[5] data_a[6] => altsyncram_epd1:auto_generated.data_a[6] data_a[7] => altsyncram_epd1:auto_generated.data_a[7] data_a[8] => altsyncram_epd1:auto_generated.data_a[8] data_a[9] => altsyncram_epd1:auto_generated.data_a[9] data_a[10] => altsyncram_epd1:auto_generated.data_a[10] data_a[11] => altsyncram_epd1:auto_generated.data_a[11] data_a[12] => altsyncram_epd1:auto_generated.data_a[12] data_a[13] => altsyncram_epd1:auto_generated.data_a[13] data_a[14] => altsyncram_epd1:auto_generated.data_a[14] data_a[15] => altsyncram_epd1:auto_generated.data_a[15] data_a[16] => altsyncram_epd1:auto_generated.data_a[16] data_a[17] => altsyncram_epd1:auto_generated.data_a[17] data_a[18] => altsyncram_epd1:auto_generated.data_a[18] data_a[19] => altsyncram_epd1:auto_generated.data_a[19] data_a[20] => altsyncram_epd1:auto_generated.data_a[20] data_a[21] => altsyncram_epd1:auto_generated.data_a[21] data_a[22] => altsyncram_epd1:auto_generated.data_a[22] data_a[23] => altsyncram_epd1:auto_generated.data_a[23] data_a[24] => altsyncram_epd1:auto_generated.data_a[24] data_a[25] => altsyncram_epd1:auto_generated.data_a[25] data_a[26] => altsyncram_epd1:auto_generated.data_a[26] data_a[27] => altsyncram_epd1:auto_generated.data_a[27] data_a[28] => altsyncram_epd1:auto_generated.data_a[28] data_a[29] => altsyncram_epd1:auto_generated.data_a[29] data_a[30] => altsyncram_epd1:auto_generated.data_a[30] data_a[31] => altsyncram_epd1:auto_generated.data_a[31] data_b[0] => ~NO_FANOUT~ data_b[1] => ~NO_FANOUT~ data_b[2] => ~NO_FANOUT~ data_b[3] => ~NO_FANOUT~ data_b[4] => ~NO_FANOUT~ data_b[5] => ~NO_FANOUT~ data_b[6] => ~NO_FANOUT~ data_b[7] => ~NO_FANOUT~ data_b[8] => ~NO_FANOUT~ data_b[9] => ~NO_FANOUT~ data_b[10] => ~NO_FANOUT~ data_b[11] => ~NO_FANOUT~ data_b[12] => ~NO_FANOUT~ data_b[13] => ~NO_FANOUT~ data_b[14] => ~NO_FANOUT~ data_b[15] => ~NO_FANOUT~ data_b[16] => ~NO_FANOUT~ data_b[17] => ~NO_FANOUT~ data_b[18] => ~NO_FANOUT~ data_b[19] => ~NO_FANOUT~ data_b[20] => ~NO_FANOUT~ data_b[21] => ~NO_FANOUT~ data_b[22] => ~NO_FANOUT~ data_b[23] => ~NO_FANOUT~ data_b[24] => ~NO_FANOUT~ data_b[25] => ~NO_FANOUT~ data_b[26] => ~NO_FANOUT~ data_b[27] => ~NO_FANOUT~ data_b[28] => ~NO_FANOUT~ data_b[29] => ~NO_FANOUT~ data_b[30] => ~NO_FANOUT~ data_b[31] => ~NO_FANOUT~ address_a[0] => altsyncram_epd1:auto_generated.address_a[0] address_a[1] => altsyncram_epd1:auto_generated.address_a[1] address_a[2] => altsyncram_epd1:auto_generated.address_a[2] address_a[3] => altsyncram_epd1:auto_generated.address_a[3] address_a[4] => altsyncram_epd1:auto_generated.address_a[4] address_b[0] => altsyncram_epd1:auto_generated.address_b[0] address_b[1] => altsyncram_epd1:auto_generated.address_b[1] address_b[2] => altsyncram_epd1:auto_generated.address_b[2] address_b[3] => altsyncram_epd1:auto_generated.address_b[3] address_b[4] => altsyncram_epd1:auto_generated.address_b[4] addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_epd1:auto_generated.clock0 clock1 => altsyncram_epd1:auto_generated.clock1 clocken0 => ~NO_FANOUT~ clocken1 => altsyncram_epd1:auto_generated.clocken1 clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= q_a[1] <= q_a[2] <= q_a[3] <= q_a[4] <= q_a[5] <= q_a[6] <= q_a[7] <= q_a[8] <= q_a[9] <= q_a[10] <= q_a[11] <= q_a[12] <= q_a[13] <= q_a[14] <= q_a[15] <= q_a[16] <= q_a[17] <= q_a[18] <= q_a[19] <= q_a[20] <= q_a[21] <= q_a[22] <= q_a[23] <= q_a[24] <= q_a[25] <= q_a[26] <= q_a[27] <= q_a[28] <= q_a[29] <= q_a[30] <= q_a[31] <= q_b[0] <= altsyncram_epd1:auto_generated.q_b[0] q_b[1] <= altsyncram_epd1:auto_generated.q_b[1] q_b[2] <= altsyncram_epd1:auto_generated.q_b[2] q_b[3] <= altsyncram_epd1:auto_generated.q_b[3] q_b[4] <= altsyncram_epd1:auto_generated.q_b[4] q_b[5] <= altsyncram_epd1:auto_generated.q_b[5] q_b[6] <= altsyncram_epd1:auto_generated.q_b[6] q_b[7] <= altsyncram_epd1:auto_generated.q_b[7] q_b[8] <= altsyncram_epd1:auto_generated.q_b[8] q_b[9] <= altsyncram_epd1:auto_generated.q_b[9] q_b[10] <= altsyncram_epd1:auto_generated.q_b[10] q_b[11] <= altsyncram_epd1:auto_generated.q_b[11] q_b[12] <= altsyncram_epd1:auto_generated.q_b[12] q_b[13] <= altsyncram_epd1:auto_generated.q_b[13] q_b[14] <= altsyncram_epd1:auto_generated.q_b[14] q_b[15] <= altsyncram_epd1:auto_generated.q_b[15] q_b[16] <= altsyncram_epd1:auto_generated.q_b[16] q_b[17] <= altsyncram_epd1:auto_generated.q_b[17] q_b[18] <= altsyncram_epd1:auto_generated.q_b[18] q_b[19] <= altsyncram_epd1:auto_generated.q_b[19] q_b[20] <= altsyncram_epd1:auto_generated.q_b[20] q_b[21] <= altsyncram_epd1:auto_generated.q_b[21] q_b[22] <= altsyncram_epd1:auto_generated.q_b[22] q_b[23] <= altsyncram_epd1:auto_generated.q_b[23] q_b[24] <= altsyncram_epd1:auto_generated.q_b[24] q_b[25] <= altsyncram_epd1:auto_generated.q_b[25] q_b[26] <= altsyncram_epd1:auto_generated.q_b[26] q_b[27] <= altsyncram_epd1:auto_generated.q_b[27] q_b[28] <= altsyncram_epd1:auto_generated.q_b[28] q_b[29] <= altsyncram_epd1:auto_generated.q_b[29] q_b[30] <= altsyncram_epd1:auto_generated.q_b[30] q_b[31] <= altsyncram_epd1:auto_generated.q_b[31] eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_epd1:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[0] => ram_block1a8.PORTAADDR address_a[0] => ram_block1a9.PORTAADDR address_a[0] => ram_block1a10.PORTAADDR address_a[0] => ram_block1a11.PORTAADDR address_a[0] => ram_block1a12.PORTAADDR address_a[0] => ram_block1a13.PORTAADDR address_a[0] => ram_block1a14.PORTAADDR address_a[0] => ram_block1a15.PORTAADDR address_a[0] => ram_block1a16.PORTAADDR address_a[0] => ram_block1a17.PORTAADDR address_a[0] => ram_block1a18.PORTAADDR address_a[0] => ram_block1a19.PORTAADDR address_a[0] => ram_block1a20.PORTAADDR address_a[0] => ram_block1a21.PORTAADDR address_a[0] => ram_block1a22.PORTAADDR address_a[0] => ram_block1a23.PORTAADDR address_a[0] => ram_block1a24.PORTAADDR address_a[0] => ram_block1a25.PORTAADDR address_a[0] => ram_block1a26.PORTAADDR address_a[0] => ram_block1a27.PORTAADDR address_a[0] => ram_block1a28.PORTAADDR address_a[0] => ram_block1a29.PORTAADDR address_a[0] => ram_block1a30.PORTAADDR address_a[0] => ram_block1a31.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[1] => ram_block1a8.PORTAADDR1 address_a[1] => ram_block1a9.PORTAADDR1 address_a[1] => ram_block1a10.PORTAADDR1 address_a[1] => ram_block1a11.PORTAADDR1 address_a[1] => ram_block1a12.PORTAADDR1 address_a[1] => ram_block1a13.PORTAADDR1 address_a[1] => ram_block1a14.PORTAADDR1 address_a[1] => ram_block1a15.PORTAADDR1 address_a[1] => ram_block1a16.PORTAADDR1 address_a[1] => ram_block1a17.PORTAADDR1 address_a[1] => ram_block1a18.PORTAADDR1 address_a[1] => ram_block1a19.PORTAADDR1 address_a[1] => ram_block1a20.PORTAADDR1 address_a[1] => ram_block1a21.PORTAADDR1 address_a[1] => ram_block1a22.PORTAADDR1 address_a[1] => ram_block1a23.PORTAADDR1 address_a[1] => ram_block1a24.PORTAADDR1 address_a[1] => ram_block1a25.PORTAADDR1 address_a[1] => ram_block1a26.PORTAADDR1 address_a[1] => ram_block1a27.PORTAADDR1 address_a[1] => ram_block1a28.PORTAADDR1 address_a[1] => ram_block1a29.PORTAADDR1 address_a[1] => ram_block1a30.PORTAADDR1 address_a[1] => ram_block1a31.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[2] => ram_block1a8.PORTAADDR2 address_a[2] => ram_block1a9.PORTAADDR2 address_a[2] => ram_block1a10.PORTAADDR2 address_a[2] => ram_block1a11.PORTAADDR2 address_a[2] => ram_block1a12.PORTAADDR2 address_a[2] => ram_block1a13.PORTAADDR2 address_a[2] => ram_block1a14.PORTAADDR2 address_a[2] => ram_block1a15.PORTAADDR2 address_a[2] => ram_block1a16.PORTAADDR2 address_a[2] => ram_block1a17.PORTAADDR2 address_a[2] => ram_block1a18.PORTAADDR2 address_a[2] => ram_block1a19.PORTAADDR2 address_a[2] => ram_block1a20.PORTAADDR2 address_a[2] => ram_block1a21.PORTAADDR2 address_a[2] => ram_block1a22.PORTAADDR2 address_a[2] => ram_block1a23.PORTAADDR2 address_a[2] => ram_block1a24.PORTAADDR2 address_a[2] => ram_block1a25.PORTAADDR2 address_a[2] => ram_block1a26.PORTAADDR2 address_a[2] => ram_block1a27.PORTAADDR2 address_a[2] => ram_block1a28.PORTAADDR2 address_a[2] => ram_block1a29.PORTAADDR2 address_a[2] => ram_block1a30.PORTAADDR2 address_a[2] => ram_block1a31.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[3] => ram_block1a8.PORTAADDR3 address_a[3] => ram_block1a9.PORTAADDR3 address_a[3] => ram_block1a10.PORTAADDR3 address_a[3] => ram_block1a11.PORTAADDR3 address_a[3] => ram_block1a12.PORTAADDR3 address_a[3] => ram_block1a13.PORTAADDR3 address_a[3] => ram_block1a14.PORTAADDR3 address_a[3] => ram_block1a15.PORTAADDR3 address_a[3] => ram_block1a16.PORTAADDR3 address_a[3] => ram_block1a17.PORTAADDR3 address_a[3] => ram_block1a18.PORTAADDR3 address_a[3] => ram_block1a19.PORTAADDR3 address_a[3] => ram_block1a20.PORTAADDR3 address_a[3] => ram_block1a21.PORTAADDR3 address_a[3] => ram_block1a22.PORTAADDR3 address_a[3] => ram_block1a23.PORTAADDR3 address_a[3] => ram_block1a24.PORTAADDR3 address_a[3] => ram_block1a25.PORTAADDR3 address_a[3] => ram_block1a26.PORTAADDR3 address_a[3] => ram_block1a27.PORTAADDR3 address_a[3] => ram_block1a28.PORTAADDR3 address_a[3] => ram_block1a29.PORTAADDR3 address_a[3] => ram_block1a30.PORTAADDR3 address_a[3] => ram_block1a31.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[4] => ram_block1a8.PORTAADDR4 address_a[4] => ram_block1a9.PORTAADDR4 address_a[4] => ram_block1a10.PORTAADDR4 address_a[4] => ram_block1a11.PORTAADDR4 address_a[4] => ram_block1a12.PORTAADDR4 address_a[4] => ram_block1a13.PORTAADDR4 address_a[4] => ram_block1a14.PORTAADDR4 address_a[4] => ram_block1a15.PORTAADDR4 address_a[4] => ram_block1a16.PORTAADDR4 address_a[4] => ram_block1a17.PORTAADDR4 address_a[4] => ram_block1a18.PORTAADDR4 address_a[4] => ram_block1a19.PORTAADDR4 address_a[4] => ram_block1a20.PORTAADDR4 address_a[4] => ram_block1a21.PORTAADDR4 address_a[4] => ram_block1a22.PORTAADDR4 address_a[4] => ram_block1a23.PORTAADDR4 address_a[4] => ram_block1a24.PORTAADDR4 address_a[4] => ram_block1a25.PORTAADDR4 address_a[4] => ram_block1a26.PORTAADDR4 address_a[4] => ram_block1a27.PORTAADDR4 address_a[4] => ram_block1a28.PORTAADDR4 address_a[4] => ram_block1a29.PORTAADDR4 address_a[4] => ram_block1a30.PORTAADDR4 address_a[4] => ram_block1a31.PORTAADDR4 address_b[0] => ram_block1a0.PORTBADDR address_b[0] => ram_block1a1.PORTBADDR address_b[0] => ram_block1a2.PORTBADDR address_b[0] => ram_block1a3.PORTBADDR address_b[0] => ram_block1a4.PORTBADDR address_b[0] => ram_block1a5.PORTBADDR address_b[0] => ram_block1a6.PORTBADDR address_b[0] => ram_block1a7.PORTBADDR address_b[0] => ram_block1a8.PORTBADDR address_b[0] => ram_block1a9.PORTBADDR address_b[0] => ram_block1a10.PORTBADDR address_b[0] => ram_block1a11.PORTBADDR address_b[0] => ram_block1a12.PORTBADDR address_b[0] => ram_block1a13.PORTBADDR address_b[0] => ram_block1a14.PORTBADDR address_b[0] => ram_block1a15.PORTBADDR address_b[0] => ram_block1a16.PORTBADDR address_b[0] => ram_block1a17.PORTBADDR address_b[0] => ram_block1a18.PORTBADDR address_b[0] => ram_block1a19.PORTBADDR address_b[0] => ram_block1a20.PORTBADDR address_b[0] => ram_block1a21.PORTBADDR address_b[0] => ram_block1a22.PORTBADDR address_b[0] => ram_block1a23.PORTBADDR address_b[0] => ram_block1a24.PORTBADDR address_b[0] => ram_block1a25.PORTBADDR address_b[0] => ram_block1a26.PORTBADDR address_b[0] => ram_block1a27.PORTBADDR address_b[0] => ram_block1a28.PORTBADDR address_b[0] => ram_block1a29.PORTBADDR address_b[0] => ram_block1a30.PORTBADDR address_b[0] => ram_block1a31.PORTBADDR address_b[1] => ram_block1a0.PORTBADDR1 address_b[1] => ram_block1a1.PORTBADDR1 address_b[1] => ram_block1a2.PORTBADDR1 address_b[1] => ram_block1a3.PORTBADDR1 address_b[1] => ram_block1a4.PORTBADDR1 address_b[1] => ram_block1a5.PORTBADDR1 address_b[1] => ram_block1a6.PORTBADDR1 address_b[1] => ram_block1a7.PORTBADDR1 address_b[1] => ram_block1a8.PORTBADDR1 address_b[1] => ram_block1a9.PORTBADDR1 address_b[1] => ram_block1a10.PORTBADDR1 address_b[1] => ram_block1a11.PORTBADDR1 address_b[1] => ram_block1a12.PORTBADDR1 address_b[1] => ram_block1a13.PORTBADDR1 address_b[1] => ram_block1a14.PORTBADDR1 address_b[1] => ram_block1a15.PORTBADDR1 address_b[1] => ram_block1a16.PORTBADDR1 address_b[1] => ram_block1a17.PORTBADDR1 address_b[1] => ram_block1a18.PORTBADDR1 address_b[1] => ram_block1a19.PORTBADDR1 address_b[1] => ram_block1a20.PORTBADDR1 address_b[1] => ram_block1a21.PORTBADDR1 address_b[1] => ram_block1a22.PORTBADDR1 address_b[1] => ram_block1a23.PORTBADDR1 address_b[1] => ram_block1a24.PORTBADDR1 address_b[1] => ram_block1a25.PORTBADDR1 address_b[1] => ram_block1a26.PORTBADDR1 address_b[1] => ram_block1a27.PORTBADDR1 address_b[1] => ram_block1a28.PORTBADDR1 address_b[1] => ram_block1a29.PORTBADDR1 address_b[1] => ram_block1a30.PORTBADDR1 address_b[1] => ram_block1a31.PORTBADDR1 address_b[2] => ram_block1a0.PORTBADDR2 address_b[2] => ram_block1a1.PORTBADDR2 address_b[2] => ram_block1a2.PORTBADDR2 address_b[2] => ram_block1a3.PORTBADDR2 address_b[2] => ram_block1a4.PORTBADDR2 address_b[2] => ram_block1a5.PORTBADDR2 address_b[2] => ram_block1a6.PORTBADDR2 address_b[2] => ram_block1a7.PORTBADDR2 address_b[2] => ram_block1a8.PORTBADDR2 address_b[2] => ram_block1a9.PORTBADDR2 address_b[2] => ram_block1a10.PORTBADDR2 address_b[2] => ram_block1a11.PORTBADDR2 address_b[2] => ram_block1a12.PORTBADDR2 address_b[2] => ram_block1a13.PORTBADDR2 address_b[2] => ram_block1a14.PORTBADDR2 address_b[2] => ram_block1a15.PORTBADDR2 address_b[2] => ram_block1a16.PORTBADDR2 address_b[2] => ram_block1a17.PORTBADDR2 address_b[2] => ram_block1a18.PORTBADDR2 address_b[2] => ram_block1a19.PORTBADDR2 address_b[2] => ram_block1a20.PORTBADDR2 address_b[2] => ram_block1a21.PORTBADDR2 address_b[2] => ram_block1a22.PORTBADDR2 address_b[2] => ram_block1a23.PORTBADDR2 address_b[2] => ram_block1a24.PORTBADDR2 address_b[2] => ram_block1a25.PORTBADDR2 address_b[2] => ram_block1a26.PORTBADDR2 address_b[2] => ram_block1a27.PORTBADDR2 address_b[2] => ram_block1a28.PORTBADDR2 address_b[2] => ram_block1a29.PORTBADDR2 address_b[2] => ram_block1a30.PORTBADDR2 address_b[2] => ram_block1a31.PORTBADDR2 address_b[3] => ram_block1a0.PORTBADDR3 address_b[3] => ram_block1a1.PORTBADDR3 address_b[3] => ram_block1a2.PORTBADDR3 address_b[3] => ram_block1a3.PORTBADDR3 address_b[3] => ram_block1a4.PORTBADDR3 address_b[3] => ram_block1a5.PORTBADDR3 address_b[3] => ram_block1a6.PORTBADDR3 address_b[3] => ram_block1a7.PORTBADDR3 address_b[3] => ram_block1a8.PORTBADDR3 address_b[3] => ram_block1a9.PORTBADDR3 address_b[3] => ram_block1a10.PORTBADDR3 address_b[3] => ram_block1a11.PORTBADDR3 address_b[3] => ram_block1a12.PORTBADDR3 address_b[3] => ram_block1a13.PORTBADDR3 address_b[3] => ram_block1a14.PORTBADDR3 address_b[3] => ram_block1a15.PORTBADDR3 address_b[3] => ram_block1a16.PORTBADDR3 address_b[3] => ram_block1a17.PORTBADDR3 address_b[3] => ram_block1a18.PORTBADDR3 address_b[3] => ram_block1a19.PORTBADDR3 address_b[3] => ram_block1a20.PORTBADDR3 address_b[3] => ram_block1a21.PORTBADDR3 address_b[3] => ram_block1a22.PORTBADDR3 address_b[3] => ram_block1a23.PORTBADDR3 address_b[3] => ram_block1a24.PORTBADDR3 address_b[3] => ram_block1a25.PORTBADDR3 address_b[3] => ram_block1a26.PORTBADDR3 address_b[3] => ram_block1a27.PORTBADDR3 address_b[3] => ram_block1a28.PORTBADDR3 address_b[3] => ram_block1a29.PORTBADDR3 address_b[3] => ram_block1a30.PORTBADDR3 address_b[3] => ram_block1a31.PORTBADDR3 address_b[4] => ram_block1a0.PORTBADDR4 address_b[4] => ram_block1a1.PORTBADDR4 address_b[4] => ram_block1a2.PORTBADDR4 address_b[4] => ram_block1a3.PORTBADDR4 address_b[4] => ram_block1a4.PORTBADDR4 address_b[4] => ram_block1a5.PORTBADDR4 address_b[4] => ram_block1a6.PORTBADDR4 address_b[4] => ram_block1a7.PORTBADDR4 address_b[4] => ram_block1a8.PORTBADDR4 address_b[4] => ram_block1a9.PORTBADDR4 address_b[4] => ram_block1a10.PORTBADDR4 address_b[4] => ram_block1a11.PORTBADDR4 address_b[4] => ram_block1a12.PORTBADDR4 address_b[4] => ram_block1a13.PORTBADDR4 address_b[4] => ram_block1a14.PORTBADDR4 address_b[4] => ram_block1a15.PORTBADDR4 address_b[4] => ram_block1a16.PORTBADDR4 address_b[4] => ram_block1a17.PORTBADDR4 address_b[4] => ram_block1a18.PORTBADDR4 address_b[4] => ram_block1a19.PORTBADDR4 address_b[4] => ram_block1a20.PORTBADDR4 address_b[4] => ram_block1a21.PORTBADDR4 address_b[4] => ram_block1a22.PORTBADDR4 address_b[4] => ram_block1a23.PORTBADDR4 address_b[4] => ram_block1a24.PORTBADDR4 address_b[4] => ram_block1a25.PORTBADDR4 address_b[4] => ram_block1a26.PORTBADDR4 address_b[4] => ram_block1a27.PORTBADDR4 address_b[4] => ram_block1a28.PORTBADDR4 address_b[4] => ram_block1a29.PORTBADDR4 address_b[4] => ram_block1a30.PORTBADDR4 address_b[4] => ram_block1a31.PORTBADDR4 clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 clock0 => ram_block1a8.CLK0 clock0 => ram_block1a9.CLK0 clock0 => ram_block1a10.CLK0 clock0 => ram_block1a11.CLK0 clock0 => ram_block1a12.CLK0 clock0 => ram_block1a13.CLK0 clock0 => ram_block1a14.CLK0 clock0 => ram_block1a15.CLK0 clock0 => ram_block1a16.CLK0 clock0 => ram_block1a17.CLK0 clock0 => ram_block1a18.CLK0 clock0 => ram_block1a19.CLK0 clock0 => ram_block1a20.CLK0 clock0 => ram_block1a21.CLK0 clock0 => ram_block1a22.CLK0 clock0 => ram_block1a23.CLK0 clock0 => ram_block1a24.CLK0 clock0 => ram_block1a25.CLK0 clock0 => ram_block1a26.CLK0 clock0 => ram_block1a27.CLK0 clock0 => ram_block1a28.CLK0 clock0 => ram_block1a29.CLK0 clock0 => ram_block1a30.CLK0 clock0 => ram_block1a31.CLK0 clock1 => ram_block1a0.CLK1 clock1 => ram_block1a1.CLK1 clock1 => ram_block1a2.CLK1 clock1 => ram_block1a3.CLK1 clock1 => ram_block1a4.CLK1 clock1 => ram_block1a5.CLK1 clock1 => ram_block1a6.CLK1 clock1 => ram_block1a7.CLK1 clock1 => ram_block1a8.CLK1 clock1 => ram_block1a9.CLK1 clock1 => ram_block1a10.CLK1 clock1 => ram_block1a11.CLK1 clock1 => ram_block1a12.CLK1 clock1 => ram_block1a13.CLK1 clock1 => ram_block1a14.CLK1 clock1 => ram_block1a15.CLK1 clock1 => ram_block1a16.CLK1 clock1 => ram_block1a17.CLK1 clock1 => ram_block1a18.CLK1 clock1 => ram_block1a19.CLK1 clock1 => ram_block1a20.CLK1 clock1 => ram_block1a21.CLK1 clock1 => ram_block1a22.CLK1 clock1 => ram_block1a23.CLK1 clock1 => ram_block1a24.CLK1 clock1 => ram_block1a25.CLK1 clock1 => ram_block1a26.CLK1 clock1 => ram_block1a27.CLK1 clock1 => ram_block1a28.CLK1 clock1 => ram_block1a29.CLK1 clock1 => ram_block1a30.CLK1 clock1 => ram_block1a31.CLK1 clocken1 => ram_block1a0.ENA1 clocken1 => ram_block1a1.ENA1 clocken1 => ram_block1a2.ENA1 clocken1 => ram_block1a3.ENA1 clocken1 => ram_block1a4.ENA1 clocken1 => ram_block1a5.ENA1 clocken1 => ram_block1a6.ENA1 clocken1 => ram_block1a7.ENA1 clocken1 => ram_block1a8.ENA1 clocken1 => ram_block1a9.ENA1 clocken1 => ram_block1a10.ENA1 clocken1 => ram_block1a11.ENA1 clocken1 => ram_block1a12.ENA1 clocken1 => ram_block1a13.ENA1 clocken1 => ram_block1a14.ENA1 clocken1 => ram_block1a15.ENA1 clocken1 => ram_block1a16.ENA1 clocken1 => ram_block1a17.ENA1 clocken1 => ram_block1a18.ENA1 clocken1 => ram_block1a19.ENA1 clocken1 => ram_block1a20.ENA1 clocken1 => ram_block1a21.ENA1 clocken1 => ram_block1a22.ENA1 clocken1 => ram_block1a23.ENA1 clocken1 => ram_block1a24.ENA1 clocken1 => ram_block1a25.ENA1 clocken1 => ram_block1a26.ENA1 clocken1 => ram_block1a27.ENA1 clocken1 => ram_block1a28.ENA1 clocken1 => ram_block1a29.ENA1 clocken1 => ram_block1a30.ENA1 clocken1 => ram_block1a31.ENA1 data_a[0] => ram_block1a0.PORTADATAIN data_a[1] => ram_block1a1.PORTADATAIN data_a[2] => ram_block1a2.PORTADATAIN data_a[3] => ram_block1a3.PORTADATAIN data_a[4] => ram_block1a4.PORTADATAIN data_a[5] => ram_block1a5.PORTADATAIN data_a[6] => ram_block1a6.PORTADATAIN data_a[7] => ram_block1a7.PORTADATAIN data_a[8] => ram_block1a8.PORTADATAIN data_a[9] => ram_block1a9.PORTADATAIN data_a[10] => ram_block1a10.PORTADATAIN data_a[11] => ram_block1a11.PORTADATAIN data_a[12] => ram_block1a12.PORTADATAIN data_a[13] => ram_block1a13.PORTADATAIN data_a[14] => ram_block1a14.PORTADATAIN data_a[15] => ram_block1a15.PORTADATAIN data_a[16] => ram_block1a16.PORTADATAIN data_a[17] => ram_block1a17.PORTADATAIN data_a[18] => ram_block1a18.PORTADATAIN data_a[19] => ram_block1a19.PORTADATAIN data_a[20] => ram_block1a20.PORTADATAIN data_a[21] => ram_block1a21.PORTADATAIN data_a[22] => ram_block1a22.PORTADATAIN data_a[23] => ram_block1a23.PORTADATAIN data_a[24] => ram_block1a24.PORTADATAIN data_a[25] => ram_block1a25.PORTADATAIN data_a[26] => ram_block1a26.PORTADATAIN data_a[27] => ram_block1a27.PORTADATAIN data_a[28] => ram_block1a28.PORTADATAIN data_a[29] => ram_block1a29.PORTADATAIN data_a[30] => ram_block1a30.PORTADATAIN data_a[31] => ram_block1a31.PORTADATAIN q_b[0] <= ram_block1a0.PORTBDATAOUT q_b[1] <= ram_block1a1.PORTBDATAOUT q_b[2] <= ram_block1a2.PORTBDATAOUT q_b[3] <= ram_block1a3.PORTBDATAOUT q_b[4] <= ram_block1a4.PORTBDATAOUT q_b[5] <= ram_block1a5.PORTBDATAOUT q_b[6] <= ram_block1a6.PORTBDATAOUT q_b[7] <= ram_block1a7.PORTBDATAOUT q_b[8] <= ram_block1a8.PORTBDATAOUT q_b[9] <= ram_block1a9.PORTBDATAOUT q_b[10] <= ram_block1a10.PORTBDATAOUT q_b[11] <= ram_block1a11.PORTBDATAOUT q_b[12] <= ram_block1a12.PORTBDATAOUT q_b[13] <= ram_block1a13.PORTBDATAOUT q_b[14] <= ram_block1a14.PORTBDATAOUT q_b[15] <= ram_block1a15.PORTBDATAOUT q_b[16] <= ram_block1a16.PORTBDATAOUT q_b[17] <= ram_block1a17.PORTBDATAOUT q_b[18] <= ram_block1a18.PORTBDATAOUT q_b[19] <= ram_block1a19.PORTBDATAOUT q_b[20] <= ram_block1a20.PORTBDATAOUT q_b[21] <= ram_block1a21.PORTBDATAOUT q_b[22] <= ram_block1a22.PORTBDATAOUT q_b[23] <= ram_block1a23.PORTBDATAOUT q_b[24] <= ram_block1a24.PORTBDATAOUT q_b[25] <= ram_block1a25.PORTBDATAOUT q_b[26] <= ram_block1a26.PORTBDATAOUT q_b[27] <= ram_block1a27.PORTBDATAOUT q_b[28] <= ram_block1a28.PORTBDATAOUT q_b[29] <= ram_block1a29.PORTBDATAOUT q_b[30] <= ram_block1a30.PORTBDATAOUT q_b[31] <= ram_block1a31.PORTBDATAOUT wren_a => ram_block1a0.ENA0 wren_a => ram_block1a1.ENA0 wren_a => ram_block1a2.ENA0 wren_a => ram_block1a3.ENA0 wren_a => ram_block1a4.ENA0 wren_a => ram_block1a5.ENA0 wren_a => ram_block1a6.ENA0 wren_a => ram_block1a7.ENA0 wren_a => ram_block1a8.ENA0 wren_a => ram_block1a9.ENA0 wren_a => ram_block1a10.ENA0 wren_a => ram_block1a11.ENA0 wren_a => ram_block1a12.ENA0 wren_a => ram_block1a13.ENA0 wren_a => ram_block1a14.ENA0 wren_a => ram_block1a15.ENA0 wren_a => ram_block1a16.ENA0 wren_a => ram_block1a17.ENA0 wren_a => ram_block1a18.ENA0 wren_a => ram_block1a19.ENA0 wren_a => ram_block1a20.ENA0 wren_a => ram_block1a21.ENA0 wren_a => ram_block1a22.ENA0 wren_a => ram_block1a23.ENA0 wren_a => ram_block1a24.ENA0 wren_a => ram_block1a25.ENA0 wren_a => ram_block1a26.ENA0 wren_a => ram_block1a27.ENA0 wren_a => ram_block1a28.ENA0 wren_a => ram_block1a29.ENA0 wren_a => ram_block1a30.ENA0 wren_a => ram_block1a31.ENA0 |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b data[0] => data[0]~31.IN1 data[1] => data[1]~30.IN1 data[2] => data[2]~29.IN1 data[3] => data[3]~28.IN1 data[4] => data[4]~27.IN1 data[5] => data[5]~26.IN1 data[6] => data[6]~25.IN1 data[7] => data[7]~24.IN1 data[8] => data[8]~23.IN1 data[9] => data[9]~22.IN1 data[10] => data[10]~21.IN1 data[11] => data[11]~20.IN1 data[12] => data[12]~19.IN1 data[13] => data[13]~18.IN1 data[14] => data[14]~17.IN1 data[15] => data[15]~16.IN1 data[16] => data[16]~15.IN1 data[17] => data[17]~14.IN1 data[18] => data[18]~13.IN1 data[19] => data[19]~12.IN1 data[20] => data[20]~11.IN1 data[21] => data[21]~10.IN1 data[22] => data[22]~9.IN1 data[23] => data[23]~8.IN1 data[24] => data[24]~7.IN1 data[25] => data[25]~6.IN1 data[26] => data[26]~5.IN1 data[27] => data[27]~4.IN1 data[28] => data[28]~3.IN1 data[29] => data[29]~2.IN1 data[30] => data[30]~1.IN1 data[31] => data[31]~0.IN1 rdaddress[0] => rdaddress[0]~4.IN1 rdaddress[1] => rdaddress[1]~3.IN1 rdaddress[2] => rdaddress[2]~2.IN1 rdaddress[3] => rdaddress[3]~1.IN1 rdaddress[4] => rdaddress[4]~0.IN1 rdclken => rdclken~0.IN1 rdclock => rdclock~0.IN1 wraddress[0] => wraddress[0]~4.IN1 wraddress[1] => wraddress[1]~3.IN1 wraddress[2] => wraddress[2]~2.IN1 wraddress[3] => wraddress[3]~1.IN1 wraddress[4] => wraddress[4]~0.IN1 wrclock => wrclock~0.IN1 wren => wren~0.IN1 q[0] <= altsyncram:the_altsyncram.q_b q[1] <= altsyncram:the_altsyncram.q_b q[2] <= altsyncram:the_altsyncram.q_b q[3] <= altsyncram:the_altsyncram.q_b q[4] <= altsyncram:the_altsyncram.q_b q[5] <= altsyncram:the_altsyncram.q_b q[6] <= altsyncram:the_altsyncram.q_b q[7] <= altsyncram:the_altsyncram.q_b q[8] <= altsyncram:the_altsyncram.q_b q[9] <= altsyncram:the_altsyncram.q_b q[10] <= altsyncram:the_altsyncram.q_b q[11] <= altsyncram:the_altsyncram.q_b q[12] <= altsyncram:the_altsyncram.q_b q[13] <= altsyncram:the_altsyncram.q_b q[14] <= altsyncram:the_altsyncram.q_b q[15] <= altsyncram:the_altsyncram.q_b q[16] <= altsyncram:the_altsyncram.q_b q[17] <= altsyncram:the_altsyncram.q_b q[18] <= altsyncram:the_altsyncram.q_b q[19] <= altsyncram:the_altsyncram.q_b q[20] <= altsyncram:the_altsyncram.q_b q[21] <= altsyncram:the_altsyncram.q_b q[22] <= altsyncram:the_altsyncram.q_b q[23] <= altsyncram:the_altsyncram.q_b q[24] <= altsyncram:the_altsyncram.q_b q[25] <= altsyncram:the_altsyncram.q_b q[26] <= altsyncram:the_altsyncram.q_b q[27] <= altsyncram:the_altsyncram.q_b q[28] <= altsyncram:the_altsyncram.q_b q[29] <= altsyncram:the_altsyncram.q_b q[30] <= altsyncram:the_altsyncram.q_b q[31] <= altsyncram:the_altsyncram.q_b |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram wren_a => altsyncram_fpd1:auto_generated.wren_a rden_a => ~NO_FANOUT~ wren_b => ~NO_FANOUT~ rden_b => ~NO_FANOUT~ data_a[0] => altsyncram_fpd1:auto_generated.data_a[0] data_a[1] => altsyncram_fpd1:auto_generated.data_a[1] data_a[2] => altsyncram_fpd1:auto_generated.data_a[2] data_a[3] => altsyncram_fpd1:auto_generated.data_a[3] data_a[4] => altsyncram_fpd1:auto_generated.data_a[4] data_a[5] => altsyncram_fpd1:auto_generated.data_a[5] data_a[6] => altsyncram_fpd1:auto_generated.data_a[6] data_a[7] => altsyncram_fpd1:auto_generated.data_a[7] data_a[8] => altsyncram_fpd1:auto_generated.data_a[8] data_a[9] => altsyncram_fpd1:auto_generated.data_a[9] data_a[10] => altsyncram_fpd1:auto_generated.data_a[10] data_a[11] => altsyncram_fpd1:auto_generated.data_a[11] data_a[12] => altsyncram_fpd1:auto_generated.data_a[12] data_a[13] => altsyncram_fpd1:auto_generated.data_a[13] data_a[14] => altsyncram_fpd1:auto_generated.data_a[14] data_a[15] => altsyncram_fpd1:auto_generated.data_a[15] data_a[16] => altsyncram_fpd1:auto_generated.data_a[16] data_a[17] => altsyncram_fpd1:auto_generated.data_a[17] data_a[18] => altsyncram_fpd1:auto_generated.data_a[18] data_a[19] => altsyncram_fpd1:auto_generated.data_a[19] data_a[20] => altsyncram_fpd1:auto_generated.data_a[20] data_a[21] => altsyncram_fpd1:auto_generated.data_a[21] data_a[22] => altsyncram_fpd1:auto_generated.data_a[22] data_a[23] => altsyncram_fpd1:auto_generated.data_a[23] data_a[24] => altsyncram_fpd1:auto_generated.data_a[24] data_a[25] => altsyncram_fpd1:auto_generated.data_a[25] data_a[26] => altsyncram_fpd1:auto_generated.data_a[26] data_a[27] => altsyncram_fpd1:auto_generated.data_a[27] data_a[28] => altsyncram_fpd1:auto_generated.data_a[28] data_a[29] => altsyncram_fpd1:auto_generated.data_a[29] data_a[30] => altsyncram_fpd1:auto_generated.data_a[30] data_a[31] => altsyncram_fpd1:auto_generated.data_a[31] data_b[0] => ~NO_FANOUT~ data_b[1] => ~NO_FANOUT~ data_b[2] => ~NO_FANOUT~ data_b[3] => ~NO_FANOUT~ data_b[4] => ~NO_FANOUT~ data_b[5] => ~NO_FANOUT~ data_b[6] => ~NO_FANOUT~ data_b[7] => ~NO_FANOUT~ data_b[8] => ~NO_FANOUT~ data_b[9] => ~NO_FANOUT~ data_b[10] => ~NO_FANOUT~ data_b[11] => ~NO_FANOUT~ data_b[12] => ~NO_FANOUT~ data_b[13] => ~NO_FANOUT~ data_b[14] => ~NO_FANOUT~ data_b[15] => ~NO_FANOUT~ data_b[16] => ~NO_FANOUT~ data_b[17] => ~NO_FANOUT~ data_b[18] => ~NO_FANOUT~ data_b[19] => ~NO_FANOUT~ data_b[20] => ~NO_FANOUT~ data_b[21] => ~NO_FANOUT~ data_b[22] => ~NO_FANOUT~ data_b[23] => ~NO_FANOUT~ data_b[24] => ~NO_FANOUT~ data_b[25] => ~NO_FANOUT~ data_b[26] => ~NO_FANOUT~ data_b[27] => ~NO_FANOUT~ data_b[28] => ~NO_FANOUT~ data_b[29] => ~NO_FANOUT~ data_b[30] => ~NO_FANOUT~ data_b[31] => ~NO_FANOUT~ address_a[0] => altsyncram_fpd1:auto_generated.address_a[0] address_a[1] => altsyncram_fpd1:auto_generated.address_a[1] address_a[2] => altsyncram_fpd1:auto_generated.address_a[2] address_a[3] => altsyncram_fpd1:auto_generated.address_a[3] address_a[4] => altsyncram_fpd1:auto_generated.address_a[4] address_b[0] => altsyncram_fpd1:auto_generated.address_b[0] address_b[1] => altsyncram_fpd1:auto_generated.address_b[1] address_b[2] => altsyncram_fpd1:auto_generated.address_b[2] address_b[3] => altsyncram_fpd1:auto_generated.address_b[3] address_b[4] => altsyncram_fpd1:auto_generated.address_b[4] addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_fpd1:auto_generated.clock0 clock1 => altsyncram_fpd1:auto_generated.clock1 clocken0 => ~NO_FANOUT~ clocken1 => altsyncram_fpd1:auto_generated.clocken1 clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= q_a[1] <= q_a[2] <= q_a[3] <= q_a[4] <= q_a[5] <= q_a[6] <= q_a[7] <= q_a[8] <= q_a[9] <= q_a[10] <= q_a[11] <= q_a[12] <= q_a[13] <= q_a[14] <= q_a[15] <= q_a[16] <= q_a[17] <= q_a[18] <= q_a[19] <= q_a[20] <= q_a[21] <= q_a[22] <= q_a[23] <= q_a[24] <= q_a[25] <= q_a[26] <= q_a[27] <= q_a[28] <= q_a[29] <= q_a[30] <= q_a[31] <= q_b[0] <= altsyncram_fpd1:auto_generated.q_b[0] q_b[1] <= altsyncram_fpd1:auto_generated.q_b[1] q_b[2] <= altsyncram_fpd1:auto_generated.q_b[2] q_b[3] <= altsyncram_fpd1:auto_generated.q_b[3] q_b[4] <= altsyncram_fpd1:auto_generated.q_b[4] q_b[5] <= altsyncram_fpd1:auto_generated.q_b[5] q_b[6] <= altsyncram_fpd1:auto_generated.q_b[6] q_b[7] <= altsyncram_fpd1:auto_generated.q_b[7] q_b[8] <= altsyncram_fpd1:auto_generated.q_b[8] q_b[9] <= altsyncram_fpd1:auto_generated.q_b[9] q_b[10] <= altsyncram_fpd1:auto_generated.q_b[10] q_b[11] <= altsyncram_fpd1:auto_generated.q_b[11] q_b[12] <= altsyncram_fpd1:auto_generated.q_b[12] q_b[13] <= altsyncram_fpd1:auto_generated.q_b[13] q_b[14] <= altsyncram_fpd1:auto_generated.q_b[14] q_b[15] <= altsyncram_fpd1:auto_generated.q_b[15] q_b[16] <= altsyncram_fpd1:auto_generated.q_b[16] q_b[17] <= altsyncram_fpd1:auto_generated.q_b[17] q_b[18] <= altsyncram_fpd1:auto_generated.q_b[18] q_b[19] <= altsyncram_fpd1:auto_generated.q_b[19] q_b[20] <= altsyncram_fpd1:auto_generated.q_b[20] q_b[21] <= altsyncram_fpd1:auto_generated.q_b[21] q_b[22] <= altsyncram_fpd1:auto_generated.q_b[22] q_b[23] <= altsyncram_fpd1:auto_generated.q_b[23] q_b[24] <= altsyncram_fpd1:auto_generated.q_b[24] q_b[25] <= altsyncram_fpd1:auto_generated.q_b[25] q_b[26] <= altsyncram_fpd1:auto_generated.q_b[26] q_b[27] <= altsyncram_fpd1:auto_generated.q_b[27] q_b[28] <= altsyncram_fpd1:auto_generated.q_b[28] q_b[29] <= altsyncram_fpd1:auto_generated.q_b[29] q_b[30] <= altsyncram_fpd1:auto_generated.q_b[30] q_b[31] <= altsyncram_fpd1:auto_generated.q_b[31] eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_fpd1:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[0] => ram_block1a8.PORTAADDR address_a[0] => ram_block1a9.PORTAADDR address_a[0] => ram_block1a10.PORTAADDR address_a[0] => ram_block1a11.PORTAADDR address_a[0] => ram_block1a12.PORTAADDR address_a[0] => ram_block1a13.PORTAADDR address_a[0] => ram_block1a14.PORTAADDR address_a[0] => ram_block1a15.PORTAADDR address_a[0] => ram_block1a16.PORTAADDR address_a[0] => ram_block1a17.PORTAADDR address_a[0] => ram_block1a18.PORTAADDR address_a[0] => ram_block1a19.PORTAADDR address_a[0] => ram_block1a20.PORTAADDR address_a[0] => ram_block1a21.PORTAADDR address_a[0] => ram_block1a22.PORTAADDR address_a[0] => ram_block1a23.PORTAADDR address_a[0] => ram_block1a24.PORTAADDR address_a[0] => ram_block1a25.PORTAADDR address_a[0] => ram_block1a26.PORTAADDR address_a[0] => ram_block1a27.PORTAADDR address_a[0] => ram_block1a28.PORTAADDR address_a[0] => ram_block1a29.PORTAADDR address_a[0] => ram_block1a30.PORTAADDR address_a[0] => ram_block1a31.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[1] => ram_block1a8.PORTAADDR1 address_a[1] => ram_block1a9.PORTAADDR1 address_a[1] => ram_block1a10.PORTAADDR1 address_a[1] => ram_block1a11.PORTAADDR1 address_a[1] => ram_block1a12.PORTAADDR1 address_a[1] => ram_block1a13.PORTAADDR1 address_a[1] => ram_block1a14.PORTAADDR1 address_a[1] => ram_block1a15.PORTAADDR1 address_a[1] => ram_block1a16.PORTAADDR1 address_a[1] => ram_block1a17.PORTAADDR1 address_a[1] => ram_block1a18.PORTAADDR1 address_a[1] => ram_block1a19.PORTAADDR1 address_a[1] => ram_block1a20.PORTAADDR1 address_a[1] => ram_block1a21.PORTAADDR1 address_a[1] => ram_block1a22.PORTAADDR1 address_a[1] => ram_block1a23.PORTAADDR1 address_a[1] => ram_block1a24.PORTAADDR1 address_a[1] => ram_block1a25.PORTAADDR1 address_a[1] => ram_block1a26.PORTAADDR1 address_a[1] => ram_block1a27.PORTAADDR1 address_a[1] => ram_block1a28.PORTAADDR1 address_a[1] => ram_block1a29.PORTAADDR1 address_a[1] => ram_block1a30.PORTAADDR1 address_a[1] => ram_block1a31.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[2] => ram_block1a8.PORTAADDR2 address_a[2] => ram_block1a9.PORTAADDR2 address_a[2] => ram_block1a10.PORTAADDR2 address_a[2] => ram_block1a11.PORTAADDR2 address_a[2] => ram_block1a12.PORTAADDR2 address_a[2] => ram_block1a13.PORTAADDR2 address_a[2] => ram_block1a14.PORTAADDR2 address_a[2] => ram_block1a15.PORTAADDR2 address_a[2] => ram_block1a16.PORTAADDR2 address_a[2] => ram_block1a17.PORTAADDR2 address_a[2] => ram_block1a18.PORTAADDR2 address_a[2] => ram_block1a19.PORTAADDR2 address_a[2] => ram_block1a20.PORTAADDR2 address_a[2] => ram_block1a21.PORTAADDR2 address_a[2] => ram_block1a22.PORTAADDR2 address_a[2] => ram_block1a23.PORTAADDR2 address_a[2] => ram_block1a24.PORTAADDR2 address_a[2] => ram_block1a25.PORTAADDR2 address_a[2] => ram_block1a26.PORTAADDR2 address_a[2] => ram_block1a27.PORTAADDR2 address_a[2] => ram_block1a28.PORTAADDR2 address_a[2] => ram_block1a29.PORTAADDR2 address_a[2] => ram_block1a30.PORTAADDR2 address_a[2] => ram_block1a31.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[3] => ram_block1a8.PORTAADDR3 address_a[3] => ram_block1a9.PORTAADDR3 address_a[3] => ram_block1a10.PORTAADDR3 address_a[3] => ram_block1a11.PORTAADDR3 address_a[3] => ram_block1a12.PORTAADDR3 address_a[3] => ram_block1a13.PORTAADDR3 address_a[3] => ram_block1a14.PORTAADDR3 address_a[3] => ram_block1a15.PORTAADDR3 address_a[3] => ram_block1a16.PORTAADDR3 address_a[3] => ram_block1a17.PORTAADDR3 address_a[3] => ram_block1a18.PORTAADDR3 address_a[3] => ram_block1a19.PORTAADDR3 address_a[3] => ram_block1a20.PORTAADDR3 address_a[3] => ram_block1a21.PORTAADDR3 address_a[3] => ram_block1a22.PORTAADDR3 address_a[3] => ram_block1a23.PORTAADDR3 address_a[3] => ram_block1a24.PORTAADDR3 address_a[3] => ram_block1a25.PORTAADDR3 address_a[3] => ram_block1a26.PORTAADDR3 address_a[3] => ram_block1a27.PORTAADDR3 address_a[3] => ram_block1a28.PORTAADDR3 address_a[3] => ram_block1a29.PORTAADDR3 address_a[3] => ram_block1a30.PORTAADDR3 address_a[3] => ram_block1a31.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[4] => ram_block1a8.PORTAADDR4 address_a[4] => ram_block1a9.PORTAADDR4 address_a[4] => ram_block1a10.PORTAADDR4 address_a[4] => ram_block1a11.PORTAADDR4 address_a[4] => ram_block1a12.PORTAADDR4 address_a[4] => ram_block1a13.PORTAADDR4 address_a[4] => ram_block1a14.PORTAADDR4 address_a[4] => ram_block1a15.PORTAADDR4 address_a[4] => ram_block1a16.PORTAADDR4 address_a[4] => ram_block1a17.PORTAADDR4 address_a[4] => ram_block1a18.PORTAADDR4 address_a[4] => ram_block1a19.PORTAADDR4 address_a[4] => ram_block1a20.PORTAADDR4 address_a[4] => ram_block1a21.PORTAADDR4 address_a[4] => ram_block1a22.PORTAADDR4 address_a[4] => ram_block1a23.PORTAADDR4 address_a[4] => ram_block1a24.PORTAADDR4 address_a[4] => ram_block1a25.PORTAADDR4 address_a[4] => ram_block1a26.PORTAADDR4 address_a[4] => ram_block1a27.PORTAADDR4 address_a[4] => ram_block1a28.PORTAADDR4 address_a[4] => ram_block1a29.PORTAADDR4 address_a[4] => ram_block1a30.PORTAADDR4 address_a[4] => ram_block1a31.PORTAADDR4 address_b[0] => ram_block1a0.PORTBADDR address_b[0] => ram_block1a1.PORTBADDR address_b[0] => ram_block1a2.PORTBADDR address_b[0] => ram_block1a3.PORTBADDR address_b[0] => ram_block1a4.PORTBADDR address_b[0] => ram_block1a5.PORTBADDR address_b[0] => ram_block1a6.PORTBADDR address_b[0] => ram_block1a7.PORTBADDR address_b[0] => ram_block1a8.PORTBADDR address_b[0] => ram_block1a9.PORTBADDR address_b[0] => ram_block1a10.PORTBADDR address_b[0] => ram_block1a11.PORTBADDR address_b[0] => ram_block1a12.PORTBADDR address_b[0] => ram_block1a13.PORTBADDR address_b[0] => ram_block1a14.PORTBADDR address_b[0] => ram_block1a15.PORTBADDR address_b[0] => ram_block1a16.PORTBADDR address_b[0] => ram_block1a17.PORTBADDR address_b[0] => ram_block1a18.PORTBADDR address_b[0] => ram_block1a19.PORTBADDR address_b[0] => ram_block1a20.PORTBADDR address_b[0] => ram_block1a21.PORTBADDR address_b[0] => ram_block1a22.PORTBADDR address_b[0] => ram_block1a23.PORTBADDR address_b[0] => ram_block1a24.PORTBADDR address_b[0] => ram_block1a25.PORTBADDR address_b[0] => ram_block1a26.PORTBADDR address_b[0] => ram_block1a27.PORTBADDR address_b[0] => ram_block1a28.PORTBADDR address_b[0] => ram_block1a29.PORTBADDR address_b[0] => ram_block1a30.PORTBADDR address_b[0] => ram_block1a31.PORTBADDR address_b[1] => ram_block1a0.PORTBADDR1 address_b[1] => ram_block1a1.PORTBADDR1 address_b[1] => ram_block1a2.PORTBADDR1 address_b[1] => ram_block1a3.PORTBADDR1 address_b[1] => ram_block1a4.PORTBADDR1 address_b[1] => ram_block1a5.PORTBADDR1 address_b[1] => ram_block1a6.PORTBADDR1 address_b[1] => ram_block1a7.PORTBADDR1 address_b[1] => ram_block1a8.PORTBADDR1 address_b[1] => ram_block1a9.PORTBADDR1 address_b[1] => ram_block1a10.PORTBADDR1 address_b[1] => ram_block1a11.PORTBADDR1 address_b[1] => ram_block1a12.PORTBADDR1 address_b[1] => ram_block1a13.PORTBADDR1 address_b[1] => ram_block1a14.PORTBADDR1 address_b[1] => ram_block1a15.PORTBADDR1 address_b[1] => ram_block1a16.PORTBADDR1 address_b[1] => ram_block1a17.PORTBADDR1 address_b[1] => ram_block1a18.PORTBADDR1 address_b[1] => ram_block1a19.PORTBADDR1 address_b[1] => ram_block1a20.PORTBADDR1 address_b[1] => ram_block1a21.PORTBADDR1 address_b[1] => ram_block1a22.PORTBADDR1 address_b[1] => ram_block1a23.PORTBADDR1 address_b[1] => ram_block1a24.PORTBADDR1 address_b[1] => ram_block1a25.PORTBADDR1 address_b[1] => ram_block1a26.PORTBADDR1 address_b[1] => ram_block1a27.PORTBADDR1 address_b[1] => ram_block1a28.PORTBADDR1 address_b[1] => ram_block1a29.PORTBADDR1 address_b[1] => ram_block1a30.PORTBADDR1 address_b[1] => ram_block1a31.PORTBADDR1 address_b[2] => ram_block1a0.PORTBADDR2 address_b[2] => ram_block1a1.PORTBADDR2 address_b[2] => ram_block1a2.PORTBADDR2 address_b[2] => ram_block1a3.PORTBADDR2 address_b[2] => ram_block1a4.PORTBADDR2 address_b[2] => ram_block1a5.PORTBADDR2 address_b[2] => ram_block1a6.PORTBADDR2 address_b[2] => ram_block1a7.PORTBADDR2 address_b[2] => ram_block1a8.PORTBADDR2 address_b[2] => ram_block1a9.PORTBADDR2 address_b[2] => ram_block1a10.PORTBADDR2 address_b[2] => ram_block1a11.PORTBADDR2 address_b[2] => ram_block1a12.PORTBADDR2 address_b[2] => ram_block1a13.PORTBADDR2 address_b[2] => ram_block1a14.PORTBADDR2 address_b[2] => ram_block1a15.PORTBADDR2 address_b[2] => ram_block1a16.PORTBADDR2 address_b[2] => ram_block1a17.PORTBADDR2 address_b[2] => ram_block1a18.PORTBADDR2 address_b[2] => ram_block1a19.PORTBADDR2 address_b[2] => ram_block1a20.PORTBADDR2 address_b[2] => ram_block1a21.PORTBADDR2 address_b[2] => ram_block1a22.PORTBADDR2 address_b[2] => ram_block1a23.PORTBADDR2 address_b[2] => ram_block1a24.PORTBADDR2 address_b[2] => ram_block1a25.PORTBADDR2 address_b[2] => ram_block1a26.PORTBADDR2 address_b[2] => ram_block1a27.PORTBADDR2 address_b[2] => ram_block1a28.PORTBADDR2 address_b[2] => ram_block1a29.PORTBADDR2 address_b[2] => ram_block1a30.PORTBADDR2 address_b[2] => ram_block1a31.PORTBADDR2 address_b[3] => ram_block1a0.PORTBADDR3 address_b[3] => ram_block1a1.PORTBADDR3 address_b[3] => ram_block1a2.PORTBADDR3 address_b[3] => ram_block1a3.PORTBADDR3 address_b[3] => ram_block1a4.PORTBADDR3 address_b[3] => ram_block1a5.PORTBADDR3 address_b[3] => ram_block1a6.PORTBADDR3 address_b[3] => ram_block1a7.PORTBADDR3 address_b[3] => ram_block1a8.PORTBADDR3 address_b[3] => ram_block1a9.PORTBADDR3 address_b[3] => ram_block1a10.PORTBADDR3 address_b[3] => ram_block1a11.PORTBADDR3 address_b[3] => ram_block1a12.PORTBADDR3 address_b[3] => ram_block1a13.PORTBADDR3 address_b[3] => ram_block1a14.PORTBADDR3 address_b[3] => ram_block1a15.PORTBADDR3 address_b[3] => ram_block1a16.PORTBADDR3 address_b[3] => ram_block1a17.PORTBADDR3 address_b[3] => ram_block1a18.PORTBADDR3 address_b[3] => ram_block1a19.PORTBADDR3 address_b[3] => ram_block1a20.PORTBADDR3 address_b[3] => ram_block1a21.PORTBADDR3 address_b[3] => ram_block1a22.PORTBADDR3 address_b[3] => ram_block1a23.PORTBADDR3 address_b[3] => ram_block1a24.PORTBADDR3 address_b[3] => ram_block1a25.PORTBADDR3 address_b[3] => ram_block1a26.PORTBADDR3 address_b[3] => ram_block1a27.PORTBADDR3 address_b[3] => ram_block1a28.PORTBADDR3 address_b[3] => ram_block1a29.PORTBADDR3 address_b[3] => ram_block1a30.PORTBADDR3 address_b[3] => ram_block1a31.PORTBADDR3 address_b[4] => ram_block1a0.PORTBADDR4 address_b[4] => ram_block1a1.PORTBADDR4 address_b[4] => ram_block1a2.PORTBADDR4 address_b[4] => ram_block1a3.PORTBADDR4 address_b[4] => ram_block1a4.PORTBADDR4 address_b[4] => ram_block1a5.PORTBADDR4 address_b[4] => ram_block1a6.PORTBADDR4 address_b[4] => ram_block1a7.PORTBADDR4 address_b[4] => ram_block1a8.PORTBADDR4 address_b[4] => ram_block1a9.PORTBADDR4 address_b[4] => ram_block1a10.PORTBADDR4 address_b[4] => ram_block1a11.PORTBADDR4 address_b[4] => ram_block1a12.PORTBADDR4 address_b[4] => ram_block1a13.PORTBADDR4 address_b[4] => ram_block1a14.PORTBADDR4 address_b[4] => ram_block1a15.PORTBADDR4 address_b[4] => ram_block1a16.PORTBADDR4 address_b[4] => ram_block1a17.PORTBADDR4 address_b[4] => ram_block1a18.PORTBADDR4 address_b[4] => ram_block1a19.PORTBADDR4 address_b[4] => ram_block1a20.PORTBADDR4 address_b[4] => ram_block1a21.PORTBADDR4 address_b[4] => ram_block1a22.PORTBADDR4 address_b[4] => ram_block1a23.PORTBADDR4 address_b[4] => ram_block1a24.PORTBADDR4 address_b[4] => ram_block1a25.PORTBADDR4 address_b[4] => ram_block1a26.PORTBADDR4 address_b[4] => ram_block1a27.PORTBADDR4 address_b[4] => ram_block1a28.PORTBADDR4 address_b[4] => ram_block1a29.PORTBADDR4 address_b[4] => ram_block1a30.PORTBADDR4 address_b[4] => ram_block1a31.PORTBADDR4 clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 clock0 => ram_block1a8.CLK0 clock0 => ram_block1a9.CLK0 clock0 => ram_block1a10.CLK0 clock0 => ram_block1a11.CLK0 clock0 => ram_block1a12.CLK0 clock0 => ram_block1a13.CLK0 clock0 => ram_block1a14.CLK0 clock0 => ram_block1a15.CLK0 clock0 => ram_block1a16.CLK0 clock0 => ram_block1a17.CLK0 clock0 => ram_block1a18.CLK0 clock0 => ram_block1a19.CLK0 clock0 => ram_block1a20.CLK0 clock0 => ram_block1a21.CLK0 clock0 => ram_block1a22.CLK0 clock0 => ram_block1a23.CLK0 clock0 => ram_block1a24.CLK0 clock0 => ram_block1a25.CLK0 clock0 => ram_block1a26.CLK0 clock0 => ram_block1a27.CLK0 clock0 => ram_block1a28.CLK0 clock0 => ram_block1a29.CLK0 clock0 => ram_block1a30.CLK0 clock0 => ram_block1a31.CLK0 clock1 => ram_block1a0.CLK1 clock1 => ram_block1a1.CLK1 clock1 => ram_block1a2.CLK1 clock1 => ram_block1a3.CLK1 clock1 => ram_block1a4.CLK1 clock1 => ram_block1a5.CLK1 clock1 => ram_block1a6.CLK1 clock1 => ram_block1a7.CLK1 clock1 => ram_block1a8.CLK1 clock1 => ram_block1a9.CLK1 clock1 => ram_block1a10.CLK1 clock1 => ram_block1a11.CLK1 clock1 => ram_block1a12.CLK1 clock1 => ram_block1a13.CLK1 clock1 => ram_block1a14.CLK1 clock1 => ram_block1a15.CLK1 clock1 => ram_block1a16.CLK1 clock1 => ram_block1a17.CLK1 clock1 => ram_block1a18.CLK1 clock1 => ram_block1a19.CLK1 clock1 => ram_block1a20.CLK1 clock1 => ram_block1a21.CLK1 clock1 => ram_block1a22.CLK1 clock1 => ram_block1a23.CLK1 clock1 => ram_block1a24.CLK1 clock1 => ram_block1a25.CLK1 clock1 => ram_block1a26.CLK1 clock1 => ram_block1a27.CLK1 clock1 => ram_block1a28.CLK1 clock1 => ram_block1a29.CLK1 clock1 => ram_block1a30.CLK1 clock1 => ram_block1a31.CLK1 clocken1 => ram_block1a0.ENA1 clocken1 => ram_block1a1.ENA1 clocken1 => ram_block1a2.ENA1 clocken1 => ram_block1a3.ENA1 clocken1 => ram_block1a4.ENA1 clocken1 => ram_block1a5.ENA1 clocken1 => ram_block1a6.ENA1 clocken1 => ram_block1a7.ENA1 clocken1 => ram_block1a8.ENA1 clocken1 => ram_block1a9.ENA1 clocken1 => ram_block1a10.ENA1 clocken1 => ram_block1a11.ENA1 clocken1 => ram_block1a12.ENA1 clocken1 => ram_block1a13.ENA1 clocken1 => ram_block1a14.ENA1 clocken1 => ram_block1a15.ENA1 clocken1 => ram_block1a16.ENA1 clocken1 => ram_block1a17.ENA1 clocken1 => ram_block1a18.ENA1 clocken1 => ram_block1a19.ENA1 clocken1 => ram_block1a20.ENA1 clocken1 => ram_block1a21.ENA1 clocken1 => ram_block1a22.ENA1 clocken1 => ram_block1a23.ENA1 clocken1 => ram_block1a24.ENA1 clocken1 => ram_block1a25.ENA1 clocken1 => ram_block1a26.ENA1 clocken1 => ram_block1a27.ENA1 clocken1 => ram_block1a28.ENA1 clocken1 => ram_block1a29.ENA1 clocken1 => ram_block1a30.ENA1 clocken1 => ram_block1a31.ENA1 data_a[0] => ram_block1a0.PORTADATAIN data_a[1] => ram_block1a1.PORTADATAIN data_a[2] => ram_block1a2.PORTADATAIN data_a[3] => ram_block1a3.PORTADATAIN data_a[4] => ram_block1a4.PORTADATAIN data_a[5] => ram_block1a5.PORTADATAIN data_a[6] => ram_block1a6.PORTADATAIN data_a[7] => ram_block1a7.PORTADATAIN data_a[8] => ram_block1a8.PORTADATAIN data_a[9] => ram_block1a9.PORTADATAIN data_a[10] => ram_block1a10.PORTADATAIN data_a[11] => ram_block1a11.PORTADATAIN data_a[12] => ram_block1a12.PORTADATAIN data_a[13] => ram_block1a13.PORTADATAIN data_a[14] => ram_block1a14.PORTADATAIN data_a[15] => ram_block1a15.PORTADATAIN data_a[16] => ram_block1a16.PORTADATAIN data_a[17] => ram_block1a17.PORTADATAIN data_a[18] => ram_block1a18.PORTADATAIN data_a[19] => ram_block1a19.PORTADATAIN data_a[20] => ram_block1a20.PORTADATAIN data_a[21] => ram_block1a21.PORTADATAIN data_a[22] => ram_block1a22.PORTADATAIN data_a[23] => ram_block1a23.PORTADATAIN data_a[24] => ram_block1a24.PORTADATAIN data_a[25] => ram_block1a25.PORTADATAIN data_a[26] => ram_block1a26.PORTADATAIN data_a[27] => ram_block1a27.PORTADATAIN data_a[28] => ram_block1a28.PORTADATAIN data_a[29] => ram_block1a29.PORTADATAIN data_a[30] => ram_block1a30.PORTADATAIN data_a[31] => ram_block1a31.PORTADATAIN q_b[0] <= ram_block1a0.PORTBDATAOUT q_b[1] <= ram_block1a1.PORTBDATAOUT q_b[2] <= ram_block1a2.PORTBDATAOUT q_b[3] <= ram_block1a3.PORTBDATAOUT q_b[4] <= ram_block1a4.PORTBDATAOUT q_b[5] <= ram_block1a5.PORTBDATAOUT q_b[6] <= ram_block1a6.PORTBDATAOUT q_b[7] <= ram_block1a7.PORTBDATAOUT q_b[8] <= ram_block1a8.PORTBDATAOUT q_b[9] <= ram_block1a9.PORTBDATAOUT q_b[10] <= ram_block1a10.PORTBDATAOUT q_b[11] <= ram_block1a11.PORTBDATAOUT q_b[12] <= ram_block1a12.PORTBDATAOUT q_b[13] <= ram_block1a13.PORTBDATAOUT q_b[14] <= ram_block1a14.PORTBDATAOUT q_b[15] <= ram_block1a15.PORTBDATAOUT q_b[16] <= ram_block1a16.PORTBDATAOUT q_b[17] <= ram_block1a17.PORTBDATAOUT q_b[18] <= ram_block1a18.PORTBDATAOUT q_b[19] <= ram_block1a19.PORTBDATAOUT q_b[20] <= ram_block1a20.PORTBDATAOUT q_b[21] <= ram_block1a21.PORTBDATAOUT q_b[22] <= ram_block1a22.PORTBDATAOUT q_b[23] <= ram_block1a23.PORTBDATAOUT q_b[24] <= ram_block1a24.PORTBDATAOUT q_b[25] <= ram_block1a25.PORTBDATAOUT q_b[26] <= ram_block1a26.PORTBDATAOUT q_b[27] <= ram_block1a27.PORTBDATAOUT q_b[28] <= ram_block1a28.PORTBDATAOUT q_b[29] <= ram_block1a29.PORTBDATAOUT q_b[30] <= ram_block1a30.PORTBDATAOUT q_b[31] <= ram_block1a31.PORTBDATAOUT wren_a => ram_block1a0.ENA0 wren_a => ram_block1a1.ENA0 wren_a => ram_block1a2.ENA0 wren_a => ram_block1a3.ENA0 wren_a => ram_block1a4.ENA0 wren_a => ram_block1a5.ENA0 wren_a => ram_block1a6.ENA0 wren_a => ram_block1a7.ENA0 wren_a => ram_block1a8.ENA0 wren_a => ram_block1a9.ENA0 wren_a => ram_block1a10.ENA0 wren_a => ram_block1a11.ENA0 wren_a => ram_block1a12.ENA0 wren_a => ram_block1a13.ENA0 wren_a => ram_block1a14.ENA0 wren_a => ram_block1a15.ENA0 wren_a => ram_block1a16.ENA0 wren_a => ram_block1a17.ENA0 wren_a => ram_block1a18.ENA0 wren_a => ram_block1a19.ENA0 wren_a => ram_block1a20.ENA0 wren_a => ram_block1a21.ENA0 wren_a => ram_block1a22.ENA0 wren_a => ram_block1a23.ENA0 wren_a => ram_block1a24.ENA0 wren_a => ram_block1a25.ENA0 wren_a => ram_block1a26.ENA0 wren_a => ram_block1a27.ENA0 wren_a => ram_block1a28.ENA0 wren_a => ram_block1a29.ENA0 wren_a => ram_block1a30.ENA0 wren_a => ram_block1a31.ENA0 |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag address_a[0] => address_a[0]~8.IN1 address_a[1] => address_a[1]~7.IN1 address_a[2] => address_a[2]~6.IN1 address_a[3] => address_a[3]~5.IN1 address_a[4] => address_a[4]~4.IN1 address_a[5] => address_a[5]~3.IN1 address_a[6] => address_a[6]~2.IN1 address_a[7] => address_a[7]~1.IN1 address_a[8] => address_a[8]~0.IN1 address_b[0] => address_b[0]~8.IN1 address_b[1] => address_b[1]~7.IN1 address_b[2] => address_b[2]~6.IN1 address_b[3] => address_b[3]~5.IN1 address_b[4] => address_b[4]~4.IN1 address_b[5] => address_b[5]~3.IN1 address_b[6] => address_b[6]~2.IN1 address_b[7] => address_b[7]~1.IN1 address_b[8] => address_b[8]~0.IN1 clock0 => clock0~0.IN1 clock1 => clock1~0.IN1 clocken0 => clocken0~0.IN1 clocken1 => clocken1~0.IN1 data_b[0] => data_b[0]~14.IN1 data_b[1] => data_b[1]~13.IN1 data_b[2] => data_b[2]~12.IN1 data_b[3] => data_b[3]~11.IN1 data_b[4] => data_b[4]~10.IN1 data_b[5] => data_b[5]~9.IN1 data_b[6] => data_b[6]~8.IN1 data_b[7] => data_b[7]~7.IN1 data_b[8] => data_b[8]~6.IN1 data_b[9] => data_b[9]~5.IN1 data_b[10] => data_b[10]~4.IN1 data_b[11] => data_b[11]~3.IN1 data_b[12] => data_b[12]~2.IN1 data_b[13] => data_b[13]~1.IN1 data_b[14] => data_b[14]~0.IN1 wren_b => wren_b~0.IN1 q_a[0] <= altsyncram:the_altsyncram.q_a q_a[1] <= altsyncram:the_altsyncram.q_a q_a[2] <= altsyncram:the_altsyncram.q_a q_a[3] <= altsyncram:the_altsyncram.q_a q_a[4] <= altsyncram:the_altsyncram.q_a q_a[5] <= altsyncram:the_altsyncram.q_a q_a[6] <= altsyncram:the_altsyncram.q_a q_a[7] <= altsyncram:the_altsyncram.q_a q_a[8] <= altsyncram:the_altsyncram.q_a q_a[9] <= altsyncram:the_altsyncram.q_a q_a[10] <= altsyncram:the_altsyncram.q_a q_a[11] <= altsyncram:the_altsyncram.q_a q_a[12] <= altsyncram:the_altsyncram.q_a q_a[13] <= altsyncram:the_altsyncram.q_a q_a[14] <= altsyncram:the_altsyncram.q_a q_b[0] <= altsyncram:the_altsyncram.q_b q_b[1] <= altsyncram:the_altsyncram.q_b q_b[2] <= altsyncram:the_altsyncram.q_b q_b[3] <= altsyncram:the_altsyncram.q_b q_b[4] <= altsyncram:the_altsyncram.q_b q_b[5] <= altsyncram:the_altsyncram.q_b q_b[6] <= altsyncram:the_altsyncram.q_b q_b[7] <= altsyncram:the_altsyncram.q_b q_b[8] <= altsyncram:the_altsyncram.q_b q_b[9] <= altsyncram:the_altsyncram.q_b q_b[10] <= altsyncram:the_altsyncram.q_b q_b[11] <= altsyncram:the_altsyncram.q_b q_b[12] <= altsyncram:the_altsyncram.q_b q_b[13] <= altsyncram:the_altsyncram.q_b q_b[14] <= altsyncram:the_altsyncram.q_b |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram wren_a => ~NO_FANOUT~ rden_a => ~NO_FANOUT~ wren_b => altsyncram_9u12:auto_generated.wren_b rden_b => ~NO_FANOUT~ data_a[0] => altsyncram_9u12:auto_generated.data_a[0] data_a[1] => altsyncram_9u12:auto_generated.data_a[1] data_a[2] => altsyncram_9u12:auto_generated.data_a[2] data_a[3] => altsyncram_9u12:auto_generated.data_a[3] data_a[4] => altsyncram_9u12:auto_generated.data_a[4] data_a[5] => altsyncram_9u12:auto_generated.data_a[5] data_a[6] => altsyncram_9u12:auto_generated.data_a[6] data_a[7] => altsyncram_9u12:auto_generated.data_a[7] data_a[8] => altsyncram_9u12:auto_generated.data_a[8] data_a[9] => altsyncram_9u12:auto_generated.data_a[9] data_a[10] => altsyncram_9u12:auto_generated.data_a[10] data_a[11] => altsyncram_9u12:auto_generated.data_a[11] data_a[12] => altsyncram_9u12:auto_generated.data_a[12] data_a[13] => altsyncram_9u12:auto_generated.data_a[13] data_a[14] => altsyncram_9u12:auto_generated.data_a[14] data_b[0] => altsyncram_9u12:auto_generated.data_b[0] data_b[1] => altsyncram_9u12:auto_generated.data_b[1] data_b[2] => altsyncram_9u12:auto_generated.data_b[2] data_b[3] => altsyncram_9u12:auto_generated.data_b[3] data_b[4] => altsyncram_9u12:auto_generated.data_b[4] data_b[5] => altsyncram_9u12:auto_generated.data_b[5] data_b[6] => altsyncram_9u12:auto_generated.data_b[6] data_b[7] => altsyncram_9u12:auto_generated.data_b[7] data_b[8] => altsyncram_9u12:auto_generated.data_b[8] data_b[9] => altsyncram_9u12:auto_generated.data_b[9] data_b[10] => altsyncram_9u12:auto_generated.data_b[10] data_b[11] => altsyncram_9u12:auto_generated.data_b[11] data_b[12] => altsyncram_9u12:auto_generated.data_b[12] data_b[13] => altsyncram_9u12:auto_generated.data_b[13] data_b[14] => altsyncram_9u12:auto_generated.data_b[14] address_a[0] => altsyncram_9u12:auto_generated.address_a[0] address_a[1] => altsyncram_9u12:auto_generated.address_a[1] address_a[2] => altsyncram_9u12:auto_generated.address_a[2] address_a[3] => altsyncram_9u12:auto_generated.address_a[3] address_a[4] => altsyncram_9u12:auto_generated.address_a[4] address_a[5] => altsyncram_9u12:auto_generated.address_a[5] address_a[6] => altsyncram_9u12:auto_generated.address_a[6] address_a[7] => altsyncram_9u12:auto_generated.address_a[7] address_a[8] => altsyncram_9u12:auto_generated.address_a[8] address_b[0] => altsyncram_9u12:auto_generated.address_b[0] address_b[1] => altsyncram_9u12:auto_generated.address_b[1] address_b[2] => altsyncram_9u12:auto_generated.address_b[2] address_b[3] => altsyncram_9u12:auto_generated.address_b[3] address_b[4] => altsyncram_9u12:auto_generated.address_b[4] address_b[5] => altsyncram_9u12:auto_generated.address_b[5] address_b[6] => altsyncram_9u12:auto_generated.address_b[6] address_b[7] => altsyncram_9u12:auto_generated.address_b[7] address_b[8] => altsyncram_9u12:auto_generated.address_b[8] addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_9u12:auto_generated.clock0 clock1 => altsyncram_9u12:auto_generated.clock1 clocken0 => altsyncram_9u12:auto_generated.clocken0 clocken1 => altsyncram_9u12:auto_generated.clocken1 clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= altsyncram_9u12:auto_generated.q_a[0] q_a[1] <= altsyncram_9u12:auto_generated.q_a[1] q_a[2] <= altsyncram_9u12:auto_generated.q_a[2] q_a[3] <= altsyncram_9u12:auto_generated.q_a[3] q_a[4] <= altsyncram_9u12:auto_generated.q_a[4] q_a[5] <= altsyncram_9u12:auto_generated.q_a[5] q_a[6] <= altsyncram_9u12:auto_generated.q_a[6] q_a[7] <= altsyncram_9u12:auto_generated.q_a[7] q_a[8] <= altsyncram_9u12:auto_generated.q_a[8] q_a[9] <= altsyncram_9u12:auto_generated.q_a[9] q_a[10] <= altsyncram_9u12:auto_generated.q_a[10] q_a[11] <= altsyncram_9u12:auto_generated.q_a[11] q_a[12] <= altsyncram_9u12:auto_generated.q_a[12] q_a[13] <= altsyncram_9u12:auto_generated.q_a[13] q_a[14] <= altsyncram_9u12:auto_generated.q_a[14] q_b[0] <= altsyncram_9u12:auto_generated.q_b[0] q_b[1] <= altsyncram_9u12:auto_generated.q_b[1] q_b[2] <= altsyncram_9u12:auto_generated.q_b[2] q_b[3] <= altsyncram_9u12:auto_generated.q_b[3] q_b[4] <= altsyncram_9u12:auto_generated.q_b[4] q_b[5] <= altsyncram_9u12:auto_generated.q_b[5] q_b[6] <= altsyncram_9u12:auto_generated.q_b[6] q_b[7] <= altsyncram_9u12:auto_generated.q_b[7] q_b[8] <= altsyncram_9u12:auto_generated.q_b[8] q_b[9] <= altsyncram_9u12:auto_generated.q_b[9] q_b[10] <= altsyncram_9u12:auto_generated.q_b[10] q_b[11] <= altsyncram_9u12:auto_generated.q_b[11] q_b[12] <= altsyncram_9u12:auto_generated.q_b[12] q_b[13] <= altsyncram_9u12:auto_generated.q_b[13] q_b[14] <= altsyncram_9u12:auto_generated.q_b[14] eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_9u12:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[0] => ram_block1a8.PORTAADDR address_a[0] => ram_block1a9.PORTAADDR address_a[0] => ram_block1a10.PORTAADDR address_a[0] => ram_block1a11.PORTAADDR address_a[0] => ram_block1a12.PORTAADDR address_a[0] => ram_block1a13.PORTAADDR address_a[0] => ram_block1a14.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[1] => ram_block1a8.PORTAADDR1 address_a[1] => ram_block1a9.PORTAADDR1 address_a[1] => ram_block1a10.PORTAADDR1 address_a[1] => ram_block1a11.PORTAADDR1 address_a[1] => ram_block1a12.PORTAADDR1 address_a[1] => ram_block1a13.PORTAADDR1 address_a[1] => ram_block1a14.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[2] => ram_block1a8.PORTAADDR2 address_a[2] => ram_block1a9.PORTAADDR2 address_a[2] => ram_block1a10.PORTAADDR2 address_a[2] => ram_block1a11.PORTAADDR2 address_a[2] => ram_block1a12.PORTAADDR2 address_a[2] => ram_block1a13.PORTAADDR2 address_a[2] => ram_block1a14.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[3] => ram_block1a8.PORTAADDR3 address_a[3] => ram_block1a9.PORTAADDR3 address_a[3] => ram_block1a10.PORTAADDR3 address_a[3] => ram_block1a11.PORTAADDR3 address_a[3] => ram_block1a12.PORTAADDR3 address_a[3] => ram_block1a13.PORTAADDR3 address_a[3] => ram_block1a14.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[4] => ram_block1a8.PORTAADDR4 address_a[4] => ram_block1a9.PORTAADDR4 address_a[4] => ram_block1a10.PORTAADDR4 address_a[4] => ram_block1a11.PORTAADDR4 address_a[4] => ram_block1a12.PORTAADDR4 address_a[4] => ram_block1a13.PORTAADDR4 address_a[4] => ram_block1a14.PORTAADDR4 address_a[5] => ram_block1a0.PORTAADDR5 address_a[5] => ram_block1a1.PORTAADDR5 address_a[5] => ram_block1a2.PORTAADDR5 address_a[5] => ram_block1a3.PORTAADDR5 address_a[5] => ram_block1a4.PORTAADDR5 address_a[5] => ram_block1a5.PORTAADDR5 address_a[5] => ram_block1a6.PORTAADDR5 address_a[5] => ram_block1a7.PORTAADDR5 address_a[5] => ram_block1a8.PORTAADDR5 address_a[5] => ram_block1a9.PORTAADDR5 address_a[5] => ram_block1a10.PORTAADDR5 address_a[5] => ram_block1a11.PORTAADDR5 address_a[5] => ram_block1a12.PORTAADDR5 address_a[5] => ram_block1a13.PORTAADDR5 address_a[5] => ram_block1a14.PORTAADDR5 address_a[6] => ram_block1a0.PORTAADDR6 address_a[6] => ram_block1a1.PORTAADDR6 address_a[6] => ram_block1a2.PORTAADDR6 address_a[6] => ram_block1a3.PORTAADDR6 address_a[6] => ram_block1a4.PORTAADDR6 address_a[6] => ram_block1a5.PORTAADDR6 address_a[6] => ram_block1a6.PORTAADDR6 address_a[6] => ram_block1a7.PORTAADDR6 address_a[6] => ram_block1a8.PORTAADDR6 address_a[6] => ram_block1a9.PORTAADDR6 address_a[6] => ram_block1a10.PORTAADDR6 address_a[6] => ram_block1a11.PORTAADDR6 address_a[6] => ram_block1a12.PORTAADDR6 address_a[6] => ram_block1a13.PORTAADDR6 address_a[6] => ram_block1a14.PORTAADDR6 address_a[7] => ram_block1a0.PORTAADDR7 address_a[7] => ram_block1a1.PORTAADDR7 address_a[7] => ram_block1a2.PORTAADDR7 address_a[7] => ram_block1a3.PORTAADDR7 address_a[7] => ram_block1a4.PORTAADDR7 address_a[7] => ram_block1a5.PORTAADDR7 address_a[7] => ram_block1a6.PORTAADDR7 address_a[7] => ram_block1a7.PORTAADDR7 address_a[7] => ram_block1a8.PORTAADDR7 address_a[7] => ram_block1a9.PORTAADDR7 address_a[7] => ram_block1a10.PORTAADDR7 address_a[7] => ram_block1a11.PORTAADDR7 address_a[7] => ram_block1a12.PORTAADDR7 address_a[7] => ram_block1a13.PORTAADDR7 address_a[7] => ram_block1a14.PORTAADDR7 address_a[8] => ram_block1a0.PORTAADDR8 address_a[8] => ram_block1a1.PORTAADDR8 address_a[8] => ram_block1a2.PORTAADDR8 address_a[8] => ram_block1a3.PORTAADDR8 address_a[8] => ram_block1a4.PORTAADDR8 address_a[8] => ram_block1a5.PORTAADDR8 address_a[8] => ram_block1a6.PORTAADDR8 address_a[8] => ram_block1a7.PORTAADDR8 address_a[8] => ram_block1a8.PORTAADDR8 address_a[8] => ram_block1a9.PORTAADDR8 address_a[8] => ram_block1a10.PORTAADDR8 address_a[8] => ram_block1a11.PORTAADDR8 address_a[8] => ram_block1a12.PORTAADDR8 address_a[8] => ram_block1a13.PORTAADDR8 address_a[8] => ram_block1a14.PORTAADDR8 address_b[0] => ram_block1a0.PORTBADDR address_b[0] => ram_block1a1.PORTBADDR address_b[0] => ram_block1a2.PORTBADDR address_b[0] => ram_block1a3.PORTBADDR address_b[0] => ram_block1a4.PORTBADDR address_b[0] => ram_block1a5.PORTBADDR address_b[0] => ram_block1a6.PORTBADDR address_b[0] => ram_block1a7.PORTBADDR address_b[0] => ram_block1a8.PORTBADDR address_b[0] => ram_block1a9.PORTBADDR address_b[0] => ram_block1a10.PORTBADDR address_b[0] => ram_block1a11.PORTBADDR address_b[0] => ram_block1a12.PORTBADDR address_b[0] => ram_block1a13.PORTBADDR address_b[0] => ram_block1a14.PORTBADDR address_b[1] => ram_block1a0.PORTBADDR1 address_b[1] => ram_block1a1.PORTBADDR1 address_b[1] => ram_block1a2.PORTBADDR1 address_b[1] => ram_block1a3.PORTBADDR1 address_b[1] => ram_block1a4.PORTBADDR1 address_b[1] => ram_block1a5.PORTBADDR1 address_b[1] => ram_block1a6.PORTBADDR1 address_b[1] => ram_block1a7.PORTBADDR1 address_b[1] => ram_block1a8.PORTBADDR1 address_b[1] => ram_block1a9.PORTBADDR1 address_b[1] => ram_block1a10.PORTBADDR1 address_b[1] => ram_block1a11.PORTBADDR1 address_b[1] => ram_block1a12.PORTBADDR1 address_b[1] => ram_block1a13.PORTBADDR1 address_b[1] => ram_block1a14.PORTBADDR1 address_b[2] => ram_block1a0.PORTBADDR2 address_b[2] => ram_block1a1.PORTBADDR2 address_b[2] => ram_block1a2.PORTBADDR2 address_b[2] => ram_block1a3.PORTBADDR2 address_b[2] => ram_block1a4.PORTBADDR2 address_b[2] => ram_block1a5.PORTBADDR2 address_b[2] => ram_block1a6.PORTBADDR2 address_b[2] => ram_block1a7.PORTBADDR2 address_b[2] => ram_block1a8.PORTBADDR2 address_b[2] => ram_block1a9.PORTBADDR2 address_b[2] => ram_block1a10.PORTBADDR2 address_b[2] => ram_block1a11.PORTBADDR2 address_b[2] => ram_block1a12.PORTBADDR2 address_b[2] => ram_block1a13.PORTBADDR2 address_b[2] => ram_block1a14.PORTBADDR2 address_b[3] => ram_block1a0.PORTBADDR3 address_b[3] => ram_block1a1.PORTBADDR3 address_b[3] => ram_block1a2.PORTBADDR3 address_b[3] => ram_block1a3.PORTBADDR3 address_b[3] => ram_block1a4.PORTBADDR3 address_b[3] => ram_block1a5.PORTBADDR3 address_b[3] => ram_block1a6.PORTBADDR3 address_b[3] => ram_block1a7.PORTBADDR3 address_b[3] => ram_block1a8.PORTBADDR3 address_b[3] => ram_block1a9.PORTBADDR3 address_b[3] => ram_block1a10.PORTBADDR3 address_b[3] => ram_block1a11.PORTBADDR3 address_b[3] => ram_block1a12.PORTBADDR3 address_b[3] => ram_block1a13.PORTBADDR3 address_b[3] => ram_block1a14.PORTBADDR3 address_b[4] => ram_block1a0.PORTBADDR4 address_b[4] => ram_block1a1.PORTBADDR4 address_b[4] => ram_block1a2.PORTBADDR4 address_b[4] => ram_block1a3.PORTBADDR4 address_b[4] => ram_block1a4.PORTBADDR4 address_b[4] => ram_block1a5.PORTBADDR4 address_b[4] => ram_block1a6.PORTBADDR4 address_b[4] => ram_block1a7.PORTBADDR4 address_b[4] => ram_block1a8.PORTBADDR4 address_b[4] => ram_block1a9.PORTBADDR4 address_b[4] => ram_block1a10.PORTBADDR4 address_b[4] => ram_block1a11.PORTBADDR4 address_b[4] => ram_block1a12.PORTBADDR4 address_b[4] => ram_block1a13.PORTBADDR4 address_b[4] => ram_block1a14.PORTBADDR4 address_b[5] => ram_block1a0.PORTBADDR5 address_b[5] => ram_block1a1.PORTBADDR5 address_b[5] => ram_block1a2.PORTBADDR5 address_b[5] => ram_block1a3.PORTBADDR5 address_b[5] => ram_block1a4.PORTBADDR5 address_b[5] => ram_block1a5.PORTBADDR5 address_b[5] => ram_block1a6.PORTBADDR5 address_b[5] => ram_block1a7.PORTBADDR5 address_b[5] => ram_block1a8.PORTBADDR5 address_b[5] => ram_block1a9.PORTBADDR5 address_b[5] => ram_block1a10.PORTBADDR5 address_b[5] => ram_block1a11.PORTBADDR5 address_b[5] => ram_block1a12.PORTBADDR5 address_b[5] => ram_block1a13.PORTBADDR5 address_b[5] => ram_block1a14.PORTBADDR5 address_b[6] => ram_block1a0.PORTBADDR6 address_b[6] => ram_block1a1.PORTBADDR6 address_b[6] => ram_block1a2.PORTBADDR6 address_b[6] => ram_block1a3.PORTBADDR6 address_b[6] => ram_block1a4.PORTBADDR6 address_b[6] => ram_block1a5.PORTBADDR6 address_b[6] => ram_block1a6.PORTBADDR6 address_b[6] => ram_block1a7.PORTBADDR6 address_b[6] => ram_block1a8.PORTBADDR6 address_b[6] => ram_block1a9.PORTBADDR6 address_b[6] => ram_block1a10.PORTBADDR6 address_b[6] => ram_block1a11.PORTBADDR6 address_b[6] => ram_block1a12.PORTBADDR6 address_b[6] => ram_block1a13.PORTBADDR6 address_b[6] => ram_block1a14.PORTBADDR6 address_b[7] => ram_block1a0.PORTBADDR7 address_b[7] => ram_block1a1.PORTBADDR7 address_b[7] => ram_block1a2.PORTBADDR7 address_b[7] => ram_block1a3.PORTBADDR7 address_b[7] => ram_block1a4.PORTBADDR7 address_b[7] => ram_block1a5.PORTBADDR7 address_b[7] => ram_block1a6.PORTBADDR7 address_b[7] => ram_block1a7.PORTBADDR7 address_b[7] => ram_block1a8.PORTBADDR7 address_b[7] => ram_block1a9.PORTBADDR7 address_b[7] => ram_block1a10.PORTBADDR7 address_b[7] => ram_block1a11.PORTBADDR7 address_b[7] => ram_block1a12.PORTBADDR7 address_b[7] => ram_block1a13.PORTBADDR7 address_b[7] => ram_block1a14.PORTBADDR7 address_b[8] => ram_block1a0.PORTBADDR8 address_b[8] => ram_block1a1.PORTBADDR8 address_b[8] => ram_block1a2.PORTBADDR8 address_b[8] => ram_block1a3.PORTBADDR8 address_b[8] => ram_block1a4.PORTBADDR8 address_b[8] => ram_block1a5.PORTBADDR8 address_b[8] => ram_block1a6.PORTBADDR8 address_b[8] => ram_block1a7.PORTBADDR8 address_b[8] => ram_block1a8.PORTBADDR8 address_b[8] => ram_block1a9.PORTBADDR8 address_b[8] => ram_block1a10.PORTBADDR8 address_b[8] => ram_block1a11.PORTBADDR8 address_b[8] => ram_block1a12.PORTBADDR8 address_b[8] => ram_block1a13.PORTBADDR8 address_b[8] => ram_block1a14.PORTBADDR8 clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 clock0 => ram_block1a8.CLK0 clock0 => ram_block1a9.CLK0 clock0 => ram_block1a10.CLK0 clock0 => ram_block1a11.CLK0 clock0 => ram_block1a12.CLK0 clock0 => ram_block1a13.CLK0 clock0 => ram_block1a14.CLK0 clock1 => ram_block1a0.CLK1 clock1 => ram_block1a1.CLK1 clock1 => ram_block1a2.CLK1 clock1 => ram_block1a3.CLK1 clock1 => ram_block1a4.CLK1 clock1 => ram_block1a5.CLK1 clock1 => ram_block1a6.CLK1 clock1 => ram_block1a7.CLK1 clock1 => ram_block1a8.CLK1 clock1 => ram_block1a9.CLK1 clock1 => ram_block1a10.CLK1 clock1 => ram_block1a11.CLK1 clock1 => ram_block1a12.CLK1 clock1 => ram_block1a13.CLK1 clock1 => ram_block1a14.CLK1 clocken0 => ram_block1a0.ENA0 clocken0 => ram_block1a1.ENA0 clocken0 => ram_block1a2.ENA0 clocken0 => ram_block1a3.ENA0 clocken0 => ram_block1a4.ENA0 clocken0 => ram_block1a5.ENA0 clocken0 => ram_block1a6.ENA0 clocken0 => ram_block1a7.ENA0 clocken0 => ram_block1a8.ENA0 clocken0 => ram_block1a9.ENA0 clocken0 => ram_block1a10.ENA0 clocken0 => ram_block1a11.ENA0 clocken0 => ram_block1a12.ENA0 clocken0 => ram_block1a13.ENA0 clocken0 => ram_block1a14.ENA0 clocken1 => ram_block1a0.ENA1 clocken1 => ram_block1a1.ENA1 clocken1 => ram_block1a2.ENA1 clocken1 => ram_block1a3.ENA1 clocken1 => ram_block1a4.ENA1 clocken1 => ram_block1a5.ENA1 clocken1 => ram_block1a6.ENA1 clocken1 => ram_block1a7.ENA1 clocken1 => ram_block1a8.ENA1 clocken1 => ram_block1a9.ENA1 clocken1 => ram_block1a10.ENA1 clocken1 => ram_block1a11.ENA1 clocken1 => ram_block1a12.ENA1 clocken1 => ram_block1a13.ENA1 clocken1 => ram_block1a14.ENA1 data_a[0] => ram_block1a0.PORTADATAIN data_a[1] => ram_block1a1.PORTADATAIN data_a[2] => ram_block1a2.PORTADATAIN data_a[3] => ram_block1a3.PORTADATAIN data_a[4] => ram_block1a4.PORTADATAIN data_a[5] => ram_block1a5.PORTADATAIN data_a[6] => ram_block1a6.PORTADATAIN data_a[7] => ram_block1a7.PORTADATAIN data_a[8] => ram_block1a8.PORTADATAIN data_a[9] => ram_block1a9.PORTADATAIN data_a[10] => ram_block1a10.PORTADATAIN data_a[11] => ram_block1a11.PORTADATAIN data_a[12] => ram_block1a12.PORTADATAIN data_a[13] => ram_block1a13.PORTADATAIN data_a[14] => ram_block1a14.PORTADATAIN data_b[0] => ram_block1a0.PORTBDATAIN data_b[1] => ram_block1a1.PORTBDATAIN data_b[2] => ram_block1a2.PORTBDATAIN data_b[3] => ram_block1a3.PORTBDATAIN data_b[4] => ram_block1a4.PORTBDATAIN data_b[5] => ram_block1a5.PORTBDATAIN data_b[6] => ram_block1a6.PORTBDATAIN data_b[7] => ram_block1a7.PORTBDATAIN data_b[8] => ram_block1a8.PORTBDATAIN data_b[9] => ram_block1a9.PORTBDATAIN data_b[10] => ram_block1a10.PORTBDATAIN data_b[11] => ram_block1a11.PORTBDATAIN data_b[12] => ram_block1a12.PORTBDATAIN data_b[13] => ram_block1a13.PORTBDATAIN data_b[14] => ram_block1a14.PORTBDATAIN q_a[0] <= ram_block1a0.PORTADATAOUT q_a[1] <= ram_block1a1.PORTADATAOUT q_a[2] <= ram_block1a2.PORTADATAOUT q_a[3] <= ram_block1a3.PORTADATAOUT q_a[4] <= ram_block1a4.PORTADATAOUT q_a[5] <= ram_block1a5.PORTADATAOUT q_a[6] <= ram_block1a6.PORTADATAOUT q_a[7] <= ram_block1a7.PORTADATAOUT q_a[8] <= ram_block1a8.PORTADATAOUT q_a[9] <= ram_block1a9.PORTADATAOUT q_a[10] <= ram_block1a10.PORTADATAOUT q_a[11] <= ram_block1a11.PORTADATAOUT q_a[12] <= ram_block1a12.PORTADATAOUT q_a[13] <= ram_block1a13.PORTADATAOUT q_a[14] <= ram_block1a14.PORTADATAOUT q_b[0] <= ram_block1a0.PORTBDATAOUT q_b[1] <= ram_block1a1.PORTBDATAOUT q_b[2] <= ram_block1a2.PORTBDATAOUT q_b[3] <= ram_block1a3.PORTBDATAOUT q_b[4] <= ram_block1a4.PORTBDATAOUT q_b[5] <= ram_block1a5.PORTBDATAOUT q_b[6] <= ram_block1a6.PORTBDATAOUT q_b[7] <= ram_block1a7.PORTBDATAOUT q_b[8] <= ram_block1a8.PORTBDATAOUT q_b[9] <= ram_block1a9.PORTBDATAOUT q_b[10] <= ram_block1a10.PORTBDATAOUT q_b[11] <= ram_block1a11.PORTBDATAOUT q_b[12] <= ram_block1a12.PORTBDATAOUT q_b[13] <= ram_block1a13.PORTBDATAOUT q_b[14] <= ram_block1a14.PORTBDATAOUT wren_b => ram_block1a0.PORTBRE wren_b => ram_block1a1.PORTBRE wren_b => ram_block1a2.PORTBRE wren_b => ram_block1a3.PORTBRE wren_b => ram_block1a4.PORTBRE wren_b => ram_block1a5.PORTBRE wren_b => ram_block1a6.PORTBRE wren_b => ram_block1a7.PORTBRE wren_b => ram_block1a8.PORTBRE wren_b => ram_block1a9.PORTBRE wren_b => ram_block1a10.PORTBRE wren_b => ram_block1a11.PORTBRE wren_b => ram_block1a12.PORTBRE wren_b => ram_block1a13.PORTBRE wren_b => ram_block1a14.PORTBRE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data address_a[0] => address_a[0]~8.IN1 address_a[1] => address_a[1]~7.IN1 address_a[2] => address_a[2]~6.IN1 address_a[3] => address_a[3]~5.IN1 address_a[4] => address_a[4]~4.IN1 address_a[5] => address_a[5]~3.IN1 address_a[6] => address_a[6]~2.IN1 address_a[7] => address_a[7]~1.IN1 address_a[8] => address_a[8]~0.IN1 address_b[0] => address_b[0]~8.IN1 address_b[1] => address_b[1]~7.IN1 address_b[2] => address_b[2]~6.IN1 address_b[3] => address_b[3]~5.IN1 address_b[4] => address_b[4]~4.IN1 address_b[5] => address_b[5]~3.IN1 address_b[6] => address_b[6]~2.IN1 address_b[7] => address_b[7]~1.IN1 address_b[8] => address_b[8]~0.IN1 byteena_b[0] => byteena_b[0]~3.IN1 byteena_b[1] => byteena_b[1]~2.IN1 byteena_b[2] => byteena_b[2]~1.IN1 byteena_b[3] => byteena_b[3]~0.IN1 clock0 => clock0~0.IN1 clock1 => clock1~0.IN1 clocken0 => clocken0~0.IN1 clocken1 => clocken1~0.IN1 data_b[0] => data_b[0]~31.IN1 data_b[1] => data_b[1]~30.IN1 data_b[2] => data_b[2]~29.IN1 data_b[3] => data_b[3]~28.IN1 data_b[4] => data_b[4]~27.IN1 data_b[5] => data_b[5]~26.IN1 data_b[6] => data_b[6]~25.IN1 data_b[7] => data_b[7]~24.IN1 data_b[8] => data_b[8]~23.IN1 data_b[9] => data_b[9]~22.IN1 data_b[10] => data_b[10]~21.IN1 data_b[11] => data_b[11]~20.IN1 data_b[12] => data_b[12]~19.IN1 data_b[13] => data_b[13]~18.IN1 data_b[14] => data_b[14]~17.IN1 data_b[15] => data_b[15]~16.IN1 data_b[16] => data_b[16]~15.IN1 data_b[17] => data_b[17]~14.IN1 data_b[18] => data_b[18]~13.IN1 data_b[19] => data_b[19]~12.IN1 data_b[20] => data_b[20]~11.IN1 data_b[21] => data_b[21]~10.IN1 data_b[22] => data_b[22]~9.IN1 data_b[23] => data_b[23]~8.IN1 data_b[24] => data_b[24]~7.IN1 data_b[25] => data_b[25]~6.IN1 data_b[26] => data_b[26]~5.IN1 data_b[27] => data_b[27]~4.IN1 data_b[28] => data_b[28]~3.IN1 data_b[29] => data_b[29]~2.IN1 data_b[30] => data_b[30]~1.IN1 data_b[31] => data_b[31]~0.IN1 wren_b => wren_b~0.IN1 q_a[0] <= altsyncram:the_altsyncram.q_a q_a[1] <= altsyncram:the_altsyncram.q_a q_a[2] <= altsyncram:the_altsyncram.q_a q_a[3] <= altsyncram:the_altsyncram.q_a q_a[4] <= altsyncram:the_altsyncram.q_a q_a[5] <= altsyncram:the_altsyncram.q_a q_a[6] <= altsyncram:the_altsyncram.q_a q_a[7] <= altsyncram:the_altsyncram.q_a q_a[8] <= altsyncram:the_altsyncram.q_a q_a[9] <= altsyncram:the_altsyncram.q_a q_a[10] <= altsyncram:the_altsyncram.q_a q_a[11] <= altsyncram:the_altsyncram.q_a q_a[12] <= altsyncram:the_altsyncram.q_a q_a[13] <= altsyncram:the_altsyncram.q_a q_a[14] <= altsyncram:the_altsyncram.q_a q_a[15] <= altsyncram:the_altsyncram.q_a q_a[16] <= altsyncram:the_altsyncram.q_a q_a[17] <= altsyncram:the_altsyncram.q_a q_a[18] <= altsyncram:the_altsyncram.q_a q_a[19] <= altsyncram:the_altsyncram.q_a q_a[20] <= altsyncram:the_altsyncram.q_a q_a[21] <= altsyncram:the_altsyncram.q_a q_a[22] <= altsyncram:the_altsyncram.q_a q_a[23] <= altsyncram:the_altsyncram.q_a q_a[24] <= altsyncram:the_altsyncram.q_a q_a[25] <= altsyncram:the_altsyncram.q_a q_a[26] <= altsyncram:the_altsyncram.q_a q_a[27] <= altsyncram:the_altsyncram.q_a q_a[28] <= altsyncram:the_altsyncram.q_a q_a[29] <= altsyncram:the_altsyncram.q_a q_a[30] <= altsyncram:the_altsyncram.q_a q_a[31] <= altsyncram:the_altsyncram.q_a q_b[0] <= altsyncram:the_altsyncram.q_b q_b[1] <= altsyncram:the_altsyncram.q_b q_b[2] <= altsyncram:the_altsyncram.q_b q_b[3] <= altsyncram:the_altsyncram.q_b q_b[4] <= altsyncram:the_altsyncram.q_b q_b[5] <= altsyncram:the_altsyncram.q_b q_b[6] <= altsyncram:the_altsyncram.q_b q_b[7] <= altsyncram:the_altsyncram.q_b q_b[8] <= altsyncram:the_altsyncram.q_b q_b[9] <= altsyncram:the_altsyncram.q_b q_b[10] <= altsyncram:the_altsyncram.q_b q_b[11] <= altsyncram:the_altsyncram.q_b q_b[12] <= altsyncram:the_altsyncram.q_b q_b[13] <= altsyncram:the_altsyncram.q_b q_b[14] <= altsyncram:the_altsyncram.q_b q_b[15] <= altsyncram:the_altsyncram.q_b q_b[16] <= altsyncram:the_altsyncram.q_b q_b[17] <= altsyncram:the_altsyncram.q_b q_b[18] <= altsyncram:the_altsyncram.q_b q_b[19] <= altsyncram:the_altsyncram.q_b q_b[20] <= altsyncram:the_altsyncram.q_b q_b[21] <= altsyncram:the_altsyncram.q_b q_b[22] <= altsyncram:the_altsyncram.q_b q_b[23] <= altsyncram:the_altsyncram.q_b q_b[24] <= altsyncram:the_altsyncram.q_b q_b[25] <= altsyncram:the_altsyncram.q_b q_b[26] <= altsyncram:the_altsyncram.q_b q_b[27] <= altsyncram:the_altsyncram.q_b q_b[28] <= altsyncram:the_altsyncram.q_b q_b[29] <= altsyncram:the_altsyncram.q_b q_b[30] <= altsyncram:the_altsyncram.q_b q_b[31] <= altsyncram:the_altsyncram.q_b |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram wren_a => ~NO_FANOUT~ rden_a => ~NO_FANOUT~ wren_b => altsyncram_a422:auto_generated.wren_b rden_b => ~NO_FANOUT~ data_a[0] => altsyncram_a422:auto_generated.data_a[0] data_a[1] => altsyncram_a422:auto_generated.data_a[1] data_a[2] => altsyncram_a422:auto_generated.data_a[2] data_a[3] => altsyncram_a422:auto_generated.data_a[3] data_a[4] => altsyncram_a422:auto_generated.data_a[4] data_a[5] => altsyncram_a422:auto_generated.data_a[5] data_a[6] => altsyncram_a422:auto_generated.data_a[6] data_a[7] => altsyncram_a422:auto_generated.data_a[7] data_a[8] => altsyncram_a422:auto_generated.data_a[8] data_a[9] => altsyncram_a422:auto_generated.data_a[9] data_a[10] => altsyncram_a422:auto_generated.data_a[10] data_a[11] => altsyncram_a422:auto_generated.data_a[11] data_a[12] => altsyncram_a422:auto_generated.data_a[12] data_a[13] => altsyncram_a422:auto_generated.data_a[13] data_a[14] => altsyncram_a422:auto_generated.data_a[14] data_a[15] => altsyncram_a422:auto_generated.data_a[15] data_a[16] => altsyncram_a422:auto_generated.data_a[16] data_a[17] => altsyncram_a422:auto_generated.data_a[17] data_a[18] => altsyncram_a422:auto_generated.data_a[18] data_a[19] => altsyncram_a422:auto_generated.data_a[19] data_a[20] => altsyncram_a422:auto_generated.data_a[20] data_a[21] => altsyncram_a422:auto_generated.data_a[21] data_a[22] => altsyncram_a422:auto_generated.data_a[22] data_a[23] => altsyncram_a422:auto_generated.data_a[23] data_a[24] => altsyncram_a422:auto_generated.data_a[24] data_a[25] => altsyncram_a422:auto_generated.data_a[25] data_a[26] => altsyncram_a422:auto_generated.data_a[26] data_a[27] => altsyncram_a422:auto_generated.data_a[27] data_a[28] => altsyncram_a422:auto_generated.data_a[28] data_a[29] => altsyncram_a422:auto_generated.data_a[29] data_a[30] => altsyncram_a422:auto_generated.data_a[30] data_a[31] => altsyncram_a422:auto_generated.data_a[31] data_b[0] => altsyncram_a422:auto_generated.data_b[0] data_b[1] => altsyncram_a422:auto_generated.data_b[1] data_b[2] => altsyncram_a422:auto_generated.data_b[2] data_b[3] => altsyncram_a422:auto_generated.data_b[3] data_b[4] => altsyncram_a422:auto_generated.data_b[4] data_b[5] => altsyncram_a422:auto_generated.data_b[5] data_b[6] => altsyncram_a422:auto_generated.data_b[6] data_b[7] => altsyncram_a422:auto_generated.data_b[7] data_b[8] => altsyncram_a422:auto_generated.data_b[8] data_b[9] => altsyncram_a422:auto_generated.data_b[9] data_b[10] => altsyncram_a422:auto_generated.data_b[10] data_b[11] => altsyncram_a422:auto_generated.data_b[11] data_b[12] => altsyncram_a422:auto_generated.data_b[12] data_b[13] => altsyncram_a422:auto_generated.data_b[13] data_b[14] => altsyncram_a422:auto_generated.data_b[14] data_b[15] => altsyncram_a422:auto_generated.data_b[15] data_b[16] => altsyncram_a422:auto_generated.data_b[16] data_b[17] => altsyncram_a422:auto_generated.data_b[17] data_b[18] => altsyncram_a422:auto_generated.data_b[18] data_b[19] => altsyncram_a422:auto_generated.data_b[19] data_b[20] => altsyncram_a422:auto_generated.data_b[20] data_b[21] => altsyncram_a422:auto_generated.data_b[21] data_b[22] => altsyncram_a422:auto_generated.data_b[22] data_b[23] => altsyncram_a422:auto_generated.data_b[23] data_b[24] => altsyncram_a422:auto_generated.data_b[24] data_b[25] => altsyncram_a422:auto_generated.data_b[25] data_b[26] => altsyncram_a422:auto_generated.data_b[26] data_b[27] => altsyncram_a422:auto_generated.data_b[27] data_b[28] => altsyncram_a422:auto_generated.data_b[28] data_b[29] => altsyncram_a422:auto_generated.data_b[29] data_b[30] => altsyncram_a422:auto_generated.data_b[30] data_b[31] => altsyncram_a422:auto_generated.data_b[31] address_a[0] => altsyncram_a422:auto_generated.address_a[0] address_a[1] => altsyncram_a422:auto_generated.address_a[1] address_a[2] => altsyncram_a422:auto_generated.address_a[2] address_a[3] => altsyncram_a422:auto_generated.address_a[3] address_a[4] => altsyncram_a422:auto_generated.address_a[4] address_a[5] => altsyncram_a422:auto_generated.address_a[5] address_a[6] => altsyncram_a422:auto_generated.address_a[6] address_a[7] => altsyncram_a422:auto_generated.address_a[7] address_a[8] => altsyncram_a422:auto_generated.address_a[8] address_b[0] => altsyncram_a422:auto_generated.address_b[0] address_b[1] => altsyncram_a422:auto_generated.address_b[1] address_b[2] => altsyncram_a422:auto_generated.address_b[2] address_b[3] => altsyncram_a422:auto_generated.address_b[3] address_b[4] => altsyncram_a422:auto_generated.address_b[4] address_b[5] => altsyncram_a422:auto_generated.address_b[5] address_b[6] => altsyncram_a422:auto_generated.address_b[6] address_b[7] => altsyncram_a422:auto_generated.address_b[7] address_b[8] => altsyncram_a422:auto_generated.address_b[8] addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_a422:auto_generated.clock0 clock1 => altsyncram_a422:auto_generated.clock1 clocken0 => altsyncram_a422:auto_generated.clocken0 clocken1 => altsyncram_a422:auto_generated.clocken1 clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => altsyncram_a422:auto_generated.byteena_b[0] byteena_b[1] => altsyncram_a422:auto_generated.byteena_b[1] byteena_b[2] => altsyncram_a422:auto_generated.byteena_b[2] byteena_b[3] => altsyncram_a422:auto_generated.byteena_b[3] q_a[0] <= altsyncram_a422:auto_generated.q_a[0] q_a[1] <= altsyncram_a422:auto_generated.q_a[1] q_a[2] <= altsyncram_a422:auto_generated.q_a[2] q_a[3] <= altsyncram_a422:auto_generated.q_a[3] q_a[4] <= altsyncram_a422:auto_generated.q_a[4] q_a[5] <= altsyncram_a422:auto_generated.q_a[5] q_a[6] <= altsyncram_a422:auto_generated.q_a[6] q_a[7] <= altsyncram_a422:auto_generated.q_a[7] q_a[8] <= altsyncram_a422:auto_generated.q_a[8] q_a[9] <= altsyncram_a422:auto_generated.q_a[9] q_a[10] <= altsyncram_a422:auto_generated.q_a[10] q_a[11] <= altsyncram_a422:auto_generated.q_a[11] q_a[12] <= altsyncram_a422:auto_generated.q_a[12] q_a[13] <= altsyncram_a422:auto_generated.q_a[13] q_a[14] <= altsyncram_a422:auto_generated.q_a[14] q_a[15] <= altsyncram_a422:auto_generated.q_a[15] q_a[16] <= altsyncram_a422:auto_generated.q_a[16] q_a[17] <= altsyncram_a422:auto_generated.q_a[17] q_a[18] <= altsyncram_a422:auto_generated.q_a[18] q_a[19] <= altsyncram_a422:auto_generated.q_a[19] q_a[20] <= altsyncram_a422:auto_generated.q_a[20] q_a[21] <= altsyncram_a422:auto_generated.q_a[21] q_a[22] <= altsyncram_a422:auto_generated.q_a[22] q_a[23] <= altsyncram_a422:auto_generated.q_a[23] q_a[24] <= altsyncram_a422:auto_generated.q_a[24] q_a[25] <= altsyncram_a422:auto_generated.q_a[25] q_a[26] <= altsyncram_a422:auto_generated.q_a[26] q_a[27] <= altsyncram_a422:auto_generated.q_a[27] q_a[28] <= altsyncram_a422:auto_generated.q_a[28] q_a[29] <= altsyncram_a422:auto_generated.q_a[29] q_a[30] <= altsyncram_a422:auto_generated.q_a[30] q_a[31] <= altsyncram_a422:auto_generated.q_a[31] q_b[0] <= altsyncram_a422:auto_generated.q_b[0] q_b[1] <= altsyncram_a422:auto_generated.q_b[1] q_b[2] <= altsyncram_a422:auto_generated.q_b[2] q_b[3] <= altsyncram_a422:auto_generated.q_b[3] q_b[4] <= altsyncram_a422:auto_generated.q_b[4] q_b[5] <= altsyncram_a422:auto_generated.q_b[5] q_b[6] <= altsyncram_a422:auto_generated.q_b[6] q_b[7] <= altsyncram_a422:auto_generated.q_b[7] q_b[8] <= altsyncram_a422:auto_generated.q_b[8] q_b[9] <= altsyncram_a422:auto_generated.q_b[9] q_b[10] <= altsyncram_a422:auto_generated.q_b[10] q_b[11] <= altsyncram_a422:auto_generated.q_b[11] q_b[12] <= altsyncram_a422:auto_generated.q_b[12] q_b[13] <= altsyncram_a422:auto_generated.q_b[13] q_b[14] <= altsyncram_a422:auto_generated.q_b[14] q_b[15] <= altsyncram_a422:auto_generated.q_b[15] q_b[16] <= altsyncram_a422:auto_generated.q_b[16] q_b[17] <= altsyncram_a422:auto_generated.q_b[17] q_b[18] <= altsyncram_a422:auto_generated.q_b[18] q_b[19] <= altsyncram_a422:auto_generated.q_b[19] q_b[20] <= altsyncram_a422:auto_generated.q_b[20] q_b[21] <= altsyncram_a422:auto_generated.q_b[21] q_b[22] <= altsyncram_a422:auto_generated.q_b[22] q_b[23] <= altsyncram_a422:auto_generated.q_b[23] q_b[24] <= altsyncram_a422:auto_generated.q_b[24] q_b[25] <= altsyncram_a422:auto_generated.q_b[25] q_b[26] <= altsyncram_a422:auto_generated.q_b[26] q_b[27] <= altsyncram_a422:auto_generated.q_b[27] q_b[28] <= altsyncram_a422:auto_generated.q_b[28] q_b[29] <= altsyncram_a422:auto_generated.q_b[29] q_b[30] <= altsyncram_a422:auto_generated.q_b[30] q_b[31] <= altsyncram_a422:auto_generated.q_b[31] eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[0] => ram_block1a8.PORTAADDR address_a[0] => ram_block1a9.PORTAADDR address_a[0] => ram_block1a10.PORTAADDR address_a[0] => ram_block1a11.PORTAADDR address_a[0] => ram_block1a12.PORTAADDR address_a[0] => ram_block1a13.PORTAADDR address_a[0] => ram_block1a14.PORTAADDR address_a[0] => ram_block1a15.PORTAADDR address_a[0] => ram_block1a16.PORTAADDR address_a[0] => ram_block1a17.PORTAADDR address_a[0] => ram_block1a18.PORTAADDR address_a[0] => ram_block1a19.PORTAADDR address_a[0] => ram_block1a20.PORTAADDR address_a[0] => ram_block1a21.PORTAADDR address_a[0] => ram_block1a22.PORTAADDR address_a[0] => ram_block1a23.PORTAADDR address_a[0] => ram_block1a24.PORTAADDR address_a[0] => ram_block1a25.PORTAADDR address_a[0] => ram_block1a26.PORTAADDR address_a[0] => ram_block1a27.PORTAADDR address_a[0] => ram_block1a28.PORTAADDR address_a[0] => ram_block1a29.PORTAADDR address_a[0] => ram_block1a30.PORTAADDR address_a[0] => ram_block1a31.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[1] => ram_block1a8.PORTAADDR1 address_a[1] => ram_block1a9.PORTAADDR1 address_a[1] => ram_block1a10.PORTAADDR1 address_a[1] => ram_block1a11.PORTAADDR1 address_a[1] => ram_block1a12.PORTAADDR1 address_a[1] => ram_block1a13.PORTAADDR1 address_a[1] => ram_block1a14.PORTAADDR1 address_a[1] => ram_block1a15.PORTAADDR1 address_a[1] => ram_block1a16.PORTAADDR1 address_a[1] => ram_block1a17.PORTAADDR1 address_a[1] => ram_block1a18.PORTAADDR1 address_a[1] => ram_block1a19.PORTAADDR1 address_a[1] => ram_block1a20.PORTAADDR1 address_a[1] => ram_block1a21.PORTAADDR1 address_a[1] => ram_block1a22.PORTAADDR1 address_a[1] => ram_block1a23.PORTAADDR1 address_a[1] => ram_block1a24.PORTAADDR1 address_a[1] => ram_block1a25.PORTAADDR1 address_a[1] => ram_block1a26.PORTAADDR1 address_a[1] => ram_block1a27.PORTAADDR1 address_a[1] => ram_block1a28.PORTAADDR1 address_a[1] => ram_block1a29.PORTAADDR1 address_a[1] => ram_block1a30.PORTAADDR1 address_a[1] => ram_block1a31.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[2] => ram_block1a8.PORTAADDR2 address_a[2] => ram_block1a9.PORTAADDR2 address_a[2] => ram_block1a10.PORTAADDR2 address_a[2] => ram_block1a11.PORTAADDR2 address_a[2] => ram_block1a12.PORTAADDR2 address_a[2] => ram_block1a13.PORTAADDR2 address_a[2] => ram_block1a14.PORTAADDR2 address_a[2] => ram_block1a15.PORTAADDR2 address_a[2] => ram_block1a16.PORTAADDR2 address_a[2] => ram_block1a17.PORTAADDR2 address_a[2] => ram_block1a18.PORTAADDR2 address_a[2] => ram_block1a19.PORTAADDR2 address_a[2] => ram_block1a20.PORTAADDR2 address_a[2] => ram_block1a21.PORTAADDR2 address_a[2] => ram_block1a22.PORTAADDR2 address_a[2] => ram_block1a23.PORTAADDR2 address_a[2] => ram_block1a24.PORTAADDR2 address_a[2] => ram_block1a25.PORTAADDR2 address_a[2] => ram_block1a26.PORTAADDR2 address_a[2] => ram_block1a27.PORTAADDR2 address_a[2] => ram_block1a28.PORTAADDR2 address_a[2] => ram_block1a29.PORTAADDR2 address_a[2] => ram_block1a30.PORTAADDR2 address_a[2] => ram_block1a31.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[3] => ram_block1a8.PORTAADDR3 address_a[3] => ram_block1a9.PORTAADDR3 address_a[3] => ram_block1a10.PORTAADDR3 address_a[3] => ram_block1a11.PORTAADDR3 address_a[3] => ram_block1a12.PORTAADDR3 address_a[3] => ram_block1a13.PORTAADDR3 address_a[3] => ram_block1a14.PORTAADDR3 address_a[3] => ram_block1a15.PORTAADDR3 address_a[3] => ram_block1a16.PORTAADDR3 address_a[3] => ram_block1a17.PORTAADDR3 address_a[3] => ram_block1a18.PORTAADDR3 address_a[3] => ram_block1a19.PORTAADDR3 address_a[3] => ram_block1a20.PORTAADDR3 address_a[3] => ram_block1a21.PORTAADDR3 address_a[3] => ram_block1a22.PORTAADDR3 address_a[3] => ram_block1a23.PORTAADDR3 address_a[3] => ram_block1a24.PORTAADDR3 address_a[3] => ram_block1a25.PORTAADDR3 address_a[3] => ram_block1a26.PORTAADDR3 address_a[3] => ram_block1a27.PORTAADDR3 address_a[3] => ram_block1a28.PORTAADDR3 address_a[3] => ram_block1a29.PORTAADDR3 address_a[3] => ram_block1a30.PORTAADDR3 address_a[3] => ram_block1a31.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[4] => ram_block1a8.PORTAADDR4 address_a[4] => ram_block1a9.PORTAADDR4 address_a[4] => ram_block1a10.PORTAADDR4 address_a[4] => ram_block1a11.PORTAADDR4 address_a[4] => ram_block1a12.PORTAADDR4 address_a[4] => ram_block1a13.PORTAADDR4 address_a[4] => ram_block1a14.PORTAADDR4 address_a[4] => ram_block1a15.PORTAADDR4 address_a[4] => ram_block1a16.PORTAADDR4 address_a[4] => ram_block1a17.PORTAADDR4 address_a[4] => ram_block1a18.PORTAADDR4 address_a[4] => ram_block1a19.PORTAADDR4 address_a[4] => ram_block1a20.PORTAADDR4 address_a[4] => ram_block1a21.PORTAADDR4 address_a[4] => ram_block1a22.PORTAADDR4 address_a[4] => ram_block1a23.PORTAADDR4 address_a[4] => ram_block1a24.PORTAADDR4 address_a[4] => ram_block1a25.PORTAADDR4 address_a[4] => ram_block1a26.PORTAADDR4 address_a[4] => ram_block1a27.PORTAADDR4 address_a[4] => ram_block1a28.PORTAADDR4 address_a[4] => ram_block1a29.PORTAADDR4 address_a[4] => ram_block1a30.PORTAADDR4 address_a[4] => ram_block1a31.PORTAADDR4 address_a[5] => ram_block1a0.PORTAADDR5 address_a[5] => ram_block1a1.PORTAADDR5 address_a[5] => ram_block1a2.PORTAADDR5 address_a[5] => ram_block1a3.PORTAADDR5 address_a[5] => ram_block1a4.PORTAADDR5 address_a[5] => ram_block1a5.PORTAADDR5 address_a[5] => ram_block1a6.PORTAADDR5 address_a[5] => ram_block1a7.PORTAADDR5 address_a[5] => ram_block1a8.PORTAADDR5 address_a[5] => ram_block1a9.PORTAADDR5 address_a[5] => ram_block1a10.PORTAADDR5 address_a[5] => ram_block1a11.PORTAADDR5 address_a[5] => ram_block1a12.PORTAADDR5 address_a[5] => ram_block1a13.PORTAADDR5 address_a[5] => ram_block1a14.PORTAADDR5 address_a[5] => ram_block1a15.PORTAADDR5 address_a[5] => ram_block1a16.PORTAADDR5 address_a[5] => ram_block1a17.PORTAADDR5 address_a[5] => ram_block1a18.PORTAADDR5 address_a[5] => ram_block1a19.PORTAADDR5 address_a[5] => ram_block1a20.PORTAADDR5 address_a[5] => ram_block1a21.PORTAADDR5 address_a[5] => ram_block1a22.PORTAADDR5 address_a[5] => ram_block1a23.PORTAADDR5 address_a[5] => ram_block1a24.PORTAADDR5 address_a[5] => ram_block1a25.PORTAADDR5 address_a[5] => ram_block1a26.PORTAADDR5 address_a[5] => ram_block1a27.PORTAADDR5 address_a[5] => ram_block1a28.PORTAADDR5 address_a[5] => ram_block1a29.PORTAADDR5 address_a[5] => ram_block1a30.PORTAADDR5 address_a[5] => ram_block1a31.PORTAADDR5 address_a[6] => ram_block1a0.PORTAADDR6 address_a[6] => ram_block1a1.PORTAADDR6 address_a[6] => ram_block1a2.PORTAADDR6 address_a[6] => ram_block1a3.PORTAADDR6 address_a[6] => ram_block1a4.PORTAADDR6 address_a[6] => ram_block1a5.PORTAADDR6 address_a[6] => ram_block1a6.PORTAADDR6 address_a[6] => ram_block1a7.PORTAADDR6 address_a[6] => ram_block1a8.PORTAADDR6 address_a[6] => ram_block1a9.PORTAADDR6 address_a[6] => ram_block1a10.PORTAADDR6 address_a[6] => ram_block1a11.PORTAADDR6 address_a[6] => ram_block1a12.PORTAADDR6 address_a[6] => ram_block1a13.PORTAADDR6 address_a[6] => ram_block1a14.PORTAADDR6 address_a[6] => ram_block1a15.PORTAADDR6 address_a[6] => ram_block1a16.PORTAADDR6 address_a[6] => ram_block1a17.PORTAADDR6 address_a[6] => ram_block1a18.PORTAADDR6 address_a[6] => ram_block1a19.PORTAADDR6 address_a[6] => ram_block1a20.PORTAADDR6 address_a[6] => ram_block1a21.PORTAADDR6 address_a[6] => ram_block1a22.PORTAADDR6 address_a[6] => ram_block1a23.PORTAADDR6 address_a[6] => ram_block1a24.PORTAADDR6 address_a[6] => ram_block1a25.PORTAADDR6 address_a[6] => ram_block1a26.PORTAADDR6 address_a[6] => ram_block1a27.PORTAADDR6 address_a[6] => ram_block1a28.PORTAADDR6 address_a[6] => ram_block1a29.PORTAADDR6 address_a[6] => ram_block1a30.PORTAADDR6 address_a[6] => ram_block1a31.PORTAADDR6 address_a[7] => ram_block1a0.PORTAADDR7 address_a[7] => ram_block1a1.PORTAADDR7 address_a[7] => ram_block1a2.PORTAADDR7 address_a[7] => ram_block1a3.PORTAADDR7 address_a[7] => ram_block1a4.PORTAADDR7 address_a[7] => ram_block1a5.PORTAADDR7 address_a[7] => ram_block1a6.PORTAADDR7 address_a[7] => ram_block1a7.PORTAADDR7 address_a[7] => ram_block1a8.PORTAADDR7 address_a[7] => ram_block1a9.PORTAADDR7 address_a[7] => ram_block1a10.PORTAADDR7 address_a[7] => ram_block1a11.PORTAADDR7 address_a[7] => ram_block1a12.PORTAADDR7 address_a[7] => ram_block1a13.PORTAADDR7 address_a[7] => ram_block1a14.PORTAADDR7 address_a[7] => ram_block1a15.PORTAADDR7 address_a[7] => ram_block1a16.PORTAADDR7 address_a[7] => ram_block1a17.PORTAADDR7 address_a[7] => ram_block1a18.PORTAADDR7 address_a[7] => ram_block1a19.PORTAADDR7 address_a[7] => ram_block1a20.PORTAADDR7 address_a[7] => ram_block1a21.PORTAADDR7 address_a[7] => ram_block1a22.PORTAADDR7 address_a[7] => ram_block1a23.PORTAADDR7 address_a[7] => ram_block1a24.PORTAADDR7 address_a[7] => ram_block1a25.PORTAADDR7 address_a[7] => ram_block1a26.PORTAADDR7 address_a[7] => ram_block1a27.PORTAADDR7 address_a[7] => ram_block1a28.PORTAADDR7 address_a[7] => ram_block1a29.PORTAADDR7 address_a[7] => ram_block1a30.PORTAADDR7 address_a[7] => ram_block1a31.PORTAADDR7 address_a[8] => ram_block1a0.PORTAADDR8 address_a[8] => ram_block1a1.PORTAADDR8 address_a[8] => ram_block1a2.PORTAADDR8 address_a[8] => ram_block1a3.PORTAADDR8 address_a[8] => ram_block1a4.PORTAADDR8 address_a[8] => ram_block1a5.PORTAADDR8 address_a[8] => ram_block1a6.PORTAADDR8 address_a[8] => ram_block1a7.PORTAADDR8 address_a[8] => ram_block1a8.PORTAADDR8 address_a[8] => ram_block1a9.PORTAADDR8 address_a[8] => ram_block1a10.PORTAADDR8 address_a[8] => ram_block1a11.PORTAADDR8 address_a[8] => ram_block1a12.PORTAADDR8 address_a[8] => ram_block1a13.PORTAADDR8 address_a[8] => ram_block1a14.PORTAADDR8 address_a[8] => ram_block1a15.PORTAADDR8 address_a[8] => ram_block1a16.PORTAADDR8 address_a[8] => ram_block1a17.PORTAADDR8 address_a[8] => ram_block1a18.PORTAADDR8 address_a[8] => ram_block1a19.PORTAADDR8 address_a[8] => ram_block1a20.PORTAADDR8 address_a[8] => ram_block1a21.PORTAADDR8 address_a[8] => ram_block1a22.PORTAADDR8 address_a[8] => ram_block1a23.PORTAADDR8 address_a[8] => ram_block1a24.PORTAADDR8 address_a[8] => ram_block1a25.PORTAADDR8 address_a[8] => ram_block1a26.PORTAADDR8 address_a[8] => ram_block1a27.PORTAADDR8 address_a[8] => ram_block1a28.PORTAADDR8 address_a[8] => ram_block1a29.PORTAADDR8 address_a[8] => ram_block1a30.PORTAADDR8 address_a[8] => ram_block1a31.PORTAADDR8 address_b[0] => ram_block1a0.PORTBADDR address_b[0] => ram_block1a1.PORTBADDR address_b[0] => ram_block1a2.PORTBADDR address_b[0] => ram_block1a3.PORTBADDR address_b[0] => ram_block1a4.PORTBADDR address_b[0] => ram_block1a5.PORTBADDR address_b[0] => ram_block1a6.PORTBADDR address_b[0] => ram_block1a7.PORTBADDR address_b[0] => ram_block1a8.PORTBADDR address_b[0] => ram_block1a9.PORTBADDR address_b[0] => ram_block1a10.PORTBADDR address_b[0] => ram_block1a11.PORTBADDR address_b[0] => ram_block1a12.PORTBADDR address_b[0] => ram_block1a13.PORTBADDR address_b[0] => ram_block1a14.PORTBADDR address_b[0] => ram_block1a15.PORTBADDR address_b[0] => ram_block1a16.PORTBADDR address_b[0] => ram_block1a17.PORTBADDR address_b[0] => ram_block1a18.PORTBADDR address_b[0] => ram_block1a19.PORTBADDR address_b[0] => ram_block1a20.PORTBADDR address_b[0] => ram_block1a21.PORTBADDR address_b[0] => ram_block1a22.PORTBADDR address_b[0] => ram_block1a23.PORTBADDR address_b[0] => ram_block1a24.PORTBADDR address_b[0] => ram_block1a25.PORTBADDR address_b[0] => ram_block1a26.PORTBADDR address_b[0] => ram_block1a27.PORTBADDR address_b[0] => ram_block1a28.PORTBADDR address_b[0] => ram_block1a29.PORTBADDR address_b[0] => ram_block1a30.PORTBADDR address_b[0] => ram_block1a31.PORTBADDR address_b[1] => ram_block1a0.PORTBADDR1 address_b[1] => ram_block1a1.PORTBADDR1 address_b[1] => ram_block1a2.PORTBADDR1 address_b[1] => ram_block1a3.PORTBADDR1 address_b[1] => ram_block1a4.PORTBADDR1 address_b[1] => ram_block1a5.PORTBADDR1 address_b[1] => ram_block1a6.PORTBADDR1 address_b[1] => ram_block1a7.PORTBADDR1 address_b[1] => ram_block1a8.PORTBADDR1 address_b[1] => ram_block1a9.PORTBADDR1 address_b[1] => ram_block1a10.PORTBADDR1 address_b[1] => ram_block1a11.PORTBADDR1 address_b[1] => ram_block1a12.PORTBADDR1 address_b[1] => ram_block1a13.PORTBADDR1 address_b[1] => ram_block1a14.PORTBADDR1 address_b[1] => ram_block1a15.PORTBADDR1 address_b[1] => ram_block1a16.PORTBADDR1 address_b[1] => ram_block1a17.PORTBADDR1 address_b[1] => ram_block1a18.PORTBADDR1 address_b[1] => ram_block1a19.PORTBADDR1 address_b[1] => ram_block1a20.PORTBADDR1 address_b[1] => ram_block1a21.PORTBADDR1 address_b[1] => ram_block1a22.PORTBADDR1 address_b[1] => ram_block1a23.PORTBADDR1 address_b[1] => ram_block1a24.PORTBADDR1 address_b[1] => ram_block1a25.PORTBADDR1 address_b[1] => ram_block1a26.PORTBADDR1 address_b[1] => ram_block1a27.PORTBADDR1 address_b[1] => ram_block1a28.PORTBADDR1 address_b[1] => ram_block1a29.PORTBADDR1 address_b[1] => ram_block1a30.PORTBADDR1 address_b[1] => ram_block1a31.PORTBADDR1 address_b[2] => ram_block1a0.PORTBADDR2 address_b[2] => ram_block1a1.PORTBADDR2 address_b[2] => ram_block1a2.PORTBADDR2 address_b[2] => ram_block1a3.PORTBADDR2 address_b[2] => ram_block1a4.PORTBADDR2 address_b[2] => ram_block1a5.PORTBADDR2 address_b[2] => ram_block1a6.PORTBADDR2 address_b[2] => ram_block1a7.PORTBADDR2 address_b[2] => ram_block1a8.PORTBADDR2 address_b[2] => ram_block1a9.PORTBADDR2 address_b[2] => ram_block1a10.PORTBADDR2 address_b[2] => ram_block1a11.PORTBADDR2 address_b[2] => ram_block1a12.PORTBADDR2 address_b[2] => ram_block1a13.PORTBADDR2 address_b[2] => ram_block1a14.PORTBADDR2 address_b[2] => ram_block1a15.PORTBADDR2 address_b[2] => ram_block1a16.PORTBADDR2 address_b[2] => ram_block1a17.PORTBADDR2 address_b[2] => ram_block1a18.PORTBADDR2 address_b[2] => ram_block1a19.PORTBADDR2 address_b[2] => ram_block1a20.PORTBADDR2 address_b[2] => ram_block1a21.PORTBADDR2 address_b[2] => ram_block1a22.PORTBADDR2 address_b[2] => ram_block1a23.PORTBADDR2 address_b[2] => ram_block1a24.PORTBADDR2 address_b[2] => ram_block1a25.PORTBADDR2 address_b[2] => ram_block1a26.PORTBADDR2 address_b[2] => ram_block1a27.PORTBADDR2 address_b[2] => ram_block1a28.PORTBADDR2 address_b[2] => ram_block1a29.PORTBADDR2 address_b[2] => ram_block1a30.PORTBADDR2 address_b[2] => ram_block1a31.PORTBADDR2 address_b[3] => ram_block1a0.PORTBADDR3 address_b[3] => ram_block1a1.PORTBADDR3 address_b[3] => ram_block1a2.PORTBADDR3 address_b[3] => ram_block1a3.PORTBADDR3 address_b[3] => ram_block1a4.PORTBADDR3 address_b[3] => ram_block1a5.PORTBADDR3 address_b[3] => ram_block1a6.PORTBADDR3 address_b[3] => ram_block1a7.PORTBADDR3 address_b[3] => ram_block1a8.PORTBADDR3 address_b[3] => ram_block1a9.PORTBADDR3 address_b[3] => ram_block1a10.PORTBADDR3 address_b[3] => ram_block1a11.PORTBADDR3 address_b[3] => ram_block1a12.PORTBADDR3 address_b[3] => ram_block1a13.PORTBADDR3 address_b[3] => ram_block1a14.PORTBADDR3 address_b[3] => ram_block1a15.PORTBADDR3 address_b[3] => ram_block1a16.PORTBADDR3 address_b[3] => ram_block1a17.PORTBADDR3 address_b[3] => ram_block1a18.PORTBADDR3 address_b[3] => ram_block1a19.PORTBADDR3 address_b[3] => ram_block1a20.PORTBADDR3 address_b[3] => ram_block1a21.PORTBADDR3 address_b[3] => ram_block1a22.PORTBADDR3 address_b[3] => ram_block1a23.PORTBADDR3 address_b[3] => ram_block1a24.PORTBADDR3 address_b[3] => ram_block1a25.PORTBADDR3 address_b[3] => ram_block1a26.PORTBADDR3 address_b[3] => ram_block1a27.PORTBADDR3 address_b[3] => ram_block1a28.PORTBADDR3 address_b[3] => ram_block1a29.PORTBADDR3 address_b[3] => ram_block1a30.PORTBADDR3 address_b[3] => ram_block1a31.PORTBADDR3 address_b[4] => ram_block1a0.PORTBADDR4 address_b[4] => ram_block1a1.PORTBADDR4 address_b[4] => ram_block1a2.PORTBADDR4 address_b[4] => ram_block1a3.PORTBADDR4 address_b[4] => ram_block1a4.PORTBADDR4 address_b[4] => ram_block1a5.PORTBADDR4 address_b[4] => ram_block1a6.PORTBADDR4 address_b[4] => ram_block1a7.PORTBADDR4 address_b[4] => ram_block1a8.PORTBADDR4 address_b[4] => ram_block1a9.PORTBADDR4 address_b[4] => ram_block1a10.PORTBADDR4 address_b[4] => ram_block1a11.PORTBADDR4 address_b[4] => ram_block1a12.PORTBADDR4 address_b[4] => ram_block1a13.PORTBADDR4 address_b[4] => ram_block1a14.PORTBADDR4 address_b[4] => ram_block1a15.PORTBADDR4 address_b[4] => ram_block1a16.PORTBADDR4 address_b[4] => ram_block1a17.PORTBADDR4 address_b[4] => ram_block1a18.PORTBADDR4 address_b[4] => ram_block1a19.PORTBADDR4 address_b[4] => ram_block1a20.PORTBADDR4 address_b[4] => ram_block1a21.PORTBADDR4 address_b[4] => ram_block1a22.PORTBADDR4 address_b[4] => ram_block1a23.PORTBADDR4 address_b[4] => ram_block1a24.PORTBADDR4 address_b[4] => ram_block1a25.PORTBADDR4 address_b[4] => ram_block1a26.PORTBADDR4 address_b[4] => ram_block1a27.PORTBADDR4 address_b[4] => ram_block1a28.PORTBADDR4 address_b[4] => ram_block1a29.PORTBADDR4 address_b[4] => ram_block1a30.PORTBADDR4 address_b[4] => ram_block1a31.PORTBADDR4 address_b[5] => ram_block1a0.PORTBADDR5 address_b[5] => ram_block1a1.PORTBADDR5 address_b[5] => ram_block1a2.PORTBADDR5 address_b[5] => ram_block1a3.PORTBADDR5 address_b[5] => ram_block1a4.PORTBADDR5 address_b[5] => ram_block1a5.PORTBADDR5 address_b[5] => ram_block1a6.PORTBADDR5 address_b[5] => ram_block1a7.PORTBADDR5 address_b[5] => ram_block1a8.PORTBADDR5 address_b[5] => ram_block1a9.PORTBADDR5 address_b[5] => ram_block1a10.PORTBADDR5 address_b[5] => ram_block1a11.PORTBADDR5 address_b[5] => ram_block1a12.PORTBADDR5 address_b[5] => ram_block1a13.PORTBADDR5 address_b[5] => ram_block1a14.PORTBADDR5 address_b[5] => ram_block1a15.PORTBADDR5 address_b[5] => ram_block1a16.PORTBADDR5 address_b[5] => ram_block1a17.PORTBADDR5 address_b[5] => ram_block1a18.PORTBADDR5 address_b[5] => ram_block1a19.PORTBADDR5 address_b[5] => ram_block1a20.PORTBADDR5 address_b[5] => ram_block1a21.PORTBADDR5 address_b[5] => ram_block1a22.PORTBADDR5 address_b[5] => ram_block1a23.PORTBADDR5 address_b[5] => ram_block1a24.PORTBADDR5 address_b[5] => ram_block1a25.PORTBADDR5 address_b[5] => ram_block1a26.PORTBADDR5 address_b[5] => ram_block1a27.PORTBADDR5 address_b[5] => ram_block1a28.PORTBADDR5 address_b[5] => ram_block1a29.PORTBADDR5 address_b[5] => ram_block1a30.PORTBADDR5 address_b[5] => ram_block1a31.PORTBADDR5 address_b[6] => ram_block1a0.PORTBADDR6 address_b[6] => ram_block1a1.PORTBADDR6 address_b[6] => ram_block1a2.PORTBADDR6 address_b[6] => ram_block1a3.PORTBADDR6 address_b[6] => ram_block1a4.PORTBADDR6 address_b[6] => ram_block1a5.PORTBADDR6 address_b[6] => ram_block1a6.PORTBADDR6 address_b[6] => ram_block1a7.PORTBADDR6 address_b[6] => ram_block1a8.PORTBADDR6 address_b[6] => ram_block1a9.PORTBADDR6 address_b[6] => ram_block1a10.PORTBADDR6 address_b[6] => ram_block1a11.PORTBADDR6 address_b[6] => ram_block1a12.PORTBADDR6 address_b[6] => ram_block1a13.PORTBADDR6 address_b[6] => ram_block1a14.PORTBADDR6 address_b[6] => ram_block1a15.PORTBADDR6 address_b[6] => ram_block1a16.PORTBADDR6 address_b[6] => ram_block1a17.PORTBADDR6 address_b[6] => ram_block1a18.PORTBADDR6 address_b[6] => ram_block1a19.PORTBADDR6 address_b[6] => ram_block1a20.PORTBADDR6 address_b[6] => ram_block1a21.PORTBADDR6 address_b[6] => ram_block1a22.PORTBADDR6 address_b[6] => ram_block1a23.PORTBADDR6 address_b[6] => ram_block1a24.PORTBADDR6 address_b[6] => ram_block1a25.PORTBADDR6 address_b[6] => ram_block1a26.PORTBADDR6 address_b[6] => ram_block1a27.PORTBADDR6 address_b[6] => ram_block1a28.PORTBADDR6 address_b[6] => ram_block1a29.PORTBADDR6 address_b[6] => ram_block1a30.PORTBADDR6 address_b[6] => ram_block1a31.PORTBADDR6 address_b[7] => ram_block1a0.PORTBADDR7 address_b[7] => ram_block1a1.PORTBADDR7 address_b[7] => ram_block1a2.PORTBADDR7 address_b[7] => ram_block1a3.PORTBADDR7 address_b[7] => ram_block1a4.PORTBADDR7 address_b[7] => ram_block1a5.PORTBADDR7 address_b[7] => ram_block1a6.PORTBADDR7 address_b[7] => ram_block1a7.PORTBADDR7 address_b[7] => ram_block1a8.PORTBADDR7 address_b[7] => ram_block1a9.PORTBADDR7 address_b[7] => ram_block1a10.PORTBADDR7 address_b[7] => ram_block1a11.PORTBADDR7 address_b[7] => ram_block1a12.PORTBADDR7 address_b[7] => ram_block1a13.PORTBADDR7 address_b[7] => ram_block1a14.PORTBADDR7 address_b[7] => ram_block1a15.PORTBADDR7 address_b[7] => ram_block1a16.PORTBADDR7 address_b[7] => ram_block1a17.PORTBADDR7 address_b[7] => ram_block1a18.PORTBADDR7 address_b[7] => ram_block1a19.PORTBADDR7 address_b[7] => ram_block1a20.PORTBADDR7 address_b[7] => ram_block1a21.PORTBADDR7 address_b[7] => ram_block1a22.PORTBADDR7 address_b[7] => ram_block1a23.PORTBADDR7 address_b[7] => ram_block1a24.PORTBADDR7 address_b[7] => ram_block1a25.PORTBADDR7 address_b[7] => ram_block1a26.PORTBADDR7 address_b[7] => ram_block1a27.PORTBADDR7 address_b[7] => ram_block1a28.PORTBADDR7 address_b[7] => ram_block1a29.PORTBADDR7 address_b[7] => ram_block1a30.PORTBADDR7 address_b[7] => ram_block1a31.PORTBADDR7 address_b[8] => ram_block1a0.PORTBADDR8 address_b[8] => ram_block1a1.PORTBADDR8 address_b[8] => ram_block1a2.PORTBADDR8 address_b[8] => ram_block1a3.PORTBADDR8 address_b[8] => ram_block1a4.PORTBADDR8 address_b[8] => ram_block1a5.PORTBADDR8 address_b[8] => ram_block1a6.PORTBADDR8 address_b[8] => ram_block1a7.PORTBADDR8 address_b[8] => ram_block1a8.PORTBADDR8 address_b[8] => ram_block1a9.PORTBADDR8 address_b[8] => ram_block1a10.PORTBADDR8 address_b[8] => ram_block1a11.PORTBADDR8 address_b[8] => ram_block1a12.PORTBADDR8 address_b[8] => ram_block1a13.PORTBADDR8 address_b[8] => ram_block1a14.PORTBADDR8 address_b[8] => ram_block1a15.PORTBADDR8 address_b[8] => ram_block1a16.PORTBADDR8 address_b[8] => ram_block1a17.PORTBADDR8 address_b[8] => ram_block1a18.PORTBADDR8 address_b[8] => ram_block1a19.PORTBADDR8 address_b[8] => ram_block1a20.PORTBADDR8 address_b[8] => ram_block1a21.PORTBADDR8 address_b[8] => ram_block1a22.PORTBADDR8 address_b[8] => ram_block1a23.PORTBADDR8 address_b[8] => ram_block1a24.PORTBADDR8 address_b[8] => ram_block1a25.PORTBADDR8 address_b[8] => ram_block1a26.PORTBADDR8 address_b[8] => ram_block1a27.PORTBADDR8 address_b[8] => ram_block1a28.PORTBADDR8 address_b[8] => ram_block1a29.PORTBADDR8 address_b[8] => ram_block1a30.PORTBADDR8 address_b[8] => ram_block1a31.PORTBADDR8 byteena_b[0] => ram_block1a0.PORTBBYTEENAMASKS byteena_b[0] => ram_block1a1.PORTBBYTEENAMASKS byteena_b[0] => ram_block1a2.PORTBBYTEENAMASKS byteena_b[0] => ram_block1a3.PORTBBYTEENAMASKS byteena_b[0] => ram_block1a4.PORTBBYTEENAMASKS byteena_b[0] => ram_block1a5.PORTBBYTEENAMASKS byteena_b[0] => ram_block1a6.PORTBBYTEENAMASKS byteena_b[0] => ram_block1a7.PORTBBYTEENAMASKS byteena_b[1] => ram_block1a8.PORTBBYTEENAMASKS byteena_b[1] => ram_block1a9.PORTBBYTEENAMASKS byteena_b[1] => ram_block1a10.PORTBBYTEENAMASKS byteena_b[1] => ram_block1a11.PORTBBYTEENAMASKS byteena_b[1] => ram_block1a12.PORTBBYTEENAMASKS byteena_b[1] => ram_block1a13.PORTBBYTEENAMASKS byteena_b[1] => ram_block1a14.PORTBBYTEENAMASKS byteena_b[1] => ram_block1a15.PORTBBYTEENAMASKS byteena_b[2] => ram_block1a16.PORTBBYTEENAMASKS byteena_b[2] => ram_block1a17.PORTBBYTEENAMASKS byteena_b[2] => ram_block1a18.PORTBBYTEENAMASKS byteena_b[2] => ram_block1a19.PORTBBYTEENAMASKS byteena_b[2] => ram_block1a20.PORTBBYTEENAMASKS byteena_b[2] => ram_block1a21.PORTBBYTEENAMASKS byteena_b[2] => ram_block1a22.PORTBBYTEENAMASKS byteena_b[2] => ram_block1a23.PORTBBYTEENAMASKS byteena_b[3] => ram_block1a24.PORTBBYTEENAMASKS byteena_b[3] => ram_block1a25.PORTBBYTEENAMASKS byteena_b[3] => ram_block1a26.PORTBBYTEENAMASKS byteena_b[3] => ram_block1a27.PORTBBYTEENAMASKS byteena_b[3] => ram_block1a28.PORTBBYTEENAMASKS byteena_b[3] => ram_block1a29.PORTBBYTEENAMASKS byteena_b[3] => ram_block1a30.PORTBBYTEENAMASKS byteena_b[3] => ram_block1a31.PORTBBYTEENAMASKS clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 clock0 => ram_block1a8.CLK0 clock0 => ram_block1a9.CLK0 clock0 => ram_block1a10.CLK0 clock0 => ram_block1a11.CLK0 clock0 => ram_block1a12.CLK0 clock0 => ram_block1a13.CLK0 clock0 => ram_block1a14.CLK0 clock0 => ram_block1a15.CLK0 clock0 => ram_block1a16.CLK0 clock0 => ram_block1a17.CLK0 clock0 => ram_block1a18.CLK0 clock0 => ram_block1a19.CLK0 clock0 => ram_block1a20.CLK0 clock0 => ram_block1a21.CLK0 clock0 => ram_block1a22.CLK0 clock0 => ram_block1a23.CLK0 clock0 => ram_block1a24.CLK0 clock0 => ram_block1a25.CLK0 clock0 => ram_block1a26.CLK0 clock0 => ram_block1a27.CLK0 clock0 => ram_block1a28.CLK0 clock0 => ram_block1a29.CLK0 clock0 => ram_block1a30.CLK0 clock0 => ram_block1a31.CLK0 clock1 => ram_block1a0.CLK1 clock1 => ram_block1a1.CLK1 clock1 => ram_block1a2.CLK1 clock1 => ram_block1a3.CLK1 clock1 => ram_block1a4.CLK1 clock1 => ram_block1a5.CLK1 clock1 => ram_block1a6.CLK1 clock1 => ram_block1a7.CLK1 clock1 => ram_block1a8.CLK1 clock1 => ram_block1a9.CLK1 clock1 => ram_block1a10.CLK1 clock1 => ram_block1a11.CLK1 clock1 => ram_block1a12.CLK1 clock1 => ram_block1a13.CLK1 clock1 => ram_block1a14.CLK1 clock1 => ram_block1a15.CLK1 clock1 => ram_block1a16.CLK1 clock1 => ram_block1a17.CLK1 clock1 => ram_block1a18.CLK1 clock1 => ram_block1a19.CLK1 clock1 => ram_block1a20.CLK1 clock1 => ram_block1a21.CLK1 clock1 => ram_block1a22.CLK1 clock1 => ram_block1a23.CLK1 clock1 => ram_block1a24.CLK1 clock1 => ram_block1a25.CLK1 clock1 => ram_block1a26.CLK1 clock1 => ram_block1a27.CLK1 clock1 => ram_block1a28.CLK1 clock1 => ram_block1a29.CLK1 clock1 => ram_block1a30.CLK1 clock1 => ram_block1a31.CLK1 clocken0 => ram_block1a0.ENA0 clocken0 => ram_block1a1.ENA0 clocken0 => ram_block1a2.ENA0 clocken0 => ram_block1a3.ENA0 clocken0 => ram_block1a4.ENA0 clocken0 => ram_block1a5.ENA0 clocken0 => ram_block1a6.ENA0 clocken0 => ram_block1a7.ENA0 clocken0 => ram_block1a8.ENA0 clocken0 => ram_block1a9.ENA0 clocken0 => ram_block1a10.ENA0 clocken0 => ram_block1a11.ENA0 clocken0 => ram_block1a12.ENA0 clocken0 => ram_block1a13.ENA0 clocken0 => ram_block1a14.ENA0 clocken0 => ram_block1a15.ENA0 clocken0 => ram_block1a16.ENA0 clocken0 => ram_block1a17.ENA0 clocken0 => ram_block1a18.ENA0 clocken0 => ram_block1a19.ENA0 clocken0 => ram_block1a20.ENA0 clocken0 => ram_block1a21.ENA0 clocken0 => ram_block1a22.ENA0 clocken0 => ram_block1a23.ENA0 clocken0 => ram_block1a24.ENA0 clocken0 => ram_block1a25.ENA0 clocken0 => ram_block1a26.ENA0 clocken0 => ram_block1a27.ENA0 clocken0 => ram_block1a28.ENA0 clocken0 => ram_block1a29.ENA0 clocken0 => ram_block1a30.ENA0 clocken0 => ram_block1a31.ENA0 clocken1 => ram_block1a0.ENA1 clocken1 => ram_block1a1.ENA1 clocken1 => ram_block1a2.ENA1 clocken1 => ram_block1a3.ENA1 clocken1 => ram_block1a4.ENA1 clocken1 => ram_block1a5.ENA1 clocken1 => ram_block1a6.ENA1 clocken1 => ram_block1a7.ENA1 clocken1 => ram_block1a8.ENA1 clocken1 => ram_block1a9.ENA1 clocken1 => ram_block1a10.ENA1 clocken1 => ram_block1a11.ENA1 clocken1 => ram_block1a12.ENA1 clocken1 => ram_block1a13.ENA1 clocken1 => ram_block1a14.ENA1 clocken1 => ram_block1a15.ENA1 clocken1 => ram_block1a16.ENA1 clocken1 => ram_block1a17.ENA1 clocken1 => ram_block1a18.ENA1 clocken1 => ram_block1a19.ENA1 clocken1 => ram_block1a20.ENA1 clocken1 => ram_block1a21.ENA1 clocken1 => ram_block1a22.ENA1 clocken1 => ram_block1a23.ENA1 clocken1 => ram_block1a24.ENA1 clocken1 => ram_block1a25.ENA1 clocken1 => ram_block1a26.ENA1 clocken1 => ram_block1a27.ENA1 clocken1 => ram_block1a28.ENA1 clocken1 => ram_block1a29.ENA1 clocken1 => ram_block1a30.ENA1 clocken1 => ram_block1a31.ENA1 data_a[0] => ram_block1a0.PORTADATAIN data_a[1] => ram_block1a1.PORTADATAIN data_a[2] => ram_block1a2.PORTADATAIN data_a[3] => ram_block1a3.PORTADATAIN data_a[4] => ram_block1a4.PORTADATAIN data_a[5] => ram_block1a5.PORTADATAIN data_a[6] => ram_block1a6.PORTADATAIN data_a[7] => ram_block1a7.PORTADATAIN data_a[8] => ram_block1a8.PORTADATAIN data_a[9] => ram_block1a9.PORTADATAIN data_a[10] => ram_block1a10.PORTADATAIN data_a[11] => ram_block1a11.PORTADATAIN data_a[12] => ram_block1a12.PORTADATAIN data_a[13] => ram_block1a13.PORTADATAIN data_a[14] => ram_block1a14.PORTADATAIN data_a[15] => ram_block1a15.PORTADATAIN data_a[16] => ram_block1a16.PORTADATAIN data_a[17] => ram_block1a17.PORTADATAIN data_a[18] => ram_block1a18.PORTADATAIN data_a[19] => ram_block1a19.PORTADATAIN data_a[20] => ram_block1a20.PORTADATAIN data_a[21] => ram_block1a21.PORTADATAIN data_a[22] => ram_block1a22.PORTADATAIN data_a[23] => ram_block1a23.PORTADATAIN data_a[24] => ram_block1a24.PORTADATAIN data_a[25] => ram_block1a25.PORTADATAIN data_a[26] => ram_block1a26.PORTADATAIN data_a[27] => ram_block1a27.PORTADATAIN data_a[28] => ram_block1a28.PORTADATAIN data_a[29] => ram_block1a29.PORTADATAIN data_a[30] => ram_block1a30.PORTADATAIN data_a[31] => ram_block1a31.PORTADATAIN data_b[0] => ram_block1a0.PORTBDATAIN data_b[1] => ram_block1a1.PORTBDATAIN data_b[2] => ram_block1a2.PORTBDATAIN data_b[3] => ram_block1a3.PORTBDATAIN data_b[4] => ram_block1a4.PORTBDATAIN data_b[5] => ram_block1a5.PORTBDATAIN data_b[6] => ram_block1a6.PORTBDATAIN data_b[7] => ram_block1a7.PORTBDATAIN data_b[8] => ram_block1a8.PORTBDATAIN data_b[9] => ram_block1a9.PORTBDATAIN data_b[10] => ram_block1a10.PORTBDATAIN data_b[11] => ram_block1a11.PORTBDATAIN data_b[12] => ram_block1a12.PORTBDATAIN data_b[13] => ram_block1a13.PORTBDATAIN data_b[14] => ram_block1a14.PORTBDATAIN data_b[15] => ram_block1a15.PORTBDATAIN data_b[16] => ram_block1a16.PORTBDATAIN data_b[17] => ram_block1a17.PORTBDATAIN data_b[18] => ram_block1a18.PORTBDATAIN data_b[19] => ram_block1a19.PORTBDATAIN data_b[20] => ram_block1a20.PORTBDATAIN data_b[21] => ram_block1a21.PORTBDATAIN data_b[22] => ram_block1a22.PORTBDATAIN data_b[23] => ram_block1a23.PORTBDATAIN data_b[24] => ram_block1a24.PORTBDATAIN data_b[25] => ram_block1a25.PORTBDATAIN data_b[26] => ram_block1a26.PORTBDATAIN data_b[27] => ram_block1a27.PORTBDATAIN data_b[28] => ram_block1a28.PORTBDATAIN data_b[29] => ram_block1a29.PORTBDATAIN data_b[30] => ram_block1a30.PORTBDATAIN data_b[31] => ram_block1a31.PORTBDATAIN q_a[0] <= ram_block1a0.PORTADATAOUT q_a[1] <= ram_block1a1.PORTADATAOUT q_a[2] <= ram_block1a2.PORTADATAOUT q_a[3] <= ram_block1a3.PORTADATAOUT q_a[4] <= ram_block1a4.PORTADATAOUT q_a[5] <= ram_block1a5.PORTADATAOUT q_a[6] <= ram_block1a6.PORTADATAOUT q_a[7] <= ram_block1a7.PORTADATAOUT q_a[8] <= ram_block1a8.PORTADATAOUT q_a[9] <= ram_block1a9.PORTADATAOUT q_a[10] <= ram_block1a10.PORTADATAOUT q_a[11] <= ram_block1a11.PORTADATAOUT q_a[12] <= ram_block1a12.PORTADATAOUT q_a[13] <= ram_block1a13.PORTADATAOUT q_a[14] <= ram_block1a14.PORTADATAOUT q_a[15] <= ram_block1a15.PORTADATAOUT q_a[16] <= ram_block1a16.PORTADATAOUT q_a[17] <= ram_block1a17.PORTADATAOUT q_a[18] <= ram_block1a18.PORTADATAOUT q_a[19] <= ram_block1a19.PORTADATAOUT q_a[20] <= ram_block1a20.PORTADATAOUT q_a[21] <= ram_block1a21.PORTADATAOUT q_a[22] <= ram_block1a22.PORTADATAOUT q_a[23] <= ram_block1a23.PORTADATAOUT q_a[24] <= ram_block1a24.PORTADATAOUT q_a[25] <= ram_block1a25.PORTADATAOUT q_a[26] <= ram_block1a26.PORTADATAOUT q_a[27] <= ram_block1a27.PORTADATAOUT q_a[28] <= ram_block1a28.PORTADATAOUT q_a[29] <= ram_block1a29.PORTADATAOUT q_a[30] <= ram_block1a30.PORTADATAOUT q_a[31] <= ram_block1a31.PORTADATAOUT q_b[0] <= ram_block1a0.PORTBDATAOUT q_b[1] <= ram_block1a1.PORTBDATAOUT q_b[2] <= ram_block1a2.PORTBDATAOUT q_b[3] <= ram_block1a3.PORTBDATAOUT q_b[4] <= ram_block1a4.PORTBDATAOUT q_b[5] <= ram_block1a5.PORTBDATAOUT q_b[6] <= ram_block1a6.PORTBDATAOUT q_b[7] <= ram_block1a7.PORTBDATAOUT q_b[8] <= ram_block1a8.PORTBDATAOUT q_b[9] <= ram_block1a9.PORTBDATAOUT q_b[10] <= ram_block1a10.PORTBDATAOUT q_b[11] <= ram_block1a11.PORTBDATAOUT q_b[12] <= ram_block1a12.PORTBDATAOUT q_b[13] <= ram_block1a13.PORTBDATAOUT q_b[14] <= ram_block1a14.PORTBDATAOUT q_b[15] <= ram_block1a15.PORTBDATAOUT q_b[16] <= ram_block1a16.PORTBDATAOUT q_b[17] <= ram_block1a17.PORTBDATAOUT q_b[18] <= ram_block1a18.PORTBDATAOUT q_b[19] <= ram_block1a19.PORTBDATAOUT q_b[20] <= ram_block1a20.PORTBDATAOUT q_b[21] <= ram_block1a21.PORTBDATAOUT q_b[22] <= ram_block1a22.PORTBDATAOUT q_b[23] <= ram_block1a23.PORTBDATAOUT q_b[24] <= ram_block1a24.PORTBDATAOUT q_b[25] <= ram_block1a25.PORTBDATAOUT q_b[26] <= ram_block1a26.PORTBDATAOUT q_b[27] <= ram_block1a27.PORTBDATAOUT q_b[28] <= ram_block1a28.PORTBDATAOUT q_b[29] <= ram_block1a29.PORTBDATAOUT q_b[30] <= ram_block1a30.PORTBDATAOUT q_b[31] <= ram_block1a31.PORTBDATAOUT wren_b => ram_block1a0.PORTBRE wren_b => ram_block1a1.PORTBRE wren_b => ram_block1a2.PORTBRE wren_b => ram_block1a3.PORTBRE wren_b => ram_block1a4.PORTBRE wren_b => ram_block1a5.PORTBRE wren_b => ram_block1a6.PORTBRE wren_b => ram_block1a7.PORTBRE wren_b => ram_block1a8.PORTBRE wren_b => ram_block1a9.PORTBRE wren_b => ram_block1a10.PORTBRE wren_b => ram_block1a11.PORTBRE wren_b => ram_block1a12.PORTBRE wren_b => ram_block1a13.PORTBRE wren_b => ram_block1a14.PORTBRE wren_b => ram_block1a15.PORTBRE wren_b => ram_block1a16.PORTBRE wren_b => ram_block1a17.PORTBRE wren_b => ram_block1a18.PORTBRE wren_b => ram_block1a19.PORTBRE wren_b => ram_block1a20.PORTBRE wren_b => ram_block1a21.PORTBRE wren_b => ram_block1a22.PORTBRE wren_b => ram_block1a23.PORTBRE wren_b => ram_block1a24.PORTBRE wren_b => ram_block1a25.PORTBRE wren_b => ram_block1a26.PORTBRE wren_b => ram_block1a27.PORTBRE wren_b => ram_block1a28.PORTBRE wren_b => ram_block1a29.PORTBRE wren_b => ram_block1a30.PORTBRE wren_b => ram_block1a31.PORTBRE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell A_mul_src1[0] => A_mul_src1[0]~31.IN1 A_mul_src1[1] => A_mul_src1[1]~30.IN1 A_mul_src1[2] => A_mul_src1[2]~29.IN1 A_mul_src1[3] => A_mul_src1[3]~28.IN1 A_mul_src1[4] => A_mul_src1[4]~27.IN1 A_mul_src1[5] => A_mul_src1[5]~26.IN1 A_mul_src1[6] => A_mul_src1[6]~25.IN1 A_mul_src1[7] => A_mul_src1[7]~24.IN1 A_mul_src1[8] => A_mul_src1[8]~23.IN1 A_mul_src1[9] => A_mul_src1[9]~22.IN1 A_mul_src1[10] => A_mul_src1[10]~21.IN1 A_mul_src1[11] => A_mul_src1[11]~20.IN1 A_mul_src1[12] => A_mul_src1[12]~19.IN1 A_mul_src1[13] => A_mul_src1[13]~18.IN1 A_mul_src1[14] => A_mul_src1[14]~17.IN1 A_mul_src1[15] => A_mul_src1[15]~16.IN1 A_mul_src1[16] => A_mul_src1[16]~15.IN1 A_mul_src1[17] => A_mul_src1[17]~14.IN1 A_mul_src1[18] => A_mul_src1[18]~13.IN1 A_mul_src1[19] => A_mul_src1[19]~12.IN1 A_mul_src1[20] => A_mul_src1[20]~11.IN1 A_mul_src1[21] => A_mul_src1[21]~10.IN1 A_mul_src1[22] => A_mul_src1[22]~9.IN1 A_mul_src1[23] => A_mul_src1[23]~8.IN1 A_mul_src1[24] => A_mul_src1[24]~7.IN1 A_mul_src1[25] => A_mul_src1[25]~6.IN1 A_mul_src1[26] => A_mul_src1[26]~5.IN1 A_mul_src1[27] => A_mul_src1[27]~4.IN1 A_mul_src1[28] => A_mul_src1[28]~3.IN1 A_mul_src1[29] => A_mul_src1[29]~2.IN1 A_mul_src1[30] => A_mul_src1[30]~1.IN1 A_mul_src1[31] => A_mul_src1[31]~0.IN1 A_mul_src2[0] => A_mul_src2[0]~15.IN2 A_mul_src2[1] => A_mul_src2[1]~14.IN2 A_mul_src2[2] => A_mul_src2[2]~13.IN2 A_mul_src2[3] => A_mul_src2[3]~12.IN2 A_mul_src2[4] => A_mul_src2[4]~11.IN2 A_mul_src2[5] => A_mul_src2[5]~10.IN2 A_mul_src2[6] => A_mul_src2[6]~9.IN2 A_mul_src2[7] => A_mul_src2[7]~8.IN2 A_mul_src2[8] => A_mul_src2[8]~7.IN2 A_mul_src2[9] => A_mul_src2[9]~6.IN2 A_mul_src2[10] => A_mul_src2[10]~5.IN2 A_mul_src2[11] => A_mul_src2[11]~4.IN2 A_mul_src2[12] => A_mul_src2[12]~3.IN2 A_mul_src2[13] => A_mul_src2[13]~2.IN2 A_mul_src2[14] => A_mul_src2[14]~1.IN2 A_mul_src2[15] => A_mul_src2[15]~0.IN2 A_mul_src2[16] => ~NO_FANOUT~ A_mul_src2[17] => ~NO_FANOUT~ A_mul_src2[18] => ~NO_FANOUT~ A_mul_src2[19] => ~NO_FANOUT~ A_mul_src2[20] => ~NO_FANOUT~ A_mul_src2[21] => ~NO_FANOUT~ A_mul_src2[22] => ~NO_FANOUT~ A_mul_src2[23] => ~NO_FANOUT~ A_mul_src2[24] => ~NO_FANOUT~ A_mul_src2[25] => ~NO_FANOUT~ A_mul_src2[26] => ~NO_FANOUT~ A_mul_src2[27] => ~NO_FANOUT~ A_mul_src2[28] => ~NO_FANOUT~ A_mul_src2[29] => ~NO_FANOUT~ A_mul_src2[30] => ~NO_FANOUT~ A_mul_src2[31] => ~NO_FANOUT~ clk => clk~0.IN2 reset_n => mul_clr.IN2 A_mul_cell_result[0] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[1] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[2] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[3] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[4] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[5] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[6] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[7] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[8] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[9] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[10] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[11] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[12] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[13] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[14] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[15] <= altmult_add:the_altmult_add_part_1.result A_mul_cell_result[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE A_mul_cell_result[17] <= Add0.DB_MAX_OUTPUT_PORT_TYPE A_mul_cell_result[18] <= Add0.DB_MAX_OUTPUT_PORT_TYPE A_mul_cell_result[19] <= Add0.DB_MAX_OUTPUT_PORT_TYPE A_mul_cell_result[20] <= Add0.DB_MAX_OUTPUT_PORT_TYPE A_mul_cell_result[21] <= Add0.DB_MAX_OUTPUT_PORT_TYPE A_mul_cell_result[22] <= Add0.DB_MAX_OUTPUT_PORT_TYPE A_mul_cell_result[23] <= Add0.DB_MAX_OUTPUT_PORT_TYPE A_mul_cell_result[24] <= Add0.DB_MAX_OUTPUT_PORT_TYPE A_mul_cell_result[25] <= Add0.DB_MAX_OUTPUT_PORT_TYPE A_mul_cell_result[26] <= Add0.DB_MAX_OUTPUT_PORT_TYPE A_mul_cell_result[27] <= Add0.DB_MAX_OUTPUT_PORT_TYPE A_mul_cell_result[28] <= Add0.DB_MAX_OUTPUT_PORT_TYPE A_mul_cell_result[29] <= Add0.DB_MAX_OUTPUT_PORT_TYPE A_mul_cell_result[30] <= Add0.DB_MAX_OUTPUT_PORT_TYPE A_mul_cell_result[31] <= Add0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1 accum_sload => ~NO_FANOUT~ aclr0 => mult_add_4cr2:auto_generated.aclr0 aclr1 => ~NO_FANOUT~ aclr2 => ~NO_FANOUT~ aclr3 => ~NO_FANOUT~ addnsub1 => ~NO_FANOUT~ addnsub1_round => ~NO_FANOUT~ addnsub3 => ~NO_FANOUT~ addnsub3_round => ~NO_FANOUT~ chainin[0] => ~NO_FANOUT~ chainout_round => ~NO_FANOUT~ chainout_sat_overflow <= chainout_sat_overflow~0.DB_MAX_OUTPUT_PORT_TYPE chainout_saturate => ~NO_FANOUT~ clock0 => mult_add_4cr2:auto_generated.clock0 clock1 => ~NO_FANOUT~ clock2 => ~NO_FANOUT~ clock3 => ~NO_FANOUT~ dataa[0] => mult_add_4cr2:auto_generated.dataa[0] dataa[1] => mult_add_4cr2:auto_generated.dataa[1] dataa[2] => mult_add_4cr2:auto_generated.dataa[2] dataa[3] => mult_add_4cr2:auto_generated.dataa[3] dataa[4] => mult_add_4cr2:auto_generated.dataa[4] dataa[5] => mult_add_4cr2:auto_generated.dataa[5] dataa[6] => mult_add_4cr2:auto_generated.dataa[6] dataa[7] => mult_add_4cr2:auto_generated.dataa[7] dataa[8] => mult_add_4cr2:auto_generated.dataa[8] dataa[9] => mult_add_4cr2:auto_generated.dataa[9] dataa[10] => mult_add_4cr2:auto_generated.dataa[10] dataa[11] => mult_add_4cr2:auto_generated.dataa[11] dataa[12] => mult_add_4cr2:auto_generated.dataa[12] dataa[13] => mult_add_4cr2:auto_generated.dataa[13] dataa[14] => mult_add_4cr2:auto_generated.dataa[14] dataa[15] => mult_add_4cr2:auto_generated.dataa[15] datab[0] => mult_add_4cr2:auto_generated.datab[0] datab[1] => mult_add_4cr2:auto_generated.datab[1] datab[2] => mult_add_4cr2:auto_generated.datab[2] datab[3] => mult_add_4cr2:auto_generated.datab[3] datab[4] => mult_add_4cr2:auto_generated.datab[4] datab[5] => mult_add_4cr2:auto_generated.datab[5] datab[6] => mult_add_4cr2:auto_generated.datab[6] datab[7] => mult_add_4cr2:auto_generated.datab[7] datab[8] => mult_add_4cr2:auto_generated.datab[8] datab[9] => mult_add_4cr2:auto_generated.datab[9] datab[10] => mult_add_4cr2:auto_generated.datab[10] datab[11] => mult_add_4cr2:auto_generated.datab[11] datab[12] => mult_add_4cr2:auto_generated.datab[12] datab[13] => mult_add_4cr2:auto_generated.datab[13] datab[14] => mult_add_4cr2:auto_generated.datab[14] datab[15] => mult_add_4cr2:auto_generated.datab[15] ena0 => ~NO_FANOUT~ ena1 => ~NO_FANOUT~ ena2 => ~NO_FANOUT~ ena3 => ~NO_FANOUT~ mult01_round => ~NO_FANOUT~ mult01_saturation => ~NO_FANOUT~ mult0_is_saturated <= mult0_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE mult1_is_saturated <= mult1_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE mult23_round => ~NO_FANOUT~ mult23_saturation => ~NO_FANOUT~ mult2_is_saturated <= mult2_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE mult3_is_saturated <= mult3_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE output_round => ~NO_FANOUT~ output_saturate => ~NO_FANOUT~ overflow <= overflow~0.DB_MAX_OUTPUT_PORT_TYPE result[0] <= mult_add_4cr2:auto_generated.result[0] result[1] <= mult_add_4cr2:auto_generated.result[1] result[2] <= mult_add_4cr2:auto_generated.result[2] result[3] <= mult_add_4cr2:auto_generated.result[3] result[4] <= mult_add_4cr2:auto_generated.result[4] result[5] <= mult_add_4cr2:auto_generated.result[5] result[6] <= mult_add_4cr2:auto_generated.result[6] result[7] <= mult_add_4cr2:auto_generated.result[7] result[8] <= mult_add_4cr2:auto_generated.result[8] result[9] <= mult_add_4cr2:auto_generated.result[9] result[10] <= mult_add_4cr2:auto_generated.result[10] result[11] <= mult_add_4cr2:auto_generated.result[11] result[12] <= mult_add_4cr2:auto_generated.result[12] result[13] <= mult_add_4cr2:auto_generated.result[13] result[14] <= mult_add_4cr2:auto_generated.result[14] result[15] <= mult_add_4cr2:auto_generated.result[15] result[16] <= mult_add_4cr2:auto_generated.result[16] result[17] <= mult_add_4cr2:auto_generated.result[17] result[18] <= mult_add_4cr2:auto_generated.result[18] result[19] <= mult_add_4cr2:auto_generated.result[19] result[20] <= mult_add_4cr2:auto_generated.result[20] result[21] <= mult_add_4cr2:auto_generated.result[21] result[22] <= mult_add_4cr2:auto_generated.result[22] result[23] <= mult_add_4cr2:auto_generated.result[23] result[24] <= mult_add_4cr2:auto_generated.result[24] result[25] <= mult_add_4cr2:auto_generated.result[25] result[26] <= mult_add_4cr2:auto_generated.result[26] result[27] <= mult_add_4cr2:auto_generated.result[27] result[28] <= mult_add_4cr2:auto_generated.result[28] result[29] <= mult_add_4cr2:auto_generated.result[29] result[30] <= mult_add_4cr2:auto_generated.result[30] result[31] <= mult_add_4cr2:auto_generated.result[31] rotate => ~NO_FANOUT~ scanina[0] => ~NO_FANOUT~ scanina[1] => ~NO_FANOUT~ scanina[2] => ~NO_FANOUT~ scanina[3] => ~NO_FANOUT~ scanina[4] => ~NO_FANOUT~ scanina[5] => ~NO_FANOUT~ scanina[6] => ~NO_FANOUT~ scanina[7] => ~NO_FANOUT~ scanina[8] => ~NO_FANOUT~ scanina[9] => ~NO_FANOUT~ scanina[10] => ~NO_FANOUT~ scanina[11] => ~NO_FANOUT~ scanina[12] => ~NO_FANOUT~ scanina[13] => ~NO_FANOUT~ scanina[14] => ~NO_FANOUT~ scanina[15] => ~NO_FANOUT~ scaninb[0] => ~NO_FANOUT~ scaninb[1] => ~NO_FANOUT~ scaninb[2] => ~NO_FANOUT~ scaninb[3] => ~NO_FANOUT~ scaninb[4] => ~NO_FANOUT~ scaninb[5] => ~NO_FANOUT~ scaninb[6] => ~NO_FANOUT~ scaninb[7] => ~NO_FANOUT~ scaninb[8] => ~NO_FANOUT~ scaninb[9] => ~NO_FANOUT~ scaninb[10] => ~NO_FANOUT~ scaninb[11] => ~NO_FANOUT~ scaninb[12] => ~NO_FANOUT~ scaninb[13] => ~NO_FANOUT~ scaninb[14] => ~NO_FANOUT~ scaninb[15] => ~NO_FANOUT~ scanouta[0] <= scanouta[0]~15.DB_MAX_OUTPUT_PORT_TYPE scanouta[1] <= scanouta[1]~14.DB_MAX_OUTPUT_PORT_TYPE scanouta[2] <= scanouta[2]~13.DB_MAX_OUTPUT_PORT_TYPE scanouta[3] <= scanouta[3]~12.DB_MAX_OUTPUT_PORT_TYPE scanouta[4] <= scanouta[4]~11.DB_MAX_OUTPUT_PORT_TYPE scanouta[5] <= scanouta[5]~10.DB_MAX_OUTPUT_PORT_TYPE scanouta[6] <= scanouta[6]~9.DB_MAX_OUTPUT_PORT_TYPE scanouta[7] <= scanouta[7]~8.DB_MAX_OUTPUT_PORT_TYPE scanouta[8] <= scanouta[8]~7.DB_MAX_OUTPUT_PORT_TYPE scanouta[9] <= scanouta[9]~6.DB_MAX_OUTPUT_PORT_TYPE scanouta[10] <= scanouta[10]~5.DB_MAX_OUTPUT_PORT_TYPE scanouta[11] <= scanouta[11]~4.DB_MAX_OUTPUT_PORT_TYPE scanouta[12] <= scanouta[12]~3.DB_MAX_OUTPUT_PORT_TYPE scanouta[13] <= scanouta[13]~2.DB_MAX_OUTPUT_PORT_TYPE scanouta[14] <= scanouta[14]~1.DB_MAX_OUTPUT_PORT_TYPE scanouta[15] <= scanouta[15]~0.DB_MAX_OUTPUT_PORT_TYPE scanoutb[0] <= scanoutb[0]~15.DB_MAX_OUTPUT_PORT_TYPE scanoutb[1] <= scanoutb[1]~14.DB_MAX_OUTPUT_PORT_TYPE scanoutb[2] <= scanoutb[2]~13.DB_MAX_OUTPUT_PORT_TYPE scanoutb[3] <= scanoutb[3]~12.DB_MAX_OUTPUT_PORT_TYPE scanoutb[4] <= scanoutb[4]~11.DB_MAX_OUTPUT_PORT_TYPE scanoutb[5] <= scanoutb[5]~10.DB_MAX_OUTPUT_PORT_TYPE scanoutb[6] <= scanoutb[6]~9.DB_MAX_OUTPUT_PORT_TYPE scanoutb[7] <= scanoutb[7]~8.DB_MAX_OUTPUT_PORT_TYPE scanoutb[8] <= scanoutb[8]~7.DB_MAX_OUTPUT_PORT_TYPE scanoutb[9] <= scanoutb[9]~6.DB_MAX_OUTPUT_PORT_TYPE scanoutb[10] <= scanoutb[10]~5.DB_MAX_OUTPUT_PORT_TYPE scanoutb[11] <= scanoutb[11]~4.DB_MAX_OUTPUT_PORT_TYPE scanoutb[12] <= scanoutb[12]~3.DB_MAX_OUTPUT_PORT_TYPE scanoutb[13] <= scanoutb[13]~2.DB_MAX_OUTPUT_PORT_TYPE scanoutb[14] <= scanoutb[14]~1.DB_MAX_OUTPUT_PORT_TYPE scanoutb[15] <= scanoutb[15]~0.DB_MAX_OUTPUT_PORT_TYPE shift_right => ~NO_FANOUT~ signa => ~NO_FANOUT~ signb => ~NO_FANOUT~ sourcea[0] => ~NO_FANOUT~ sourceb[0] => ~NO_FANOUT~ zero_chainout => ~NO_FANOUT~ zero_loopback => ~NO_FANOUT~ |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated aclr0 => ded_mult_2o81:ded_mult1.aclr[0] clock0 => ded_mult_2o81:ded_mult1.clock[0] dataa[0] => ded_mult_2o81:ded_mult1.dataa[0] dataa[1] => ded_mult_2o81:ded_mult1.dataa[1] dataa[2] => ded_mult_2o81:ded_mult1.dataa[2] dataa[3] => ded_mult_2o81:ded_mult1.dataa[3] dataa[4] => ded_mult_2o81:ded_mult1.dataa[4] dataa[5] => ded_mult_2o81:ded_mult1.dataa[5] dataa[6] => ded_mult_2o81:ded_mult1.dataa[6] dataa[7] => ded_mult_2o81:ded_mult1.dataa[7] dataa[8] => ded_mult_2o81:ded_mult1.dataa[8] dataa[9] => ded_mult_2o81:ded_mult1.dataa[9] dataa[10] => ded_mult_2o81:ded_mult1.dataa[10] dataa[11] => ded_mult_2o81:ded_mult1.dataa[11] dataa[12] => ded_mult_2o81:ded_mult1.dataa[12] dataa[13] => ded_mult_2o81:ded_mult1.dataa[13] dataa[14] => ded_mult_2o81:ded_mult1.dataa[14] dataa[15] => ded_mult_2o81:ded_mult1.dataa[15] datab[0] => ded_mult_2o81:ded_mult1.datab[0] datab[1] => ded_mult_2o81:ded_mult1.datab[1] datab[2] => ded_mult_2o81:ded_mult1.datab[2] datab[3] => ded_mult_2o81:ded_mult1.datab[3] datab[4] => ded_mult_2o81:ded_mult1.datab[4] datab[5] => ded_mult_2o81:ded_mult1.datab[5] datab[6] => ded_mult_2o81:ded_mult1.datab[6] datab[7] => ded_mult_2o81:ded_mult1.datab[7] datab[8] => ded_mult_2o81:ded_mult1.datab[8] datab[9] => ded_mult_2o81:ded_mult1.datab[9] datab[10] => ded_mult_2o81:ded_mult1.datab[10] datab[11] => ded_mult_2o81:ded_mult1.datab[11] datab[12] => ded_mult_2o81:ded_mult1.datab[12] datab[13] => ded_mult_2o81:ded_mult1.datab[13] datab[14] => ded_mult_2o81:ded_mult1.datab[14] datab[15] => ded_mult_2o81:ded_mult1.datab[15] result[0] <= pre_result[0].DB_MAX_OUTPUT_PORT_TYPE result[1] <= pre_result[1].DB_MAX_OUTPUT_PORT_TYPE result[2] <= pre_result[2].DB_MAX_OUTPUT_PORT_TYPE result[3] <= pre_result[3].DB_MAX_OUTPUT_PORT_TYPE result[4] <= pre_result[4].DB_MAX_OUTPUT_PORT_TYPE result[5] <= pre_result[5].DB_MAX_OUTPUT_PORT_TYPE result[6] <= pre_result[6].DB_MAX_OUTPUT_PORT_TYPE result[7] <= pre_result[7].DB_MAX_OUTPUT_PORT_TYPE result[8] <= pre_result[8].DB_MAX_OUTPUT_PORT_TYPE result[9] <= pre_result[9].DB_MAX_OUTPUT_PORT_TYPE result[10] <= pre_result[10].DB_MAX_OUTPUT_PORT_TYPE result[11] <= pre_result[11].DB_MAX_OUTPUT_PORT_TYPE result[12] <= pre_result[12].DB_MAX_OUTPUT_PORT_TYPE result[13] <= pre_result[13].DB_MAX_OUTPUT_PORT_TYPE result[14] <= pre_result[14].DB_MAX_OUTPUT_PORT_TYPE result[15] <= pre_result[15].DB_MAX_OUTPUT_PORT_TYPE result[16] <= pre_result[16].DB_MAX_OUTPUT_PORT_TYPE result[17] <= pre_result[17].DB_MAX_OUTPUT_PORT_TYPE result[18] <= pre_result[18].DB_MAX_OUTPUT_PORT_TYPE result[19] <= pre_result[19].DB_MAX_OUTPUT_PORT_TYPE result[20] <= pre_result[20].DB_MAX_OUTPUT_PORT_TYPE result[21] <= pre_result[21].DB_MAX_OUTPUT_PORT_TYPE result[22] <= pre_result[22].DB_MAX_OUTPUT_PORT_TYPE result[23] <= pre_result[23].DB_MAX_OUTPUT_PORT_TYPE result[24] <= pre_result[24].DB_MAX_OUTPUT_PORT_TYPE result[25] <= pre_result[25].DB_MAX_OUTPUT_PORT_TYPE result[26] <= pre_result[26].DB_MAX_OUTPUT_PORT_TYPE result[27] <= pre_result[27].DB_MAX_OUTPUT_PORT_TYPE result[28] <= pre_result[28].DB_MAX_OUTPUT_PORT_TYPE result[29] <= pre_result[29].DB_MAX_OUTPUT_PORT_TYPE result[30] <= pre_result[30].DB_MAX_OUTPUT_PORT_TYPE result[31] <= pre_result[31].DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1 aclr[0] => mac_mult2.ACLR aclr[0] => mac_out3.ACLR aclr[1] => ~NO_FANOUT~ aclr[2] => ~NO_FANOUT~ aclr[3] => ~NO_FANOUT~ clock[0] => mac_mult2.CLK clock[0] => mac_out3.CLK clock[1] => ~NO_FANOUT~ clock[2] => ~NO_FANOUT~ clock[3] => ~NO_FANOUT~ dataa[0] => mac_mult2.DATAA dataa[1] => mac_mult2.DATAA1 dataa[2] => mac_mult2.DATAA2 dataa[3] => mac_mult2.DATAA3 dataa[4] => mac_mult2.DATAA4 dataa[5] => mac_mult2.DATAA5 dataa[6] => mac_mult2.DATAA6 dataa[7] => mac_mult2.DATAA7 dataa[8] => mac_mult2.DATAA8 dataa[9] => mac_mult2.DATAA9 dataa[10] => mac_mult2.DATAA10 dataa[11] => mac_mult2.DATAA11 dataa[12] => mac_mult2.DATAA12 dataa[13] => mac_mult2.DATAA13 dataa[14] => mac_mult2.DATAA14 dataa[15] => mac_mult2.DATAA15 datab[0] => mac_mult2.DATAB datab[1] => mac_mult2.DATAB1 datab[2] => mac_mult2.DATAB2 datab[3] => mac_mult2.DATAB3 datab[4] => mac_mult2.DATAB4 datab[5] => mac_mult2.DATAB5 datab[6] => mac_mult2.DATAB6 datab[7] => mac_mult2.DATAB7 datab[8] => mac_mult2.DATAB8 datab[9] => mac_mult2.DATAB9 datab[10] => mac_mult2.DATAB10 datab[11] => mac_mult2.DATAB11 datab[12] => mac_mult2.DATAB12 datab[13] => mac_mult2.DATAB13 datab[14] => mac_mult2.DATAB14 datab[15] => mac_mult2.DATAB15 ena[0] => mac_mult2.ENA ena[0] => mac_out3.ENA ena[1] => ~NO_FANOUT~ ena[2] => ~NO_FANOUT~ ena[3] => ~NO_FANOUT~ result[0] <= dffpipe_93c:pre_result.q[0] result[1] <= dffpipe_93c:pre_result.q[1] result[2] <= dffpipe_93c:pre_result.q[2] result[3] <= dffpipe_93c:pre_result.q[3] result[4] <= dffpipe_93c:pre_result.q[4] result[5] <= dffpipe_93c:pre_result.q[5] result[6] <= dffpipe_93c:pre_result.q[6] result[7] <= dffpipe_93c:pre_result.q[7] result[8] <= dffpipe_93c:pre_result.q[8] result[9] <= dffpipe_93c:pre_result.q[9] result[10] <= dffpipe_93c:pre_result.q[10] result[11] <= dffpipe_93c:pre_result.q[11] result[12] <= dffpipe_93c:pre_result.q[12] result[13] <= dffpipe_93c:pre_result.q[13] result[14] <= dffpipe_93c:pre_result.q[14] result[15] <= dffpipe_93c:pre_result.q[15] result[16] <= dffpipe_93c:pre_result.q[16] result[17] <= dffpipe_93c:pre_result.q[17] result[18] <= dffpipe_93c:pre_result.q[18] result[19] <= dffpipe_93c:pre_result.q[19] result[20] <= dffpipe_93c:pre_result.q[20] result[21] <= dffpipe_93c:pre_result.q[21] result[22] <= dffpipe_93c:pre_result.q[22] result[23] <= dffpipe_93c:pre_result.q[23] result[24] <= dffpipe_93c:pre_result.q[24] result[25] <= dffpipe_93c:pre_result.q[25] result[26] <= dffpipe_93c:pre_result.q[26] result[27] <= dffpipe_93c:pre_result.q[27] result[28] <= dffpipe_93c:pre_result.q[28] result[29] <= dffpipe_93c:pre_result.q[29] result[30] <= dffpipe_93c:pre_result.q[30] result[31] <= dffpipe_93c:pre_result.q[31] |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result d[0] => q[0].DATAIN d[1] => q[1].DATAIN d[2] => q[2].DATAIN d[3] => q[3].DATAIN d[4] => q[4].DATAIN d[5] => q[5].DATAIN d[6] => q[6].DATAIN d[7] => q[7].DATAIN d[8] => q[8].DATAIN d[9] => q[9].DATAIN d[10] => q[10].DATAIN d[11] => q[11].DATAIN d[12] => q[12].DATAIN d[13] => q[13].DATAIN d[14] => q[14].DATAIN d[15] => q[15].DATAIN d[16] => q[16].DATAIN d[17] => q[17].DATAIN d[18] => q[18].DATAIN d[19] => q[19].DATAIN d[20] => q[20].DATAIN d[21] => q[21].DATAIN d[22] => q[22].DATAIN d[23] => q[23].DATAIN d[24] => q[24].DATAIN d[25] => q[25].DATAIN d[26] => q[26].DATAIN d[27] => q[27].DATAIN d[28] => q[28].DATAIN d[29] => q[29].DATAIN d[30] => q[30].DATAIN d[31] => q[31].DATAIN q[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE q[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE q[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE q[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE q[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE q[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE q[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE q[7] <= d[7].DB_MAX_OUTPUT_PORT_TYPE q[8] <= d[8].DB_MAX_OUTPUT_PORT_TYPE q[9] <= d[9].DB_MAX_OUTPUT_PORT_TYPE q[10] <= d[10].DB_MAX_OUTPUT_PORT_TYPE q[11] <= d[11].DB_MAX_OUTPUT_PORT_TYPE q[12] <= d[12].DB_MAX_OUTPUT_PORT_TYPE q[13] <= d[13].DB_MAX_OUTPUT_PORT_TYPE q[14] <= d[14].DB_MAX_OUTPUT_PORT_TYPE q[15] <= d[15].DB_MAX_OUTPUT_PORT_TYPE q[16] <= d[16].DB_MAX_OUTPUT_PORT_TYPE q[17] <= d[17].DB_MAX_OUTPUT_PORT_TYPE q[18] <= d[18].DB_MAX_OUTPUT_PORT_TYPE q[19] <= d[19].DB_MAX_OUTPUT_PORT_TYPE q[20] <= d[20].DB_MAX_OUTPUT_PORT_TYPE q[21] <= d[21].DB_MAX_OUTPUT_PORT_TYPE q[22] <= d[22].DB_MAX_OUTPUT_PORT_TYPE q[23] <= d[23].DB_MAX_OUTPUT_PORT_TYPE q[24] <= d[24].DB_MAX_OUTPUT_PORT_TYPE q[25] <= d[25].DB_MAX_OUTPUT_PORT_TYPE q[26] <= d[26].DB_MAX_OUTPUT_PORT_TYPE q[27] <= d[27].DB_MAX_OUTPUT_PORT_TYPE q[28] <= d[28].DB_MAX_OUTPUT_PORT_TYPE q[29] <= d[29].DB_MAX_OUTPUT_PORT_TYPE q[30] <= d[30].DB_MAX_OUTPUT_PORT_TYPE q[31] <= d[31].DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2 accum_sload => ~NO_FANOUT~ aclr0 => mult_add_6cr2:auto_generated.aclr0 aclr1 => ~NO_FANOUT~ aclr2 => ~NO_FANOUT~ aclr3 => ~NO_FANOUT~ addnsub1 => ~NO_FANOUT~ addnsub1_round => ~NO_FANOUT~ addnsub3 => ~NO_FANOUT~ addnsub3_round => ~NO_FANOUT~ chainin[0] => ~NO_FANOUT~ chainout_round => ~NO_FANOUT~ chainout_sat_overflow <= chainout_sat_overflow~0.DB_MAX_OUTPUT_PORT_TYPE chainout_saturate => ~NO_FANOUT~ clock0 => mult_add_6cr2:auto_generated.clock0 clock1 => ~NO_FANOUT~ clock2 => ~NO_FANOUT~ clock3 => ~NO_FANOUT~ dataa[0] => mult_add_6cr2:auto_generated.dataa[0] dataa[1] => mult_add_6cr2:auto_generated.dataa[1] dataa[2] => mult_add_6cr2:auto_generated.dataa[2] dataa[3] => mult_add_6cr2:auto_generated.dataa[3] dataa[4] => mult_add_6cr2:auto_generated.dataa[4] dataa[5] => mult_add_6cr2:auto_generated.dataa[5] dataa[6] => mult_add_6cr2:auto_generated.dataa[6] dataa[7] => mult_add_6cr2:auto_generated.dataa[7] dataa[8] => mult_add_6cr2:auto_generated.dataa[8] dataa[9] => mult_add_6cr2:auto_generated.dataa[9] dataa[10] => mult_add_6cr2:auto_generated.dataa[10] dataa[11] => mult_add_6cr2:auto_generated.dataa[11] dataa[12] => mult_add_6cr2:auto_generated.dataa[12] dataa[13] => mult_add_6cr2:auto_generated.dataa[13] dataa[14] => mult_add_6cr2:auto_generated.dataa[14] dataa[15] => mult_add_6cr2:auto_generated.dataa[15] datab[0] => mult_add_6cr2:auto_generated.datab[0] datab[1] => mult_add_6cr2:auto_generated.datab[1] datab[2] => mult_add_6cr2:auto_generated.datab[2] datab[3] => mult_add_6cr2:auto_generated.datab[3] datab[4] => mult_add_6cr2:auto_generated.datab[4] datab[5] => mult_add_6cr2:auto_generated.datab[5] datab[6] => mult_add_6cr2:auto_generated.datab[6] datab[7] => mult_add_6cr2:auto_generated.datab[7] datab[8] => mult_add_6cr2:auto_generated.datab[8] datab[9] => mult_add_6cr2:auto_generated.datab[9] datab[10] => mult_add_6cr2:auto_generated.datab[10] datab[11] => mult_add_6cr2:auto_generated.datab[11] datab[12] => mult_add_6cr2:auto_generated.datab[12] datab[13] => mult_add_6cr2:auto_generated.datab[13] datab[14] => mult_add_6cr2:auto_generated.datab[14] datab[15] => mult_add_6cr2:auto_generated.datab[15] ena0 => ~NO_FANOUT~ ena1 => ~NO_FANOUT~ ena2 => ~NO_FANOUT~ ena3 => ~NO_FANOUT~ mult01_round => ~NO_FANOUT~ mult01_saturation => ~NO_FANOUT~ mult0_is_saturated <= mult0_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE mult1_is_saturated <= mult1_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE mult23_round => ~NO_FANOUT~ mult23_saturation => ~NO_FANOUT~ mult2_is_saturated <= mult2_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE mult3_is_saturated <= mult3_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE output_round => ~NO_FANOUT~ output_saturate => ~NO_FANOUT~ overflow <= overflow~0.DB_MAX_OUTPUT_PORT_TYPE result[0] <= mult_add_6cr2:auto_generated.result[0] result[1] <= mult_add_6cr2:auto_generated.result[1] result[2] <= mult_add_6cr2:auto_generated.result[2] result[3] <= mult_add_6cr2:auto_generated.result[3] result[4] <= mult_add_6cr2:auto_generated.result[4] result[5] <= mult_add_6cr2:auto_generated.result[5] result[6] <= mult_add_6cr2:auto_generated.result[6] result[7] <= mult_add_6cr2:auto_generated.result[7] result[8] <= mult_add_6cr2:auto_generated.result[8] result[9] <= mult_add_6cr2:auto_generated.result[9] result[10] <= mult_add_6cr2:auto_generated.result[10] result[11] <= mult_add_6cr2:auto_generated.result[11] result[12] <= mult_add_6cr2:auto_generated.result[12] result[13] <= mult_add_6cr2:auto_generated.result[13] result[14] <= mult_add_6cr2:auto_generated.result[14] result[15] <= mult_add_6cr2:auto_generated.result[15] rotate => ~NO_FANOUT~ scanina[0] => ~NO_FANOUT~ scanina[1] => ~NO_FANOUT~ scanina[2] => ~NO_FANOUT~ scanina[3] => ~NO_FANOUT~ scanina[4] => ~NO_FANOUT~ scanina[5] => ~NO_FANOUT~ scanina[6] => ~NO_FANOUT~ scanina[7] => ~NO_FANOUT~ scanina[8] => ~NO_FANOUT~ scanina[9] => ~NO_FANOUT~ scanina[10] => ~NO_FANOUT~ scanina[11] => ~NO_FANOUT~ scanina[12] => ~NO_FANOUT~ scanina[13] => ~NO_FANOUT~ scanina[14] => ~NO_FANOUT~ scanina[15] => ~NO_FANOUT~ scaninb[0] => ~NO_FANOUT~ scaninb[1] => ~NO_FANOUT~ scaninb[2] => ~NO_FANOUT~ scaninb[3] => ~NO_FANOUT~ scaninb[4] => ~NO_FANOUT~ scaninb[5] => ~NO_FANOUT~ scaninb[6] => ~NO_FANOUT~ scaninb[7] => ~NO_FANOUT~ scaninb[8] => ~NO_FANOUT~ scaninb[9] => ~NO_FANOUT~ scaninb[10] => ~NO_FANOUT~ scaninb[11] => ~NO_FANOUT~ scaninb[12] => ~NO_FANOUT~ scaninb[13] => ~NO_FANOUT~ scaninb[14] => ~NO_FANOUT~ scaninb[15] => ~NO_FANOUT~ scanouta[0] <= scanouta[0]~15.DB_MAX_OUTPUT_PORT_TYPE scanouta[1] <= scanouta[1]~14.DB_MAX_OUTPUT_PORT_TYPE scanouta[2] <= scanouta[2]~13.DB_MAX_OUTPUT_PORT_TYPE scanouta[3] <= scanouta[3]~12.DB_MAX_OUTPUT_PORT_TYPE scanouta[4] <= scanouta[4]~11.DB_MAX_OUTPUT_PORT_TYPE scanouta[5] <= scanouta[5]~10.DB_MAX_OUTPUT_PORT_TYPE scanouta[6] <= scanouta[6]~9.DB_MAX_OUTPUT_PORT_TYPE scanouta[7] <= scanouta[7]~8.DB_MAX_OUTPUT_PORT_TYPE scanouta[8] <= scanouta[8]~7.DB_MAX_OUTPUT_PORT_TYPE scanouta[9] <= scanouta[9]~6.DB_MAX_OUTPUT_PORT_TYPE scanouta[10] <= scanouta[10]~5.DB_MAX_OUTPUT_PORT_TYPE scanouta[11] <= scanouta[11]~4.DB_MAX_OUTPUT_PORT_TYPE scanouta[12] <= scanouta[12]~3.DB_MAX_OUTPUT_PORT_TYPE scanouta[13] <= scanouta[13]~2.DB_MAX_OUTPUT_PORT_TYPE scanouta[14] <= scanouta[14]~1.DB_MAX_OUTPUT_PORT_TYPE scanouta[15] <= scanouta[15]~0.DB_MAX_OUTPUT_PORT_TYPE scanoutb[0] <= scanoutb[0]~15.DB_MAX_OUTPUT_PORT_TYPE scanoutb[1] <= scanoutb[1]~14.DB_MAX_OUTPUT_PORT_TYPE scanoutb[2] <= scanoutb[2]~13.DB_MAX_OUTPUT_PORT_TYPE scanoutb[3] <= scanoutb[3]~12.DB_MAX_OUTPUT_PORT_TYPE scanoutb[4] <= scanoutb[4]~11.DB_MAX_OUTPUT_PORT_TYPE scanoutb[5] <= scanoutb[5]~10.DB_MAX_OUTPUT_PORT_TYPE scanoutb[6] <= scanoutb[6]~9.DB_MAX_OUTPUT_PORT_TYPE scanoutb[7] <= scanoutb[7]~8.DB_MAX_OUTPUT_PORT_TYPE scanoutb[8] <= scanoutb[8]~7.DB_MAX_OUTPUT_PORT_TYPE scanoutb[9] <= scanoutb[9]~6.DB_MAX_OUTPUT_PORT_TYPE scanoutb[10] <= scanoutb[10]~5.DB_MAX_OUTPUT_PORT_TYPE scanoutb[11] <= scanoutb[11]~4.DB_MAX_OUTPUT_PORT_TYPE scanoutb[12] <= scanoutb[12]~3.DB_MAX_OUTPUT_PORT_TYPE scanoutb[13] <= scanoutb[13]~2.DB_MAX_OUTPUT_PORT_TYPE scanoutb[14] <= scanoutb[14]~1.DB_MAX_OUTPUT_PORT_TYPE scanoutb[15] <= scanoutb[15]~0.DB_MAX_OUTPUT_PORT_TYPE shift_right => ~NO_FANOUT~ signa => ~NO_FANOUT~ signb => ~NO_FANOUT~ sourcea[0] => ~NO_FANOUT~ sourceb[0] => ~NO_FANOUT~ zero_chainout => ~NO_FANOUT~ zero_loopback => ~NO_FANOUT~ |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated aclr0 => ded_mult_2o81:ded_mult1.aclr[0] clock0 => ded_mult_2o81:ded_mult1.clock[0] dataa[0] => ded_mult_2o81:ded_mult1.dataa[0] dataa[1] => ded_mult_2o81:ded_mult1.dataa[1] dataa[2] => ded_mult_2o81:ded_mult1.dataa[2] dataa[3] => ded_mult_2o81:ded_mult1.dataa[3] dataa[4] => ded_mult_2o81:ded_mult1.dataa[4] dataa[5] => ded_mult_2o81:ded_mult1.dataa[5] dataa[6] => ded_mult_2o81:ded_mult1.dataa[6] dataa[7] => ded_mult_2o81:ded_mult1.dataa[7] dataa[8] => ded_mult_2o81:ded_mult1.dataa[8] dataa[9] => ded_mult_2o81:ded_mult1.dataa[9] dataa[10] => ded_mult_2o81:ded_mult1.dataa[10] dataa[11] => ded_mult_2o81:ded_mult1.dataa[11] dataa[12] => ded_mult_2o81:ded_mult1.dataa[12] dataa[13] => ded_mult_2o81:ded_mult1.dataa[13] dataa[14] => ded_mult_2o81:ded_mult1.dataa[14] dataa[15] => ded_mult_2o81:ded_mult1.dataa[15] datab[0] => ded_mult_2o81:ded_mult1.datab[0] datab[1] => ded_mult_2o81:ded_mult1.datab[1] datab[2] => ded_mult_2o81:ded_mult1.datab[2] datab[3] => ded_mult_2o81:ded_mult1.datab[3] datab[4] => ded_mult_2o81:ded_mult1.datab[4] datab[5] => ded_mult_2o81:ded_mult1.datab[5] datab[6] => ded_mult_2o81:ded_mult1.datab[6] datab[7] => ded_mult_2o81:ded_mult1.datab[7] datab[8] => ded_mult_2o81:ded_mult1.datab[8] datab[9] => ded_mult_2o81:ded_mult1.datab[9] datab[10] => ded_mult_2o81:ded_mult1.datab[10] datab[11] => ded_mult_2o81:ded_mult1.datab[11] datab[12] => ded_mult_2o81:ded_mult1.datab[12] datab[13] => ded_mult_2o81:ded_mult1.datab[13] datab[14] => ded_mult_2o81:ded_mult1.datab[14] datab[15] => ded_mult_2o81:ded_mult1.datab[15] result[0] <= pre_result[0].DB_MAX_OUTPUT_PORT_TYPE result[1] <= pre_result[1].DB_MAX_OUTPUT_PORT_TYPE result[2] <= pre_result[2].DB_MAX_OUTPUT_PORT_TYPE result[3] <= pre_result[3].DB_MAX_OUTPUT_PORT_TYPE result[4] <= pre_result[4].DB_MAX_OUTPUT_PORT_TYPE result[5] <= pre_result[5].DB_MAX_OUTPUT_PORT_TYPE result[6] <= pre_result[6].DB_MAX_OUTPUT_PORT_TYPE result[7] <= pre_result[7].DB_MAX_OUTPUT_PORT_TYPE result[8] <= pre_result[8].DB_MAX_OUTPUT_PORT_TYPE result[9] <= pre_result[9].DB_MAX_OUTPUT_PORT_TYPE result[10] <= pre_result[10].DB_MAX_OUTPUT_PORT_TYPE result[11] <= pre_result[11].DB_MAX_OUTPUT_PORT_TYPE result[12] <= pre_result[12].DB_MAX_OUTPUT_PORT_TYPE result[13] <= pre_result[13].DB_MAX_OUTPUT_PORT_TYPE result[14] <= pre_result[14].DB_MAX_OUTPUT_PORT_TYPE result[15] <= pre_result[15].DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1 aclr[0] => mac_mult2.ACLR aclr[0] => mac_out3.ACLR aclr[1] => ~NO_FANOUT~ aclr[2] => ~NO_FANOUT~ aclr[3] => ~NO_FANOUT~ clock[0] => mac_mult2.CLK clock[0] => mac_out3.CLK clock[1] => ~NO_FANOUT~ clock[2] => ~NO_FANOUT~ clock[3] => ~NO_FANOUT~ dataa[0] => mac_mult2.DATAA dataa[1] => mac_mult2.DATAA1 dataa[2] => mac_mult2.DATAA2 dataa[3] => mac_mult2.DATAA3 dataa[4] => mac_mult2.DATAA4 dataa[5] => mac_mult2.DATAA5 dataa[6] => mac_mult2.DATAA6 dataa[7] => mac_mult2.DATAA7 dataa[8] => mac_mult2.DATAA8 dataa[9] => mac_mult2.DATAA9 dataa[10] => mac_mult2.DATAA10 dataa[11] => mac_mult2.DATAA11 dataa[12] => mac_mult2.DATAA12 dataa[13] => mac_mult2.DATAA13 dataa[14] => mac_mult2.DATAA14 dataa[15] => mac_mult2.DATAA15 datab[0] => mac_mult2.DATAB datab[1] => mac_mult2.DATAB1 datab[2] => mac_mult2.DATAB2 datab[3] => mac_mult2.DATAB3 datab[4] => mac_mult2.DATAB4 datab[5] => mac_mult2.DATAB5 datab[6] => mac_mult2.DATAB6 datab[7] => mac_mult2.DATAB7 datab[8] => mac_mult2.DATAB8 datab[9] => mac_mult2.DATAB9 datab[10] => mac_mult2.DATAB10 datab[11] => mac_mult2.DATAB11 datab[12] => mac_mult2.DATAB12 datab[13] => mac_mult2.DATAB13 datab[14] => mac_mult2.DATAB14 datab[15] => mac_mult2.DATAB15 ena[0] => mac_mult2.ENA ena[0] => mac_out3.ENA ena[1] => ~NO_FANOUT~ ena[2] => ~NO_FANOUT~ ena[3] => ~NO_FANOUT~ result[0] <= dffpipe_93c:pre_result.q[0] result[1] <= dffpipe_93c:pre_result.q[1] result[2] <= dffpipe_93c:pre_result.q[2] result[3] <= dffpipe_93c:pre_result.q[3] result[4] <= dffpipe_93c:pre_result.q[4] result[5] <= dffpipe_93c:pre_result.q[5] result[6] <= dffpipe_93c:pre_result.q[6] result[7] <= dffpipe_93c:pre_result.q[7] result[8] <= dffpipe_93c:pre_result.q[8] result[9] <= dffpipe_93c:pre_result.q[9] result[10] <= dffpipe_93c:pre_result.q[10] result[11] <= dffpipe_93c:pre_result.q[11] result[12] <= dffpipe_93c:pre_result.q[12] result[13] <= dffpipe_93c:pre_result.q[13] result[14] <= dffpipe_93c:pre_result.q[14] result[15] <= dffpipe_93c:pre_result.q[15] result[16] <= dffpipe_93c:pre_result.q[16] result[17] <= dffpipe_93c:pre_result.q[17] result[18] <= dffpipe_93c:pre_result.q[18] result[19] <= dffpipe_93c:pre_result.q[19] result[20] <= dffpipe_93c:pre_result.q[20] result[21] <= dffpipe_93c:pre_result.q[21] result[22] <= dffpipe_93c:pre_result.q[22] result[23] <= dffpipe_93c:pre_result.q[23] result[24] <= dffpipe_93c:pre_result.q[24] result[25] <= dffpipe_93c:pre_result.q[25] result[26] <= dffpipe_93c:pre_result.q[26] result[27] <= dffpipe_93c:pre_result.q[27] result[28] <= dffpipe_93c:pre_result.q[28] result[29] <= dffpipe_93c:pre_result.q[29] result[30] <= dffpipe_93c:pre_result.q[30] result[31] <= dffpipe_93c:pre_result.q[31] |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result d[0] => q[0].DATAIN d[1] => q[1].DATAIN d[2] => q[2].DATAIN d[3] => q[3].DATAIN d[4] => q[4].DATAIN d[5] => q[5].DATAIN d[6] => q[6].DATAIN d[7] => q[7].DATAIN d[8] => q[8].DATAIN d[9] => q[9].DATAIN d[10] => q[10].DATAIN d[11] => q[11].DATAIN d[12] => q[12].DATAIN d[13] => q[13].DATAIN d[14] => q[14].DATAIN d[15] => q[15].DATAIN d[16] => q[16].DATAIN d[17] => q[17].DATAIN d[18] => q[18].DATAIN d[19] => q[19].DATAIN d[20] => q[20].DATAIN d[21] => q[21].DATAIN d[22] => q[22].DATAIN d[23] => q[23].DATAIN d[24] => q[24].DATAIN d[25] => q[25].DATAIN d[26] => q[26].DATAIN d[27] => q[27].DATAIN d[28] => q[28].DATAIN d[29] => q[29].DATAIN d[30] => q[30].DATAIN d[31] => q[31].DATAIN q[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE q[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE q[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE q[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE q[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE q[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE q[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE q[7] <= d[7].DB_MAX_OUTPUT_PORT_TYPE q[8] <= d[8].DB_MAX_OUTPUT_PORT_TYPE q[9] <= d[9].DB_MAX_OUTPUT_PORT_TYPE q[10] <= d[10].DB_MAX_OUTPUT_PORT_TYPE q[11] <= d[11].DB_MAX_OUTPUT_PORT_TYPE q[12] <= d[12].DB_MAX_OUTPUT_PORT_TYPE q[13] <= d[13].DB_MAX_OUTPUT_PORT_TYPE q[14] <= d[14].DB_MAX_OUTPUT_PORT_TYPE q[15] <= d[15].DB_MAX_OUTPUT_PORT_TYPE q[16] <= d[16].DB_MAX_OUTPUT_PORT_TYPE q[17] <= d[17].DB_MAX_OUTPUT_PORT_TYPE q[18] <= d[18].DB_MAX_OUTPUT_PORT_TYPE q[19] <= d[19].DB_MAX_OUTPUT_PORT_TYPE q[20] <= d[20].DB_MAX_OUTPUT_PORT_TYPE q[21] <= d[21].DB_MAX_OUTPUT_PORT_TYPE q[22] <= d[22].DB_MAX_OUTPUT_PORT_TYPE q[23] <= d[23].DB_MAX_OUTPUT_PORT_TYPE q[24] <= d[24].DB_MAX_OUTPUT_PORT_TYPE q[25] <= d[25].DB_MAX_OUTPUT_PORT_TYPE q[26] <= d[26].DB_MAX_OUTPUT_PORT_TYPE q[27] <= d[27].DB_MAX_OUTPUT_PORT_TYPE q[28] <= d[28].DB_MAX_OUTPUT_PORT_TYPE q[29] <= d[29].DB_MAX_OUTPUT_PORT_TYPE q[30] <= d[30].DB_MAX_OUTPUT_PORT_TYPE q[31] <= d[31].DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci A_cmp_result => A_cmp_result~0.IN1 A_ctrl_exception => A_ctrl_exception~0.IN1 A_ctrl_ld => A_ctrl_ld~0.IN1 A_ctrl_st => A_ctrl_st~0.IN1 A_en => A_en~0.IN2 A_mem_baddr[0] => A_mem_baddr[0]~23.IN1 A_mem_baddr[1] => A_mem_baddr[1]~22.IN1 A_mem_baddr[2] => A_mem_baddr[2]~21.IN1 A_mem_baddr[3] => A_mem_baddr[3]~20.IN1 A_mem_baddr[4] => A_mem_baddr[4]~19.IN1 A_mem_baddr[5] => A_mem_baddr[5]~18.IN1 A_mem_baddr[6] => A_mem_baddr[6]~17.IN1 A_mem_baddr[7] => A_mem_baddr[7]~16.IN1 A_mem_baddr[8] => A_mem_baddr[8]~15.IN1 A_mem_baddr[9] => A_mem_baddr[9]~14.IN1 A_mem_baddr[10] => A_mem_baddr[10]~13.IN1 A_mem_baddr[11] => A_mem_baddr[11]~12.IN1 A_mem_baddr[12] => A_mem_baddr[12]~11.IN1 A_mem_baddr[13] => A_mem_baddr[13]~10.IN1 A_mem_baddr[14] => A_mem_baddr[14]~9.IN1 A_mem_baddr[15] => A_mem_baddr[15]~8.IN1 A_mem_baddr[16] => A_mem_baddr[16]~7.IN1 A_mem_baddr[17] => A_mem_baddr[17]~6.IN1 A_mem_baddr[18] => A_mem_baddr[18]~5.IN1 A_mem_baddr[19] => A_mem_baddr[19]~4.IN1 A_mem_baddr[20] => A_mem_baddr[20]~3.IN1 A_mem_baddr[21] => A_mem_baddr[21]~2.IN1 A_mem_baddr[22] => A_mem_baddr[22]~1.IN1 A_mem_baddr[23] => A_mem_baddr[23]~0.IN1 A_op_beq => A_op_beq~0.IN1 A_op_bge => A_op_bge~0.IN1 A_op_bgeu => A_op_bgeu~0.IN1 A_op_blt => A_op_blt~0.IN1 A_op_bltu => A_op_bltu~0.IN1 A_op_bne => A_op_bne~0.IN1 A_op_br => A_op_br~0.IN1 A_op_bret => A_op_bret~0.IN1 A_op_call => A_op_call~0.IN1 A_op_callr => A_op_callr~0.IN1 A_op_eret => A_op_eret~0.IN1 A_op_jmp => A_op_jmp~0.IN1 A_op_ret => A_op_ret~0.IN1 A_pcb[0] => A_pcb[0]~23.IN1 A_pcb[1] => A_pcb[1]~22.IN1 A_pcb[2] => A_pcb[2]~21.IN1 A_pcb[3] => A_pcb[3]~20.IN1 A_pcb[4] => A_pcb[4]~19.IN1 A_pcb[5] => A_pcb[5]~18.IN1 A_pcb[6] => A_pcb[6]~17.IN1 A_pcb[7] => A_pcb[7]~16.IN1 A_pcb[8] => A_pcb[8]~15.IN1 A_pcb[9] => A_pcb[9]~14.IN1 A_pcb[10] => A_pcb[10]~13.IN1 A_pcb[11] => A_pcb[11]~12.IN1 A_pcb[12] => A_pcb[12]~11.IN1 A_pcb[13] => A_pcb[13]~10.IN1 A_pcb[14] => A_pcb[14]~9.IN1 A_pcb[15] => A_pcb[15]~8.IN1 A_pcb[16] => A_pcb[16]~7.IN1 A_pcb[17] => A_pcb[17]~6.IN1 A_pcb[18] => A_pcb[18]~5.IN1 A_pcb[19] => A_pcb[19]~4.IN1 A_pcb[20] => A_pcb[20]~3.IN1 A_pcb[21] => A_pcb[21]~2.IN1 A_pcb[22] => A_pcb[22]~1.IN1 A_pcb[23] => A_pcb[23]~0.IN1 A_st_data[0] => A_st_data[0]~31.IN1 A_st_data[1] => A_st_data[1]~30.IN1 A_st_data[2] => A_st_data[2]~29.IN1 A_st_data[3] => A_st_data[3]~28.IN1 A_st_data[4] => A_st_data[4]~27.IN1 A_st_data[5] => A_st_data[5]~26.IN1 A_st_data[6] => A_st_data[6]~25.IN1 A_st_data[7] => A_st_data[7]~24.IN1 A_st_data[8] => A_st_data[8]~23.IN1 A_st_data[9] => A_st_data[9]~22.IN1 A_st_data[10] => A_st_data[10]~21.IN1 A_st_data[11] => A_st_data[11]~20.IN1 A_st_data[12] => A_st_data[12]~19.IN1 A_st_data[13] => A_st_data[13]~18.IN1 A_st_data[14] => A_st_data[14]~17.IN1 A_st_data[15] => A_st_data[15]~16.IN1 A_st_data[16] => A_st_data[16]~15.IN1 A_st_data[17] => A_st_data[17]~14.IN1 A_st_data[18] => A_st_data[18]~13.IN1 A_st_data[19] => A_st_data[19]~12.IN1 A_st_data[20] => A_st_data[20]~11.IN1 A_st_data[21] => A_st_data[21]~10.IN1 A_st_data[22] => A_st_data[22]~9.IN1 A_st_data[23] => A_st_data[23]~8.IN1 A_st_data[24] => A_st_data[24]~7.IN1 A_st_data[25] => A_st_data[25]~6.IN1 A_st_data[26] => A_st_data[26]~5.IN1 A_st_data[27] => A_st_data[27]~4.IN1 A_st_data[28] => A_st_data[28]~3.IN1 A_st_data[29] => A_st_data[29]~2.IN1 A_st_data[30] => A_st_data[30]~1.IN1 A_st_data[31] => A_st_data[31]~0.IN1 A_valid => A_valid~0.IN2 A_wr_data_filtered[0] => A_wr_data_filtered[0]~31.IN2 A_wr_data_filtered[1] => A_wr_data_filtered[1]~30.IN2 A_wr_data_filtered[2] => A_wr_data_filtered[2]~29.IN2 A_wr_data_filtered[3] => A_wr_data_filtered[3]~28.IN2 A_wr_data_filtered[4] => A_wr_data_filtered[4]~27.IN2 A_wr_data_filtered[5] => A_wr_data_filtered[5]~26.IN2 A_wr_data_filtered[6] => A_wr_data_filtered[6]~25.IN2 A_wr_data_filtered[7] => A_wr_data_filtered[7]~24.IN2 A_wr_data_filtered[8] => A_wr_data_filtered[8]~23.IN2 A_wr_data_filtered[9] => A_wr_data_filtered[9]~22.IN2 A_wr_data_filtered[10] => A_wr_data_filtered[10]~21.IN2 A_wr_data_filtered[11] => A_wr_data_filtered[11]~20.IN2 A_wr_data_filtered[12] => A_wr_data_filtered[12]~19.IN2 A_wr_data_filtered[13] => A_wr_data_filtered[13]~18.IN2 A_wr_data_filtered[14] => A_wr_data_filtered[14]~17.IN2 A_wr_data_filtered[15] => A_wr_data_filtered[15]~16.IN2 A_wr_data_filtered[16] => A_wr_data_filtered[16]~15.IN2 A_wr_data_filtered[17] => A_wr_data_filtered[17]~14.IN2 A_wr_data_filtered[18] => A_wr_data_filtered[18]~13.IN2 A_wr_data_filtered[19] => A_wr_data_filtered[19]~12.IN2 A_wr_data_filtered[20] => A_wr_data_filtered[20]~11.IN2 A_wr_data_filtered[21] => A_wr_data_filtered[21]~10.IN2 A_wr_data_filtered[22] => A_wr_data_filtered[22]~9.IN2 A_wr_data_filtered[23] => A_wr_data_filtered[23]~8.IN2 A_wr_data_filtered[24] => A_wr_data_filtered[24]~7.IN2 A_wr_data_filtered[25] => A_wr_data_filtered[25]~6.IN2 A_wr_data_filtered[26] => A_wr_data_filtered[26]~5.IN2 A_wr_data_filtered[27] => A_wr_data_filtered[27]~4.IN2 A_wr_data_filtered[28] => A_wr_data_filtered[28]~3.IN2 A_wr_data_filtered[29] => A_wr_data_filtered[29]~2.IN2 A_wr_data_filtered[30] => A_wr_data_filtered[30]~1.IN2 A_wr_data_filtered[31] => A_wr_data_filtered[31]~0.IN2 D_en => D_en~0.IN1 E_en => E_en~0.IN1 E_valid => E_valid~0.IN1 F_pc[0] => F_pc[0]~21.IN1 F_pc[1] => F_pc[1]~20.IN1 F_pc[2] => F_pc[2]~19.IN1 F_pc[3] => F_pc[3]~18.IN1 F_pc[4] => F_pc[4]~17.IN1 F_pc[5] => F_pc[5]~16.IN1 F_pc[6] => F_pc[6]~15.IN1 F_pc[7] => F_pc[7]~14.IN1 F_pc[8] => F_pc[8]~13.IN1 F_pc[9] => F_pc[9]~12.IN1 F_pc[10] => F_pc[10]~11.IN1 F_pc[11] => F_pc[11]~10.IN1 F_pc[12] => F_pc[12]~9.IN1 F_pc[13] => F_pc[13]~8.IN1 F_pc[14] => F_pc[14]~7.IN1 F_pc[15] => F_pc[15]~6.IN1 F_pc[16] => F_pc[16]~5.IN1 F_pc[17] => F_pc[17]~4.IN1 F_pc[18] => F_pc[18]~3.IN1 F_pc[19] => F_pc[19]~2.IN1 F_pc[20] => F_pc[20]~1.IN1 F_pc[21] => F_pc[21]~0.IN1 M_en => M_en~0.IN1 address[0] => address[0]~8.IN2 address[1] => address[1]~7.IN2 address[2] => address[2]~6.IN2 address[3] => address[3]~5.IN2 address[4] => address[4]~4.IN2 address[5] => address[5]~3.IN2 address[6] => address[6]~2.IN2 address[7] => address[7]~1.IN2 address[8] => address[8]~0.IN2 begintransfer => begintransfer~0.IN1 byteenable[0] => byteenable[0]~3.IN1 byteenable[1] => byteenable[1]~2.IN1 byteenable[2] => byteenable[2]~1.IN1 byteenable[3] => byteenable[3]~0.IN1 chipselect => chipselect~0.IN2 clk => clk~0.IN12 debugaccess => debugaccess~0.IN2 hbreak_enabled => hbreak_enabled~0.IN1 reset => reset~0.IN1 reset_n => reset_n~0.IN8 write => write~0.IN2 writedata[0] => writedata[0]~31.IN2 writedata[1] => writedata[1]~30.IN2 writedata[2] => writedata[2]~29.IN2 writedata[3] => writedata[3]~28.IN2 writedata[4] => writedata[4]~27.IN2 writedata[5] => writedata[5]~26.IN2 writedata[6] => writedata[6]~25.IN2 writedata[7] => writedata[7]~24.IN2 writedata[8] => writedata[8]~23.IN2 writedata[9] => writedata[9]~22.IN2 writedata[10] => writedata[10]~21.IN2 writedata[11] => writedata[11]~20.IN2 writedata[12] => writedata[12]~19.IN2 writedata[13] => writedata[13]~18.IN2 writedata[14] => writedata[14]~17.IN2 writedata[15] => writedata[15]~16.IN2 writedata[16] => writedata[16]~15.IN2 writedata[17] => writedata[17]~14.IN2 writedata[18] => writedata[18]~13.IN2 writedata[19] => writedata[19]~12.IN2 writedata[20] => writedata[20]~11.IN2 writedata[21] => writedata[21]~10.IN2 writedata[22] => writedata[22]~9.IN2 writedata[23] => writedata[23]~8.IN2 writedata[24] => writedata[24]~7.IN2 writedata[25] => writedata[25]~6.IN2 writedata[26] => writedata[26]~5.IN2 writedata[27] => writedata[27]~4.IN2 writedata[28] => writedata[28]~3.IN2 writedata[29] => writedata[29]~2.IN2 writedata[30] => writedata[30]~1.IN2 writedata[31] => writedata[31]~0.IN2 jtag_debug_module_debugaccess_to_roms <= debugack.DB_MAX_OUTPUT_PORT_TYPE oci_hbreak_req <= cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug.oci_hbreak_req oci_ienable[0] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[1] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[2] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[3] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[4] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[5] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[6] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[7] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[8] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[9] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[10] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[11] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[12] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[13] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[14] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[15] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[16] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[17] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[18] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[19] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[20] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[21] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[22] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[23] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[24] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[25] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[26] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[27] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[28] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[29] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[30] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_ienable[31] <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_ienable oci_single_step_mode <= cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg.oci_single_step_mode readdata[0] <= readdata~31.DB_MAX_OUTPUT_PORT_TYPE readdata[1] <= readdata~30.DB_MAX_OUTPUT_PORT_TYPE readdata[2] <= readdata~29.DB_MAX_OUTPUT_PORT_TYPE readdata[3] <= readdata~28.DB_MAX_OUTPUT_PORT_TYPE readdata[4] <= readdata~27.DB_MAX_OUTPUT_PORT_TYPE readdata[5] <= readdata~26.DB_MAX_OUTPUT_PORT_TYPE readdata[6] <= readdata~25.DB_MAX_OUTPUT_PORT_TYPE readdata[7] <= readdata~24.DB_MAX_OUTPUT_PORT_TYPE readdata[8] <= readdata~23.DB_MAX_OUTPUT_PORT_TYPE readdata[9] <= readdata~22.DB_MAX_OUTPUT_PORT_TYPE readdata[10] <= readdata~21.DB_MAX_OUTPUT_PORT_TYPE readdata[11] <= readdata~20.DB_MAX_OUTPUT_PORT_TYPE readdata[12] <= readdata~19.DB_MAX_OUTPUT_PORT_TYPE readdata[13] <= readdata~18.DB_MAX_OUTPUT_PORT_TYPE readdata[14] <= readdata~17.DB_MAX_OUTPUT_PORT_TYPE readdata[15] <= readdata~16.DB_MAX_OUTPUT_PORT_TYPE readdata[16] <= readdata~15.DB_MAX_OUTPUT_PORT_TYPE readdata[17] <= readdata~14.DB_MAX_OUTPUT_PORT_TYPE readdata[18] <= readdata~13.DB_MAX_OUTPUT_PORT_TYPE readdata[19] <= readdata~12.DB_MAX_OUTPUT_PORT_TYPE readdata[20] <= readdata~11.DB_MAX_OUTPUT_PORT_TYPE readdata[21] <= readdata~10.DB_MAX_OUTPUT_PORT_TYPE readdata[22] <= readdata~9.DB_MAX_OUTPUT_PORT_TYPE readdata[23] <= readdata~8.DB_MAX_OUTPUT_PORT_TYPE readdata[24] <= readdata~7.DB_MAX_OUTPUT_PORT_TYPE readdata[25] <= readdata~6.DB_MAX_OUTPUT_PORT_TYPE readdata[26] <= readdata~5.DB_MAX_OUTPUT_PORT_TYPE readdata[27] <= readdata~4.DB_MAX_OUTPUT_PORT_TYPE readdata[28] <= readdata~3.DB_MAX_OUTPUT_PORT_TYPE readdata[29] <= readdata~2.DB_MAX_OUTPUT_PORT_TYPE readdata[30] <= readdata~1.DB_MAX_OUTPUT_PORT_TYPE readdata[31] <= readdata~0.DB_MAX_OUTPUT_PORT_TYPE resetrequest <= resetrequest~0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug clk => probepresent.CLK clk => resetrequest~reg0.CLK clk => jtag_break.CLK clk => resetlatch~reg0.CLK clk => monitor_ready~reg0.CLK clk => monitor_error~reg0.CLK clk => monitor_go~reg0.CLK dbrk_break => oci_hbreak_req~0.IN1 debugreq => oci_hbreak_req~2.IN0 debugreq => always0~0.IN0 hbreak_enabled => always0~0.IN1 hbreak_enabled => debugack.DATAIN jdo[0] => ~NO_FANOUT~ jdo[1] => ~NO_FANOUT~ jdo[2] => ~NO_FANOUT~ jdo[3] => ~NO_FANOUT~ jdo[4] => ~NO_FANOUT~ jdo[5] => ~NO_FANOUT~ jdo[6] => ~NO_FANOUT~ jdo[7] => ~NO_FANOUT~ jdo[8] => ~NO_FANOUT~ jdo[9] => ~NO_FANOUT~ jdo[10] => ~NO_FANOUT~ jdo[11] => ~NO_FANOUT~ jdo[12] => ~NO_FANOUT~ jdo[13] => ~NO_FANOUT~ jdo[14] => ~NO_FANOUT~ jdo[15] => ~NO_FANOUT~ jdo[16] => ~NO_FANOUT~ jdo[17] => ~NO_FANOUT~ jdo[18] => probepresent~0.OUTPUTSELECT jdo[19] => probepresent~1.OUTPUTSELECT jdo[20] => jtag_break~0.OUTPUTSELECT jdo[21] => jtag_break~1.OUTPUTSELECT jdo[22] => resetrequest~reg0.DATAIN jdo[23] => monitor_go~0.OUTPUTSELECT jdo[24] => resetlatch~0.OUTPUTSELECT jdo[25] => monitor_error~0.OUTPUTSELECT jdo[25] => monitor_ready~0.OUTPUTSELECT jdo[26] => ~NO_FANOUT~ jdo[27] => ~NO_FANOUT~ jdo[28] => ~NO_FANOUT~ jdo[29] => ~NO_FANOUT~ jdo[30] => ~NO_FANOUT~ jdo[31] => ~NO_FANOUT~ jdo[32] => ~NO_FANOUT~ jdo[33] => ~NO_FANOUT~ jdo[34] => ~NO_FANOUT~ jdo[35] => ~NO_FANOUT~ jdo[36] => ~NO_FANOUT~ jdo[37] => ~NO_FANOUT~ jrst_n => probepresent.ACLR jrst_n => resetrequest~reg0.ACLR jrst_n => jtag_break.ACLR jrst_n => resetlatch~reg0.ENA ocireg_ers => monitor_error~1.OUTPUTSELECT ocireg_mrs => monitor_ready~1.OUTPUTSELECT reset => resetlatch~1.OUTPUTSELECT reset => jtag_break~3.OUTPUTSELECT st_ready_test_idle => monitor_go~1.OUTPUTSELECT take_action_ocimem_a => monitor_go~3.OUTPUTSELECT take_action_ocimem_a => monitor_error~3.OUTPUTSELECT take_action_ocimem_a => monitor_ready~3.OUTPUTSELECT take_action_ocimem_a => resetlatch~2.OUTPUTSELECT take_action_ocimem_a => jtag_break~4.OUTPUTSELECT take_action_ocimem_a => probepresent.ENA take_action_ocimem_a => resetrequest~reg0.ENA take_action_ocireg => monitor_go~2.OUTPUTSELECT take_action_ocireg => monitor_error~2.OUTPUTSELECT take_action_ocireg => monitor_ready~2.OUTPUTSELECT xbrk_break => oci_hbreak_req~1.IN1 debugack <= hbreak_enabled.DB_MAX_OUTPUT_PORT_TYPE monitor_error <= monitor_error~reg0.DB_MAX_OUTPUT_PORT_TYPE monitor_go <= monitor_go~reg0.DB_MAX_OUTPUT_PORT_TYPE monitor_ready <= monitor_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_hbreak_req <= oci_hbreak_req~2.DB_MAX_OUTPUT_PORT_TYPE resetlatch <= resetlatch~reg0.DB_MAX_OUTPUT_PORT_TYPE resetrequest <= resetrequest~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem address[0] => address[0]~7.IN1 address[1] => address[1]~6.IN1 address[2] => address[2]~5.IN1 address[3] => address[3]~4.IN1 address[4] => address[4]~3.IN1 address[5] => address[5]~2.IN1 address[6] => address[6]~1.IN1 address[7] => address[7]~0.IN1 address[8] => comb~2.IN1 begintransfer => avalon.IN1 byteenable[0] => byteenable[0]~3.IN1 byteenable[1] => byteenable[1]~2.IN1 byteenable[2] => byteenable[2]~1.IN1 byteenable[3] => byteenable[3]~0.IN1 chipselect => comb~0.IN0 clk => clk~0.IN2 debugaccess => comb~1.IN1 jdo[0] => ~NO_FANOUT~ jdo[1] => ~NO_FANOUT~ jdo[2] => ~NO_FANOUT~ jdo[3] => MonDReg~127.DATAB jdo[4] => MonDReg~126.DATAB jdo[5] => MonDReg~125.DATAB jdo[6] => MonDReg~124.DATAB jdo[7] => MonDReg~123.DATAB jdo[8] => MonDReg~122.DATAB jdo[9] => MonDReg~121.DATAB jdo[10] => MonDReg~120.DATAB jdo[11] => MonDReg~119.DATAB jdo[12] => MonDReg~118.DATAB jdo[13] => MonDReg~117.DATAB jdo[14] => MonDReg~116.DATAB jdo[15] => MonDReg~115.DATAB jdo[16] => MonDReg~114.DATAB jdo[17] => MonAReg~17.DATAB jdo[17] => MonDReg~113.DATAB jdo[18] => MonDReg~112.DATAB jdo[19] => MonDReg~111.DATAB jdo[20] => MonDReg~110.DATAB jdo[21] => MonDReg~109.DATAB jdo[22] => MonDReg~108.DATAB jdo[23] => MonDReg~107.DATAB jdo[24] => MonDReg~106.DATAB jdo[25] => MonDReg~105.DATAB jdo[26] => MonAReg~25.DATAB jdo[26] => MonDReg~104.DATAB jdo[27] => MonAReg~24.DATAB jdo[27] => MonDReg~103.DATAB jdo[28] => MonAReg~23.DATAB jdo[28] => MonDReg~102.DATAB jdo[29] => MonAReg~22.DATAB jdo[29] => MonDReg~101.DATAB jdo[30] => MonAReg~21.DATAB jdo[30] => MonDReg~100.DATAB jdo[31] => MonAReg~20.DATAB jdo[31] => MonDReg~99.DATAB jdo[32] => MonAReg~19.DATAB jdo[32] => MonDReg~98.DATAB jdo[33] => MonAReg~18.DATAB jdo[33] => MonDReg~97.DATAB jdo[34] => MonDReg~96.DATAB jdo[35] => ~NO_FANOUT~ jdo[36] => ~NO_FANOUT~ jdo[37] => ~NO_FANOUT~ jrst_n => MonWr.ACLR jrst_n => MonRd.ACLR jrst_n => MonRd1.ACLR jrst_n => MonAReg[10].ACLR jrst_n => MonAReg[9].ACLR jrst_n => MonAReg[8].ACLR jrst_n => MonAReg[7].ACLR jrst_n => MonAReg[6].ACLR jrst_n => MonAReg[5].ACLR jrst_n => MonAReg[4].ACLR jrst_n => MonAReg[3].ACLR jrst_n => MonAReg[2].ACLR jrst_n => MonDReg[31]~reg0.ACLR jrst_n => MonDReg[30]~reg0.ACLR jrst_n => MonDReg[29]~reg0.ACLR jrst_n => MonDReg[28]~reg0.ACLR jrst_n => MonDReg[27]~reg0.ACLR jrst_n => MonDReg[26]~reg0.ACLR jrst_n => MonDReg[25]~reg0.ACLR jrst_n => MonDReg[24]~reg0.ACLR jrst_n => MonDReg[23]~reg0.ACLR jrst_n => MonDReg[22]~reg0.ACLR jrst_n => MonDReg[21]~reg0.ACLR jrst_n => MonDReg[20]~reg0.ACLR jrst_n => MonDReg[19]~reg0.ACLR jrst_n => MonDReg[18]~reg0.ACLR jrst_n => MonDReg[17]~reg0.ACLR jrst_n => MonDReg[16]~reg0.ACLR jrst_n => MonDReg[15]~reg0.ACLR jrst_n => MonDReg[14]~reg0.ACLR jrst_n => MonDReg[13]~reg0.ACLR jrst_n => MonDReg[12]~reg0.ACLR jrst_n => MonDReg[11]~reg0.ACLR jrst_n => MonDReg[10]~reg0.ACLR jrst_n => MonDReg[9]~reg0.ACLR jrst_n => MonDReg[8]~reg0.ACLR jrst_n => MonDReg[7]~reg0.ACLR jrst_n => MonDReg[6]~reg0.ACLR jrst_n => MonDReg[5]~reg0.ACLR jrst_n => MonDReg[4]~reg0.ACLR jrst_n => MonDReg[3]~reg0.ACLR jrst_n => MonDReg[2]~reg0.ACLR jrst_n => MonDReg[1]~reg0.ACLR jrst_n => MonDReg[0]~reg0.ACLR resetrequest => avalon.IN0 take_action_ocimem_a => MonWr~2.OUTPUTSELECT take_action_ocimem_a => MonDReg~159.OUTPUTSELECT take_action_ocimem_a => MonDReg~158.OUTPUTSELECT take_action_ocimem_a => MonDReg~157.OUTPUTSELECT take_action_ocimem_a => MonDReg~156.OUTPUTSELECT take_action_ocimem_a => MonDReg~155.OUTPUTSELECT take_action_ocimem_a => MonDReg~154.OUTPUTSELECT take_action_ocimem_a => MonDReg~153.OUTPUTSELECT take_action_ocimem_a => MonDReg~152.OUTPUTSELECT take_action_ocimem_a => MonDReg~151.OUTPUTSELECT take_action_ocimem_a => MonDReg~150.OUTPUTSELECT take_action_ocimem_a => MonDReg~149.OUTPUTSELECT take_action_ocimem_a => MonDReg~148.OUTPUTSELECT take_action_ocimem_a => MonDReg~147.OUTPUTSELECT take_action_ocimem_a => MonDReg~146.OUTPUTSELECT take_action_ocimem_a => MonDReg~145.OUTPUTSELECT take_action_ocimem_a => MonDReg~144.OUTPUTSELECT take_action_ocimem_a => MonDReg~143.OUTPUTSELECT take_action_ocimem_a => MonDReg~142.OUTPUTSELECT take_action_ocimem_a => MonDReg~141.OUTPUTSELECT take_action_ocimem_a => MonDReg~140.OUTPUTSELECT take_action_ocimem_a => MonDReg~139.OUTPUTSELECT take_action_ocimem_a => MonDReg~138.OUTPUTSELECT take_action_ocimem_a => MonDReg~137.OUTPUTSELECT take_action_ocimem_a => MonDReg~136.OUTPUTSELECT take_action_ocimem_a => MonDReg~135.OUTPUTSELECT take_action_ocimem_a => MonDReg~134.OUTPUTSELECT take_action_ocimem_a => MonDReg~133.OUTPUTSELECT take_action_ocimem_a => MonDReg~132.OUTPUTSELECT take_action_ocimem_a => MonDReg~131.OUTPUTSELECT take_action_ocimem_a => MonDReg~130.OUTPUTSELECT take_action_ocimem_a => MonDReg~129.OUTPUTSELECT take_action_ocimem_a => MonDReg~128.OUTPUTSELECT take_action_ocimem_a => MonRd~2.OUTPUTSELECT take_action_ocimem_a => MonAReg~25.OUTPUTSELECT take_action_ocimem_a => MonAReg~24.OUTPUTSELECT take_action_ocimem_a => MonAReg~23.OUTPUTSELECT take_action_ocimem_a => MonAReg~22.OUTPUTSELECT take_action_ocimem_a => MonAReg~21.OUTPUTSELECT take_action_ocimem_a => MonAReg~20.OUTPUTSELECT take_action_ocimem_a => MonAReg~19.OUTPUTSELECT take_action_ocimem_a => MonAReg~18.OUTPUTSELECT take_action_ocimem_a => MonAReg~17.OUTPUTSELECT take_action_ocimem_b => MonRd~1.OUTPUTSELECT take_action_ocimem_b => MonWr~1.OUTPUTSELECT take_action_ocimem_b => MonDReg~127.OUTPUTSELECT take_action_ocimem_b => MonDReg~126.OUTPUTSELECT take_action_ocimem_b => MonDReg~125.OUTPUTSELECT take_action_ocimem_b => MonDReg~124.OUTPUTSELECT take_action_ocimem_b => MonDReg~123.OUTPUTSELECT take_action_ocimem_b => MonDReg~122.OUTPUTSELECT take_action_ocimem_b => MonDReg~121.OUTPUTSELECT take_action_ocimem_b => MonDReg~120.OUTPUTSELECT take_action_ocimem_b => MonDReg~119.OUTPUTSELECT take_action_ocimem_b => MonDReg~118.OUTPUTSELECT take_action_ocimem_b => MonDReg~117.OUTPUTSELECT take_action_ocimem_b => MonDReg~116.OUTPUTSELECT take_action_ocimem_b => MonDReg~115.OUTPUTSELECT take_action_ocimem_b => MonDReg~114.OUTPUTSELECT take_action_ocimem_b => MonDReg~113.OUTPUTSELECT take_action_ocimem_b => MonDReg~112.OUTPUTSELECT take_action_ocimem_b => MonDReg~111.OUTPUTSELECT take_action_ocimem_b => MonDReg~110.OUTPUTSELECT take_action_ocimem_b => MonDReg~109.OUTPUTSELECT take_action_ocimem_b => MonDReg~108.OUTPUTSELECT take_action_ocimem_b => MonDReg~107.OUTPUTSELECT take_action_ocimem_b => MonDReg~106.OUTPUTSELECT take_action_ocimem_b => MonDReg~105.OUTPUTSELECT take_action_ocimem_b => MonDReg~104.OUTPUTSELECT take_action_ocimem_b => MonDReg~103.OUTPUTSELECT take_action_ocimem_b => MonDReg~102.OUTPUTSELECT take_action_ocimem_b => MonDReg~101.OUTPUTSELECT take_action_ocimem_b => MonDReg~100.OUTPUTSELECT take_action_ocimem_b => MonDReg~99.OUTPUTSELECT take_action_ocimem_b => MonDReg~98.OUTPUTSELECT take_action_ocimem_b => MonDReg~97.OUTPUTSELECT take_action_ocimem_b => MonDReg~96.OUTPUTSELECT take_action_ocimem_b => MonAReg~16.OUTPUTSELECT take_action_ocimem_b => MonAReg~15.OUTPUTSELECT take_action_ocimem_b => MonAReg~14.OUTPUTSELECT take_action_ocimem_b => MonAReg~13.OUTPUTSELECT take_action_ocimem_b => MonAReg~12.OUTPUTSELECT take_action_ocimem_b => MonAReg~11.OUTPUTSELECT take_action_ocimem_b => MonAReg~10.OUTPUTSELECT take_action_ocimem_b => MonAReg~9.OUTPUTSELECT take_action_ocimem_b => MonAReg~8.OUTPUTSELECT take_no_action_ocimem_a => MonWr~3.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~191.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~190.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~189.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~188.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~187.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~186.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~185.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~184.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~183.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~182.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~181.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~180.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~179.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~178.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~177.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~176.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~175.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~174.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~173.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~172.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~171.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~170.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~169.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~168.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~167.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~166.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~165.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~164.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~163.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~162.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~161.OUTPUTSELECT take_no_action_ocimem_a => MonDReg~160.OUTPUTSELECT take_no_action_ocimem_a => MonRd~3.OUTPUTSELECT take_no_action_ocimem_a => MonAReg~34.OUTPUTSELECT take_no_action_ocimem_a => MonAReg~33.OUTPUTSELECT take_no_action_ocimem_a => MonAReg~32.OUTPUTSELECT take_no_action_ocimem_a => MonAReg~31.OUTPUTSELECT take_no_action_ocimem_a => MonAReg~30.OUTPUTSELECT take_no_action_ocimem_a => MonAReg~29.OUTPUTSELECT take_no_action_ocimem_a => MonAReg~28.OUTPUTSELECT take_no_action_ocimem_a => MonAReg~27.OUTPUTSELECT take_no_action_ocimem_a => MonAReg~26.OUTPUTSELECT write => comb~0.IN1 writedata[0] => writedata[0]~31.IN1 writedata[1] => writedata[1]~30.IN1 writedata[2] => writedata[2]~29.IN1 writedata[3] => writedata[3]~28.IN1 writedata[4] => writedata[4]~27.IN1 writedata[5] => writedata[5]~26.IN1 writedata[6] => writedata[6]~25.IN1 writedata[7] => writedata[7]~24.IN1 writedata[8] => writedata[8]~23.IN1 writedata[9] => writedata[9]~22.IN1 writedata[10] => writedata[10]~21.IN1 writedata[11] => writedata[11]~20.IN1 writedata[12] => writedata[12]~19.IN1 writedata[13] => writedata[13]~18.IN1 writedata[14] => writedata[14]~17.IN1 writedata[15] => writedata[15]~16.IN1 writedata[16] => writedata[16]~15.IN1 writedata[17] => writedata[17]~14.IN1 writedata[18] => writedata[18]~13.IN1 writedata[19] => writedata[19]~12.IN1 writedata[20] => writedata[20]~11.IN1 writedata[21] => writedata[21]~10.IN1 writedata[22] => writedata[22]~9.IN1 writedata[23] => writedata[23]~8.IN1 writedata[24] => writedata[24]~7.IN1 writedata[25] => writedata[25]~6.IN1 writedata[26] => writedata[26]~5.IN1 writedata[27] => writedata[27]~4.IN1 writedata[28] => writedata[28]~3.IN1 writedata[29] => writedata[29]~2.IN1 writedata[30] => writedata[30]~1.IN1 writedata[31] => writedata[31]~0.IN1 MonDReg[0] <= MonDReg[0]~31.DB_MAX_OUTPUT_PORT_TYPE MonDReg[1] <= MonDReg[1]~30.DB_MAX_OUTPUT_PORT_TYPE MonDReg[2] <= MonDReg[2]~29.DB_MAX_OUTPUT_PORT_TYPE MonDReg[3] <= MonDReg[3]~28.DB_MAX_OUTPUT_PORT_TYPE MonDReg[4] <= MonDReg[4]~27.DB_MAX_OUTPUT_PORT_TYPE MonDReg[5] <= MonDReg[5]~26.DB_MAX_OUTPUT_PORT_TYPE MonDReg[6] <= MonDReg[6]~25.DB_MAX_OUTPUT_PORT_TYPE MonDReg[7] <= MonDReg[7]~24.DB_MAX_OUTPUT_PORT_TYPE MonDReg[8] <= MonDReg[8]~23.DB_MAX_OUTPUT_PORT_TYPE MonDReg[9] <= MonDReg[9]~22.DB_MAX_OUTPUT_PORT_TYPE MonDReg[10] <= MonDReg[10]~21.DB_MAX_OUTPUT_PORT_TYPE MonDReg[11] <= MonDReg[11]~20.DB_MAX_OUTPUT_PORT_TYPE MonDReg[12] <= MonDReg[12]~19.DB_MAX_OUTPUT_PORT_TYPE MonDReg[13] <= MonDReg[13]~18.DB_MAX_OUTPUT_PORT_TYPE MonDReg[14] <= MonDReg[14]~17.DB_MAX_OUTPUT_PORT_TYPE MonDReg[15] <= MonDReg[15]~16.DB_MAX_OUTPUT_PORT_TYPE MonDReg[16] <= MonDReg[16]~15.DB_MAX_OUTPUT_PORT_TYPE MonDReg[17] <= MonDReg[17]~14.DB_MAX_OUTPUT_PORT_TYPE MonDReg[18] <= MonDReg[18]~13.DB_MAX_OUTPUT_PORT_TYPE MonDReg[19] <= MonDReg[19]~12.DB_MAX_OUTPUT_PORT_TYPE MonDReg[20] <= MonDReg[20]~11.DB_MAX_OUTPUT_PORT_TYPE MonDReg[21] <= MonDReg[21]~10.DB_MAX_OUTPUT_PORT_TYPE MonDReg[22] <= MonDReg[22]~9.DB_MAX_OUTPUT_PORT_TYPE MonDReg[23] <= MonDReg[23]~8.DB_MAX_OUTPUT_PORT_TYPE MonDReg[24] <= MonDReg[24]~7.DB_MAX_OUTPUT_PORT_TYPE MonDReg[25] <= MonDReg[25]~6.DB_MAX_OUTPUT_PORT_TYPE MonDReg[26] <= MonDReg[26]~5.DB_MAX_OUTPUT_PORT_TYPE MonDReg[27] <= MonDReg[27]~4.DB_MAX_OUTPUT_PORT_TYPE MonDReg[28] <= MonDReg[28]~3.DB_MAX_OUTPUT_PORT_TYPE MonDReg[29] <= MonDReg[29]~2.DB_MAX_OUTPUT_PORT_TYPE MonDReg[30] <= MonDReg[30]~1.DB_MAX_OUTPUT_PORT_TYPE MonDReg[31] <= MonDReg[31]~0.DB_MAX_OUTPUT_PORT_TYPE oci_ram_readdata[0] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[1] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[2] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[3] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[4] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[5] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[6] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[7] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[8] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[9] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[10] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[11] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[12] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[13] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[14] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[15] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[16] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[17] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[18] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[19] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[20] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[21] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[22] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[23] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[24] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[25] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[26] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[27] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[28] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[29] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[30] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a oci_ram_readdata[31] <= cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component.q_a |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component address_a[0] => address_a[0]~7.IN1 address_a[1] => address_a[1]~6.IN1 address_a[2] => address_a[2]~5.IN1 address_a[3] => address_a[3]~4.IN1 address_a[4] => address_a[4]~3.IN1 address_a[5] => address_a[5]~2.IN1 address_a[6] => address_a[6]~1.IN1 address_a[7] => address_a[7]~0.IN1 address_b[0] => address_b[0]~7.IN1 address_b[1] => address_b[1]~6.IN1 address_b[2] => address_b[2]~5.IN1 address_b[3] => address_b[3]~4.IN1 address_b[4] => address_b[4]~3.IN1 address_b[5] => address_b[5]~2.IN1 address_b[6] => address_b[6]~1.IN1 address_b[7] => address_b[7]~0.IN1 byteena_a[0] => byteena_a[0]~3.IN1 byteena_a[1] => byteena_a[1]~2.IN1 byteena_a[2] => byteena_a[2]~1.IN1 byteena_a[3] => byteena_a[3]~0.IN1 clock0 => clock0~0.IN1 clock1 => clock1~0.IN1 clocken0 => clocken0~0.IN1 clocken1 => clocken1~0.IN1 data_a[0] => data_a[0]~31.IN1 data_a[1] => data_a[1]~30.IN1 data_a[2] => data_a[2]~29.IN1 data_a[3] => data_a[3]~28.IN1 data_a[4] => data_a[4]~27.IN1 data_a[5] => data_a[5]~26.IN1 data_a[6] => data_a[6]~25.IN1 data_a[7] => data_a[7]~24.IN1 data_a[8] => data_a[8]~23.IN1 data_a[9] => data_a[9]~22.IN1 data_a[10] => data_a[10]~21.IN1 data_a[11] => data_a[11]~20.IN1 data_a[12] => data_a[12]~19.IN1 data_a[13] => data_a[13]~18.IN1 data_a[14] => data_a[14]~17.IN1 data_a[15] => data_a[15]~16.IN1 data_a[16] => data_a[16]~15.IN1 data_a[17] => data_a[17]~14.IN1 data_a[18] => data_a[18]~13.IN1 data_a[19] => data_a[19]~12.IN1 data_a[20] => data_a[20]~11.IN1 data_a[21] => data_a[21]~10.IN1 data_a[22] => data_a[22]~9.IN1 data_a[23] => data_a[23]~8.IN1 data_a[24] => data_a[24]~7.IN1 data_a[25] => data_a[25]~6.IN1 data_a[26] => data_a[26]~5.IN1 data_a[27] => data_a[27]~4.IN1 data_a[28] => data_a[28]~3.IN1 data_a[29] => data_a[29]~2.IN1 data_a[30] => data_a[30]~1.IN1 data_a[31] => data_a[31]~0.IN1 data_b[0] => data_b[0]~31.IN1 data_b[1] => data_b[1]~30.IN1 data_b[2] => data_b[2]~29.IN1 data_b[3] => data_b[3]~28.IN1 data_b[4] => data_b[4]~27.IN1 data_b[5] => data_b[5]~26.IN1 data_b[6] => data_b[6]~25.IN1 data_b[7] => data_b[7]~24.IN1 data_b[8] => data_b[8]~23.IN1 data_b[9] => data_b[9]~22.IN1 data_b[10] => data_b[10]~21.IN1 data_b[11] => data_b[11]~20.IN1 data_b[12] => data_b[12]~19.IN1 data_b[13] => data_b[13]~18.IN1 data_b[14] => data_b[14]~17.IN1 data_b[15] => data_b[15]~16.IN1 data_b[16] => data_b[16]~15.IN1 data_b[17] => data_b[17]~14.IN1 data_b[18] => data_b[18]~13.IN1 data_b[19] => data_b[19]~12.IN1 data_b[20] => data_b[20]~11.IN1 data_b[21] => data_b[21]~10.IN1 data_b[22] => data_b[22]~9.IN1 data_b[23] => data_b[23]~8.IN1 data_b[24] => data_b[24]~7.IN1 data_b[25] => data_b[25]~6.IN1 data_b[26] => data_b[26]~5.IN1 data_b[27] => data_b[27]~4.IN1 data_b[28] => data_b[28]~3.IN1 data_b[29] => data_b[29]~2.IN1 data_b[30] => data_b[30]~1.IN1 data_b[31] => data_b[31]~0.IN1 wren_a => wren_a~0.IN1 wren_b => wren_b~0.IN1 q_a[0] <= altsyncram:the_altsyncram.q_a q_a[1] <= altsyncram:the_altsyncram.q_a q_a[2] <= altsyncram:the_altsyncram.q_a q_a[3] <= altsyncram:the_altsyncram.q_a q_a[4] <= altsyncram:the_altsyncram.q_a q_a[5] <= altsyncram:the_altsyncram.q_a q_a[6] <= altsyncram:the_altsyncram.q_a q_a[7] <= altsyncram:the_altsyncram.q_a q_a[8] <= altsyncram:the_altsyncram.q_a q_a[9] <= altsyncram:the_altsyncram.q_a q_a[10] <= altsyncram:the_altsyncram.q_a q_a[11] <= altsyncram:the_altsyncram.q_a q_a[12] <= altsyncram:the_altsyncram.q_a q_a[13] <= altsyncram:the_altsyncram.q_a q_a[14] <= altsyncram:the_altsyncram.q_a q_a[15] <= altsyncram:the_altsyncram.q_a q_a[16] <= altsyncram:the_altsyncram.q_a q_a[17] <= altsyncram:the_altsyncram.q_a q_a[18] <= altsyncram:the_altsyncram.q_a q_a[19] <= altsyncram:the_altsyncram.q_a q_a[20] <= altsyncram:the_altsyncram.q_a q_a[21] <= altsyncram:the_altsyncram.q_a q_a[22] <= altsyncram:the_altsyncram.q_a q_a[23] <= altsyncram:the_altsyncram.q_a q_a[24] <= altsyncram:the_altsyncram.q_a q_a[25] <= altsyncram:the_altsyncram.q_a q_a[26] <= altsyncram:the_altsyncram.q_a q_a[27] <= altsyncram:the_altsyncram.q_a q_a[28] <= altsyncram:the_altsyncram.q_a q_a[29] <= altsyncram:the_altsyncram.q_a q_a[30] <= altsyncram:the_altsyncram.q_a q_a[31] <= altsyncram:the_altsyncram.q_a q_b[0] <= altsyncram:the_altsyncram.q_b q_b[1] <= altsyncram:the_altsyncram.q_b q_b[2] <= altsyncram:the_altsyncram.q_b q_b[3] <= altsyncram:the_altsyncram.q_b q_b[4] <= altsyncram:the_altsyncram.q_b q_b[5] <= altsyncram:the_altsyncram.q_b q_b[6] <= altsyncram:the_altsyncram.q_b q_b[7] <= altsyncram:the_altsyncram.q_b q_b[8] <= altsyncram:the_altsyncram.q_b q_b[9] <= altsyncram:the_altsyncram.q_b q_b[10] <= altsyncram:the_altsyncram.q_b q_b[11] <= altsyncram:the_altsyncram.q_b q_b[12] <= altsyncram:the_altsyncram.q_b q_b[13] <= altsyncram:the_altsyncram.q_b q_b[14] <= altsyncram:the_altsyncram.q_b q_b[15] <= altsyncram:the_altsyncram.q_b q_b[16] <= altsyncram:the_altsyncram.q_b q_b[17] <= altsyncram:the_altsyncram.q_b q_b[18] <= altsyncram:the_altsyncram.q_b q_b[19] <= altsyncram:the_altsyncram.q_b q_b[20] <= altsyncram:the_altsyncram.q_b q_b[21] <= altsyncram:the_altsyncram.q_b q_b[22] <= altsyncram:the_altsyncram.q_b q_b[23] <= altsyncram:the_altsyncram.q_b q_b[24] <= altsyncram:the_altsyncram.q_b q_b[25] <= altsyncram:the_altsyncram.q_b q_b[26] <= altsyncram:the_altsyncram.q_b q_b[27] <= altsyncram:the_altsyncram.q_b q_b[28] <= altsyncram:the_altsyncram.q_b q_b[29] <= altsyncram:the_altsyncram.q_b q_b[30] <= altsyncram:the_altsyncram.q_b q_b[31] <= altsyncram:the_altsyncram.q_b |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram wren_a => altsyncram_c572:auto_generated.wren_a rden_a => ~NO_FANOUT~ wren_b => altsyncram_c572:auto_generated.wren_b rden_b => ~NO_FANOUT~ data_a[0] => altsyncram_c572:auto_generated.data_a[0] data_a[1] => altsyncram_c572:auto_generated.data_a[1] data_a[2] => altsyncram_c572:auto_generated.data_a[2] data_a[3] => altsyncram_c572:auto_generated.data_a[3] data_a[4] => altsyncram_c572:auto_generated.data_a[4] data_a[5] => altsyncram_c572:auto_generated.data_a[5] data_a[6] => altsyncram_c572:auto_generated.data_a[6] data_a[7] => altsyncram_c572:auto_generated.data_a[7] data_a[8] => altsyncram_c572:auto_generated.data_a[8] data_a[9] => altsyncram_c572:auto_generated.data_a[9] data_a[10] => altsyncram_c572:auto_generated.data_a[10] data_a[11] => altsyncram_c572:auto_generated.data_a[11] data_a[12] => altsyncram_c572:auto_generated.data_a[12] data_a[13] => altsyncram_c572:auto_generated.data_a[13] data_a[14] => altsyncram_c572:auto_generated.data_a[14] data_a[15] => altsyncram_c572:auto_generated.data_a[15] data_a[16] => altsyncram_c572:auto_generated.data_a[16] data_a[17] => altsyncram_c572:auto_generated.data_a[17] data_a[18] => altsyncram_c572:auto_generated.data_a[18] data_a[19] => altsyncram_c572:auto_generated.data_a[19] data_a[20] => altsyncram_c572:auto_generated.data_a[20] data_a[21] => altsyncram_c572:auto_generated.data_a[21] data_a[22] => altsyncram_c572:auto_generated.data_a[22] data_a[23] => altsyncram_c572:auto_generated.data_a[23] data_a[24] => altsyncram_c572:auto_generated.data_a[24] data_a[25] => altsyncram_c572:auto_generated.data_a[25] data_a[26] => altsyncram_c572:auto_generated.data_a[26] data_a[27] => altsyncram_c572:auto_generated.data_a[27] data_a[28] => altsyncram_c572:auto_generated.data_a[28] data_a[29] => altsyncram_c572:auto_generated.data_a[29] data_a[30] => altsyncram_c572:auto_generated.data_a[30] data_a[31] => altsyncram_c572:auto_generated.data_a[31] data_b[0] => altsyncram_c572:auto_generated.data_b[0] data_b[1] => altsyncram_c572:auto_generated.data_b[1] data_b[2] => altsyncram_c572:auto_generated.data_b[2] data_b[3] => altsyncram_c572:auto_generated.data_b[3] data_b[4] => altsyncram_c572:auto_generated.data_b[4] data_b[5] => altsyncram_c572:auto_generated.data_b[5] data_b[6] => altsyncram_c572:auto_generated.data_b[6] data_b[7] => altsyncram_c572:auto_generated.data_b[7] data_b[8] => altsyncram_c572:auto_generated.data_b[8] data_b[9] => altsyncram_c572:auto_generated.data_b[9] data_b[10] => altsyncram_c572:auto_generated.data_b[10] data_b[11] => altsyncram_c572:auto_generated.data_b[11] data_b[12] => altsyncram_c572:auto_generated.data_b[12] data_b[13] => altsyncram_c572:auto_generated.data_b[13] data_b[14] => altsyncram_c572:auto_generated.data_b[14] data_b[15] => altsyncram_c572:auto_generated.data_b[15] data_b[16] => altsyncram_c572:auto_generated.data_b[16] data_b[17] => altsyncram_c572:auto_generated.data_b[17] data_b[18] => altsyncram_c572:auto_generated.data_b[18] data_b[19] => altsyncram_c572:auto_generated.data_b[19] data_b[20] => altsyncram_c572:auto_generated.data_b[20] data_b[21] => altsyncram_c572:auto_generated.data_b[21] data_b[22] => altsyncram_c572:auto_generated.data_b[22] data_b[23] => altsyncram_c572:auto_generated.data_b[23] data_b[24] => altsyncram_c572:auto_generated.data_b[24] data_b[25] => altsyncram_c572:auto_generated.data_b[25] data_b[26] => altsyncram_c572:auto_generated.data_b[26] data_b[27] => altsyncram_c572:auto_generated.data_b[27] data_b[28] => altsyncram_c572:auto_generated.data_b[28] data_b[29] => altsyncram_c572:auto_generated.data_b[29] data_b[30] => altsyncram_c572:auto_generated.data_b[30] data_b[31] => altsyncram_c572:auto_generated.data_b[31] address_a[0] => altsyncram_c572:auto_generated.address_a[0] address_a[1] => altsyncram_c572:auto_generated.address_a[1] address_a[2] => altsyncram_c572:auto_generated.address_a[2] address_a[3] => altsyncram_c572:auto_generated.address_a[3] address_a[4] => altsyncram_c572:auto_generated.address_a[4] address_a[5] => altsyncram_c572:auto_generated.address_a[5] address_a[6] => altsyncram_c572:auto_generated.address_a[6] address_a[7] => altsyncram_c572:auto_generated.address_a[7] address_b[0] => altsyncram_c572:auto_generated.address_b[0] address_b[1] => altsyncram_c572:auto_generated.address_b[1] address_b[2] => altsyncram_c572:auto_generated.address_b[2] address_b[3] => altsyncram_c572:auto_generated.address_b[3] address_b[4] => altsyncram_c572:auto_generated.address_b[4] address_b[5] => altsyncram_c572:auto_generated.address_b[5] address_b[6] => altsyncram_c572:auto_generated.address_b[6] address_b[7] => altsyncram_c572:auto_generated.address_b[7] addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_c572:auto_generated.clock0 clock1 => altsyncram_c572:auto_generated.clock1 clocken0 => altsyncram_c572:auto_generated.clocken0 clocken1 => altsyncram_c572:auto_generated.clocken1 clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => altsyncram_c572:auto_generated.byteena_a[0] byteena_a[1] => altsyncram_c572:auto_generated.byteena_a[1] byteena_a[2] => altsyncram_c572:auto_generated.byteena_a[2] byteena_a[3] => altsyncram_c572:auto_generated.byteena_a[3] byteena_b[0] => ~NO_FANOUT~ q_a[0] <= altsyncram_c572:auto_generated.q_a[0] q_a[1] <= altsyncram_c572:auto_generated.q_a[1] q_a[2] <= altsyncram_c572:auto_generated.q_a[2] q_a[3] <= altsyncram_c572:auto_generated.q_a[3] q_a[4] <= altsyncram_c572:auto_generated.q_a[4] q_a[5] <= altsyncram_c572:auto_generated.q_a[5] q_a[6] <= altsyncram_c572:auto_generated.q_a[6] q_a[7] <= altsyncram_c572:auto_generated.q_a[7] q_a[8] <= altsyncram_c572:auto_generated.q_a[8] q_a[9] <= altsyncram_c572:auto_generated.q_a[9] q_a[10] <= altsyncram_c572:auto_generated.q_a[10] q_a[11] <= altsyncram_c572:auto_generated.q_a[11] q_a[12] <= altsyncram_c572:auto_generated.q_a[12] q_a[13] <= altsyncram_c572:auto_generated.q_a[13] q_a[14] <= altsyncram_c572:auto_generated.q_a[14] q_a[15] <= altsyncram_c572:auto_generated.q_a[15] q_a[16] <= altsyncram_c572:auto_generated.q_a[16] q_a[17] <= altsyncram_c572:auto_generated.q_a[17] q_a[18] <= altsyncram_c572:auto_generated.q_a[18] q_a[19] <= altsyncram_c572:auto_generated.q_a[19] q_a[20] <= altsyncram_c572:auto_generated.q_a[20] q_a[21] <= altsyncram_c572:auto_generated.q_a[21] q_a[22] <= altsyncram_c572:auto_generated.q_a[22] q_a[23] <= altsyncram_c572:auto_generated.q_a[23] q_a[24] <= altsyncram_c572:auto_generated.q_a[24] q_a[25] <= altsyncram_c572:auto_generated.q_a[25] q_a[26] <= altsyncram_c572:auto_generated.q_a[26] q_a[27] <= altsyncram_c572:auto_generated.q_a[27] q_a[28] <= altsyncram_c572:auto_generated.q_a[28] q_a[29] <= altsyncram_c572:auto_generated.q_a[29] q_a[30] <= altsyncram_c572:auto_generated.q_a[30] q_a[31] <= altsyncram_c572:auto_generated.q_a[31] q_b[0] <= altsyncram_c572:auto_generated.q_b[0] q_b[1] <= altsyncram_c572:auto_generated.q_b[1] q_b[2] <= altsyncram_c572:auto_generated.q_b[2] q_b[3] <= altsyncram_c572:auto_generated.q_b[3] q_b[4] <= altsyncram_c572:auto_generated.q_b[4] q_b[5] <= altsyncram_c572:auto_generated.q_b[5] q_b[6] <= altsyncram_c572:auto_generated.q_b[6] q_b[7] <= altsyncram_c572:auto_generated.q_b[7] q_b[8] <= altsyncram_c572:auto_generated.q_b[8] q_b[9] <= altsyncram_c572:auto_generated.q_b[9] q_b[10] <= altsyncram_c572:auto_generated.q_b[10] q_b[11] <= altsyncram_c572:auto_generated.q_b[11] q_b[12] <= altsyncram_c572:auto_generated.q_b[12] q_b[13] <= altsyncram_c572:auto_generated.q_b[13] q_b[14] <= altsyncram_c572:auto_generated.q_b[14] q_b[15] <= altsyncram_c572:auto_generated.q_b[15] q_b[16] <= altsyncram_c572:auto_generated.q_b[16] q_b[17] <= altsyncram_c572:auto_generated.q_b[17] q_b[18] <= altsyncram_c572:auto_generated.q_b[18] q_b[19] <= altsyncram_c572:auto_generated.q_b[19] q_b[20] <= altsyncram_c572:auto_generated.q_b[20] q_b[21] <= altsyncram_c572:auto_generated.q_b[21] q_b[22] <= altsyncram_c572:auto_generated.q_b[22] q_b[23] <= altsyncram_c572:auto_generated.q_b[23] q_b[24] <= altsyncram_c572:auto_generated.q_b[24] q_b[25] <= altsyncram_c572:auto_generated.q_b[25] q_b[26] <= altsyncram_c572:auto_generated.q_b[26] q_b[27] <= altsyncram_c572:auto_generated.q_b[27] q_b[28] <= altsyncram_c572:auto_generated.q_b[28] q_b[29] <= altsyncram_c572:auto_generated.q_b[29] q_b[30] <= altsyncram_c572:auto_generated.q_b[30] q_b[31] <= altsyncram_c572:auto_generated.q_b[31] eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[0] => ram_block1a8.PORTAADDR address_a[0] => ram_block1a9.PORTAADDR address_a[0] => ram_block1a10.PORTAADDR address_a[0] => ram_block1a11.PORTAADDR address_a[0] => ram_block1a12.PORTAADDR address_a[0] => ram_block1a13.PORTAADDR address_a[0] => ram_block1a14.PORTAADDR address_a[0] => ram_block1a15.PORTAADDR address_a[0] => ram_block1a16.PORTAADDR address_a[0] => ram_block1a17.PORTAADDR address_a[0] => ram_block1a18.PORTAADDR address_a[0] => ram_block1a19.PORTAADDR address_a[0] => ram_block1a20.PORTAADDR address_a[0] => ram_block1a21.PORTAADDR address_a[0] => ram_block1a22.PORTAADDR address_a[0] => ram_block1a23.PORTAADDR address_a[0] => ram_block1a24.PORTAADDR address_a[0] => ram_block1a25.PORTAADDR address_a[0] => ram_block1a26.PORTAADDR address_a[0] => ram_block1a27.PORTAADDR address_a[0] => ram_block1a28.PORTAADDR address_a[0] => ram_block1a29.PORTAADDR address_a[0] => ram_block1a30.PORTAADDR address_a[0] => ram_block1a31.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[1] => ram_block1a8.PORTAADDR1 address_a[1] => ram_block1a9.PORTAADDR1 address_a[1] => ram_block1a10.PORTAADDR1 address_a[1] => ram_block1a11.PORTAADDR1 address_a[1] => ram_block1a12.PORTAADDR1 address_a[1] => ram_block1a13.PORTAADDR1 address_a[1] => ram_block1a14.PORTAADDR1 address_a[1] => ram_block1a15.PORTAADDR1 address_a[1] => ram_block1a16.PORTAADDR1 address_a[1] => ram_block1a17.PORTAADDR1 address_a[1] => ram_block1a18.PORTAADDR1 address_a[1] => ram_block1a19.PORTAADDR1 address_a[1] => ram_block1a20.PORTAADDR1 address_a[1] => ram_block1a21.PORTAADDR1 address_a[1] => ram_block1a22.PORTAADDR1 address_a[1] => ram_block1a23.PORTAADDR1 address_a[1] => ram_block1a24.PORTAADDR1 address_a[1] => ram_block1a25.PORTAADDR1 address_a[1] => ram_block1a26.PORTAADDR1 address_a[1] => ram_block1a27.PORTAADDR1 address_a[1] => ram_block1a28.PORTAADDR1 address_a[1] => ram_block1a29.PORTAADDR1 address_a[1] => ram_block1a30.PORTAADDR1 address_a[1] => ram_block1a31.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[2] => ram_block1a8.PORTAADDR2 address_a[2] => ram_block1a9.PORTAADDR2 address_a[2] => ram_block1a10.PORTAADDR2 address_a[2] => ram_block1a11.PORTAADDR2 address_a[2] => ram_block1a12.PORTAADDR2 address_a[2] => ram_block1a13.PORTAADDR2 address_a[2] => ram_block1a14.PORTAADDR2 address_a[2] => ram_block1a15.PORTAADDR2 address_a[2] => ram_block1a16.PORTAADDR2 address_a[2] => ram_block1a17.PORTAADDR2 address_a[2] => ram_block1a18.PORTAADDR2 address_a[2] => ram_block1a19.PORTAADDR2 address_a[2] => ram_block1a20.PORTAADDR2 address_a[2] => ram_block1a21.PORTAADDR2 address_a[2] => ram_block1a22.PORTAADDR2 address_a[2] => ram_block1a23.PORTAADDR2 address_a[2] => ram_block1a24.PORTAADDR2 address_a[2] => ram_block1a25.PORTAADDR2 address_a[2] => ram_block1a26.PORTAADDR2 address_a[2] => ram_block1a27.PORTAADDR2 address_a[2] => ram_block1a28.PORTAADDR2 address_a[2] => ram_block1a29.PORTAADDR2 address_a[2] => ram_block1a30.PORTAADDR2 address_a[2] => ram_block1a31.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[3] => ram_block1a8.PORTAADDR3 address_a[3] => ram_block1a9.PORTAADDR3 address_a[3] => ram_block1a10.PORTAADDR3 address_a[3] => ram_block1a11.PORTAADDR3 address_a[3] => ram_block1a12.PORTAADDR3 address_a[3] => ram_block1a13.PORTAADDR3 address_a[3] => ram_block1a14.PORTAADDR3 address_a[3] => ram_block1a15.PORTAADDR3 address_a[3] => ram_block1a16.PORTAADDR3 address_a[3] => ram_block1a17.PORTAADDR3 address_a[3] => ram_block1a18.PORTAADDR3 address_a[3] => ram_block1a19.PORTAADDR3 address_a[3] => ram_block1a20.PORTAADDR3 address_a[3] => ram_block1a21.PORTAADDR3 address_a[3] => ram_block1a22.PORTAADDR3 address_a[3] => ram_block1a23.PORTAADDR3 address_a[3] => ram_block1a24.PORTAADDR3 address_a[3] => ram_block1a25.PORTAADDR3 address_a[3] => ram_block1a26.PORTAADDR3 address_a[3] => ram_block1a27.PORTAADDR3 address_a[3] => ram_block1a28.PORTAADDR3 address_a[3] => ram_block1a29.PORTAADDR3 address_a[3] => ram_block1a30.PORTAADDR3 address_a[3] => ram_block1a31.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[4] => ram_block1a8.PORTAADDR4 address_a[4] => ram_block1a9.PORTAADDR4 address_a[4] => ram_block1a10.PORTAADDR4 address_a[4] => ram_block1a11.PORTAADDR4 address_a[4] => ram_block1a12.PORTAADDR4 address_a[4] => ram_block1a13.PORTAADDR4 address_a[4] => ram_block1a14.PORTAADDR4 address_a[4] => ram_block1a15.PORTAADDR4 address_a[4] => ram_block1a16.PORTAADDR4 address_a[4] => ram_block1a17.PORTAADDR4 address_a[4] => ram_block1a18.PORTAADDR4 address_a[4] => ram_block1a19.PORTAADDR4 address_a[4] => ram_block1a20.PORTAADDR4 address_a[4] => ram_block1a21.PORTAADDR4 address_a[4] => ram_block1a22.PORTAADDR4 address_a[4] => ram_block1a23.PORTAADDR4 address_a[4] => ram_block1a24.PORTAADDR4 address_a[4] => ram_block1a25.PORTAADDR4 address_a[4] => ram_block1a26.PORTAADDR4 address_a[4] => ram_block1a27.PORTAADDR4 address_a[4] => ram_block1a28.PORTAADDR4 address_a[4] => ram_block1a29.PORTAADDR4 address_a[4] => ram_block1a30.PORTAADDR4 address_a[4] => ram_block1a31.PORTAADDR4 address_a[5] => ram_block1a0.PORTAADDR5 address_a[5] => ram_block1a1.PORTAADDR5 address_a[5] => ram_block1a2.PORTAADDR5 address_a[5] => ram_block1a3.PORTAADDR5 address_a[5] => ram_block1a4.PORTAADDR5 address_a[5] => ram_block1a5.PORTAADDR5 address_a[5] => ram_block1a6.PORTAADDR5 address_a[5] => ram_block1a7.PORTAADDR5 address_a[5] => ram_block1a8.PORTAADDR5 address_a[5] => ram_block1a9.PORTAADDR5 address_a[5] => ram_block1a10.PORTAADDR5 address_a[5] => ram_block1a11.PORTAADDR5 address_a[5] => ram_block1a12.PORTAADDR5 address_a[5] => ram_block1a13.PORTAADDR5 address_a[5] => ram_block1a14.PORTAADDR5 address_a[5] => ram_block1a15.PORTAADDR5 address_a[5] => ram_block1a16.PORTAADDR5 address_a[5] => ram_block1a17.PORTAADDR5 address_a[5] => ram_block1a18.PORTAADDR5 address_a[5] => ram_block1a19.PORTAADDR5 address_a[5] => ram_block1a20.PORTAADDR5 address_a[5] => ram_block1a21.PORTAADDR5 address_a[5] => ram_block1a22.PORTAADDR5 address_a[5] => ram_block1a23.PORTAADDR5 address_a[5] => ram_block1a24.PORTAADDR5 address_a[5] => ram_block1a25.PORTAADDR5 address_a[5] => ram_block1a26.PORTAADDR5 address_a[5] => ram_block1a27.PORTAADDR5 address_a[5] => ram_block1a28.PORTAADDR5 address_a[5] => ram_block1a29.PORTAADDR5 address_a[5] => ram_block1a30.PORTAADDR5 address_a[5] => ram_block1a31.PORTAADDR5 address_a[6] => ram_block1a0.PORTAADDR6 address_a[6] => ram_block1a1.PORTAADDR6 address_a[6] => ram_block1a2.PORTAADDR6 address_a[6] => ram_block1a3.PORTAADDR6 address_a[6] => ram_block1a4.PORTAADDR6 address_a[6] => ram_block1a5.PORTAADDR6 address_a[6] => ram_block1a6.PORTAADDR6 address_a[6] => ram_block1a7.PORTAADDR6 address_a[6] => ram_block1a8.PORTAADDR6 address_a[6] => ram_block1a9.PORTAADDR6 address_a[6] => ram_block1a10.PORTAADDR6 address_a[6] => ram_block1a11.PORTAADDR6 address_a[6] => ram_block1a12.PORTAADDR6 address_a[6] => ram_block1a13.PORTAADDR6 address_a[6] => ram_block1a14.PORTAADDR6 address_a[6] => ram_block1a15.PORTAADDR6 address_a[6] => ram_block1a16.PORTAADDR6 address_a[6] => ram_block1a17.PORTAADDR6 address_a[6] => ram_block1a18.PORTAADDR6 address_a[6] => ram_block1a19.PORTAADDR6 address_a[6] => ram_block1a20.PORTAADDR6 address_a[6] => ram_block1a21.PORTAADDR6 address_a[6] => ram_block1a22.PORTAADDR6 address_a[6] => ram_block1a23.PORTAADDR6 address_a[6] => ram_block1a24.PORTAADDR6 address_a[6] => ram_block1a25.PORTAADDR6 address_a[6] => ram_block1a26.PORTAADDR6 address_a[6] => ram_block1a27.PORTAADDR6 address_a[6] => ram_block1a28.PORTAADDR6 address_a[6] => ram_block1a29.PORTAADDR6 address_a[6] => ram_block1a30.PORTAADDR6 address_a[6] => ram_block1a31.PORTAADDR6 address_a[7] => ram_block1a0.PORTAADDR7 address_a[7] => ram_block1a1.PORTAADDR7 address_a[7] => ram_block1a2.PORTAADDR7 address_a[7] => ram_block1a3.PORTAADDR7 address_a[7] => ram_block1a4.PORTAADDR7 address_a[7] => ram_block1a5.PORTAADDR7 address_a[7] => ram_block1a6.PORTAADDR7 address_a[7] => ram_block1a7.PORTAADDR7 address_a[7] => ram_block1a8.PORTAADDR7 address_a[7] => ram_block1a9.PORTAADDR7 address_a[7] => ram_block1a10.PORTAADDR7 address_a[7] => ram_block1a11.PORTAADDR7 address_a[7] => ram_block1a12.PORTAADDR7 address_a[7] => ram_block1a13.PORTAADDR7 address_a[7] => ram_block1a14.PORTAADDR7 address_a[7] => ram_block1a15.PORTAADDR7 address_a[7] => ram_block1a16.PORTAADDR7 address_a[7] => ram_block1a17.PORTAADDR7 address_a[7] => ram_block1a18.PORTAADDR7 address_a[7] => ram_block1a19.PORTAADDR7 address_a[7] => ram_block1a20.PORTAADDR7 address_a[7] => ram_block1a21.PORTAADDR7 address_a[7] => ram_block1a22.PORTAADDR7 address_a[7] => ram_block1a23.PORTAADDR7 address_a[7] => ram_block1a24.PORTAADDR7 address_a[7] => ram_block1a25.PORTAADDR7 address_a[7] => ram_block1a26.PORTAADDR7 address_a[7] => ram_block1a27.PORTAADDR7 address_a[7] => ram_block1a28.PORTAADDR7 address_a[7] => ram_block1a29.PORTAADDR7 address_a[7] => ram_block1a30.PORTAADDR7 address_a[7] => ram_block1a31.PORTAADDR7 address_b[0] => ram_block1a0.PORTBADDR address_b[0] => ram_block1a1.PORTBADDR address_b[0] => ram_block1a2.PORTBADDR address_b[0] => ram_block1a3.PORTBADDR address_b[0] => ram_block1a4.PORTBADDR address_b[0] => ram_block1a5.PORTBADDR address_b[0] => ram_block1a6.PORTBADDR address_b[0] => ram_block1a7.PORTBADDR address_b[0] => ram_block1a8.PORTBADDR address_b[0] => ram_block1a9.PORTBADDR address_b[0] => ram_block1a10.PORTBADDR address_b[0] => ram_block1a11.PORTBADDR address_b[0] => ram_block1a12.PORTBADDR address_b[0] => ram_block1a13.PORTBADDR address_b[0] => ram_block1a14.PORTBADDR address_b[0] => ram_block1a15.PORTBADDR address_b[0] => ram_block1a16.PORTBADDR address_b[0] => ram_block1a17.PORTBADDR address_b[0] => ram_block1a18.PORTBADDR address_b[0] => ram_block1a19.PORTBADDR address_b[0] => ram_block1a20.PORTBADDR address_b[0] => ram_block1a21.PORTBADDR address_b[0] => ram_block1a22.PORTBADDR address_b[0] => ram_block1a23.PORTBADDR address_b[0] => ram_block1a24.PORTBADDR address_b[0] => ram_block1a25.PORTBADDR address_b[0] => ram_block1a26.PORTBADDR address_b[0] => ram_block1a27.PORTBADDR address_b[0] => ram_block1a28.PORTBADDR address_b[0] => ram_block1a29.PORTBADDR address_b[0] => ram_block1a30.PORTBADDR address_b[0] => ram_block1a31.PORTBADDR address_b[1] => ram_block1a0.PORTBADDR1 address_b[1] => ram_block1a1.PORTBADDR1 address_b[1] => ram_block1a2.PORTBADDR1 address_b[1] => ram_block1a3.PORTBADDR1 address_b[1] => ram_block1a4.PORTBADDR1 address_b[1] => ram_block1a5.PORTBADDR1 address_b[1] => ram_block1a6.PORTBADDR1 address_b[1] => ram_block1a7.PORTBADDR1 address_b[1] => ram_block1a8.PORTBADDR1 address_b[1] => ram_block1a9.PORTBADDR1 address_b[1] => ram_block1a10.PORTBADDR1 address_b[1] => ram_block1a11.PORTBADDR1 address_b[1] => ram_block1a12.PORTBADDR1 address_b[1] => ram_block1a13.PORTBADDR1 address_b[1] => ram_block1a14.PORTBADDR1 address_b[1] => ram_block1a15.PORTBADDR1 address_b[1] => ram_block1a16.PORTBADDR1 address_b[1] => ram_block1a17.PORTBADDR1 address_b[1] => ram_block1a18.PORTBADDR1 address_b[1] => ram_block1a19.PORTBADDR1 address_b[1] => ram_block1a20.PORTBADDR1 address_b[1] => ram_block1a21.PORTBADDR1 address_b[1] => ram_block1a22.PORTBADDR1 address_b[1] => ram_block1a23.PORTBADDR1 address_b[1] => ram_block1a24.PORTBADDR1 address_b[1] => ram_block1a25.PORTBADDR1 address_b[1] => ram_block1a26.PORTBADDR1 address_b[1] => ram_block1a27.PORTBADDR1 address_b[1] => ram_block1a28.PORTBADDR1 address_b[1] => ram_block1a29.PORTBADDR1 address_b[1] => ram_block1a30.PORTBADDR1 address_b[1] => ram_block1a31.PORTBADDR1 address_b[2] => ram_block1a0.PORTBADDR2 address_b[2] => ram_block1a1.PORTBADDR2 address_b[2] => ram_block1a2.PORTBADDR2 address_b[2] => ram_block1a3.PORTBADDR2 address_b[2] => ram_block1a4.PORTBADDR2 address_b[2] => ram_block1a5.PORTBADDR2 address_b[2] => ram_block1a6.PORTBADDR2 address_b[2] => ram_block1a7.PORTBADDR2 address_b[2] => ram_block1a8.PORTBADDR2 address_b[2] => ram_block1a9.PORTBADDR2 address_b[2] => ram_block1a10.PORTBADDR2 address_b[2] => ram_block1a11.PORTBADDR2 address_b[2] => ram_block1a12.PORTBADDR2 address_b[2] => ram_block1a13.PORTBADDR2 address_b[2] => ram_block1a14.PORTBADDR2 address_b[2] => ram_block1a15.PORTBADDR2 address_b[2] => ram_block1a16.PORTBADDR2 address_b[2] => ram_block1a17.PORTBADDR2 address_b[2] => ram_block1a18.PORTBADDR2 address_b[2] => ram_block1a19.PORTBADDR2 address_b[2] => ram_block1a20.PORTBADDR2 address_b[2] => ram_block1a21.PORTBADDR2 address_b[2] => ram_block1a22.PORTBADDR2 address_b[2] => ram_block1a23.PORTBADDR2 address_b[2] => ram_block1a24.PORTBADDR2 address_b[2] => ram_block1a25.PORTBADDR2 address_b[2] => ram_block1a26.PORTBADDR2 address_b[2] => ram_block1a27.PORTBADDR2 address_b[2] => ram_block1a28.PORTBADDR2 address_b[2] => ram_block1a29.PORTBADDR2 address_b[2] => ram_block1a30.PORTBADDR2 address_b[2] => ram_block1a31.PORTBADDR2 address_b[3] => ram_block1a0.PORTBADDR3 address_b[3] => ram_block1a1.PORTBADDR3 address_b[3] => ram_block1a2.PORTBADDR3 address_b[3] => ram_block1a3.PORTBADDR3 address_b[3] => ram_block1a4.PORTBADDR3 address_b[3] => ram_block1a5.PORTBADDR3 address_b[3] => ram_block1a6.PORTBADDR3 address_b[3] => ram_block1a7.PORTBADDR3 address_b[3] => ram_block1a8.PORTBADDR3 address_b[3] => ram_block1a9.PORTBADDR3 address_b[3] => ram_block1a10.PORTBADDR3 address_b[3] => ram_block1a11.PORTBADDR3 address_b[3] => ram_block1a12.PORTBADDR3 address_b[3] => ram_block1a13.PORTBADDR3 address_b[3] => ram_block1a14.PORTBADDR3 address_b[3] => ram_block1a15.PORTBADDR3 address_b[3] => ram_block1a16.PORTBADDR3 address_b[3] => ram_block1a17.PORTBADDR3 address_b[3] => ram_block1a18.PORTBADDR3 address_b[3] => ram_block1a19.PORTBADDR3 address_b[3] => ram_block1a20.PORTBADDR3 address_b[3] => ram_block1a21.PORTBADDR3 address_b[3] => ram_block1a22.PORTBADDR3 address_b[3] => ram_block1a23.PORTBADDR3 address_b[3] => ram_block1a24.PORTBADDR3 address_b[3] => ram_block1a25.PORTBADDR3 address_b[3] => ram_block1a26.PORTBADDR3 address_b[3] => ram_block1a27.PORTBADDR3 address_b[3] => ram_block1a28.PORTBADDR3 address_b[3] => ram_block1a29.PORTBADDR3 address_b[3] => ram_block1a30.PORTBADDR3 address_b[3] => ram_block1a31.PORTBADDR3 address_b[4] => ram_block1a0.PORTBADDR4 address_b[4] => ram_block1a1.PORTBADDR4 address_b[4] => ram_block1a2.PORTBADDR4 address_b[4] => ram_block1a3.PORTBADDR4 address_b[4] => ram_block1a4.PORTBADDR4 address_b[4] => ram_block1a5.PORTBADDR4 address_b[4] => ram_block1a6.PORTBADDR4 address_b[4] => ram_block1a7.PORTBADDR4 address_b[4] => ram_block1a8.PORTBADDR4 address_b[4] => ram_block1a9.PORTBADDR4 address_b[4] => ram_block1a10.PORTBADDR4 address_b[4] => ram_block1a11.PORTBADDR4 address_b[4] => ram_block1a12.PORTBADDR4 address_b[4] => ram_block1a13.PORTBADDR4 address_b[4] => ram_block1a14.PORTBADDR4 address_b[4] => ram_block1a15.PORTBADDR4 address_b[4] => ram_block1a16.PORTBADDR4 address_b[4] => ram_block1a17.PORTBADDR4 address_b[4] => ram_block1a18.PORTBADDR4 address_b[4] => ram_block1a19.PORTBADDR4 address_b[4] => ram_block1a20.PORTBADDR4 address_b[4] => ram_block1a21.PORTBADDR4 address_b[4] => ram_block1a22.PORTBADDR4 address_b[4] => ram_block1a23.PORTBADDR4 address_b[4] => ram_block1a24.PORTBADDR4 address_b[4] => ram_block1a25.PORTBADDR4 address_b[4] => ram_block1a26.PORTBADDR4 address_b[4] => ram_block1a27.PORTBADDR4 address_b[4] => ram_block1a28.PORTBADDR4 address_b[4] => ram_block1a29.PORTBADDR4 address_b[4] => ram_block1a30.PORTBADDR4 address_b[4] => ram_block1a31.PORTBADDR4 address_b[5] => ram_block1a0.PORTBADDR5 address_b[5] => ram_block1a1.PORTBADDR5 address_b[5] => ram_block1a2.PORTBADDR5 address_b[5] => ram_block1a3.PORTBADDR5 address_b[5] => ram_block1a4.PORTBADDR5 address_b[5] => ram_block1a5.PORTBADDR5 address_b[5] => ram_block1a6.PORTBADDR5 address_b[5] => ram_block1a7.PORTBADDR5 address_b[5] => ram_block1a8.PORTBADDR5 address_b[5] => ram_block1a9.PORTBADDR5 address_b[5] => ram_block1a10.PORTBADDR5 address_b[5] => ram_block1a11.PORTBADDR5 address_b[5] => ram_block1a12.PORTBADDR5 address_b[5] => ram_block1a13.PORTBADDR5 address_b[5] => ram_block1a14.PORTBADDR5 address_b[5] => ram_block1a15.PORTBADDR5 address_b[5] => ram_block1a16.PORTBADDR5 address_b[5] => ram_block1a17.PORTBADDR5 address_b[5] => ram_block1a18.PORTBADDR5 address_b[5] => ram_block1a19.PORTBADDR5 address_b[5] => ram_block1a20.PORTBADDR5 address_b[5] => ram_block1a21.PORTBADDR5 address_b[5] => ram_block1a22.PORTBADDR5 address_b[5] => ram_block1a23.PORTBADDR5 address_b[5] => ram_block1a24.PORTBADDR5 address_b[5] => ram_block1a25.PORTBADDR5 address_b[5] => ram_block1a26.PORTBADDR5 address_b[5] => ram_block1a27.PORTBADDR5 address_b[5] => ram_block1a28.PORTBADDR5 address_b[5] => ram_block1a29.PORTBADDR5 address_b[5] => ram_block1a30.PORTBADDR5 address_b[5] => ram_block1a31.PORTBADDR5 address_b[6] => ram_block1a0.PORTBADDR6 address_b[6] => ram_block1a1.PORTBADDR6 address_b[6] => ram_block1a2.PORTBADDR6 address_b[6] => ram_block1a3.PORTBADDR6 address_b[6] => ram_block1a4.PORTBADDR6 address_b[6] => ram_block1a5.PORTBADDR6 address_b[6] => ram_block1a6.PORTBADDR6 address_b[6] => ram_block1a7.PORTBADDR6 address_b[6] => ram_block1a8.PORTBADDR6 address_b[6] => ram_block1a9.PORTBADDR6 address_b[6] => ram_block1a10.PORTBADDR6 address_b[6] => ram_block1a11.PORTBADDR6 address_b[6] => ram_block1a12.PORTBADDR6 address_b[6] => ram_block1a13.PORTBADDR6 address_b[6] => ram_block1a14.PORTBADDR6 address_b[6] => ram_block1a15.PORTBADDR6 address_b[6] => ram_block1a16.PORTBADDR6 address_b[6] => ram_block1a17.PORTBADDR6 address_b[6] => ram_block1a18.PORTBADDR6 address_b[6] => ram_block1a19.PORTBADDR6 address_b[6] => ram_block1a20.PORTBADDR6 address_b[6] => ram_block1a21.PORTBADDR6 address_b[6] => ram_block1a22.PORTBADDR6 address_b[6] => ram_block1a23.PORTBADDR6 address_b[6] => ram_block1a24.PORTBADDR6 address_b[6] => ram_block1a25.PORTBADDR6 address_b[6] => ram_block1a26.PORTBADDR6 address_b[6] => ram_block1a27.PORTBADDR6 address_b[6] => ram_block1a28.PORTBADDR6 address_b[6] => ram_block1a29.PORTBADDR6 address_b[6] => ram_block1a30.PORTBADDR6 address_b[6] => ram_block1a31.PORTBADDR6 address_b[7] => ram_block1a0.PORTBADDR7 address_b[7] => ram_block1a1.PORTBADDR7 address_b[7] => ram_block1a2.PORTBADDR7 address_b[7] => ram_block1a3.PORTBADDR7 address_b[7] => ram_block1a4.PORTBADDR7 address_b[7] => ram_block1a5.PORTBADDR7 address_b[7] => ram_block1a6.PORTBADDR7 address_b[7] => ram_block1a7.PORTBADDR7 address_b[7] => ram_block1a8.PORTBADDR7 address_b[7] => ram_block1a9.PORTBADDR7 address_b[7] => ram_block1a10.PORTBADDR7 address_b[7] => ram_block1a11.PORTBADDR7 address_b[7] => ram_block1a12.PORTBADDR7 address_b[7] => ram_block1a13.PORTBADDR7 address_b[7] => ram_block1a14.PORTBADDR7 address_b[7] => ram_block1a15.PORTBADDR7 address_b[7] => ram_block1a16.PORTBADDR7 address_b[7] => ram_block1a17.PORTBADDR7 address_b[7] => ram_block1a18.PORTBADDR7 address_b[7] => ram_block1a19.PORTBADDR7 address_b[7] => ram_block1a20.PORTBADDR7 address_b[7] => ram_block1a21.PORTBADDR7 address_b[7] => ram_block1a22.PORTBADDR7 address_b[7] => ram_block1a23.PORTBADDR7 address_b[7] => ram_block1a24.PORTBADDR7 address_b[7] => ram_block1a25.PORTBADDR7 address_b[7] => ram_block1a26.PORTBADDR7 address_b[7] => ram_block1a27.PORTBADDR7 address_b[7] => ram_block1a28.PORTBADDR7 address_b[7] => ram_block1a29.PORTBADDR7 address_b[7] => ram_block1a30.PORTBADDR7 address_b[7] => ram_block1a31.PORTBADDR7 byteena_a[0] => ram_block1a0.PORTABYTEENAMASKS byteena_a[0] => ram_block1a1.PORTABYTEENAMASKS byteena_a[0] => ram_block1a2.PORTABYTEENAMASKS byteena_a[0] => ram_block1a3.PORTABYTEENAMASKS byteena_a[0] => ram_block1a4.PORTABYTEENAMASKS byteena_a[0] => ram_block1a5.PORTABYTEENAMASKS byteena_a[0] => ram_block1a6.PORTABYTEENAMASKS byteena_a[0] => ram_block1a7.PORTABYTEENAMASKS byteena_a[1] => ram_block1a8.PORTABYTEENAMASKS byteena_a[1] => ram_block1a9.PORTABYTEENAMASKS byteena_a[1] => ram_block1a10.PORTABYTEENAMASKS byteena_a[1] => ram_block1a11.PORTABYTEENAMASKS byteena_a[1] => ram_block1a12.PORTABYTEENAMASKS byteena_a[1] => ram_block1a13.PORTABYTEENAMASKS byteena_a[1] => ram_block1a14.PORTABYTEENAMASKS byteena_a[1] => ram_block1a15.PORTABYTEENAMASKS byteena_a[2] => ram_block1a16.PORTABYTEENAMASKS byteena_a[2] => ram_block1a17.PORTABYTEENAMASKS byteena_a[2] => ram_block1a18.PORTABYTEENAMASKS byteena_a[2] => ram_block1a19.PORTABYTEENAMASKS byteena_a[2] => ram_block1a20.PORTABYTEENAMASKS byteena_a[2] => ram_block1a21.PORTABYTEENAMASKS byteena_a[2] => ram_block1a22.PORTABYTEENAMASKS byteena_a[2] => ram_block1a23.PORTABYTEENAMASKS byteena_a[3] => ram_block1a24.PORTABYTEENAMASKS byteena_a[3] => ram_block1a25.PORTABYTEENAMASKS byteena_a[3] => ram_block1a26.PORTABYTEENAMASKS byteena_a[3] => ram_block1a27.PORTABYTEENAMASKS byteena_a[3] => ram_block1a28.PORTABYTEENAMASKS byteena_a[3] => ram_block1a29.PORTABYTEENAMASKS byteena_a[3] => ram_block1a30.PORTABYTEENAMASKS byteena_a[3] => ram_block1a31.PORTABYTEENAMASKS clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 clock0 => ram_block1a8.CLK0 clock0 => ram_block1a9.CLK0 clock0 => ram_block1a10.CLK0 clock0 => ram_block1a11.CLK0 clock0 => ram_block1a12.CLK0 clock0 => ram_block1a13.CLK0 clock0 => ram_block1a14.CLK0 clock0 => ram_block1a15.CLK0 clock0 => ram_block1a16.CLK0 clock0 => ram_block1a17.CLK0 clock0 => ram_block1a18.CLK0 clock0 => ram_block1a19.CLK0 clock0 => ram_block1a20.CLK0 clock0 => ram_block1a21.CLK0 clock0 => ram_block1a22.CLK0 clock0 => ram_block1a23.CLK0 clock0 => ram_block1a24.CLK0 clock0 => ram_block1a25.CLK0 clock0 => ram_block1a26.CLK0 clock0 => ram_block1a27.CLK0 clock0 => ram_block1a28.CLK0 clock0 => ram_block1a29.CLK0 clock0 => ram_block1a30.CLK0 clock0 => ram_block1a31.CLK0 clock1 => ram_block1a0.CLK1 clock1 => ram_block1a1.CLK1 clock1 => ram_block1a2.CLK1 clock1 => ram_block1a3.CLK1 clock1 => ram_block1a4.CLK1 clock1 => ram_block1a5.CLK1 clock1 => ram_block1a6.CLK1 clock1 => ram_block1a7.CLK1 clock1 => ram_block1a8.CLK1 clock1 => ram_block1a9.CLK1 clock1 => ram_block1a10.CLK1 clock1 => ram_block1a11.CLK1 clock1 => ram_block1a12.CLK1 clock1 => ram_block1a13.CLK1 clock1 => ram_block1a14.CLK1 clock1 => ram_block1a15.CLK1 clock1 => ram_block1a16.CLK1 clock1 => ram_block1a17.CLK1 clock1 => ram_block1a18.CLK1 clock1 => ram_block1a19.CLK1 clock1 => ram_block1a20.CLK1 clock1 => ram_block1a21.CLK1 clock1 => ram_block1a22.CLK1 clock1 => ram_block1a23.CLK1 clock1 => ram_block1a24.CLK1 clock1 => ram_block1a25.CLK1 clock1 => ram_block1a26.CLK1 clock1 => ram_block1a27.CLK1 clock1 => ram_block1a28.CLK1 clock1 => ram_block1a29.CLK1 clock1 => ram_block1a30.CLK1 clock1 => ram_block1a31.CLK1 clocken0 => ram_block1a0.ENA0 clocken0 => ram_block1a1.ENA0 clocken0 => ram_block1a2.ENA0 clocken0 => ram_block1a3.ENA0 clocken0 => ram_block1a4.ENA0 clocken0 => ram_block1a5.ENA0 clocken0 => ram_block1a6.ENA0 clocken0 => ram_block1a7.ENA0 clocken0 => ram_block1a8.ENA0 clocken0 => ram_block1a9.ENA0 clocken0 => ram_block1a10.ENA0 clocken0 => ram_block1a11.ENA0 clocken0 => ram_block1a12.ENA0 clocken0 => ram_block1a13.ENA0 clocken0 => ram_block1a14.ENA0 clocken0 => ram_block1a15.ENA0 clocken0 => ram_block1a16.ENA0 clocken0 => ram_block1a17.ENA0 clocken0 => ram_block1a18.ENA0 clocken0 => ram_block1a19.ENA0 clocken0 => ram_block1a20.ENA0 clocken0 => ram_block1a21.ENA0 clocken0 => ram_block1a22.ENA0 clocken0 => ram_block1a23.ENA0 clocken0 => ram_block1a24.ENA0 clocken0 => ram_block1a25.ENA0 clocken0 => ram_block1a26.ENA0 clocken0 => ram_block1a27.ENA0 clocken0 => ram_block1a28.ENA0 clocken0 => ram_block1a29.ENA0 clocken0 => ram_block1a30.ENA0 clocken0 => ram_block1a31.ENA0 clocken1 => ram_block1a0.ENA1 clocken1 => ram_block1a1.ENA1 clocken1 => ram_block1a2.ENA1 clocken1 => ram_block1a3.ENA1 clocken1 => ram_block1a4.ENA1 clocken1 => ram_block1a5.ENA1 clocken1 => ram_block1a6.ENA1 clocken1 => ram_block1a7.ENA1 clocken1 => ram_block1a8.ENA1 clocken1 => ram_block1a9.ENA1 clocken1 => ram_block1a10.ENA1 clocken1 => ram_block1a11.ENA1 clocken1 => ram_block1a12.ENA1 clocken1 => ram_block1a13.ENA1 clocken1 => ram_block1a14.ENA1 clocken1 => ram_block1a15.ENA1 clocken1 => ram_block1a16.ENA1 clocken1 => ram_block1a17.ENA1 clocken1 => ram_block1a18.ENA1 clocken1 => ram_block1a19.ENA1 clocken1 => ram_block1a20.ENA1 clocken1 => ram_block1a21.ENA1 clocken1 => ram_block1a22.ENA1 clocken1 => ram_block1a23.ENA1 clocken1 => ram_block1a24.ENA1 clocken1 => ram_block1a25.ENA1 clocken1 => ram_block1a26.ENA1 clocken1 => ram_block1a27.ENA1 clocken1 => ram_block1a28.ENA1 clocken1 => ram_block1a29.ENA1 clocken1 => ram_block1a30.ENA1 clocken1 => ram_block1a31.ENA1 data_a[0] => ram_block1a0.PORTADATAIN data_a[1] => ram_block1a1.PORTADATAIN data_a[2] => ram_block1a2.PORTADATAIN data_a[3] => ram_block1a3.PORTADATAIN data_a[4] => ram_block1a4.PORTADATAIN data_a[5] => ram_block1a5.PORTADATAIN data_a[6] => ram_block1a6.PORTADATAIN data_a[7] => ram_block1a7.PORTADATAIN data_a[8] => ram_block1a8.PORTADATAIN data_a[9] => ram_block1a9.PORTADATAIN data_a[10] => ram_block1a10.PORTADATAIN data_a[11] => ram_block1a11.PORTADATAIN data_a[12] => ram_block1a12.PORTADATAIN data_a[13] => ram_block1a13.PORTADATAIN data_a[14] => ram_block1a14.PORTADATAIN data_a[15] => ram_block1a15.PORTADATAIN data_a[16] => ram_block1a16.PORTADATAIN data_a[17] => ram_block1a17.PORTADATAIN data_a[18] => ram_block1a18.PORTADATAIN data_a[19] => ram_block1a19.PORTADATAIN data_a[20] => ram_block1a20.PORTADATAIN data_a[21] => ram_block1a21.PORTADATAIN data_a[22] => ram_block1a22.PORTADATAIN data_a[23] => ram_block1a23.PORTADATAIN data_a[24] => ram_block1a24.PORTADATAIN data_a[25] => ram_block1a25.PORTADATAIN data_a[26] => ram_block1a26.PORTADATAIN data_a[27] => ram_block1a27.PORTADATAIN data_a[28] => ram_block1a28.PORTADATAIN data_a[29] => ram_block1a29.PORTADATAIN data_a[30] => ram_block1a30.PORTADATAIN data_a[31] => ram_block1a31.PORTADATAIN data_b[0] => ram_block1a0.PORTBDATAIN data_b[1] => ram_block1a1.PORTBDATAIN data_b[2] => ram_block1a2.PORTBDATAIN data_b[3] => ram_block1a3.PORTBDATAIN data_b[4] => ram_block1a4.PORTBDATAIN data_b[5] => ram_block1a5.PORTBDATAIN data_b[6] => ram_block1a6.PORTBDATAIN data_b[7] => ram_block1a7.PORTBDATAIN data_b[8] => ram_block1a8.PORTBDATAIN data_b[9] => ram_block1a9.PORTBDATAIN data_b[10] => ram_block1a10.PORTBDATAIN data_b[11] => ram_block1a11.PORTBDATAIN data_b[12] => ram_block1a12.PORTBDATAIN data_b[13] => ram_block1a13.PORTBDATAIN data_b[14] => ram_block1a14.PORTBDATAIN data_b[15] => ram_block1a15.PORTBDATAIN data_b[16] => ram_block1a16.PORTBDATAIN data_b[17] => ram_block1a17.PORTBDATAIN data_b[18] => ram_block1a18.PORTBDATAIN data_b[19] => ram_block1a19.PORTBDATAIN data_b[20] => ram_block1a20.PORTBDATAIN data_b[21] => ram_block1a21.PORTBDATAIN data_b[22] => ram_block1a22.PORTBDATAIN data_b[23] => ram_block1a23.PORTBDATAIN data_b[24] => ram_block1a24.PORTBDATAIN data_b[25] => ram_block1a25.PORTBDATAIN data_b[26] => ram_block1a26.PORTBDATAIN data_b[27] => ram_block1a27.PORTBDATAIN data_b[28] => ram_block1a28.PORTBDATAIN data_b[29] => ram_block1a29.PORTBDATAIN data_b[30] => ram_block1a30.PORTBDATAIN data_b[31] => ram_block1a31.PORTBDATAIN q_a[0] <= ram_block1a0.PORTADATAOUT q_a[1] <= ram_block1a1.PORTADATAOUT q_a[2] <= ram_block1a2.PORTADATAOUT q_a[3] <= ram_block1a3.PORTADATAOUT q_a[4] <= ram_block1a4.PORTADATAOUT q_a[5] <= ram_block1a5.PORTADATAOUT q_a[6] <= ram_block1a6.PORTADATAOUT q_a[7] <= ram_block1a7.PORTADATAOUT q_a[8] <= ram_block1a8.PORTADATAOUT q_a[9] <= ram_block1a9.PORTADATAOUT q_a[10] <= ram_block1a10.PORTADATAOUT q_a[11] <= ram_block1a11.PORTADATAOUT q_a[12] <= ram_block1a12.PORTADATAOUT q_a[13] <= ram_block1a13.PORTADATAOUT q_a[14] <= ram_block1a14.PORTADATAOUT q_a[15] <= ram_block1a15.PORTADATAOUT q_a[16] <= ram_block1a16.PORTADATAOUT q_a[17] <= ram_block1a17.PORTADATAOUT q_a[18] <= ram_block1a18.PORTADATAOUT q_a[19] <= ram_block1a19.PORTADATAOUT q_a[20] <= ram_block1a20.PORTADATAOUT q_a[21] <= ram_block1a21.PORTADATAOUT q_a[22] <= ram_block1a22.PORTADATAOUT q_a[23] <= ram_block1a23.PORTADATAOUT q_a[24] <= ram_block1a24.PORTADATAOUT q_a[25] <= ram_block1a25.PORTADATAOUT q_a[26] <= ram_block1a26.PORTADATAOUT q_a[27] <= ram_block1a27.PORTADATAOUT q_a[28] <= ram_block1a28.PORTADATAOUT q_a[29] <= ram_block1a29.PORTADATAOUT q_a[30] <= ram_block1a30.PORTADATAOUT q_a[31] <= ram_block1a31.PORTADATAOUT q_b[0] <= ram_block1a0.PORTBDATAOUT q_b[1] <= ram_block1a1.PORTBDATAOUT q_b[2] <= ram_block1a2.PORTBDATAOUT q_b[3] <= ram_block1a3.PORTBDATAOUT q_b[4] <= ram_block1a4.PORTBDATAOUT q_b[5] <= ram_block1a5.PORTBDATAOUT q_b[6] <= ram_block1a6.PORTBDATAOUT q_b[7] <= ram_block1a7.PORTBDATAOUT q_b[8] <= ram_block1a8.PORTBDATAOUT q_b[9] <= ram_block1a9.PORTBDATAOUT q_b[10] <= ram_block1a10.PORTBDATAOUT q_b[11] <= ram_block1a11.PORTBDATAOUT q_b[12] <= ram_block1a12.PORTBDATAOUT q_b[13] <= ram_block1a13.PORTBDATAOUT q_b[14] <= ram_block1a14.PORTBDATAOUT q_b[15] <= ram_block1a15.PORTBDATAOUT q_b[16] <= ram_block1a16.PORTBDATAOUT q_b[17] <= ram_block1a17.PORTBDATAOUT q_b[18] <= ram_block1a18.PORTBDATAOUT q_b[19] <= ram_block1a19.PORTBDATAOUT q_b[20] <= ram_block1a20.PORTBDATAOUT q_b[21] <= ram_block1a21.PORTBDATAOUT q_b[22] <= ram_block1a22.PORTBDATAOUT q_b[23] <= ram_block1a23.PORTBDATAOUT q_b[24] <= ram_block1a24.PORTBDATAOUT q_b[25] <= ram_block1a25.PORTBDATAOUT q_b[26] <= ram_block1a26.PORTBDATAOUT q_b[27] <= ram_block1a27.PORTBDATAOUT q_b[28] <= ram_block1a28.PORTBDATAOUT q_b[29] <= ram_block1a29.PORTBDATAOUT q_b[30] <= ram_block1a30.PORTBDATAOUT q_b[31] <= ram_block1a31.PORTBDATAOUT wren_a => ram_block1a0.PORTAWE wren_a => ram_block1a1.PORTAWE wren_a => ram_block1a2.PORTAWE wren_a => ram_block1a3.PORTAWE wren_a => ram_block1a4.PORTAWE wren_a => ram_block1a5.PORTAWE wren_a => ram_block1a6.PORTAWE wren_a => ram_block1a7.PORTAWE wren_a => ram_block1a8.PORTAWE wren_a => ram_block1a9.PORTAWE wren_a => ram_block1a10.PORTAWE wren_a => ram_block1a11.PORTAWE wren_a => ram_block1a12.PORTAWE wren_a => ram_block1a13.PORTAWE wren_a => ram_block1a14.PORTAWE wren_a => ram_block1a15.PORTAWE wren_a => ram_block1a16.PORTAWE wren_a => ram_block1a17.PORTAWE wren_a => ram_block1a18.PORTAWE wren_a => ram_block1a19.PORTAWE wren_a => ram_block1a20.PORTAWE wren_a => ram_block1a21.PORTAWE wren_a => ram_block1a22.PORTAWE wren_a => ram_block1a23.PORTAWE wren_a => ram_block1a24.PORTAWE wren_a => ram_block1a25.PORTAWE wren_a => ram_block1a26.PORTAWE wren_a => ram_block1a27.PORTAWE wren_a => ram_block1a28.PORTAWE wren_a => ram_block1a29.PORTAWE wren_a => ram_block1a30.PORTAWE wren_a => ram_block1a31.PORTAWE wren_b => ram_block1a0.PORTBRE wren_b => ram_block1a1.PORTBRE wren_b => ram_block1a2.PORTBRE wren_b => ram_block1a3.PORTBRE wren_b => ram_block1a4.PORTBRE wren_b => ram_block1a5.PORTBRE wren_b => ram_block1a6.PORTBRE wren_b => ram_block1a7.PORTBRE wren_b => ram_block1a8.PORTBRE wren_b => ram_block1a9.PORTBRE wren_b => ram_block1a10.PORTBRE wren_b => ram_block1a11.PORTBRE wren_b => ram_block1a12.PORTBRE wren_b => ram_block1a13.PORTBRE wren_b => ram_block1a14.PORTBRE wren_b => ram_block1a15.PORTBRE wren_b => ram_block1a16.PORTBRE wren_b => ram_block1a17.PORTBRE wren_b => ram_block1a18.PORTBRE wren_b => ram_block1a19.PORTBRE wren_b => ram_block1a20.PORTBRE wren_b => ram_block1a21.PORTBRE wren_b => ram_block1a22.PORTBRE wren_b => ram_block1a23.PORTBRE wren_b => ram_block1a24.PORTBRE wren_b => ram_block1a25.PORTBRE wren_b => ram_block1a26.PORTBRE wren_b => ram_block1a27.PORTBRE wren_b => ram_block1a28.PORTBRE wren_b => ram_block1a29.PORTBRE wren_b => ram_block1a30.PORTBRE wren_b => ram_block1a31.PORTBRE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg address[0] => Equal0.IN1 address[0] => Equal1.IN0 address[1] => Equal0.IN2 address[1] => Equal1.IN2 address[2] => Equal0.IN3 address[2] => Equal1.IN3 address[3] => Equal0.IN4 address[3] => Equal1.IN4 address[4] => Equal0.IN5 address[4] => Equal1.IN5 address[5] => Equal0.IN6 address[5] => Equal1.IN6 address[6] => Equal0.IN7 address[6] => Equal1.IN7 address[7] => Equal0.IN8 address[7] => Equal1.IN8 address[8] => Equal0.IN0 address[8] => Equal1.IN1 chipselect => write_strobe~0.IN0 clk => oci_single_step_mode~reg0.CLK clk => oci_ienable[31]~reg0.CLK clk => oci_ienable[30]~reg0.CLK clk => oci_ienable[29]~reg0.CLK clk => oci_ienable[28]~reg0.CLK clk => oci_ienable[27]~reg0.CLK clk => oci_ienable[26]~reg0.CLK clk => oci_ienable[25]~reg0.CLK clk => oci_ienable[24]~reg0.CLK clk => oci_ienable[23]~reg0.CLK clk => oci_ienable[22]~reg0.CLK clk => oci_ienable[21]~reg0.CLK clk => oci_ienable[20]~reg0.CLK clk => oci_ienable[19]~reg0.CLK clk => oci_ienable[18]~reg0.CLK clk => oci_ienable[17]~reg0.CLK clk => oci_ienable[16]~reg0.CLK clk => oci_ienable[15]~reg0.CLK clk => oci_ienable[14]~reg0.CLK clk => oci_ienable[13]~reg0.CLK clk => oci_ienable[12]~reg0.CLK clk => oci_ienable[11]~reg0.CLK clk => oci_ienable[10]~reg0.CLK clk => oci_ienable[9]~reg0.CLK clk => oci_ienable[8]~reg0.CLK clk => oci_ienable[7]~reg0.CLK clk => oci_ienable[6]~reg0.CLK clk => oci_ienable[5]~reg0.CLK clk => oci_ienable[4]~reg0.CLK clk => oci_ienable[3]~reg0.CLK clk => oci_ienable[2]~reg0.CLK clk => oci_ienable[1]~reg0.CLK clk => oci_ienable[0]~reg0.CLK debugaccess => write_strobe.IN1 monitor_error => oci_reg_readdata~63.DATAB monitor_go => oci_reg_readdata~61.DATAB monitor_ready => oci_reg_readdata~62.DATAB reset_n => oci_single_step_mode~reg0.ACLR reset_n => oci_ienable[31]~reg0.PRESET reset_n => oci_ienable[30]~reg0.PRESET reset_n => oci_ienable[29]~reg0.PRESET reset_n => oci_ienable[28]~reg0.PRESET reset_n => oci_ienable[27]~reg0.PRESET reset_n => oci_ienable[26]~reg0.PRESET reset_n => oci_ienable[25]~reg0.PRESET reset_n => oci_ienable[24]~reg0.PRESET reset_n => oci_ienable[23]~reg0.PRESET reset_n => oci_ienable[22]~reg0.PRESET reset_n => oci_ienable[21]~reg0.PRESET reset_n => oci_ienable[20]~reg0.PRESET reset_n => oci_ienable[19]~reg0.PRESET reset_n => oci_ienable[18]~reg0.PRESET reset_n => oci_ienable[17]~reg0.PRESET reset_n => oci_ienable[16]~reg0.PRESET reset_n => oci_ienable[15]~reg0.PRESET reset_n => oci_ienable[14]~reg0.PRESET reset_n => oci_ienable[13]~reg0.PRESET reset_n => oci_ienable[12]~reg0.PRESET reset_n => oci_ienable[11]~reg0.PRESET reset_n => oci_ienable[10]~reg0.PRESET reset_n => oci_ienable[9]~reg0.PRESET reset_n => oci_ienable[8]~reg0.PRESET reset_n => oci_ienable[7]~reg0.PRESET reset_n => oci_ienable[6]~reg0.PRESET reset_n => oci_ienable[5]~reg0.PRESET reset_n => oci_ienable[4]~reg0.PRESET reset_n => oci_ienable[3]~reg0.PRESET reset_n => oci_ienable[2]~reg0.PRESET reset_n => oci_ienable[1]~reg0.PRESET reset_n => oci_ienable[0]~reg0.PRESET write => write_strobe~0.IN1 writedata[0] => ocireg_mrs.DATAIN writedata[0] => oci_ienable[0]~reg0.DATAIN writedata[1] => ocireg_ers.DATAIN writedata[1] => oci_ienable[1]~reg0.DATAIN writedata[2] => oci_ienable[2]~reg0.DATAIN writedata[3] => oci_single_step_mode~reg0.DATAIN writedata[3] => oci_ienable[3]~reg0.DATAIN writedata[4] => ~NO_FANOUT~ writedata[5] => ~NO_FANOUT~ writedata[6] => ~NO_FANOUT~ writedata[7] => ~NO_FANOUT~ writedata[8] => ~NO_FANOUT~ writedata[9] => ~NO_FANOUT~ writedata[10] => ~NO_FANOUT~ writedata[11] => ~NO_FANOUT~ writedata[12] => ~NO_FANOUT~ writedata[13] => ~NO_FANOUT~ writedata[14] => ~NO_FANOUT~ writedata[15] => ~NO_FANOUT~ writedata[16] => ~NO_FANOUT~ writedata[17] => ~NO_FANOUT~ writedata[18] => ~NO_FANOUT~ writedata[19] => ~NO_FANOUT~ writedata[20] => ~NO_FANOUT~ writedata[21] => ~NO_FANOUT~ writedata[22] => ~NO_FANOUT~ writedata[23] => ~NO_FANOUT~ writedata[24] => ~NO_FANOUT~ writedata[25] => ~NO_FANOUT~ writedata[26] => ~NO_FANOUT~ writedata[27] => ~NO_FANOUT~ writedata[28] => ~NO_FANOUT~ writedata[29] => ~NO_FANOUT~ writedata[30] => ~NO_FANOUT~ writedata[31] => ~NO_FANOUT~ oci_ienable[0] <= oci_ienable[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[1] <= oci_ienable[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[2] <= oci_ienable[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[3] <= oci_ienable[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[4] <= oci_ienable[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[5] <= oci_ienable[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[6] <= oci_ienable[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[7] <= oci_ienable[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[8] <= oci_ienable[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[9] <= oci_ienable[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[10] <= oci_ienable[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[11] <= oci_ienable[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[12] <= oci_ienable[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[13] <= oci_ienable[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[14] <= oci_ienable[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[15] <= oci_ienable[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[16] <= oci_ienable[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[17] <= oci_ienable[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[18] <= oci_ienable[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[19] <= oci_ienable[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[20] <= oci_ienable[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[21] <= oci_ienable[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[22] <= oci_ienable[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[23] <= oci_ienable[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[24] <= oci_ienable[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[25] <= oci_ienable[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[26] <= oci_ienable[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[27] <= oci_ienable[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[28] <= oci_ienable[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[29] <= oci_ienable[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[30] <= oci_ienable[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_ienable[31] <= oci_ienable[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[0] <= oci_reg_readdata~63.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[1] <= oci_reg_readdata~62.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[2] <= oci_reg_readdata~61.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[3] <= oci_reg_readdata~60.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[4] <= oci_reg_readdata~59.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[5] <= oci_reg_readdata~58.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[6] <= oci_reg_readdata~57.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[7] <= oci_reg_readdata~56.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[8] <= oci_reg_readdata~55.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[9] <= oci_reg_readdata~54.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[10] <= oci_reg_readdata~53.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[11] <= oci_reg_readdata~52.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[12] <= oci_reg_readdata~51.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[13] <= oci_reg_readdata~50.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[14] <= oci_reg_readdata~49.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[15] <= oci_reg_readdata~48.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[16] <= oci_reg_readdata~47.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[17] <= oci_reg_readdata~46.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[18] <= oci_reg_readdata~45.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[19] <= oci_reg_readdata~44.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[20] <= oci_reg_readdata~43.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[21] <= oci_reg_readdata~42.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[22] <= oci_reg_readdata~41.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[23] <= oci_reg_readdata~40.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[24] <= oci_reg_readdata~39.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[25] <= oci_reg_readdata~38.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[26] <= oci_reg_readdata~37.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[27] <= oci_reg_readdata~36.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[28] <= oci_reg_readdata~35.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[29] <= oci_reg_readdata~34.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[30] <= oci_reg_readdata~33.DB_MAX_OUTPUT_PORT_TYPE oci_reg_readdata[31] <= oci_reg_readdata~32.DB_MAX_OUTPUT_PORT_TYPE oci_single_step_mode <= oci_single_step_mode~reg0.DB_MAX_OUTPUT_PORT_TYPE ocireg_ers <= writedata[1].DB_MAX_OUTPUT_PORT_TYPE ocireg_mrs <= writedata[0].DB_MAX_OUTPUT_PORT_TYPE take_action_ocireg <= take_action_ocireg~0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break clk => trigbrktype~reg0.CLK clk => dbrk_hit0_latch~reg0.CLK clk => dbrk_hit1_latch~reg0.CLK clk => dbrk_hit2_latch~reg0.CLK clk => dbrk_hit3_latch~reg0.CLK clk => break_readreg[31]~reg0.CLK clk => break_readreg[30]~reg0.CLK clk => break_readreg[29]~reg0.CLK clk => break_readreg[28]~reg0.CLK clk => break_readreg[27]~reg0.CLK clk => break_readreg[26]~reg0.CLK clk => break_readreg[25]~reg0.CLK clk => break_readreg[24]~reg0.CLK clk => break_readreg[23]~reg0.CLK clk => break_readreg[22]~reg0.CLK clk => break_readreg[21]~reg0.CLK clk => break_readreg[20]~reg0.CLK clk => break_readreg[19]~reg0.CLK clk => break_readreg[18]~reg0.CLK clk => break_readreg[17]~reg0.CLK clk => break_readreg[16]~reg0.CLK clk => break_readreg[15]~reg0.CLK clk => break_readreg[14]~reg0.CLK clk => break_readreg[13]~reg0.CLK clk => break_readreg[12]~reg0.CLK clk => break_readreg[11]~reg0.CLK clk => break_readreg[10]~reg0.CLK clk => break_readreg[9]~reg0.CLK clk => break_readreg[8]~reg0.CLK clk => break_readreg[7]~reg0.CLK clk => break_readreg[6]~reg0.CLK clk => break_readreg[5]~reg0.CLK clk => break_readreg[4]~reg0.CLK clk => break_readreg[3]~reg0.CLK clk => break_readreg[2]~reg0.CLK clk => break_readreg[1]~reg0.CLK clk => break_readreg[0]~reg0.CLK clk => trigger_state.CLK dbrk_break => trigbrktype~0.OUTPUTSELECT dbrk_goto0 => always3~0.IN0 dbrk_goto1 => always3~2.IN0 dbrk_hit0 => ~NO_FANOUT~ dbrk_hit1 => ~NO_FANOUT~ dbrk_hit2 => ~NO_FANOUT~ dbrk_hit3 => ~NO_FANOUT~ jdo[0] => break_readreg~127.DATAB jdo[0] => break_readreg~63.DATAB jdo[0] => break_readreg~31.DATAB jdo[1] => break_readreg~126.DATAB jdo[1] => break_readreg~62.DATAB jdo[1] => break_readreg~30.DATAB jdo[2] => break_readreg~125.DATAB jdo[2] => break_readreg~61.DATAB jdo[2] => break_readreg~29.DATAB jdo[3] => break_readreg~124.DATAB jdo[3] => break_readreg~60.DATAB jdo[3] => break_readreg~28.DATAB jdo[4] => break_readreg~123.DATAB jdo[4] => break_readreg~59.DATAB jdo[4] => break_readreg~27.DATAB jdo[5] => break_readreg~122.DATAB jdo[5] => break_readreg~58.DATAB jdo[5] => break_readreg~26.DATAB jdo[6] => break_readreg~121.DATAB jdo[6] => break_readreg~57.DATAB jdo[6] => break_readreg~25.DATAB jdo[7] => break_readreg~120.DATAB jdo[7] => break_readreg~56.DATAB jdo[7] => break_readreg~24.DATAB jdo[8] => break_readreg~119.DATAB jdo[8] => break_readreg~55.DATAB jdo[8] => break_readreg~23.DATAB jdo[9] => break_readreg~118.DATAB jdo[9] => break_readreg~54.DATAB jdo[9] => break_readreg~22.DATAB jdo[10] => break_readreg~117.DATAB jdo[10] => break_readreg~53.DATAB jdo[10] => break_readreg~21.DATAB jdo[11] => break_readreg~116.DATAB jdo[11] => break_readreg~52.DATAB jdo[11] => break_readreg~20.DATAB jdo[12] => break_readreg~115.DATAB jdo[12] => break_readreg~51.DATAB jdo[12] => break_readreg~19.DATAB jdo[13] => break_readreg~114.DATAB jdo[13] => break_readreg~50.DATAB jdo[13] => break_readreg~18.DATAB jdo[14] => break_readreg~113.DATAB jdo[14] => break_readreg~49.DATAB jdo[14] => break_readreg~17.DATAB jdo[15] => break_readreg~112.DATAB jdo[15] => break_readreg~48.DATAB jdo[15] => break_readreg~16.DATAB jdo[16] => break_readreg~111.DATAB jdo[16] => break_readreg~47.DATAB jdo[16] => break_readreg~15.DATAB jdo[17] => break_readreg~110.DATAB jdo[17] => break_readreg~46.DATAB jdo[17] => break_readreg~14.DATAB jdo[18] => break_readreg~109.DATAB jdo[18] => break_readreg~45.DATAB jdo[18] => break_readreg~13.DATAB jdo[19] => break_readreg~108.DATAB jdo[19] => break_readreg~44.DATAB jdo[19] => break_readreg~12.DATAB jdo[20] => break_readreg~107.DATAB jdo[20] => break_readreg~43.DATAB jdo[20] => break_readreg~11.DATAB jdo[21] => break_readreg~106.DATAB jdo[21] => break_readreg~42.DATAB jdo[21] => break_readreg~10.DATAB jdo[22] => break_readreg~105.DATAB jdo[22] => break_readreg~41.DATAB jdo[22] => break_readreg~9.DATAB jdo[23] => break_readreg~104.DATAB jdo[23] => break_readreg~40.DATAB jdo[23] => break_readreg~8.DATAB jdo[24] => break_readreg~103.DATAB jdo[24] => break_readreg~39.DATAB jdo[24] => break_readreg~7.DATAB jdo[25] => break_readreg~102.DATAB jdo[25] => break_readreg~38.DATAB jdo[25] => break_readreg~6.DATAB jdo[26] => break_readreg~101.DATAB jdo[26] => break_readreg~37.DATAB jdo[26] => break_readreg~5.DATAB jdo[27] => break_readreg~100.DATAB jdo[27] => break_readreg~36.DATAB jdo[27] => break_readreg~4.DATAB jdo[28] => break_readreg~99.DATAB jdo[28] => break_readreg~35.DATAB jdo[28] => break_readreg~3.DATAB jdo[29] => break_readreg~98.DATAB jdo[29] => break_readreg~34.DATAB jdo[29] => break_readreg~2.DATAB jdo[30] => break_readreg~97.DATAB jdo[30] => break_readreg~33.DATAB jdo[30] => break_readreg~1.DATAB jdo[31] => break_readreg~96.DATAB jdo[31] => break_readreg~32.DATAB jdo[31] => break_readreg~0.DATAB jdo[32] => ~NO_FANOUT~ jdo[33] => ~NO_FANOUT~ jdo[34] => ~NO_FANOUT~ jdo[35] => ~NO_FANOUT~ jdo[36] => ~NO_FANOUT~ jdo[37] => ~NO_FANOUT~ jrst_n => trigbrktype~reg0.ACLR jrst_n => break_readreg[31]~reg0.ACLR jrst_n => break_readreg[30]~reg0.ACLR jrst_n => break_readreg[29]~reg0.ACLR jrst_n => break_readreg[28]~reg0.ACLR jrst_n => break_readreg[27]~reg0.ACLR jrst_n => break_readreg[26]~reg0.ACLR jrst_n => break_readreg[25]~reg0.ACLR jrst_n => break_readreg[24]~reg0.ACLR jrst_n => break_readreg[23]~reg0.ACLR jrst_n => break_readreg[22]~reg0.ACLR jrst_n => break_readreg[21]~reg0.ACLR jrst_n => break_readreg[20]~reg0.ACLR jrst_n => break_readreg[19]~reg0.ACLR jrst_n => break_readreg[18]~reg0.ACLR jrst_n => break_readreg[17]~reg0.ACLR jrst_n => break_readreg[16]~reg0.ACLR jrst_n => break_readreg[15]~reg0.ACLR jrst_n => break_readreg[14]~reg0.ACLR jrst_n => break_readreg[13]~reg0.ACLR jrst_n => break_readreg[12]~reg0.ACLR jrst_n => break_readreg[11]~reg0.ACLR jrst_n => break_readreg[10]~reg0.ACLR jrst_n => break_readreg[9]~reg0.ACLR jrst_n => break_readreg[8]~reg0.ACLR jrst_n => break_readreg[7]~reg0.ACLR jrst_n => break_readreg[6]~reg0.ACLR jrst_n => break_readreg[5]~reg0.ACLR jrst_n => break_readreg[4]~reg0.ACLR jrst_n => break_readreg[3]~reg0.ACLR jrst_n => break_readreg[2]~reg0.ACLR jrst_n => break_readreg[1]~reg0.ACLR jrst_n => break_readreg[0]~reg0.ACLR reset_n => trigger_state.ACLR take_action_break_a => take_action_any_break~0.IN0 take_action_break_b => take_action_any_break~0.IN1 take_action_break_c => take_action_any_break.IN1 take_no_action_break_a => break_readreg~95.OUTPUTSELECT take_no_action_break_a => break_readreg~94.OUTPUTSELECT take_no_action_break_a => break_readreg~93.OUTPUTSELECT take_no_action_break_a => break_readreg~92.OUTPUTSELECT take_no_action_break_a => break_readreg~91.OUTPUTSELECT take_no_action_break_a => break_readreg~90.OUTPUTSELECT take_no_action_break_a => break_readreg~89.OUTPUTSELECT take_no_action_break_a => break_readreg~88.OUTPUTSELECT take_no_action_break_a => break_readreg~87.OUTPUTSELECT take_no_action_break_a => break_readreg~86.OUTPUTSELECT take_no_action_break_a => break_readreg~85.OUTPUTSELECT take_no_action_break_a => break_readreg~84.OUTPUTSELECT take_no_action_break_a => break_readreg~83.OUTPUTSELECT take_no_action_break_a => break_readreg~82.OUTPUTSELECT take_no_action_break_a => break_readreg~81.OUTPUTSELECT take_no_action_break_a => break_readreg~80.OUTPUTSELECT take_no_action_break_a => break_readreg~79.OUTPUTSELECT take_no_action_break_a => break_readreg~78.OUTPUTSELECT take_no_action_break_a => break_readreg~77.OUTPUTSELECT take_no_action_break_a => break_readreg~76.OUTPUTSELECT take_no_action_break_a => break_readreg~75.OUTPUTSELECT take_no_action_break_a => break_readreg~74.OUTPUTSELECT take_no_action_break_a => break_readreg~73.OUTPUTSELECT take_no_action_break_a => break_readreg~72.OUTPUTSELECT take_no_action_break_a => break_readreg~71.OUTPUTSELECT take_no_action_break_a => break_readreg~70.OUTPUTSELECT take_no_action_break_a => break_readreg~69.OUTPUTSELECT take_no_action_break_a => break_readreg~68.OUTPUTSELECT take_no_action_break_a => break_readreg~67.OUTPUTSELECT take_no_action_break_a => break_readreg~66.OUTPUTSELECT take_no_action_break_a => break_readreg~65.OUTPUTSELECT take_no_action_break_a => break_readreg~64.OUTPUTSELECT take_no_action_break_b => break_readreg~63.OUTPUTSELECT take_no_action_break_b => break_readreg~62.OUTPUTSELECT take_no_action_break_b => break_readreg~61.OUTPUTSELECT take_no_action_break_b => break_readreg~60.OUTPUTSELECT take_no_action_break_b => break_readreg~59.OUTPUTSELECT take_no_action_break_b => break_readreg~58.OUTPUTSELECT take_no_action_break_b => break_readreg~57.OUTPUTSELECT take_no_action_break_b => break_readreg~56.OUTPUTSELECT take_no_action_break_b => break_readreg~55.OUTPUTSELECT take_no_action_break_b => break_readreg~54.OUTPUTSELECT take_no_action_break_b => break_readreg~53.OUTPUTSELECT take_no_action_break_b => break_readreg~52.OUTPUTSELECT take_no_action_break_b => break_readreg~51.OUTPUTSELECT take_no_action_break_b => break_readreg~50.OUTPUTSELECT take_no_action_break_b => break_readreg~49.OUTPUTSELECT take_no_action_break_b => break_readreg~48.OUTPUTSELECT take_no_action_break_b => break_readreg~47.OUTPUTSELECT take_no_action_break_b => break_readreg~46.OUTPUTSELECT take_no_action_break_b => break_readreg~45.OUTPUTSELECT take_no_action_break_b => break_readreg~44.OUTPUTSELECT take_no_action_break_b => break_readreg~43.OUTPUTSELECT take_no_action_break_b => break_readreg~42.OUTPUTSELECT take_no_action_break_b => break_readreg~41.OUTPUTSELECT take_no_action_break_b => break_readreg~40.OUTPUTSELECT take_no_action_break_b => break_readreg~39.OUTPUTSELECT take_no_action_break_b => break_readreg~38.OUTPUTSELECT take_no_action_break_b => break_readreg~37.OUTPUTSELECT take_no_action_break_b => break_readreg~36.OUTPUTSELECT take_no_action_break_b => break_readreg~35.OUTPUTSELECT take_no_action_break_b => break_readreg~34.OUTPUTSELECT take_no_action_break_b => break_readreg~33.OUTPUTSELECT take_no_action_break_b => break_readreg~32.OUTPUTSELECT take_no_action_break_c => break_readreg~31.OUTPUTSELECT take_no_action_break_c => break_readreg~30.OUTPUTSELECT take_no_action_break_c => break_readreg~29.OUTPUTSELECT take_no_action_break_c => break_readreg~28.OUTPUTSELECT take_no_action_break_c => break_readreg~27.OUTPUTSELECT take_no_action_break_c => break_readreg~26.OUTPUTSELECT take_no_action_break_c => break_readreg~25.OUTPUTSELECT take_no_action_break_c => break_readreg~24.OUTPUTSELECT take_no_action_break_c => break_readreg~23.OUTPUTSELECT take_no_action_break_c => break_readreg~22.OUTPUTSELECT take_no_action_break_c => break_readreg~21.OUTPUTSELECT take_no_action_break_c => break_readreg~20.OUTPUTSELECT take_no_action_break_c => break_readreg~19.OUTPUTSELECT take_no_action_break_c => break_readreg~18.OUTPUTSELECT take_no_action_break_c => break_readreg~17.OUTPUTSELECT take_no_action_break_c => break_readreg~16.OUTPUTSELECT take_no_action_break_c => break_readreg~15.OUTPUTSELECT take_no_action_break_c => break_readreg~14.OUTPUTSELECT take_no_action_break_c => break_readreg~13.OUTPUTSELECT take_no_action_break_c => break_readreg~12.OUTPUTSELECT take_no_action_break_c => break_readreg~11.OUTPUTSELECT take_no_action_break_c => break_readreg~10.OUTPUTSELECT take_no_action_break_c => break_readreg~9.OUTPUTSELECT take_no_action_break_c => break_readreg~8.OUTPUTSELECT take_no_action_break_c => break_readreg~7.OUTPUTSELECT take_no_action_break_c => break_readreg~6.OUTPUTSELECT take_no_action_break_c => break_readreg~5.OUTPUTSELECT take_no_action_break_c => break_readreg~4.OUTPUTSELECT take_no_action_break_c => break_readreg~3.OUTPUTSELECT take_no_action_break_c => break_readreg~2.OUTPUTSELECT take_no_action_break_c => break_readreg~1.OUTPUTSELECT take_no_action_break_c => break_readreg~0.OUTPUTSELECT xbrk_goto0 => always3~0.IN1 xbrk_goto1 => always3~2.IN1 break_readreg[0] <= break_readreg[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[1] <= break_readreg[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[2] <= break_readreg[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[3] <= break_readreg[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[4] <= break_readreg[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[5] <= break_readreg[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[6] <= break_readreg[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[7] <= break_readreg[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[8] <= break_readreg[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[9] <= break_readreg[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[10] <= break_readreg[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[11] <= break_readreg[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[12] <= break_readreg[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[13] <= break_readreg[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[14] <= break_readreg[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[15] <= break_readreg[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[16] <= break_readreg[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[17] <= break_readreg[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[18] <= break_readreg[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[19] <= break_readreg[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[20] <= break_readreg[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[21] <= break_readreg[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[22] <= break_readreg[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[23] <= break_readreg[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[24] <= break_readreg[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[25] <= break_readreg[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[26] <= break_readreg[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[27] <= break_readreg[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[28] <= break_readreg[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[29] <= break_readreg[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[30] <= break_readreg[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE break_readreg[31] <= break_readreg[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE dbrk0[0] <= dbrk0[1] <= dbrk0[2] <= dbrk0[3] <= dbrk0[4] <= dbrk0[5] <= dbrk0[6] <= dbrk0[7] <= dbrk0[8] <= dbrk0[9] <= dbrk0[10] <= dbrk0[11] <= dbrk0[12] <= dbrk0[13] <= dbrk0[14] <= dbrk0[15] <= dbrk0[16] <= dbrk0[17] <= dbrk0[18] <= dbrk0[19] <= dbrk0[20] <= dbrk0[21] <= dbrk0[22] <= dbrk0[23] <= dbrk0[24] <= dbrk0[25] <= dbrk0[26] <= dbrk0[27] <= dbrk0[28] <= dbrk0[29] <= dbrk0[30] <= dbrk0[31] <= dbrk0[32] <= dbrk0[33] <= dbrk0[34] <= dbrk0[35] <= dbrk0[36] <= dbrk0[37] <= dbrk0[38] <= dbrk0[39] <= dbrk0[40] <= dbrk0[41] <= dbrk0[42] <= dbrk0[43] <= dbrk0[44] <= dbrk0[45] <= dbrk0[46] <= dbrk0[47] <= dbrk0[48] <= dbrk0[49] <= dbrk0[50] <= dbrk0[51] <= dbrk0[52] <= dbrk0[53] <= dbrk0[54] <= dbrk0[55] <= dbrk0[56] <= dbrk0[57] <= dbrk0[58] <= dbrk0[59] <= dbrk0[60] <= dbrk0[61] <= dbrk0[62] <= dbrk0[63] <= dbrk0[64] <= dbrk0[65] <= dbrk0[66] <= dbrk0[67] <= dbrk0[68] <= dbrk0[69] <= dbrk0[70] <= dbrk0[71] <= dbrk0[72] <= dbrk0[73] <= dbrk0[74] <= dbrk0[75] <= dbrk0[76] <= dbrk0[77] <= dbrk1[0] <= dbrk1[1] <= dbrk1[2] <= dbrk1[3] <= dbrk1[4] <= dbrk1[5] <= dbrk1[6] <= dbrk1[7] <= dbrk1[8] <= dbrk1[9] <= dbrk1[10] <= dbrk1[11] <= dbrk1[12] <= dbrk1[13] <= dbrk1[14] <= dbrk1[15] <= dbrk1[16] <= dbrk1[17] <= dbrk1[18] <= dbrk1[19] <= dbrk1[20] <= dbrk1[21] <= dbrk1[22] <= dbrk1[23] <= dbrk1[24] <= dbrk1[25] <= dbrk1[26] <= dbrk1[27] <= dbrk1[28] <= dbrk1[29] <= dbrk1[30] <= dbrk1[31] <= dbrk1[32] <= dbrk1[33] <= dbrk1[34] <= dbrk1[35] <= dbrk1[36] <= dbrk1[37] <= dbrk1[38] <= dbrk1[39] <= dbrk1[40] <= dbrk1[41] <= dbrk1[42] <= dbrk1[43] <= dbrk1[44] <= dbrk1[45] <= dbrk1[46] <= dbrk1[47] <= dbrk1[48] <= dbrk1[49] <= dbrk1[50] <= dbrk1[51] <= dbrk1[52] <= dbrk1[53] <= dbrk1[54] <= dbrk1[55] <= dbrk1[56] <= dbrk1[57] <= dbrk1[58] <= dbrk1[59] <= dbrk1[60] <= dbrk1[61] <= dbrk1[62] <= dbrk1[63] <= dbrk1[64] <= dbrk1[65] <= dbrk1[66] <= dbrk1[67] <= dbrk1[68] <= dbrk1[69] <= dbrk1[70] <= dbrk1[71] <= dbrk1[72] <= dbrk1[73] <= dbrk1[74] <= dbrk1[75] <= dbrk1[76] <= dbrk1[77] <= dbrk2[0] <= dbrk2[1] <= dbrk2[2] <= dbrk2[3] <= dbrk2[4] <= dbrk2[5] <= dbrk2[6] <= dbrk2[7] <= dbrk2[8] <= dbrk2[9] <= dbrk2[10] <= dbrk2[11] <= dbrk2[12] <= dbrk2[13] <= dbrk2[14] <= dbrk2[15] <= dbrk2[16] <= dbrk2[17] <= dbrk2[18] <= dbrk2[19] <= dbrk2[20] <= dbrk2[21] <= dbrk2[22] <= dbrk2[23] <= dbrk2[24] <= dbrk2[25] <= dbrk2[26] <= dbrk2[27] <= dbrk2[28] <= dbrk2[29] <= dbrk2[30] <= dbrk2[31] <= dbrk2[32] <= dbrk2[33] <= dbrk2[34] <= dbrk2[35] <= dbrk2[36] <= dbrk2[37] <= dbrk2[38] <= dbrk2[39] <= dbrk2[40] <= dbrk2[41] <= dbrk2[42] <= dbrk2[43] <= dbrk2[44] <= dbrk2[45] <= dbrk2[46] <= dbrk2[47] <= dbrk2[48] <= dbrk2[49] <= dbrk2[50] <= dbrk2[51] <= dbrk2[52] <= dbrk2[53] <= dbrk2[54] <= dbrk2[55] <= dbrk2[56] <= dbrk2[57] <= dbrk2[58] <= dbrk2[59] <= dbrk2[60] <= dbrk2[61] <= dbrk2[62] <= dbrk2[63] <= dbrk2[64] <= dbrk2[65] <= dbrk2[66] <= dbrk2[67] <= dbrk2[68] <= dbrk2[69] <= dbrk2[70] <= dbrk2[71] <= dbrk2[72] <= dbrk2[73] <= dbrk2[74] <= dbrk2[75] <= dbrk2[76] <= dbrk2[77] <= dbrk3[0] <= dbrk3[1] <= dbrk3[2] <= dbrk3[3] <= dbrk3[4] <= dbrk3[5] <= dbrk3[6] <= dbrk3[7] <= dbrk3[8] <= dbrk3[9] <= dbrk3[10] <= dbrk3[11] <= dbrk3[12] <= dbrk3[13] <= dbrk3[14] <= dbrk3[15] <= dbrk3[16] <= dbrk3[17] <= dbrk3[18] <= dbrk3[19] <= dbrk3[20] <= dbrk3[21] <= dbrk3[22] <= dbrk3[23] <= dbrk3[24] <= dbrk3[25] <= dbrk3[26] <= dbrk3[27] <= dbrk3[28] <= dbrk3[29] <= dbrk3[30] <= dbrk3[31] <= dbrk3[32] <= dbrk3[33] <= dbrk3[34] <= dbrk3[35] <= dbrk3[36] <= dbrk3[37] <= dbrk3[38] <= dbrk3[39] <= dbrk3[40] <= dbrk3[41] <= dbrk3[42] <= dbrk3[43] <= dbrk3[44] <= dbrk3[45] <= dbrk3[46] <= dbrk3[47] <= dbrk3[48] <= dbrk3[49] <= dbrk3[50] <= dbrk3[51] <= dbrk3[52] <= dbrk3[53] <= dbrk3[54] <= dbrk3[55] <= dbrk3[56] <= dbrk3[57] <= dbrk3[58] <= dbrk3[59] <= dbrk3[60] <= dbrk3[61] <= dbrk3[62] <= dbrk3[63] <= dbrk3[64] <= dbrk3[65] <= dbrk3[66] <= dbrk3[67] <= dbrk3[68] <= dbrk3[69] <= dbrk3[70] <= dbrk3[71] <= dbrk3[72] <= dbrk3[73] <= dbrk3[74] <= dbrk3[75] <= dbrk3[76] <= dbrk3[77] <= dbrk_hit0_latch <= dbrk_hit0_latch~reg0.DB_MAX_OUTPUT_PORT_TYPE dbrk_hit1_latch <= dbrk_hit1_latch~reg0.DB_MAX_OUTPUT_PORT_TYPE dbrk_hit2_latch <= dbrk_hit2_latch~reg0.DB_MAX_OUTPUT_PORT_TYPE dbrk_hit3_latch <= dbrk_hit3_latch~reg0.DB_MAX_OUTPUT_PORT_TYPE trigbrktype <= trigbrktype~reg0.DB_MAX_OUTPUT_PORT_TYPE trigger_state_0 <= trigger_state.DB_MAX_OUTPUT_PORT_TYPE trigger_state_1 <= trigger_state.DB_MAX_OUTPUT_PORT_TYPE xbrk0[0] <= xbrk0[1] <= xbrk0[2] <= xbrk0[3] <= xbrk0[4] <= xbrk0[5] <= xbrk0[6] <= xbrk0[7] <= xbrk0[8] <= xbrk0[9] <= xbrk0[10] <= xbrk0[11] <= xbrk0[12] <= xbrk0[13] <= xbrk0[14] <= xbrk0[15] <= xbrk0[16] <= xbrk0[17] <= xbrk0[18] <= xbrk0[19] <= xbrk0[20] <= xbrk0[21] <= xbrk0[22] <= xbrk0[23] <= xbrk1[0] <= xbrk1[1] <= xbrk1[2] <= xbrk1[3] <= xbrk1[4] <= xbrk1[5] <= xbrk1[6] <= xbrk1[7] <= xbrk1[8] <= xbrk1[9] <= xbrk1[10] <= xbrk1[11] <= xbrk1[12] <= xbrk1[13] <= xbrk1[14] <= xbrk1[15] <= xbrk1[16] <= xbrk1[17] <= xbrk1[18] <= xbrk1[19] <= xbrk1[20] <= xbrk1[21] <= xbrk1[22] <= xbrk1[23] <= xbrk2[0] <= xbrk2[1] <= xbrk2[2] <= xbrk2[3] <= xbrk2[4] <= xbrk2[5] <= xbrk2[6] <= xbrk2[7] <= xbrk2[8] <= xbrk2[9] <= xbrk2[10] <= xbrk2[11] <= xbrk2[12] <= xbrk2[13] <= xbrk2[14] <= xbrk2[15] <= xbrk2[16] <= xbrk2[17] <= xbrk2[18] <= xbrk2[19] <= xbrk2[20] <= xbrk2[21] <= xbrk2[22] <= xbrk2[23] <= xbrk3[0] <= xbrk3[1] <= xbrk3[2] <= xbrk3[3] <= xbrk3[4] <= xbrk3[5] <= xbrk3[6] <= xbrk3[7] <= xbrk3[8] <= xbrk3[9] <= xbrk3[10] <= xbrk3[11] <= xbrk3[12] <= xbrk3[13] <= xbrk3[14] <= xbrk3[15] <= xbrk3[16] <= xbrk3[17] <= xbrk3[18] <= xbrk3[19] <= xbrk3[20] <= xbrk3[21] <= xbrk3[22] <= xbrk3[23] <= xbrk_ctrl0[0] <= xbrk_ctrl0[1] <= xbrk_ctrl0[2] <= xbrk_ctrl0[3] <= xbrk_ctrl0[4] <= xbrk_ctrl0[5] <= xbrk_ctrl0[6] <= xbrk_ctrl0[7] <= xbrk_ctrl1[0] <= xbrk_ctrl1[1] <= xbrk_ctrl1[2] <= xbrk_ctrl1[3] <= xbrk_ctrl1[4] <= xbrk_ctrl1[5] <= xbrk_ctrl1[6] <= xbrk_ctrl1[7] <= xbrk_ctrl2[0] <= xbrk_ctrl2[1] <= xbrk_ctrl2[2] <= xbrk_ctrl2[3] <= xbrk_ctrl2[4] <= xbrk_ctrl2[5] <= xbrk_ctrl2[6] <= xbrk_ctrl2[7] <= xbrk_ctrl3[0] <= xbrk_ctrl3[1] <= xbrk_ctrl3[2] <= xbrk_ctrl3[3] <= xbrk_ctrl3[4] <= xbrk_ctrl3[5] <= xbrk_ctrl3[6] <= xbrk_ctrl3[7] <= |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk D_en => xbrk_hit0.ENA D_en => xbrk_hit1.ENA D_en => xbrk_hit2.ENA D_en => xbrk_hit3.ENA E_en => xbrk_break~reg0.ENA E_en => E_xbrk_traceon.ENA E_en => E_xbrk_traceoff.ENA E_en => E_xbrk_trigout.ENA E_en => E_xbrk_goto0.ENA E_en => E_xbrk_goto1.ENA E_valid => M_xbrk_goto1~0.IN1 E_valid => M_xbrk_goto0~0.IN1 E_valid => M_xbrk_trigout~0.IN1 E_valid => M_xbrk_traceoff~0.IN1 E_valid => M_xbrk_traceon~0.IN1 F_pc[0] => ~NO_FANOUT~ F_pc[1] => ~NO_FANOUT~ F_pc[2] => ~NO_FANOUT~ F_pc[3] => ~NO_FANOUT~ F_pc[4] => ~NO_FANOUT~ F_pc[5] => ~NO_FANOUT~ F_pc[6] => ~NO_FANOUT~ F_pc[7] => ~NO_FANOUT~ F_pc[8] => ~NO_FANOUT~ F_pc[9] => ~NO_FANOUT~ F_pc[10] => ~NO_FANOUT~ F_pc[11] => ~NO_FANOUT~ F_pc[12] => ~NO_FANOUT~ F_pc[13] => ~NO_FANOUT~ F_pc[14] => ~NO_FANOUT~ F_pc[15] => ~NO_FANOUT~ F_pc[16] => ~NO_FANOUT~ F_pc[17] => ~NO_FANOUT~ F_pc[18] => ~NO_FANOUT~ F_pc[19] => ~NO_FANOUT~ F_pc[20] => ~NO_FANOUT~ F_pc[21] => ~NO_FANOUT~ M_en => M_xbrk_traceon.ENA M_en => M_xbrk_goto1.ENA M_en => M_xbrk_traceoff.ENA M_en => M_xbrk_trigout.ENA M_en => M_xbrk_goto0.ENA clk => xbrk_hit0.CLK clk => xbrk_hit1.CLK clk => xbrk_hit2.CLK clk => xbrk_hit3.CLK clk => xbrk_break~reg0.CLK clk => E_xbrk_traceon.CLK clk => E_xbrk_traceoff.CLK clk => E_xbrk_trigout.CLK clk => E_xbrk_goto0.CLK clk => E_xbrk_goto1.CLK clk => M_xbrk_traceon.CLK clk => M_xbrk_traceoff.CLK clk => M_xbrk_trigout.CLK clk => M_xbrk_goto0.CLK clk => M_xbrk_goto1.CLK reset_n => E_xbrk_goto1.ACLR reset_n => E_xbrk_goto0.ACLR reset_n => E_xbrk_trigout.ACLR reset_n => E_xbrk_traceoff.ACLR reset_n => E_xbrk_traceon.ACLR reset_n => xbrk_hit3.ACLR reset_n => xbrk_hit2.ACLR reset_n => xbrk_hit1.ACLR reset_n => xbrk_hit0.ACLR reset_n => M_xbrk_trigout.ACLR reset_n => M_xbrk_traceon.ACLR reset_n => M_xbrk_traceoff.ACLR reset_n => M_xbrk_goto1.ACLR reset_n => M_xbrk_goto0.ACLR reset_n => xbrk_break~reg0.ACLR trigger_state_0 => xbrk3_armed~0.IN0 trigger_state_0 => xbrk2_armed~0.IN0 trigger_state_0 => xbrk1_armed~0.IN0 trigger_state_0 => xbrk0_armed~0.IN0 trigger_state_1 => xbrk3_armed~1.IN0 trigger_state_1 => xbrk2_armed~1.IN0 trigger_state_1 => xbrk1_armed~1.IN0 trigger_state_1 => xbrk0_armed~1.IN0 xbrk0[0] => ~NO_FANOUT~ xbrk0[1] => ~NO_FANOUT~ xbrk0[2] => ~NO_FANOUT~ xbrk0[3] => ~NO_FANOUT~ xbrk0[4] => ~NO_FANOUT~ xbrk0[5] => ~NO_FANOUT~ xbrk0[6] => ~NO_FANOUT~ xbrk0[7] => ~NO_FANOUT~ xbrk0[8] => ~NO_FANOUT~ xbrk0[9] => ~NO_FANOUT~ xbrk0[10] => ~NO_FANOUT~ xbrk0[11] => ~NO_FANOUT~ xbrk0[12] => ~NO_FANOUT~ xbrk0[13] => ~NO_FANOUT~ xbrk0[14] => ~NO_FANOUT~ xbrk0[15] => ~NO_FANOUT~ xbrk0[16] => ~NO_FANOUT~ xbrk0[17] => ~NO_FANOUT~ xbrk0[18] => ~NO_FANOUT~ xbrk0[19] => ~NO_FANOUT~ xbrk0[20] => ~NO_FANOUT~ xbrk0[21] => ~NO_FANOUT~ xbrk0[22] => ~NO_FANOUT~ xbrk0[23] => ~NO_FANOUT~ xbrk1[0] => ~NO_FANOUT~ xbrk1[1] => ~NO_FANOUT~ xbrk1[2] => ~NO_FANOUT~ xbrk1[3] => ~NO_FANOUT~ xbrk1[4] => ~NO_FANOUT~ xbrk1[5] => ~NO_FANOUT~ xbrk1[6] => ~NO_FANOUT~ xbrk1[7] => ~NO_FANOUT~ xbrk1[8] => ~NO_FANOUT~ xbrk1[9] => ~NO_FANOUT~ xbrk1[10] => ~NO_FANOUT~ xbrk1[11] => ~NO_FANOUT~ xbrk1[12] => ~NO_FANOUT~ xbrk1[13] => ~NO_FANOUT~ xbrk1[14] => ~NO_FANOUT~ xbrk1[15] => ~NO_FANOUT~ xbrk1[16] => ~NO_FANOUT~ xbrk1[17] => ~NO_FANOUT~ xbrk1[18] => ~NO_FANOUT~ xbrk1[19] => ~NO_FANOUT~ xbrk1[20] => ~NO_FANOUT~ xbrk1[21] => ~NO_FANOUT~ xbrk1[22] => ~NO_FANOUT~ xbrk1[23] => ~NO_FANOUT~ xbrk2[0] => ~NO_FANOUT~ xbrk2[1] => ~NO_FANOUT~ xbrk2[2] => ~NO_FANOUT~ xbrk2[3] => ~NO_FANOUT~ xbrk2[4] => ~NO_FANOUT~ xbrk2[5] => ~NO_FANOUT~ xbrk2[6] => ~NO_FANOUT~ xbrk2[7] => ~NO_FANOUT~ xbrk2[8] => ~NO_FANOUT~ xbrk2[9] => ~NO_FANOUT~ xbrk2[10] => ~NO_FANOUT~ xbrk2[11] => ~NO_FANOUT~ xbrk2[12] => ~NO_FANOUT~ xbrk2[13] => ~NO_FANOUT~ xbrk2[14] => ~NO_FANOUT~ xbrk2[15] => ~NO_FANOUT~ xbrk2[16] => ~NO_FANOUT~ xbrk2[17] => ~NO_FANOUT~ xbrk2[18] => ~NO_FANOUT~ xbrk2[19] => ~NO_FANOUT~ xbrk2[20] => ~NO_FANOUT~ xbrk2[21] => ~NO_FANOUT~ xbrk2[22] => ~NO_FANOUT~ xbrk2[23] => ~NO_FANOUT~ xbrk3[0] => ~NO_FANOUT~ xbrk3[1] => ~NO_FANOUT~ xbrk3[2] => ~NO_FANOUT~ xbrk3[3] => ~NO_FANOUT~ xbrk3[4] => ~NO_FANOUT~ xbrk3[5] => ~NO_FANOUT~ xbrk3[6] => ~NO_FANOUT~ xbrk3[7] => ~NO_FANOUT~ xbrk3[8] => ~NO_FANOUT~ xbrk3[9] => ~NO_FANOUT~ xbrk3[10] => ~NO_FANOUT~ xbrk3[11] => ~NO_FANOUT~ xbrk3[12] => ~NO_FANOUT~ xbrk3[13] => ~NO_FANOUT~ xbrk3[14] => ~NO_FANOUT~ xbrk3[15] => ~NO_FANOUT~ xbrk3[16] => ~NO_FANOUT~ xbrk3[17] => ~NO_FANOUT~ xbrk3[18] => ~NO_FANOUT~ xbrk3[19] => ~NO_FANOUT~ xbrk3[20] => ~NO_FANOUT~ xbrk3[21] => ~NO_FANOUT~ xbrk3[22] => ~NO_FANOUT~ xbrk3[23] => ~NO_FANOUT~ xbrk_ctrl0[0] => xbrk_break_hit~1.IN1 xbrk_ctrl0[1] => xbrk_tout_hit~0.IN1 xbrk_ctrl0[2] => xbrk_toff_hit~0.IN1 xbrk_ctrl0[3] => xbrk_ton_hit~0.IN1 xbrk_ctrl0[4] => xbrk0_armed~0.IN1 xbrk_ctrl0[5] => xbrk0_armed~1.IN1 xbrk_ctrl0[6] => xbrk_goto0_hit~0.IN1 xbrk_ctrl0[7] => xbrk_goto1_hit~0.IN1 xbrk_ctrl1[0] => xbrk_break_hit~3.IN1 xbrk_ctrl1[1] => xbrk_tout_hit~1.IN1 xbrk_ctrl1[2] => xbrk_toff_hit~1.IN1 xbrk_ctrl1[3] => xbrk_ton_hit~1.IN1 xbrk_ctrl1[4] => xbrk1_armed~0.IN1 xbrk_ctrl1[5] => xbrk1_armed~1.IN1 xbrk_ctrl1[6] => xbrk_goto0_hit~1.IN1 xbrk_ctrl1[7] => xbrk_goto1_hit~1.IN1 xbrk_ctrl2[0] => xbrk_break_hit~6.IN1 xbrk_ctrl2[1] => xbrk_tout_hit~3.IN1 xbrk_ctrl2[2] => xbrk_toff_hit~3.IN1 xbrk_ctrl2[3] => xbrk_ton_hit~3.IN1 xbrk_ctrl2[4] => xbrk2_armed~0.IN1 xbrk_ctrl2[5] => xbrk2_armed~1.IN1 xbrk_ctrl2[6] => xbrk_goto0_hit~3.IN1 xbrk_ctrl2[7] => xbrk_goto1_hit~3.IN1 xbrk_ctrl3[0] => xbrk_break_hit~9.IN1 xbrk_ctrl3[1] => xbrk_tout_hit~5.IN1 xbrk_ctrl3[2] => xbrk_toff_hit~5.IN1 xbrk_ctrl3[3] => xbrk_ton_hit~5.IN1 xbrk_ctrl3[4] => xbrk3_armed~0.IN1 xbrk_ctrl3[5] => xbrk3_armed~1.IN1 xbrk_ctrl3[6] => xbrk_goto0_hit~5.IN1 xbrk_ctrl3[7] => xbrk_goto1_hit~5.IN1 xbrk_break <= xbrk_break~reg0.DB_MAX_OUTPUT_PORT_TYPE xbrk_goto0 <= M_xbrk_goto0.DB_MAX_OUTPUT_PORT_TYPE xbrk_goto1 <= M_xbrk_goto1.DB_MAX_OUTPUT_PORT_TYPE xbrk_traceoff <= M_xbrk_traceoff.DB_MAX_OUTPUT_PORT_TYPE xbrk_traceon <= M_xbrk_traceon.DB_MAX_OUTPUT_PORT_TYPE xbrk_trigout <= M_xbrk_trigout.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk A_ctrl_ld => cpu_d_read~0.IN0 A_ctrl_st => cpu_d_write~0.IN1 A_en => cpu_d_read_valid~0.IN1 A_en => cpu_d_wait.DATAIN A_mem_baddr[0] => cpu_d_address[0]~23.IN6 A_mem_baddr[1] => cpu_d_address[1]~22.IN6 A_mem_baddr[2] => cpu_d_address[2]~21.IN6 A_mem_baddr[3] => cpu_d_address[3]~20.IN6 A_mem_baddr[4] => cpu_d_address[4]~19.IN6 A_mem_baddr[5] => cpu_d_address[5]~18.IN6 A_mem_baddr[6] => cpu_d_address[6]~17.IN6 A_mem_baddr[7] => cpu_d_address[7]~16.IN6 A_mem_baddr[8] => cpu_d_address[8]~15.IN6 A_mem_baddr[9] => cpu_d_address[9]~14.IN6 A_mem_baddr[10] => cpu_d_address[10]~13.IN6 A_mem_baddr[11] => cpu_d_address[11]~12.IN6 A_mem_baddr[12] => cpu_d_address[12]~11.IN6 A_mem_baddr[13] => cpu_d_address[13]~10.IN6 A_mem_baddr[14] => cpu_d_address[14]~9.IN6 A_mem_baddr[15] => cpu_d_address[15]~8.IN6 A_mem_baddr[16] => cpu_d_address[16]~7.IN6 A_mem_baddr[17] => cpu_d_address[17]~6.IN6 A_mem_baddr[18] => cpu_d_address[18]~5.IN6 A_mem_baddr[19] => cpu_d_address[19]~4.IN6 A_mem_baddr[20] => cpu_d_address[20]~3.IN6 A_mem_baddr[21] => cpu_d_address[21]~2.IN6 A_mem_baddr[22] => cpu_d_address[22]~1.IN6 A_mem_baddr[23] => cpu_d_address[23]~0.IN6 A_st_data[0] => dbrk_data~31.DATAB A_st_data[0] => cpu_d_writedata[0].DATAIN A_st_data[1] => dbrk_data~30.DATAB A_st_data[1] => cpu_d_writedata[1].DATAIN A_st_data[2] => dbrk_data~29.DATAB A_st_data[2] => cpu_d_writedata[2].DATAIN A_st_data[3] => dbrk_data~28.DATAB A_st_data[3] => cpu_d_writedata[3].DATAIN A_st_data[4] => dbrk_data~27.DATAB A_st_data[4] => cpu_d_writedata[4].DATAIN A_st_data[5] => dbrk_data~26.DATAB A_st_data[5] => cpu_d_writedata[5].DATAIN A_st_data[6] => dbrk_data~25.DATAB A_st_data[6] => cpu_d_writedata[6].DATAIN A_st_data[7] => dbrk_data~24.DATAB A_st_data[7] => cpu_d_writedata[7].DATAIN A_st_data[8] => dbrk_data~23.DATAB A_st_data[8] => cpu_d_writedata[8].DATAIN A_st_data[9] => dbrk_data~22.DATAB A_st_data[9] => cpu_d_writedata[9].DATAIN A_st_data[10] => dbrk_data~21.DATAB A_st_data[10] => cpu_d_writedata[10].DATAIN A_st_data[11] => dbrk_data~20.DATAB A_st_data[11] => cpu_d_writedata[11].DATAIN A_st_data[12] => dbrk_data~19.DATAB A_st_data[12] => cpu_d_writedata[12].DATAIN A_st_data[13] => dbrk_data~18.DATAB A_st_data[13] => cpu_d_writedata[13].DATAIN A_st_data[14] => dbrk_data~17.DATAB A_st_data[14] => cpu_d_writedata[14].DATAIN A_st_data[15] => dbrk_data~16.DATAB A_st_data[15] => cpu_d_writedata[15].DATAIN A_st_data[16] => dbrk_data~15.DATAB A_st_data[16] => cpu_d_writedata[16].DATAIN A_st_data[17] => dbrk_data~14.DATAB A_st_data[17] => cpu_d_writedata[17].DATAIN A_st_data[18] => dbrk_data~13.DATAB A_st_data[18] => cpu_d_writedata[18].DATAIN A_st_data[19] => dbrk_data~12.DATAB A_st_data[19] => cpu_d_writedata[19].DATAIN A_st_data[20] => dbrk_data~11.DATAB A_st_data[20] => cpu_d_writedata[20].DATAIN A_st_data[21] => dbrk_data~10.DATAB A_st_data[21] => cpu_d_writedata[21].DATAIN A_st_data[22] => dbrk_data~9.DATAB A_st_data[22] => cpu_d_writedata[22].DATAIN A_st_data[23] => dbrk_data~8.DATAB A_st_data[23] => cpu_d_writedata[23].DATAIN A_st_data[24] => dbrk_data~7.DATAB A_st_data[24] => cpu_d_writedata[24].DATAIN A_st_data[25] => dbrk_data~6.DATAB A_st_data[25] => cpu_d_writedata[25].DATAIN A_st_data[26] => dbrk_data~5.DATAB A_st_data[26] => cpu_d_writedata[26].DATAIN A_st_data[27] => dbrk_data~4.DATAB A_st_data[27] => cpu_d_writedata[27].DATAIN A_st_data[28] => dbrk_data~3.DATAB A_st_data[28] => cpu_d_writedata[28].DATAIN A_st_data[29] => dbrk_data~2.DATAB A_st_data[29] => cpu_d_writedata[29].DATAIN A_st_data[30] => dbrk_data~1.DATAB A_st_data[30] => cpu_d_writedata[30].DATAIN A_st_data[31] => dbrk_data~0.DATAB A_st_data[31] => cpu_d_writedata[31].DATAIN A_valid => cpu_d_write~0.IN0 A_valid => cpu_d_read~0.IN1 A_wr_data_filtered[0] => dbrk_data~31.DATAA A_wr_data_filtered[0] => cpu_d_readdata[0].DATAIN A_wr_data_filtered[1] => dbrk_data~30.DATAA A_wr_data_filtered[1] => cpu_d_readdata[1].DATAIN A_wr_data_filtered[2] => dbrk_data~29.DATAA A_wr_data_filtered[2] => cpu_d_readdata[2].DATAIN A_wr_data_filtered[3] => dbrk_data~28.DATAA A_wr_data_filtered[3] => cpu_d_readdata[3].DATAIN A_wr_data_filtered[4] => dbrk_data~27.DATAA A_wr_data_filtered[4] => cpu_d_readdata[4].DATAIN A_wr_data_filtered[5] => dbrk_data~26.DATAA A_wr_data_filtered[5] => cpu_d_readdata[5].DATAIN A_wr_data_filtered[6] => dbrk_data~25.DATAA A_wr_data_filtered[6] => cpu_d_readdata[6].DATAIN A_wr_data_filtered[7] => dbrk_data~24.DATAA A_wr_data_filtered[7] => cpu_d_readdata[7].DATAIN A_wr_data_filtered[8] => dbrk_data~23.DATAA A_wr_data_filtered[8] => cpu_d_readdata[8].DATAIN A_wr_data_filtered[9] => dbrk_data~22.DATAA A_wr_data_filtered[9] => cpu_d_readdata[9].DATAIN A_wr_data_filtered[10] => dbrk_data~21.DATAA A_wr_data_filtered[10] => cpu_d_readdata[10].DATAIN A_wr_data_filtered[11] => dbrk_data~20.DATAA A_wr_data_filtered[11] => cpu_d_readdata[11].DATAIN A_wr_data_filtered[12] => dbrk_data~19.DATAA A_wr_data_filtered[12] => cpu_d_readdata[12].DATAIN A_wr_data_filtered[13] => dbrk_data~18.DATAA A_wr_data_filtered[13] => cpu_d_readdata[13].DATAIN A_wr_data_filtered[14] => dbrk_data~17.DATAA A_wr_data_filtered[14] => cpu_d_readdata[14].DATAIN A_wr_data_filtered[15] => dbrk_data~16.DATAA A_wr_data_filtered[15] => cpu_d_readdata[15].DATAIN A_wr_data_filtered[16] => dbrk_data~15.DATAA A_wr_data_filtered[16] => cpu_d_readdata[16].DATAIN A_wr_data_filtered[17] => dbrk_data~14.DATAA A_wr_data_filtered[17] => cpu_d_readdata[17].DATAIN A_wr_data_filtered[18] => dbrk_data~13.DATAA A_wr_data_filtered[18] => cpu_d_readdata[18].DATAIN A_wr_data_filtered[19] => dbrk_data~12.DATAA A_wr_data_filtered[19] => cpu_d_readdata[19].DATAIN A_wr_data_filtered[20] => dbrk_data~11.DATAA A_wr_data_filtered[20] => cpu_d_readdata[20].DATAIN A_wr_data_filtered[21] => dbrk_data~10.DATAA A_wr_data_filtered[21] => cpu_d_readdata[21].DATAIN A_wr_data_filtered[22] => dbrk_data~9.DATAA A_wr_data_filtered[22] => cpu_d_readdata[22].DATAIN A_wr_data_filtered[23] => dbrk_data~8.DATAA A_wr_data_filtered[23] => cpu_d_readdata[23].DATAIN A_wr_data_filtered[24] => dbrk_data~7.DATAA A_wr_data_filtered[24] => cpu_d_readdata[24].DATAIN A_wr_data_filtered[25] => dbrk_data~6.DATAA A_wr_data_filtered[25] => cpu_d_readdata[25].DATAIN A_wr_data_filtered[26] => dbrk_data~5.DATAA A_wr_data_filtered[26] => cpu_d_readdata[26].DATAIN A_wr_data_filtered[27] => dbrk_data~4.DATAA A_wr_data_filtered[27] => cpu_d_readdata[27].DATAIN A_wr_data_filtered[28] => dbrk_data~3.DATAA A_wr_data_filtered[28] => cpu_d_readdata[28].DATAIN A_wr_data_filtered[29] => dbrk_data~2.DATAA A_wr_data_filtered[29] => cpu_d_readdata[29].DATAIN A_wr_data_filtered[30] => dbrk_data~1.DATAA A_wr_data_filtered[30] => cpu_d_readdata[30].DATAIN A_wr_data_filtered[31] => dbrk_data~0.DATAA A_wr_data_filtered[31] => cpu_d_readdata[31].DATAIN clk => dbrk_break~reg0.CLK clk => dbrk_trigout~reg0.CLK clk => dbrk_break_pulse.CLK clk => dbrk_traceoff~reg0.CLK clk => dbrk_traceon~reg0.CLK clk => dbrk_traceme~reg0.CLK clk => dbrk_goto0~reg0.CLK clk => dbrk_goto1~reg0.CLK dbrk0[0] => dbrk0[0]~77.IN2 dbrk0[1] => dbrk0[1]~76.IN2 dbrk0[2] => dbrk0[2]~75.IN2 dbrk0[3] => dbrk0[3]~74.IN2 dbrk0[4] => dbrk0[4]~73.IN2 dbrk0[5] => dbrk0[5]~72.IN2 dbrk0[6] => dbrk0[6]~71.IN2 dbrk0[7] => dbrk0[7]~70.IN2 dbrk0[8] => dbrk0[8]~69.IN2 dbrk0[9] => dbrk0[9]~68.IN2 dbrk0[10] => dbrk0[10]~67.IN2 dbrk0[11] => dbrk0[11]~66.IN2 dbrk0[12] => dbrk0[12]~65.IN2 dbrk0[13] => dbrk0[13]~64.IN2 dbrk0[14] => dbrk0[14]~63.IN2 dbrk0[15] => dbrk0[15]~62.IN2 dbrk0[16] => dbrk0[16]~61.IN2 dbrk0[17] => dbrk0[17]~60.IN2 dbrk0[18] => dbrk0[18]~59.IN2 dbrk0[19] => dbrk0[19]~58.IN2 dbrk0[20] => dbrk0[20]~57.IN2 dbrk0[21] => dbrk0[21]~56.IN2 dbrk0[22] => dbrk0[22]~55.IN2 dbrk0[23] => dbrk0[23]~54.IN2 dbrk0[24] => dbrk0[24]~53.IN2 dbrk0[25] => dbrk0[25]~52.IN2 dbrk0[26] => dbrk0[26]~51.IN2 dbrk0[27] => dbrk0[27]~50.IN2 dbrk0[28] => dbrk0[28]~49.IN2 dbrk0[29] => dbrk0[29]~48.IN2 dbrk0[30] => dbrk0[30]~47.IN2 dbrk0[31] => dbrk0[31]~46.IN2 dbrk0[32] => dbrk0[32]~45.IN2 dbrk0[33] => dbrk0[33]~44.IN2 dbrk0[34] => dbrk0[34]~43.IN2 dbrk0[35] => dbrk0[35]~42.IN2 dbrk0[36] => dbrk0[36]~41.IN2 dbrk0[37] => dbrk0[37]~40.IN2 dbrk0[38] => dbrk0[38]~39.IN2 dbrk0[39] => dbrk0[39]~38.IN2 dbrk0[40] => dbrk0[40]~37.IN2 dbrk0[41] => dbrk0[41]~36.IN2 dbrk0[42] => dbrk0[42]~35.IN2 dbrk0[43] => dbrk0[43]~34.IN2 dbrk0[44] => dbrk0[44]~33.IN2 dbrk0[45] => dbrk0[45]~32.IN2 dbrk0[46] => dbrk0[46]~31.IN2 dbrk0[47] => dbrk0[47]~30.IN2 dbrk0[48] => dbrk0[48]~29.IN2 dbrk0[49] => dbrk0[49]~28.IN2 dbrk0[50] => dbrk0[50]~27.IN2 dbrk0[51] => dbrk0[51]~26.IN2 dbrk0[52] => dbrk0[52]~25.IN2 dbrk0[53] => dbrk0[53]~24.IN2 dbrk0[54] => dbrk0[54]~23.IN2 dbrk0[55] => dbrk0[55]~22.IN2 dbrk0[56] => dbrk0[56]~21.IN2 dbrk0[57] => dbrk0[57]~20.IN2 dbrk0[58] => dbrk0[58]~19.IN2 dbrk0[59] => dbrk0[59]~18.IN2 dbrk0[60] => dbrk0[60]~17.IN2 dbrk0[61] => dbrk0[61]~16.IN2 dbrk0[62] => dbrk0[62]~15.IN2 dbrk0[63] => dbrk0[63]~14.IN2 dbrk0[64] => dbrk0[64]~13.IN2 dbrk0[65] => dbrk0[65]~12.IN2 dbrk0[66] => dbrk0[66]~11.IN2 dbrk0[67] => dbrk0[67]~10.IN2 dbrk0[68] => dbrk0[68]~9.IN2 dbrk0[69] => dbrk0[69]~8.IN2 dbrk0[70] => dbrk0[70]~7.IN2 dbrk0[71] => dbrk0[71]~6.IN2 dbrk0[72] => dbrk0[72]~5.IN2 dbrk0[73] => dbrk0[73]~4.IN2 dbrk0[74] => dbrk0[74]~3.IN2 dbrk0[75] => dbrk0[75]~2.IN2 dbrk0[76] => dbrk0[76]~1.IN2 dbrk0[77] => dbrk0[77]~0.IN2 dbrk1[0] => dbrk1[0]~77.IN2 dbrk1[1] => dbrk1[1]~76.IN2 dbrk1[2] => dbrk1[2]~75.IN2 dbrk1[3] => dbrk1[3]~74.IN2 dbrk1[4] => dbrk1[4]~73.IN2 dbrk1[5] => dbrk1[5]~72.IN2 dbrk1[6] => dbrk1[6]~71.IN2 dbrk1[7] => dbrk1[7]~70.IN2 dbrk1[8] => dbrk1[8]~69.IN2 dbrk1[9] => dbrk1[9]~68.IN2 dbrk1[10] => dbrk1[10]~67.IN2 dbrk1[11] => dbrk1[11]~66.IN2 dbrk1[12] => dbrk1[12]~65.IN2 dbrk1[13] => dbrk1[13]~64.IN2 dbrk1[14] => dbrk1[14]~63.IN2 dbrk1[15] => dbrk1[15]~62.IN2 dbrk1[16] => dbrk1[16]~61.IN2 dbrk1[17] => dbrk1[17]~60.IN2 dbrk1[18] => dbrk1[18]~59.IN2 dbrk1[19] => dbrk1[19]~58.IN2 dbrk1[20] => dbrk1[20]~57.IN2 dbrk1[21] => dbrk1[21]~56.IN2 dbrk1[22] => dbrk1[22]~55.IN2 dbrk1[23] => dbrk1[23]~54.IN2 dbrk1[24] => dbrk1[24]~53.IN2 dbrk1[25] => dbrk1[25]~52.IN2 dbrk1[26] => dbrk1[26]~51.IN2 dbrk1[27] => dbrk1[27]~50.IN2 dbrk1[28] => dbrk1[28]~49.IN2 dbrk1[29] => dbrk1[29]~48.IN2 dbrk1[30] => dbrk1[30]~47.IN2 dbrk1[31] => dbrk1[31]~46.IN2 dbrk1[32] => dbrk1[32]~45.IN2 dbrk1[33] => dbrk1[33]~44.IN2 dbrk1[34] => dbrk1[34]~43.IN2 dbrk1[35] => dbrk1[35]~42.IN2 dbrk1[36] => dbrk1[36]~41.IN2 dbrk1[37] => dbrk1[37]~40.IN2 dbrk1[38] => dbrk1[38]~39.IN2 dbrk1[39] => dbrk1[39]~38.IN2 dbrk1[40] => dbrk1[40]~37.IN2 dbrk1[41] => dbrk1[41]~36.IN2 dbrk1[42] => dbrk1[42]~35.IN2 dbrk1[43] => dbrk1[43]~34.IN2 dbrk1[44] => dbrk1[44]~33.IN2 dbrk1[45] => dbrk1[45]~32.IN2 dbrk1[46] => dbrk1[46]~31.IN2 dbrk1[47] => dbrk1[47]~30.IN2 dbrk1[48] => dbrk1[48]~29.IN2 dbrk1[49] => dbrk1[49]~28.IN2 dbrk1[50] => dbrk1[50]~27.IN2 dbrk1[51] => dbrk1[51]~26.IN2 dbrk1[52] => dbrk1[52]~25.IN2 dbrk1[53] => dbrk1[53]~24.IN2 dbrk1[54] => dbrk1[54]~23.IN2 dbrk1[55] => dbrk1[55]~22.IN2 dbrk1[56] => dbrk1[56]~21.IN2 dbrk1[57] => dbrk1[57]~20.IN2 dbrk1[58] => dbrk1[58]~19.IN2 dbrk1[59] => dbrk1[59]~18.IN2 dbrk1[60] => dbrk1[60]~17.IN2 dbrk1[61] => dbrk1[61]~16.IN2 dbrk1[62] => dbrk1[62]~15.IN2 dbrk1[63] => dbrk1[63]~14.IN2 dbrk1[64] => dbrk1[64]~13.IN2 dbrk1[65] => dbrk1[65]~12.IN2 dbrk1[66] => dbrk1[66]~11.IN2 dbrk1[67] => dbrk1[67]~10.IN2 dbrk1[68] => dbrk1[68]~9.IN2 dbrk1[69] => dbrk1[69]~8.IN2 dbrk1[70] => dbrk1[70]~7.IN2 dbrk1[71] => dbrk1[71]~6.IN2 dbrk1[72] => dbrk1[72]~5.IN2 dbrk1[73] => dbrk1[73]~4.IN2 dbrk1[74] => dbrk1[74]~3.IN2 dbrk1[75] => dbrk1[75]~2.IN2 dbrk1[76] => dbrk1[76]~1.IN2 dbrk1[77] => dbrk1[77]~0.IN2 dbrk2[0] => dbrk2[0]~77.IN2 dbrk2[1] => dbrk2[1]~76.IN2 dbrk2[2] => dbrk2[2]~75.IN2 dbrk2[3] => dbrk2[3]~74.IN2 dbrk2[4] => dbrk2[4]~73.IN2 dbrk2[5] => dbrk2[5]~72.IN2 dbrk2[6] => dbrk2[6]~71.IN2 dbrk2[7] => dbrk2[7]~70.IN2 dbrk2[8] => dbrk2[8]~69.IN2 dbrk2[9] => dbrk2[9]~68.IN2 dbrk2[10] => dbrk2[10]~67.IN2 dbrk2[11] => dbrk2[11]~66.IN2 dbrk2[12] => dbrk2[12]~65.IN2 dbrk2[13] => dbrk2[13]~64.IN2 dbrk2[14] => dbrk2[14]~63.IN2 dbrk2[15] => dbrk2[15]~62.IN2 dbrk2[16] => dbrk2[16]~61.IN2 dbrk2[17] => dbrk2[17]~60.IN2 dbrk2[18] => dbrk2[18]~59.IN2 dbrk2[19] => dbrk2[19]~58.IN2 dbrk2[20] => dbrk2[20]~57.IN2 dbrk2[21] => dbrk2[21]~56.IN2 dbrk2[22] => dbrk2[22]~55.IN2 dbrk2[23] => dbrk2[23]~54.IN2 dbrk2[24] => dbrk2[24]~53.IN2 dbrk2[25] => dbrk2[25]~52.IN2 dbrk2[26] => dbrk2[26]~51.IN2 dbrk2[27] => dbrk2[27]~50.IN2 dbrk2[28] => dbrk2[28]~49.IN2 dbrk2[29] => dbrk2[29]~48.IN2 dbrk2[30] => dbrk2[30]~47.IN2 dbrk2[31] => dbrk2[31]~46.IN2 dbrk2[32] => dbrk2[32]~45.IN2 dbrk2[33] => dbrk2[33]~44.IN2 dbrk2[34] => dbrk2[34]~43.IN2 dbrk2[35] => dbrk2[35]~42.IN2 dbrk2[36] => dbrk2[36]~41.IN2 dbrk2[37] => dbrk2[37]~40.IN2 dbrk2[38] => dbrk2[38]~39.IN2 dbrk2[39] => dbrk2[39]~38.IN2 dbrk2[40] => dbrk2[40]~37.IN2 dbrk2[41] => dbrk2[41]~36.IN2 dbrk2[42] => dbrk2[42]~35.IN2 dbrk2[43] => dbrk2[43]~34.IN2 dbrk2[44] => dbrk2[44]~33.IN2 dbrk2[45] => dbrk2[45]~32.IN2 dbrk2[46] => dbrk2[46]~31.IN2 dbrk2[47] => dbrk2[47]~30.IN2 dbrk2[48] => dbrk2[48]~29.IN2 dbrk2[49] => dbrk2[49]~28.IN2 dbrk2[50] => dbrk2[50]~27.IN2 dbrk2[51] => dbrk2[51]~26.IN2 dbrk2[52] => dbrk2[52]~25.IN2 dbrk2[53] => dbrk2[53]~24.IN2 dbrk2[54] => dbrk2[54]~23.IN2 dbrk2[55] => dbrk2[55]~22.IN2 dbrk2[56] => dbrk2[56]~21.IN2 dbrk2[57] => dbrk2[57]~20.IN2 dbrk2[58] => dbrk2[58]~19.IN2 dbrk2[59] => dbrk2[59]~18.IN2 dbrk2[60] => dbrk2[60]~17.IN2 dbrk2[61] => dbrk2[61]~16.IN2 dbrk2[62] => dbrk2[62]~15.IN2 dbrk2[63] => dbrk2[63]~14.IN2 dbrk2[64] => dbrk2[64]~13.IN2 dbrk2[65] => dbrk2[65]~12.IN2 dbrk2[66] => dbrk2[66]~11.IN2 dbrk2[67] => dbrk2[67]~10.IN2 dbrk2[68] => dbrk2[68]~9.IN2 dbrk2[69] => dbrk2[69]~8.IN2 dbrk2[70] => dbrk2[70]~7.IN2 dbrk2[71] => dbrk2[71]~6.IN2 dbrk2[72] => dbrk2[72]~5.IN2 dbrk2[73] => dbrk2[73]~4.IN2 dbrk2[74] => dbrk2[74]~3.IN2 dbrk2[75] => dbrk2[75]~2.IN2 dbrk2[76] => dbrk2[76]~1.IN2 dbrk2[77] => dbrk2[77]~0.IN2 dbrk3[0] => dbrk3[0]~77.IN2 dbrk3[1] => dbrk3[1]~76.IN2 dbrk3[2] => dbrk3[2]~75.IN2 dbrk3[3] => dbrk3[3]~74.IN2 dbrk3[4] => dbrk3[4]~73.IN2 dbrk3[5] => dbrk3[5]~72.IN2 dbrk3[6] => dbrk3[6]~71.IN2 dbrk3[7] => dbrk3[7]~70.IN2 dbrk3[8] => dbrk3[8]~69.IN2 dbrk3[9] => dbrk3[9]~68.IN2 dbrk3[10] => dbrk3[10]~67.IN2 dbrk3[11] => dbrk3[11]~66.IN2 dbrk3[12] => dbrk3[12]~65.IN2 dbrk3[13] => dbrk3[13]~64.IN2 dbrk3[14] => dbrk3[14]~63.IN2 dbrk3[15] => dbrk3[15]~62.IN2 dbrk3[16] => dbrk3[16]~61.IN2 dbrk3[17] => dbrk3[17]~60.IN2 dbrk3[18] => dbrk3[18]~59.IN2 dbrk3[19] => dbrk3[19]~58.IN2 dbrk3[20] => dbrk3[20]~57.IN2 dbrk3[21] => dbrk3[21]~56.IN2 dbrk3[22] => dbrk3[22]~55.IN2 dbrk3[23] => dbrk3[23]~54.IN2 dbrk3[24] => dbrk3[24]~53.IN2 dbrk3[25] => dbrk3[25]~52.IN2 dbrk3[26] => dbrk3[26]~51.IN2 dbrk3[27] => dbrk3[27]~50.IN2 dbrk3[28] => dbrk3[28]~49.IN2 dbrk3[29] => dbrk3[29]~48.IN2 dbrk3[30] => dbrk3[30]~47.IN2 dbrk3[31] => dbrk3[31]~46.IN2 dbrk3[32] => dbrk3[32]~45.IN2 dbrk3[33] => dbrk3[33]~44.IN2 dbrk3[34] => dbrk3[34]~43.IN2 dbrk3[35] => dbrk3[35]~42.IN2 dbrk3[36] => dbrk3[36]~41.IN2 dbrk3[37] => dbrk3[37]~40.IN2 dbrk3[38] => dbrk3[38]~39.IN2 dbrk3[39] => dbrk3[39]~38.IN2 dbrk3[40] => dbrk3[40]~37.IN2 dbrk3[41] => dbrk3[41]~36.IN2 dbrk3[42] => dbrk3[42]~35.IN2 dbrk3[43] => dbrk3[43]~34.IN2 dbrk3[44] => dbrk3[44]~33.IN2 dbrk3[45] => dbrk3[45]~32.IN2 dbrk3[46] => dbrk3[46]~31.IN2 dbrk3[47] => dbrk3[47]~30.IN2 dbrk3[48] => dbrk3[48]~29.IN2 dbrk3[49] => dbrk3[49]~28.IN2 dbrk3[50] => dbrk3[50]~27.IN2 dbrk3[51] => dbrk3[51]~26.IN2 dbrk3[52] => dbrk3[52]~25.IN2 dbrk3[53] => dbrk3[53]~24.IN2 dbrk3[54] => dbrk3[54]~23.IN2 dbrk3[55] => dbrk3[55]~22.IN2 dbrk3[56] => dbrk3[56]~21.IN2 dbrk3[57] => dbrk3[57]~20.IN2 dbrk3[58] => dbrk3[58]~19.IN2 dbrk3[59] => dbrk3[59]~18.IN2 dbrk3[60] => dbrk3[60]~17.IN2 dbrk3[61] => dbrk3[61]~16.IN2 dbrk3[62] => dbrk3[62]~15.IN2 dbrk3[63] => dbrk3[63]~14.IN2 dbrk3[64] => dbrk3[64]~13.IN2 dbrk3[65] => dbrk3[65]~12.IN2 dbrk3[66] => dbrk3[66]~11.IN2 dbrk3[67] => dbrk3[67]~10.IN2 dbrk3[68] => dbrk3[68]~9.IN2 dbrk3[69] => dbrk3[69]~8.IN2 dbrk3[70] => dbrk3[70]~7.IN2 dbrk3[71] => dbrk3[71]~6.IN2 dbrk3[72] => dbrk3[72]~5.IN2 dbrk3[73] => dbrk3[73]~4.IN2 dbrk3[74] => dbrk3[74]~3.IN2 dbrk3[75] => dbrk3[75]~2.IN2 dbrk3[76] => dbrk3[76]~1.IN2 dbrk3[77] => dbrk3[77]~0.IN2 debugack => dbrk_break~0.DATAB reset_n => dbrk_break~reg0.ACLR trigger_state_0 => ~NO_FANOUT~ trigger_state_1 => ~NO_FANOUT~ cpu_d_address[0] <= cpu_d_address[0]~23.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[1] <= cpu_d_address[1]~22.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[2] <= cpu_d_address[2]~21.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[3] <= cpu_d_address[3]~20.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[4] <= cpu_d_address[4]~19.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[5] <= cpu_d_address[5]~18.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[6] <= cpu_d_address[6]~17.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[7] <= cpu_d_address[7]~16.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[8] <= cpu_d_address[8]~15.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[9] <= cpu_d_address[9]~14.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[10] <= cpu_d_address[10]~13.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[11] <= cpu_d_address[11]~12.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[12] <= cpu_d_address[12]~11.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[13] <= cpu_d_address[13]~10.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[14] <= cpu_d_address[14]~9.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[15] <= cpu_d_address[15]~8.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[16] <= cpu_d_address[16]~7.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[17] <= cpu_d_address[17]~6.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[18] <= cpu_d_address[18]~5.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[19] <= cpu_d_address[19]~4.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[20] <= cpu_d_address[20]~3.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[21] <= cpu_d_address[21]~2.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[22] <= cpu_d_address[22]~1.DB_MAX_OUTPUT_PORT_TYPE cpu_d_address[23] <= cpu_d_address[23]~0.DB_MAX_OUTPUT_PORT_TYPE cpu_d_read <= cpu_d_read~0.DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[0] <= A_wr_data_filtered[0].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[1] <= A_wr_data_filtered[1].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[2] <= A_wr_data_filtered[2].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[3] <= A_wr_data_filtered[3].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[4] <= A_wr_data_filtered[4].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[5] <= A_wr_data_filtered[5].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[6] <= A_wr_data_filtered[6].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[7] <= A_wr_data_filtered[7].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[8] <= A_wr_data_filtered[8].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[9] <= A_wr_data_filtered[9].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[10] <= A_wr_data_filtered[10].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[11] <= A_wr_data_filtered[11].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[12] <= A_wr_data_filtered[12].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[13] <= A_wr_data_filtered[13].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[14] <= A_wr_data_filtered[14].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[15] <= A_wr_data_filtered[15].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[16] <= A_wr_data_filtered[16].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[17] <= A_wr_data_filtered[17].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[18] <= A_wr_data_filtered[18].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[19] <= A_wr_data_filtered[19].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[20] <= A_wr_data_filtered[20].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[21] <= A_wr_data_filtered[21].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[22] <= A_wr_data_filtered[22].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[23] <= A_wr_data_filtered[23].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[24] <= A_wr_data_filtered[24].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[25] <= A_wr_data_filtered[25].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[26] <= A_wr_data_filtered[26].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[27] <= A_wr_data_filtered[27].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[28] <= A_wr_data_filtered[28].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[29] <= A_wr_data_filtered[29].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[30] <= A_wr_data_filtered[30].DB_MAX_OUTPUT_PORT_TYPE cpu_d_readdata[31] <= A_wr_data_filtered[31].DB_MAX_OUTPUT_PORT_TYPE cpu_d_wait <= A_en.DB_MAX_OUTPUT_PORT_TYPE cpu_d_write <= cpu_d_write~1.DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[0] <= A_st_data[0].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[1] <= A_st_data[1].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[2] <= A_st_data[2].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[3] <= A_st_data[3].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[4] <= A_st_data[4].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[5] <= A_st_data[5].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[6] <= A_st_data[6].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[7] <= A_st_data[7].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[8] <= A_st_data[8].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[9] <= A_st_data[9].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[10] <= A_st_data[10].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[11] <= A_st_data[11].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[12] <= A_st_data[12].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[13] <= A_st_data[13].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[14] <= A_st_data[14].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[15] <= A_st_data[15].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[16] <= A_st_data[16].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[17] <= A_st_data[17].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[18] <= A_st_data[18].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[19] <= A_st_data[19].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[20] <= A_st_data[20].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[21] <= A_st_data[21].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[22] <= A_st_data[22].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[23] <= A_st_data[23].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[24] <= A_st_data[24].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[25] <= A_st_data[25].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[26] <= A_st_data[26].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[27] <= A_st_data[27].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[28] <= A_st_data[28].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[29] <= A_st_data[29].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[30] <= A_st_data[30].DB_MAX_OUTPUT_PORT_TYPE cpu_d_writedata[31] <= A_st_data[31].DB_MAX_OUTPUT_PORT_TYPE dbrk_break <= dbrk_break~reg0.DB_MAX_OUTPUT_PORT_TYPE dbrk_goto0 <= dbrk_goto0~reg0.DB_MAX_OUTPUT_PORT_TYPE dbrk_goto1 <= dbrk_goto1~reg0.DB_MAX_OUTPUT_PORT_TYPE dbrk_hit0 <= dbrk_hit1 <= dbrk_hit2 <= dbrk_hit3 <= dbrk_traceme <= dbrk_traceme~reg0.DB_MAX_OUTPUT_PORT_TYPE dbrk_traceoff <= dbrk_traceoff~reg0.DB_MAX_OUTPUT_PORT_TYPE dbrk_traceon <= dbrk_traceon~reg0.DB_MAX_OUTPUT_PORT_TYPE dbrk_trigout <= dbrk_trigout~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_paired:cpu_0_nios2_oci_dbrk_hit0_match_paired addr[0] => LessThan1.IN24 addr[0] => LessThan0.IN24 addr[1] => LessThan1.IN23 addr[1] => LessThan0.IN23 addr[2] => LessThan1.IN22 addr[2] => LessThan0.IN22 addr[3] => LessThan1.IN21 addr[3] => LessThan0.IN21 addr[4] => LessThan1.IN20 addr[4] => LessThan0.IN20 addr[5] => LessThan1.IN19 addr[5] => LessThan0.IN19 addr[6] => LessThan1.IN18 addr[6] => LessThan0.IN18 addr[7] => LessThan1.IN17 addr[7] => LessThan0.IN17 addr[8] => LessThan1.IN16 addr[8] => LessThan0.IN16 addr[9] => LessThan1.IN15 addr[9] => LessThan0.IN15 addr[10] => LessThan1.IN14 addr[10] => LessThan0.IN14 addr[11] => LessThan1.IN13 addr[11] => LessThan0.IN13 addr[12] => LessThan1.IN12 addr[12] => LessThan0.IN12 addr[13] => LessThan1.IN11 addr[13] => LessThan0.IN11 addr[14] => LessThan1.IN10 addr[14] => LessThan0.IN10 addr[15] => LessThan1.IN9 addr[15] => LessThan0.IN9 addr[16] => LessThan1.IN8 addr[16] => LessThan0.IN8 addr[17] => LessThan1.IN7 addr[17] => LessThan0.IN7 addr[18] => LessThan1.IN6 addr[18] => LessThan0.IN6 addr[19] => LessThan1.IN5 addr[19] => LessThan0.IN5 addr[20] => LessThan1.IN4 addr[20] => LessThan0.IN4 addr[21] => LessThan1.IN3 addr[21] => LessThan0.IN3 addr[22] => LessThan1.IN2 addr[22] => LessThan0.IN2 addr[23] => LessThan1.IN1 addr[23] => LessThan0.IN1 data[0] => match_paired_combinatorial~2.IN0 data[1] => match_paired_combinatorial~3.IN0 data[2] => match_paired_combinatorial~4.IN0 data[3] => match_paired_combinatorial~5.IN0 data[4] => match_paired_combinatorial~6.IN0 data[5] => match_paired_combinatorial~7.IN0 data[6] => match_paired_combinatorial~8.IN0 data[7] => match_paired_combinatorial~9.IN0 data[8] => match_paired_combinatorial~10.IN0 data[9] => match_paired_combinatorial~11.IN0 data[10] => match_paired_combinatorial~12.IN0 data[11] => match_paired_combinatorial~13.IN0 data[12] => match_paired_combinatorial~14.IN0 data[13] => match_paired_combinatorial~15.IN0 data[14] => match_paired_combinatorial~16.IN0 data[15] => match_paired_combinatorial~17.IN0 data[16] => match_paired_combinatorial~18.IN0 data[17] => match_paired_combinatorial~19.IN0 data[18] => match_paired_combinatorial~20.IN0 data[19] => match_paired_combinatorial~21.IN0 data[20] => match_paired_combinatorial~22.IN0 data[21] => match_paired_combinatorial~23.IN0 data[22] => match_paired_combinatorial~24.IN0 data[23] => match_paired_combinatorial~25.IN0 data[24] => match_paired_combinatorial~26.IN0 data[25] => match_paired_combinatorial~27.IN0 data[26] => match_paired_combinatorial~28.IN0 data[27] => match_paired_combinatorial~29.IN0 data[28] => match_paired_combinatorial~30.IN0 data[29] => match_paired_combinatorial~31.IN0 data[30] => match_paired_combinatorial~32.IN0 data[31] => match_paired_combinatorial~33.IN0 dbrka[0] => LessThan0.IN48 dbrka[1] => LessThan0.IN47 dbrka[2] => LessThan0.IN46 dbrka[3] => LessThan0.IN45 dbrka[4] => LessThan0.IN44 dbrka[5] => LessThan0.IN43 dbrka[6] => LessThan0.IN42 dbrka[7] => LessThan0.IN41 dbrka[8] => LessThan0.IN40 dbrka[9] => LessThan0.IN39 dbrka[10] => LessThan0.IN38 dbrka[11] => LessThan0.IN37 dbrka[12] => LessThan0.IN36 dbrka[13] => LessThan0.IN35 dbrka[14] => LessThan0.IN34 dbrka[15] => LessThan0.IN33 dbrka[16] => LessThan0.IN32 dbrka[17] => LessThan0.IN31 dbrka[18] => LessThan0.IN30 dbrka[19] => LessThan0.IN29 dbrka[20] => LessThan0.IN28 dbrka[21] => LessThan0.IN27 dbrka[22] => LessThan0.IN26 dbrka[23] => LessThan0.IN25 dbrka[24] => ~NO_FANOUT~ dbrka[25] => ~NO_FANOUT~ dbrka[26] => ~NO_FANOUT~ dbrka[27] => ~NO_FANOUT~ dbrka[28] => ~NO_FANOUT~ dbrka[29] => ~NO_FANOUT~ dbrka[30] => ~NO_FANOUT~ dbrka[31] => ~NO_FANOUT~ dbrka[32] => match_paired_combinatorial~2.IN1 dbrka[33] => match_paired_combinatorial~3.IN1 dbrka[34] => match_paired_combinatorial~4.IN1 dbrka[35] => match_paired_combinatorial~5.IN1 dbrka[36] => match_paired_combinatorial~6.IN1 dbrka[37] => match_paired_combinatorial~7.IN1 dbrka[38] => match_paired_combinatorial~8.IN1 dbrka[39] => match_paired_combinatorial~9.IN1 dbrka[40] => match_paired_combinatorial~10.IN1 dbrka[41] => match_paired_combinatorial~11.IN1 dbrka[42] => match_paired_combinatorial~12.IN1 dbrka[43] => match_paired_combinatorial~13.IN1 dbrka[44] => match_paired_combinatorial~14.IN1 dbrka[45] => match_paired_combinatorial~15.IN1 dbrka[46] => match_paired_combinatorial~16.IN1 dbrka[47] => match_paired_combinatorial~17.IN1 dbrka[48] => match_paired_combinatorial~18.IN1 dbrka[49] => match_paired_combinatorial~19.IN1 dbrka[50] => match_paired_combinatorial~20.IN1 dbrka[51] => match_paired_combinatorial~21.IN1 dbrka[52] => match_paired_combinatorial~22.IN1 dbrka[53] => match_paired_combinatorial~23.IN1 dbrka[54] => match_paired_combinatorial~24.IN1 dbrka[55] => match_paired_combinatorial~25.IN1 dbrka[56] => match_paired_combinatorial~26.IN1 dbrka[57] => match_paired_combinatorial~27.IN1 dbrka[58] => match_paired_combinatorial~28.IN1 dbrka[59] => match_paired_combinatorial~29.IN1 dbrka[60] => match_paired_combinatorial~30.IN1 dbrka[61] => match_paired_combinatorial~31.IN1 dbrka[62] => match_paired_combinatorial~32.IN1 dbrka[63] => match_paired_combinatorial~33.IN1 dbrka[64] => ~NO_FANOUT~ dbrka[65] => match_paired_combinatorial~69.IN0 dbrka[66] => match_paired_combinatorial~68.IN0 dbrka[67] => match_paired_combinatorial~1.IN0 dbrka[68] => match_paired_combinatorial~66.IN0 dbrka[69] => ~NO_FANOUT~ dbrka[70] => ~NO_FANOUT~ dbrkb[0] => LessThan1.IN48 dbrkb[1] => LessThan1.IN47 dbrkb[2] => LessThan1.IN46 dbrkb[3] => LessThan1.IN45 dbrkb[4] => LessThan1.IN44 dbrkb[5] => LessThan1.IN43 dbrkb[6] => LessThan1.IN42 dbrkb[7] => LessThan1.IN41 dbrkb[8] => LessThan1.IN40 dbrkb[9] => LessThan1.IN39 dbrkb[10] => LessThan1.IN38 dbrkb[11] => LessThan1.IN37 dbrkb[12] => LessThan1.IN36 dbrkb[13] => LessThan1.IN35 dbrkb[14] => LessThan1.IN34 dbrkb[15] => LessThan1.IN33 dbrkb[16] => LessThan1.IN32 dbrkb[17] => LessThan1.IN31 dbrkb[18] => LessThan1.IN30 dbrkb[19] => LessThan1.IN29 dbrkb[20] => LessThan1.IN28 dbrkb[21] => LessThan1.IN27 dbrkb[22] => LessThan1.IN26 dbrkb[23] => LessThan1.IN25 dbrkb[24] => ~NO_FANOUT~ dbrkb[25] => ~NO_FANOUT~ dbrkb[26] => ~NO_FANOUT~ dbrkb[27] => ~NO_FANOUT~ dbrkb[28] => ~NO_FANOUT~ dbrkb[29] => ~NO_FANOUT~ dbrkb[30] => ~NO_FANOUT~ dbrkb[31] => ~NO_FANOUT~ dbrkb[32] => match_paired_combinatorial~34.IN1 dbrkb[33] => match_paired_combinatorial~35.IN1 dbrkb[34] => match_paired_combinatorial~36.IN1 dbrkb[35] => match_paired_combinatorial~37.IN1 dbrkb[36] => match_paired_combinatorial~38.IN1 dbrkb[37] => match_paired_combinatorial~39.IN1 dbrkb[38] => match_paired_combinatorial~40.IN1 dbrkb[39] => match_paired_combinatorial~41.IN1 dbrkb[40] => match_paired_combinatorial~42.IN1 dbrkb[41] => match_paired_combinatorial~43.IN1 dbrkb[42] => match_paired_combinatorial~44.IN1 dbrkb[43] => match_paired_combinatorial~45.IN1 dbrkb[44] => match_paired_combinatorial~46.IN1 dbrkb[45] => match_paired_combinatorial~47.IN1 dbrkb[46] => match_paired_combinatorial~48.IN1 dbrkb[47] => match_paired_combinatorial~49.IN1 dbrkb[48] => match_paired_combinatorial~50.IN1 dbrkb[49] => match_paired_combinatorial~51.IN1 dbrkb[50] => match_paired_combinatorial~52.IN1 dbrkb[51] => match_paired_combinatorial~53.IN1 dbrkb[52] => match_paired_combinatorial~54.IN1 dbrkb[53] => match_paired_combinatorial~55.IN1 dbrkb[54] => match_paired_combinatorial~56.IN1 dbrkb[55] => match_paired_combinatorial~57.IN1 dbrkb[56] => match_paired_combinatorial~58.IN1 dbrkb[57] => match_paired_combinatorial~59.IN1 dbrkb[58] => match_paired_combinatorial~60.IN1 dbrkb[59] => match_paired_combinatorial~61.IN1 dbrkb[60] => match_paired_combinatorial~62.IN1 dbrkb[61] => match_paired_combinatorial~63.IN1 dbrkb[62] => match_paired_combinatorial~64.IN1 dbrkb[63] => match_paired_combinatorial~65.IN1 dbrkb[64] => ~NO_FANOUT~ dbrkb[65] => ~NO_FANOUT~ dbrkb[66] => ~NO_FANOUT~ dbrkb[67] => ~NO_FANOUT~ dbrkb[68] => ~NO_FANOUT~ dbrkb[69] => ~NO_FANOUT~ dbrkb[70] => ~NO_FANOUT~ read => match_paired_combinatorial~68.IN1 write => match_paired_combinatorial~69.IN1 match_paired <= match_paired_combinatorial~71.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit0_match_single addr[0] => Equal0.IN23 addr[1] => Equal0.IN22 addr[2] => Equal0.IN21 addr[3] => Equal0.IN20 addr[4] => Equal0.IN19 addr[5] => Equal0.IN18 addr[6] => Equal0.IN17 addr[7] => Equal0.IN16 addr[8] => Equal0.IN15 addr[9] => Equal0.IN14 addr[10] => Equal0.IN13 addr[11] => Equal0.IN12 addr[12] => Equal0.IN11 addr[13] => Equal0.IN10 addr[14] => Equal0.IN9 addr[15] => Equal0.IN8 addr[16] => Equal0.IN7 addr[17] => Equal0.IN6 addr[18] => Equal0.IN5 addr[19] => Equal0.IN4 addr[20] => Equal0.IN3 addr[21] => Equal0.IN2 addr[22] => Equal0.IN1 addr[23] => Equal0.IN0 data[0] => Equal1.IN31 data[1] => Equal1.IN30 data[2] => Equal1.IN29 data[3] => Equal1.IN28 data[4] => Equal1.IN27 data[5] => Equal1.IN26 data[6] => Equal1.IN25 data[7] => Equal1.IN24 data[8] => Equal1.IN23 data[9] => Equal1.IN22 data[10] => Equal1.IN21 data[11] => Equal1.IN20 data[12] => Equal1.IN19 data[13] => Equal1.IN18 data[14] => Equal1.IN17 data[15] => Equal1.IN16 data[16] => Equal1.IN15 data[17] => Equal1.IN14 data[18] => Equal1.IN13 data[19] => Equal1.IN12 data[20] => Equal1.IN11 data[21] => Equal1.IN10 data[22] => Equal1.IN9 data[23] => Equal1.IN8 data[24] => Equal1.IN7 data[25] => Equal1.IN6 data[26] => Equal1.IN5 data[27] => Equal1.IN4 data[28] => Equal1.IN3 data[29] => Equal1.IN2 data[30] => Equal1.IN1 data[31] => Equal1.IN0 dbrk[0] => Equal0.IN47 dbrk[1] => Equal0.IN46 dbrk[2] => Equal0.IN45 dbrk[3] => Equal0.IN44 dbrk[4] => Equal0.IN43 dbrk[5] => Equal0.IN42 dbrk[6] => Equal0.IN41 dbrk[7] => Equal0.IN40 dbrk[8] => Equal0.IN39 dbrk[9] => Equal0.IN38 dbrk[10] => Equal0.IN37 dbrk[11] => Equal0.IN36 dbrk[12] => Equal0.IN35 dbrk[13] => Equal0.IN34 dbrk[14] => Equal0.IN33 dbrk[15] => Equal0.IN32 dbrk[16] => Equal0.IN31 dbrk[17] => Equal0.IN30 dbrk[18] => Equal0.IN29 dbrk[19] => Equal0.IN28 dbrk[20] => Equal0.IN27 dbrk[21] => Equal0.IN26 dbrk[22] => Equal0.IN25 dbrk[23] => Equal0.IN24 dbrk[24] => ~NO_FANOUT~ dbrk[25] => ~NO_FANOUT~ dbrk[26] => ~NO_FANOUT~ dbrk[27] => ~NO_FANOUT~ dbrk[28] => ~NO_FANOUT~ dbrk[29] => ~NO_FANOUT~ dbrk[30] => ~NO_FANOUT~ dbrk[31] => ~NO_FANOUT~ dbrk[32] => Equal1.IN63 dbrk[33] => Equal1.IN62 dbrk[34] => Equal1.IN61 dbrk[35] => Equal1.IN60 dbrk[36] => Equal1.IN59 dbrk[37] => Equal1.IN58 dbrk[38] => Equal1.IN57 dbrk[39] => Equal1.IN56 dbrk[40] => Equal1.IN55 dbrk[41] => Equal1.IN54 dbrk[42] => Equal1.IN53 dbrk[43] => Equal1.IN52 dbrk[44] => Equal1.IN51 dbrk[45] => Equal1.IN50 dbrk[46] => Equal1.IN49 dbrk[47] => Equal1.IN48 dbrk[48] => Equal1.IN47 dbrk[49] => Equal1.IN46 dbrk[50] => Equal1.IN45 dbrk[51] => Equal1.IN44 dbrk[52] => Equal1.IN43 dbrk[53] => Equal1.IN42 dbrk[54] => Equal1.IN41 dbrk[55] => Equal1.IN40 dbrk[56] => Equal1.IN39 dbrk[57] => Equal1.IN38 dbrk[58] => Equal1.IN37 dbrk[59] => Equal1.IN36 dbrk[60] => Equal1.IN35 dbrk[61] => Equal1.IN34 dbrk[62] => Equal1.IN33 dbrk[63] => Equal1.IN32 dbrk[64] => ~NO_FANOUT~ dbrk[65] => match_single_combinatorial~4.IN0 dbrk[66] => match_single_combinatorial~3.IN0 dbrk[67] => match_single_combinatorial~0.IN0 dbrk[68] => match_single_combinatorial~1.IN0 dbrk[69] => ~NO_FANOUT~ dbrk[70] => ~NO_FANOUT~ read => match_single_combinatorial~3.IN1 write => match_single_combinatorial~4.IN1 match_single <= match_single_combinatorial~6.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit1_match_single addr[0] => Equal0.IN23 addr[1] => Equal0.IN22 addr[2] => Equal0.IN21 addr[3] => Equal0.IN20 addr[4] => Equal0.IN19 addr[5] => Equal0.IN18 addr[6] => Equal0.IN17 addr[7] => Equal0.IN16 addr[8] => Equal0.IN15 addr[9] => Equal0.IN14 addr[10] => Equal0.IN13 addr[11] => Equal0.IN12 addr[12] => Equal0.IN11 addr[13] => Equal0.IN10 addr[14] => Equal0.IN9 addr[15] => Equal0.IN8 addr[16] => Equal0.IN7 addr[17] => Equal0.IN6 addr[18] => Equal0.IN5 addr[19] => Equal0.IN4 addr[20] => Equal0.IN3 addr[21] => Equal0.IN2 addr[22] => Equal0.IN1 addr[23] => Equal0.IN0 data[0] => Equal1.IN31 data[1] => Equal1.IN30 data[2] => Equal1.IN29 data[3] => Equal1.IN28 data[4] => Equal1.IN27 data[5] => Equal1.IN26 data[6] => Equal1.IN25 data[7] => Equal1.IN24 data[8] => Equal1.IN23 data[9] => Equal1.IN22 data[10] => Equal1.IN21 data[11] => Equal1.IN20 data[12] => Equal1.IN19 data[13] => Equal1.IN18 data[14] => Equal1.IN17 data[15] => Equal1.IN16 data[16] => Equal1.IN15 data[17] => Equal1.IN14 data[18] => Equal1.IN13 data[19] => Equal1.IN12 data[20] => Equal1.IN11 data[21] => Equal1.IN10 data[22] => Equal1.IN9 data[23] => Equal1.IN8 data[24] => Equal1.IN7 data[25] => Equal1.IN6 data[26] => Equal1.IN5 data[27] => Equal1.IN4 data[28] => Equal1.IN3 data[29] => Equal1.IN2 data[30] => Equal1.IN1 data[31] => Equal1.IN0 dbrk[0] => Equal0.IN47 dbrk[1] => Equal0.IN46 dbrk[2] => Equal0.IN45 dbrk[3] => Equal0.IN44 dbrk[4] => Equal0.IN43 dbrk[5] => Equal0.IN42 dbrk[6] => Equal0.IN41 dbrk[7] => Equal0.IN40 dbrk[8] => Equal0.IN39 dbrk[9] => Equal0.IN38 dbrk[10] => Equal0.IN37 dbrk[11] => Equal0.IN36 dbrk[12] => Equal0.IN35 dbrk[13] => Equal0.IN34 dbrk[14] => Equal0.IN33 dbrk[15] => Equal0.IN32 dbrk[16] => Equal0.IN31 dbrk[17] => Equal0.IN30 dbrk[18] => Equal0.IN29 dbrk[19] => Equal0.IN28 dbrk[20] => Equal0.IN27 dbrk[21] => Equal0.IN26 dbrk[22] => Equal0.IN25 dbrk[23] => Equal0.IN24 dbrk[24] => ~NO_FANOUT~ dbrk[25] => ~NO_FANOUT~ dbrk[26] => ~NO_FANOUT~ dbrk[27] => ~NO_FANOUT~ dbrk[28] => ~NO_FANOUT~ dbrk[29] => ~NO_FANOUT~ dbrk[30] => ~NO_FANOUT~ dbrk[31] => ~NO_FANOUT~ dbrk[32] => Equal1.IN63 dbrk[33] => Equal1.IN62 dbrk[34] => Equal1.IN61 dbrk[35] => Equal1.IN60 dbrk[36] => Equal1.IN59 dbrk[37] => Equal1.IN58 dbrk[38] => Equal1.IN57 dbrk[39] => Equal1.IN56 dbrk[40] => Equal1.IN55 dbrk[41] => Equal1.IN54 dbrk[42] => Equal1.IN53 dbrk[43] => Equal1.IN52 dbrk[44] => Equal1.IN51 dbrk[45] => Equal1.IN50 dbrk[46] => Equal1.IN49 dbrk[47] => Equal1.IN48 dbrk[48] => Equal1.IN47 dbrk[49] => Equal1.IN46 dbrk[50] => Equal1.IN45 dbrk[51] => Equal1.IN44 dbrk[52] => Equal1.IN43 dbrk[53] => Equal1.IN42 dbrk[54] => Equal1.IN41 dbrk[55] => Equal1.IN40 dbrk[56] => Equal1.IN39 dbrk[57] => Equal1.IN38 dbrk[58] => Equal1.IN37 dbrk[59] => Equal1.IN36 dbrk[60] => Equal1.IN35 dbrk[61] => Equal1.IN34 dbrk[62] => Equal1.IN33 dbrk[63] => Equal1.IN32 dbrk[64] => ~NO_FANOUT~ dbrk[65] => match_single_combinatorial~4.IN0 dbrk[66] => match_single_combinatorial~3.IN0 dbrk[67] => match_single_combinatorial~0.IN0 dbrk[68] => match_single_combinatorial~1.IN0 dbrk[69] => ~NO_FANOUT~ dbrk[70] => ~NO_FANOUT~ read => match_single_combinatorial~3.IN1 write => match_single_combinatorial~4.IN1 match_single <= match_single_combinatorial~6.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_paired:cpu_0_nios2_oci_dbrk_hit2_match_paired addr[0] => LessThan1.IN24 addr[0] => LessThan0.IN24 addr[1] => LessThan1.IN23 addr[1] => LessThan0.IN23 addr[2] => LessThan1.IN22 addr[2] => LessThan0.IN22 addr[3] => LessThan1.IN21 addr[3] => LessThan0.IN21 addr[4] => LessThan1.IN20 addr[4] => LessThan0.IN20 addr[5] => LessThan1.IN19 addr[5] => LessThan0.IN19 addr[6] => LessThan1.IN18 addr[6] => LessThan0.IN18 addr[7] => LessThan1.IN17 addr[7] => LessThan0.IN17 addr[8] => LessThan1.IN16 addr[8] => LessThan0.IN16 addr[9] => LessThan1.IN15 addr[9] => LessThan0.IN15 addr[10] => LessThan1.IN14 addr[10] => LessThan0.IN14 addr[11] => LessThan1.IN13 addr[11] => LessThan0.IN13 addr[12] => LessThan1.IN12 addr[12] => LessThan0.IN12 addr[13] => LessThan1.IN11 addr[13] => LessThan0.IN11 addr[14] => LessThan1.IN10 addr[14] => LessThan0.IN10 addr[15] => LessThan1.IN9 addr[15] => LessThan0.IN9 addr[16] => LessThan1.IN8 addr[16] => LessThan0.IN8 addr[17] => LessThan1.IN7 addr[17] => LessThan0.IN7 addr[18] => LessThan1.IN6 addr[18] => LessThan0.IN6 addr[19] => LessThan1.IN5 addr[19] => LessThan0.IN5 addr[20] => LessThan1.IN4 addr[20] => LessThan0.IN4 addr[21] => LessThan1.IN3 addr[21] => LessThan0.IN3 addr[22] => LessThan1.IN2 addr[22] => LessThan0.IN2 addr[23] => LessThan1.IN1 addr[23] => LessThan0.IN1 data[0] => match_paired_combinatorial~2.IN0 data[1] => match_paired_combinatorial~3.IN0 data[2] => match_paired_combinatorial~4.IN0 data[3] => match_paired_combinatorial~5.IN0 data[4] => match_paired_combinatorial~6.IN0 data[5] => match_paired_combinatorial~7.IN0 data[6] => match_paired_combinatorial~8.IN0 data[7] => match_paired_combinatorial~9.IN0 data[8] => match_paired_combinatorial~10.IN0 data[9] => match_paired_combinatorial~11.IN0 data[10] => match_paired_combinatorial~12.IN0 data[11] => match_paired_combinatorial~13.IN0 data[12] => match_paired_combinatorial~14.IN0 data[13] => match_paired_combinatorial~15.IN0 data[14] => match_paired_combinatorial~16.IN0 data[15] => match_paired_combinatorial~17.IN0 data[16] => match_paired_combinatorial~18.IN0 data[17] => match_paired_combinatorial~19.IN0 data[18] => match_paired_combinatorial~20.IN0 data[19] => match_paired_combinatorial~21.IN0 data[20] => match_paired_combinatorial~22.IN0 data[21] => match_paired_combinatorial~23.IN0 data[22] => match_paired_combinatorial~24.IN0 data[23] => match_paired_combinatorial~25.IN0 data[24] => match_paired_combinatorial~26.IN0 data[25] => match_paired_combinatorial~27.IN0 data[26] => match_paired_combinatorial~28.IN0 data[27] => match_paired_combinatorial~29.IN0 data[28] => match_paired_combinatorial~30.IN0 data[29] => match_paired_combinatorial~31.IN0 data[30] => match_paired_combinatorial~32.IN0 data[31] => match_paired_combinatorial~33.IN0 dbrka[0] => LessThan0.IN48 dbrka[1] => LessThan0.IN47 dbrka[2] => LessThan0.IN46 dbrka[3] => LessThan0.IN45 dbrka[4] => LessThan0.IN44 dbrka[5] => LessThan0.IN43 dbrka[6] => LessThan0.IN42 dbrka[7] => LessThan0.IN41 dbrka[8] => LessThan0.IN40 dbrka[9] => LessThan0.IN39 dbrka[10] => LessThan0.IN38 dbrka[11] => LessThan0.IN37 dbrka[12] => LessThan0.IN36 dbrka[13] => LessThan0.IN35 dbrka[14] => LessThan0.IN34 dbrka[15] => LessThan0.IN33 dbrka[16] => LessThan0.IN32 dbrka[17] => LessThan0.IN31 dbrka[18] => LessThan0.IN30 dbrka[19] => LessThan0.IN29 dbrka[20] => LessThan0.IN28 dbrka[21] => LessThan0.IN27 dbrka[22] => LessThan0.IN26 dbrka[23] => LessThan0.IN25 dbrka[24] => ~NO_FANOUT~ dbrka[25] => ~NO_FANOUT~ dbrka[26] => ~NO_FANOUT~ dbrka[27] => ~NO_FANOUT~ dbrka[28] => ~NO_FANOUT~ dbrka[29] => ~NO_FANOUT~ dbrka[30] => ~NO_FANOUT~ dbrka[31] => ~NO_FANOUT~ dbrka[32] => match_paired_combinatorial~2.IN1 dbrka[33] => match_paired_combinatorial~3.IN1 dbrka[34] => match_paired_combinatorial~4.IN1 dbrka[35] => match_paired_combinatorial~5.IN1 dbrka[36] => match_paired_combinatorial~6.IN1 dbrka[37] => match_paired_combinatorial~7.IN1 dbrka[38] => match_paired_combinatorial~8.IN1 dbrka[39] => match_paired_combinatorial~9.IN1 dbrka[40] => match_paired_combinatorial~10.IN1 dbrka[41] => match_paired_combinatorial~11.IN1 dbrka[42] => match_paired_combinatorial~12.IN1 dbrka[43] => match_paired_combinatorial~13.IN1 dbrka[44] => match_paired_combinatorial~14.IN1 dbrka[45] => match_paired_combinatorial~15.IN1 dbrka[46] => match_paired_combinatorial~16.IN1 dbrka[47] => match_paired_combinatorial~17.IN1 dbrka[48] => match_paired_combinatorial~18.IN1 dbrka[49] => match_paired_combinatorial~19.IN1 dbrka[50] => match_paired_combinatorial~20.IN1 dbrka[51] => match_paired_combinatorial~21.IN1 dbrka[52] => match_paired_combinatorial~22.IN1 dbrka[53] => match_paired_combinatorial~23.IN1 dbrka[54] => match_paired_combinatorial~24.IN1 dbrka[55] => match_paired_combinatorial~25.IN1 dbrka[56] => match_paired_combinatorial~26.IN1 dbrka[57] => match_paired_combinatorial~27.IN1 dbrka[58] => match_paired_combinatorial~28.IN1 dbrka[59] => match_paired_combinatorial~29.IN1 dbrka[60] => match_paired_combinatorial~30.IN1 dbrka[61] => match_paired_combinatorial~31.IN1 dbrka[62] => match_paired_combinatorial~32.IN1 dbrka[63] => match_paired_combinatorial~33.IN1 dbrka[64] => ~NO_FANOUT~ dbrka[65] => match_paired_combinatorial~69.IN0 dbrka[66] => match_paired_combinatorial~68.IN0 dbrka[67] => match_paired_combinatorial~1.IN0 dbrka[68] => match_paired_combinatorial~66.IN0 dbrka[69] => ~NO_FANOUT~ dbrka[70] => ~NO_FANOUT~ dbrkb[0] => LessThan1.IN48 dbrkb[1] => LessThan1.IN47 dbrkb[2] => LessThan1.IN46 dbrkb[3] => LessThan1.IN45 dbrkb[4] => LessThan1.IN44 dbrkb[5] => LessThan1.IN43 dbrkb[6] => LessThan1.IN42 dbrkb[7] => LessThan1.IN41 dbrkb[8] => LessThan1.IN40 dbrkb[9] => LessThan1.IN39 dbrkb[10] => LessThan1.IN38 dbrkb[11] => LessThan1.IN37 dbrkb[12] => LessThan1.IN36 dbrkb[13] => LessThan1.IN35 dbrkb[14] => LessThan1.IN34 dbrkb[15] => LessThan1.IN33 dbrkb[16] => LessThan1.IN32 dbrkb[17] => LessThan1.IN31 dbrkb[18] => LessThan1.IN30 dbrkb[19] => LessThan1.IN29 dbrkb[20] => LessThan1.IN28 dbrkb[21] => LessThan1.IN27 dbrkb[22] => LessThan1.IN26 dbrkb[23] => LessThan1.IN25 dbrkb[24] => ~NO_FANOUT~ dbrkb[25] => ~NO_FANOUT~ dbrkb[26] => ~NO_FANOUT~ dbrkb[27] => ~NO_FANOUT~ dbrkb[28] => ~NO_FANOUT~ dbrkb[29] => ~NO_FANOUT~ dbrkb[30] => ~NO_FANOUT~ dbrkb[31] => ~NO_FANOUT~ dbrkb[32] => match_paired_combinatorial~34.IN1 dbrkb[33] => match_paired_combinatorial~35.IN1 dbrkb[34] => match_paired_combinatorial~36.IN1 dbrkb[35] => match_paired_combinatorial~37.IN1 dbrkb[36] => match_paired_combinatorial~38.IN1 dbrkb[37] => match_paired_combinatorial~39.IN1 dbrkb[38] => match_paired_combinatorial~40.IN1 dbrkb[39] => match_paired_combinatorial~41.IN1 dbrkb[40] => match_paired_combinatorial~42.IN1 dbrkb[41] => match_paired_combinatorial~43.IN1 dbrkb[42] => match_paired_combinatorial~44.IN1 dbrkb[43] => match_paired_combinatorial~45.IN1 dbrkb[44] => match_paired_combinatorial~46.IN1 dbrkb[45] => match_paired_combinatorial~47.IN1 dbrkb[46] => match_paired_combinatorial~48.IN1 dbrkb[47] => match_paired_combinatorial~49.IN1 dbrkb[48] => match_paired_combinatorial~50.IN1 dbrkb[49] => match_paired_combinatorial~51.IN1 dbrkb[50] => match_paired_combinatorial~52.IN1 dbrkb[51] => match_paired_combinatorial~53.IN1 dbrkb[52] => match_paired_combinatorial~54.IN1 dbrkb[53] => match_paired_combinatorial~55.IN1 dbrkb[54] => match_paired_combinatorial~56.IN1 dbrkb[55] => match_paired_combinatorial~57.IN1 dbrkb[56] => match_paired_combinatorial~58.IN1 dbrkb[57] => match_paired_combinatorial~59.IN1 dbrkb[58] => match_paired_combinatorial~60.IN1 dbrkb[59] => match_paired_combinatorial~61.IN1 dbrkb[60] => match_paired_combinatorial~62.IN1 dbrkb[61] => match_paired_combinatorial~63.IN1 dbrkb[62] => match_paired_combinatorial~64.IN1 dbrkb[63] => match_paired_combinatorial~65.IN1 dbrkb[64] => ~NO_FANOUT~ dbrkb[65] => ~NO_FANOUT~ dbrkb[66] => ~NO_FANOUT~ dbrkb[67] => ~NO_FANOUT~ dbrkb[68] => ~NO_FANOUT~ dbrkb[69] => ~NO_FANOUT~ dbrkb[70] => ~NO_FANOUT~ read => match_paired_combinatorial~68.IN1 write => match_paired_combinatorial~69.IN1 match_paired <= match_paired_combinatorial~71.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit2_match_single addr[0] => Equal0.IN23 addr[1] => Equal0.IN22 addr[2] => Equal0.IN21 addr[3] => Equal0.IN20 addr[4] => Equal0.IN19 addr[5] => Equal0.IN18 addr[6] => Equal0.IN17 addr[7] => Equal0.IN16 addr[8] => Equal0.IN15 addr[9] => Equal0.IN14 addr[10] => Equal0.IN13 addr[11] => Equal0.IN12 addr[12] => Equal0.IN11 addr[13] => Equal0.IN10 addr[14] => Equal0.IN9 addr[15] => Equal0.IN8 addr[16] => Equal0.IN7 addr[17] => Equal0.IN6 addr[18] => Equal0.IN5 addr[19] => Equal0.IN4 addr[20] => Equal0.IN3 addr[21] => Equal0.IN2 addr[22] => Equal0.IN1 addr[23] => Equal0.IN0 data[0] => Equal1.IN31 data[1] => Equal1.IN30 data[2] => Equal1.IN29 data[3] => Equal1.IN28 data[4] => Equal1.IN27 data[5] => Equal1.IN26 data[6] => Equal1.IN25 data[7] => Equal1.IN24 data[8] => Equal1.IN23 data[9] => Equal1.IN22 data[10] => Equal1.IN21 data[11] => Equal1.IN20 data[12] => Equal1.IN19 data[13] => Equal1.IN18 data[14] => Equal1.IN17 data[15] => Equal1.IN16 data[16] => Equal1.IN15 data[17] => Equal1.IN14 data[18] => Equal1.IN13 data[19] => Equal1.IN12 data[20] => Equal1.IN11 data[21] => Equal1.IN10 data[22] => Equal1.IN9 data[23] => Equal1.IN8 data[24] => Equal1.IN7 data[25] => Equal1.IN6 data[26] => Equal1.IN5 data[27] => Equal1.IN4 data[28] => Equal1.IN3 data[29] => Equal1.IN2 data[30] => Equal1.IN1 data[31] => Equal1.IN0 dbrk[0] => Equal0.IN47 dbrk[1] => Equal0.IN46 dbrk[2] => Equal0.IN45 dbrk[3] => Equal0.IN44 dbrk[4] => Equal0.IN43 dbrk[5] => Equal0.IN42 dbrk[6] => Equal0.IN41 dbrk[7] => Equal0.IN40 dbrk[8] => Equal0.IN39 dbrk[9] => Equal0.IN38 dbrk[10] => Equal0.IN37 dbrk[11] => Equal0.IN36 dbrk[12] => Equal0.IN35 dbrk[13] => Equal0.IN34 dbrk[14] => Equal0.IN33 dbrk[15] => Equal0.IN32 dbrk[16] => Equal0.IN31 dbrk[17] => Equal0.IN30 dbrk[18] => Equal0.IN29 dbrk[19] => Equal0.IN28 dbrk[20] => Equal0.IN27 dbrk[21] => Equal0.IN26 dbrk[22] => Equal0.IN25 dbrk[23] => Equal0.IN24 dbrk[24] => ~NO_FANOUT~ dbrk[25] => ~NO_FANOUT~ dbrk[26] => ~NO_FANOUT~ dbrk[27] => ~NO_FANOUT~ dbrk[28] => ~NO_FANOUT~ dbrk[29] => ~NO_FANOUT~ dbrk[30] => ~NO_FANOUT~ dbrk[31] => ~NO_FANOUT~ dbrk[32] => Equal1.IN63 dbrk[33] => Equal1.IN62 dbrk[34] => Equal1.IN61 dbrk[35] => Equal1.IN60 dbrk[36] => Equal1.IN59 dbrk[37] => Equal1.IN58 dbrk[38] => Equal1.IN57 dbrk[39] => Equal1.IN56 dbrk[40] => Equal1.IN55 dbrk[41] => Equal1.IN54 dbrk[42] => Equal1.IN53 dbrk[43] => Equal1.IN52 dbrk[44] => Equal1.IN51 dbrk[45] => Equal1.IN50 dbrk[46] => Equal1.IN49 dbrk[47] => Equal1.IN48 dbrk[48] => Equal1.IN47 dbrk[49] => Equal1.IN46 dbrk[50] => Equal1.IN45 dbrk[51] => Equal1.IN44 dbrk[52] => Equal1.IN43 dbrk[53] => Equal1.IN42 dbrk[54] => Equal1.IN41 dbrk[55] => Equal1.IN40 dbrk[56] => Equal1.IN39 dbrk[57] => Equal1.IN38 dbrk[58] => Equal1.IN37 dbrk[59] => Equal1.IN36 dbrk[60] => Equal1.IN35 dbrk[61] => Equal1.IN34 dbrk[62] => Equal1.IN33 dbrk[63] => Equal1.IN32 dbrk[64] => ~NO_FANOUT~ dbrk[65] => match_single_combinatorial~4.IN0 dbrk[66] => match_single_combinatorial~3.IN0 dbrk[67] => match_single_combinatorial~0.IN0 dbrk[68] => match_single_combinatorial~1.IN0 dbrk[69] => ~NO_FANOUT~ dbrk[70] => ~NO_FANOUT~ read => match_single_combinatorial~3.IN1 write => match_single_combinatorial~4.IN1 match_single <= match_single_combinatorial~6.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit3_match_single addr[0] => Equal0.IN23 addr[1] => Equal0.IN22 addr[2] => Equal0.IN21 addr[3] => Equal0.IN20 addr[4] => Equal0.IN19 addr[5] => Equal0.IN18 addr[6] => Equal0.IN17 addr[7] => Equal0.IN16 addr[8] => Equal0.IN15 addr[9] => Equal0.IN14 addr[10] => Equal0.IN13 addr[11] => Equal0.IN12 addr[12] => Equal0.IN11 addr[13] => Equal0.IN10 addr[14] => Equal0.IN9 addr[15] => Equal0.IN8 addr[16] => Equal0.IN7 addr[17] => Equal0.IN6 addr[18] => Equal0.IN5 addr[19] => Equal0.IN4 addr[20] => Equal0.IN3 addr[21] => Equal0.IN2 addr[22] => Equal0.IN1 addr[23] => Equal0.IN0 data[0] => Equal1.IN31 data[1] => Equal1.IN30 data[2] => Equal1.IN29 data[3] => Equal1.IN28 data[4] => Equal1.IN27 data[5] => Equal1.IN26 data[6] => Equal1.IN25 data[7] => Equal1.IN24 data[8] => Equal1.IN23 data[9] => Equal1.IN22 data[10] => Equal1.IN21 data[11] => Equal1.IN20 data[12] => Equal1.IN19 data[13] => Equal1.IN18 data[14] => Equal1.IN17 data[15] => Equal1.IN16 data[16] => Equal1.IN15 data[17] => Equal1.IN14 data[18] => Equal1.IN13 data[19] => Equal1.IN12 data[20] => Equal1.IN11 data[21] => Equal1.IN10 data[22] => Equal1.IN9 data[23] => Equal1.IN8 data[24] => Equal1.IN7 data[25] => Equal1.IN6 data[26] => Equal1.IN5 data[27] => Equal1.IN4 data[28] => Equal1.IN3 data[29] => Equal1.IN2 data[30] => Equal1.IN1 data[31] => Equal1.IN0 dbrk[0] => Equal0.IN47 dbrk[1] => Equal0.IN46 dbrk[2] => Equal0.IN45 dbrk[3] => Equal0.IN44 dbrk[4] => Equal0.IN43 dbrk[5] => Equal0.IN42 dbrk[6] => Equal0.IN41 dbrk[7] => Equal0.IN40 dbrk[8] => Equal0.IN39 dbrk[9] => Equal0.IN38 dbrk[10] => Equal0.IN37 dbrk[11] => Equal0.IN36 dbrk[12] => Equal0.IN35 dbrk[13] => Equal0.IN34 dbrk[14] => Equal0.IN33 dbrk[15] => Equal0.IN32 dbrk[16] => Equal0.IN31 dbrk[17] => Equal0.IN30 dbrk[18] => Equal0.IN29 dbrk[19] => Equal0.IN28 dbrk[20] => Equal0.IN27 dbrk[21] => Equal0.IN26 dbrk[22] => Equal0.IN25 dbrk[23] => Equal0.IN24 dbrk[24] => ~NO_FANOUT~ dbrk[25] => ~NO_FANOUT~ dbrk[26] => ~NO_FANOUT~ dbrk[27] => ~NO_FANOUT~ dbrk[28] => ~NO_FANOUT~ dbrk[29] => ~NO_FANOUT~ dbrk[30] => ~NO_FANOUT~ dbrk[31] => ~NO_FANOUT~ dbrk[32] => Equal1.IN63 dbrk[33] => Equal1.IN62 dbrk[34] => Equal1.IN61 dbrk[35] => Equal1.IN60 dbrk[36] => Equal1.IN59 dbrk[37] => Equal1.IN58 dbrk[38] => Equal1.IN57 dbrk[39] => Equal1.IN56 dbrk[40] => Equal1.IN55 dbrk[41] => Equal1.IN54 dbrk[42] => Equal1.IN53 dbrk[43] => Equal1.IN52 dbrk[44] => Equal1.IN51 dbrk[45] => Equal1.IN50 dbrk[46] => Equal1.IN49 dbrk[47] => Equal1.IN48 dbrk[48] => Equal1.IN47 dbrk[49] => Equal1.IN46 dbrk[50] => Equal1.IN45 dbrk[51] => Equal1.IN44 dbrk[52] => Equal1.IN43 dbrk[53] => Equal1.IN42 dbrk[54] => Equal1.IN41 dbrk[55] => Equal1.IN40 dbrk[56] => Equal1.IN39 dbrk[57] => Equal1.IN38 dbrk[58] => Equal1.IN37 dbrk[59] => Equal1.IN36 dbrk[60] => Equal1.IN35 dbrk[61] => Equal1.IN34 dbrk[62] => Equal1.IN33 dbrk[63] => Equal1.IN32 dbrk[64] => ~NO_FANOUT~ dbrk[65] => match_single_combinatorial~4.IN0 dbrk[66] => match_single_combinatorial~3.IN0 dbrk[67] => match_single_combinatorial~0.IN0 dbrk[68] => match_single_combinatorial~1.IN0 dbrk[69] => ~NO_FANOUT~ dbrk[70] => ~NO_FANOUT~ read => match_single_combinatorial~3.IN1 write => match_single_combinatorial~4.IN1 match_single <= match_single_combinatorial~6.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace A_cmp_result => ~NO_FANOUT~ A_ctrl_exception => ~NO_FANOUT~ A_en => ~NO_FANOUT~ A_op_beq => ~NO_FANOUT~ A_op_bge => ~NO_FANOUT~ A_op_bgeu => ~NO_FANOUT~ A_op_blt => ~NO_FANOUT~ A_op_bltu => ~NO_FANOUT~ A_op_bne => ~NO_FANOUT~ A_op_br => ~NO_FANOUT~ A_op_bret => ~NO_FANOUT~ A_op_call => ~NO_FANOUT~ A_op_callr => ~NO_FANOUT~ A_op_eret => ~NO_FANOUT~ A_op_jmp => ~NO_FANOUT~ A_op_ret => ~NO_FANOUT~ A_pcb[0] => ~NO_FANOUT~ A_pcb[1] => ~NO_FANOUT~ A_pcb[2] => ~NO_FANOUT~ A_pcb[3] => ~NO_FANOUT~ A_pcb[4] => ~NO_FANOUT~ A_pcb[5] => ~NO_FANOUT~ A_pcb[6] => ~NO_FANOUT~ A_pcb[7] => ~NO_FANOUT~ A_pcb[8] => ~NO_FANOUT~ A_pcb[9] => ~NO_FANOUT~ A_pcb[10] => ~NO_FANOUT~ A_pcb[11] => ~NO_FANOUT~ A_pcb[12] => ~NO_FANOUT~ A_pcb[13] => ~NO_FANOUT~ A_pcb[14] => ~NO_FANOUT~ A_pcb[15] => ~NO_FANOUT~ A_pcb[16] => ~NO_FANOUT~ A_pcb[17] => ~NO_FANOUT~ A_pcb[18] => ~NO_FANOUT~ A_pcb[19] => ~NO_FANOUT~ A_pcb[20] => ~NO_FANOUT~ A_pcb[21] => ~NO_FANOUT~ A_pcb[22] => ~NO_FANOUT~ A_pcb[23] => ~NO_FANOUT~ A_valid => ~NO_FANOUT~ A_wr_data_filtered[0] => ~NO_FANOUT~ A_wr_data_filtered[1] => ~NO_FANOUT~ A_wr_data_filtered[2] => ~NO_FANOUT~ A_wr_data_filtered[3] => ~NO_FANOUT~ A_wr_data_filtered[4] => ~NO_FANOUT~ A_wr_data_filtered[5] => ~NO_FANOUT~ A_wr_data_filtered[6] => ~NO_FANOUT~ A_wr_data_filtered[7] => ~NO_FANOUT~ A_wr_data_filtered[8] => ~NO_FANOUT~ A_wr_data_filtered[9] => ~NO_FANOUT~ A_wr_data_filtered[10] => ~NO_FANOUT~ A_wr_data_filtered[11] => ~NO_FANOUT~ A_wr_data_filtered[12] => ~NO_FANOUT~ A_wr_data_filtered[13] => ~NO_FANOUT~ A_wr_data_filtered[14] => ~NO_FANOUT~ A_wr_data_filtered[15] => ~NO_FANOUT~ A_wr_data_filtered[16] => ~NO_FANOUT~ A_wr_data_filtered[17] => ~NO_FANOUT~ A_wr_data_filtered[18] => ~NO_FANOUT~ A_wr_data_filtered[19] => ~NO_FANOUT~ A_wr_data_filtered[20] => ~NO_FANOUT~ A_wr_data_filtered[21] => ~NO_FANOUT~ A_wr_data_filtered[22] => ~NO_FANOUT~ A_wr_data_filtered[23] => ~NO_FANOUT~ A_wr_data_filtered[24] => ~NO_FANOUT~ A_wr_data_filtered[25] => ~NO_FANOUT~ A_wr_data_filtered[26] => ~NO_FANOUT~ A_wr_data_filtered[27] => ~NO_FANOUT~ A_wr_data_filtered[28] => ~NO_FANOUT~ A_wr_data_filtered[29] => ~NO_FANOUT~ A_wr_data_filtered[30] => ~NO_FANOUT~ A_wr_data_filtered[31] => ~NO_FANOUT~ clk => itm[35]~reg0.CLK clk => itm[34]~reg0.CLK clk => itm[33]~reg0.CLK clk => itm[32]~reg0.CLK clk => itm[31]~reg0.CLK clk => itm[30]~reg0.CLK clk => itm[29]~reg0.CLK clk => itm[28]~reg0.CLK clk => itm[27]~reg0.CLK clk => itm[26]~reg0.CLK clk => itm[25]~reg0.CLK clk => itm[24]~reg0.CLK clk => itm[23]~reg0.CLK clk => itm[22]~reg0.CLK clk => itm[21]~reg0.CLK clk => itm[20]~reg0.CLK clk => itm[19]~reg0.CLK clk => itm[18]~reg0.CLK clk => itm[17]~reg0.CLK clk => itm[16]~reg0.CLK clk => itm[15]~reg0.CLK clk => itm[14]~reg0.CLK clk => itm[13]~reg0.CLK clk => itm[12]~reg0.CLK clk => itm[11]~reg0.CLK clk => itm[10]~reg0.CLK clk => itm[9]~reg0.CLK clk => itm[8]~reg0.CLK clk => itm[7]~reg0.CLK clk => itm[6]~reg0.CLK clk => itm[5]~reg0.CLK clk => itm[4]~reg0.CLK clk => itm[3]~reg0.CLK clk => itm[2]~reg0.CLK clk => itm[1]~reg0.CLK clk => itm[0]~reg0.CLK dbrk_traceoff => ~NO_FANOUT~ dbrk_traceon => ~NO_FANOUT~ debugack => ~NO_FANOUT~ jdo[0] => ~NO_FANOUT~ jdo[1] => ~NO_FANOUT~ jdo[2] => ~NO_FANOUT~ jdo[3] => ~NO_FANOUT~ jdo[4] => ~NO_FANOUT~ jdo[5] => ~NO_FANOUT~ jdo[6] => ~NO_FANOUT~ jdo[7] => ~NO_FANOUT~ jdo[8] => ~NO_FANOUT~ jdo[9] => ~NO_FANOUT~ jdo[10] => ~NO_FANOUT~ jdo[11] => ~NO_FANOUT~ jdo[12] => ~NO_FANOUT~ jdo[13] => ~NO_FANOUT~ jdo[14] => ~NO_FANOUT~ jdo[15] => ~NO_FANOUT~ jrst_n => itm[35]~reg0.ACLR jrst_n => itm[34]~reg0.ACLR jrst_n => itm[33]~reg0.ACLR jrst_n => itm[32]~reg0.ACLR jrst_n => itm[31]~reg0.ACLR jrst_n => itm[30]~reg0.ACLR jrst_n => itm[29]~reg0.ACLR jrst_n => itm[28]~reg0.ACLR jrst_n => itm[27]~reg0.ACLR jrst_n => itm[26]~reg0.ACLR jrst_n => itm[25]~reg0.ACLR jrst_n => itm[24]~reg0.ACLR jrst_n => itm[23]~reg0.ACLR jrst_n => itm[22]~reg0.ACLR jrst_n => itm[21]~reg0.ACLR jrst_n => itm[20]~reg0.ACLR jrst_n => itm[19]~reg0.ACLR jrst_n => itm[18]~reg0.ACLR jrst_n => itm[17]~reg0.ACLR jrst_n => itm[16]~reg0.ACLR jrst_n => itm[15]~reg0.ACLR jrst_n => itm[14]~reg0.ACLR jrst_n => itm[13]~reg0.ACLR jrst_n => itm[12]~reg0.ACLR jrst_n => itm[11]~reg0.ACLR jrst_n => itm[10]~reg0.ACLR jrst_n => itm[9]~reg0.ACLR jrst_n => itm[8]~reg0.ACLR jrst_n => itm[7]~reg0.ACLR jrst_n => itm[6]~reg0.ACLR jrst_n => itm[5]~reg0.ACLR jrst_n => itm[4]~reg0.ACLR jrst_n => itm[3]~reg0.ACLR jrst_n => itm[2]~reg0.ACLR jrst_n => itm[1]~reg0.ACLR jrst_n => itm[0]~reg0.ACLR reset_n => ~NO_FANOUT~ take_action_tracectrl => ~NO_FANOUT~ trc_enb => ~NO_FANOUT~ xbrk_traceoff => ~NO_FANOUT~ xbrk_traceon => ~NO_FANOUT~ xbrk_wrap_traceoff => ~NO_FANOUT~ itm[0] <= itm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[1] <= itm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[2] <= itm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[3] <= itm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[4] <= itm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[5] <= itm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[6] <= itm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[7] <= itm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[8] <= itm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[9] <= itm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[10] <= itm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[11] <= itm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[12] <= itm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[13] <= itm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[14] <= itm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[15] <= itm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[16] <= itm[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[17] <= itm[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[18] <= itm[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[19] <= itm[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[20] <= itm[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[21] <= itm[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[22] <= itm[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[23] <= itm[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[24] <= itm[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[25] <= itm[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[26] <= itm[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[27] <= itm[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[28] <= itm[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[29] <= itm[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[30] <= itm[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[31] <= itm[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[32] <= itm[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[33] <= itm[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[34] <= itm[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE itm[35] <= itm[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE trc_ctrl[0] <= trc_ctrl[1] <= trc_ctrl[2] <= trc_ctrl[3] <= trc_ctrl[4] <= trc_ctrl[5] <= trc_ctrl[6] <= trc_ctrl[7] <= trc_ctrl[8] <= trc_ctrl[9] <= trc_ctrl[10] <= trc_ctrl[11] <= trc_ctrl[12] <= trc_ctrl[13] <= trc_ctrl[14] <= trc_ctrl[15] <= trc_on <= |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace clk => atm[35]~reg0.CLK clk => atm[34]~reg0.CLK clk => atm[33]~reg0.CLK clk => atm[32]~reg0.CLK clk => atm[31]~reg0.CLK clk => atm[30]~reg0.CLK clk => atm[29]~reg0.CLK clk => atm[28]~reg0.CLK clk => atm[27]~reg0.CLK clk => atm[26]~reg0.CLK clk => atm[25]~reg0.CLK clk => atm[24]~reg0.CLK clk => atm[23]~reg0.CLK clk => atm[22]~reg0.CLK clk => atm[21]~reg0.CLK clk => atm[20]~reg0.CLK clk => atm[19]~reg0.CLK clk => atm[18]~reg0.CLK clk => atm[17]~reg0.CLK clk => atm[16]~reg0.CLK clk => atm[15]~reg0.CLK clk => atm[14]~reg0.CLK clk => atm[13]~reg0.CLK clk => atm[12]~reg0.CLK clk => atm[11]~reg0.CLK clk => atm[10]~reg0.CLK clk => atm[9]~reg0.CLK clk => atm[8]~reg0.CLK clk => atm[7]~reg0.CLK clk => atm[6]~reg0.CLK clk => atm[5]~reg0.CLK clk => atm[4]~reg0.CLK clk => atm[3]~reg0.CLK clk => atm[2]~reg0.CLK clk => atm[1]~reg0.CLK clk => atm[0]~reg0.CLK clk => dtm[35]~reg0.CLK clk => dtm[34]~reg0.CLK clk => dtm[33]~reg0.CLK clk => dtm[32]~reg0.CLK clk => dtm[31]~reg0.CLK clk => dtm[30]~reg0.CLK clk => dtm[29]~reg0.CLK clk => dtm[28]~reg0.CLK clk => dtm[27]~reg0.CLK clk => dtm[26]~reg0.CLK clk => dtm[25]~reg0.CLK clk => dtm[24]~reg0.CLK clk => dtm[23]~reg0.CLK clk => dtm[22]~reg0.CLK clk => dtm[21]~reg0.CLK clk => dtm[20]~reg0.CLK clk => dtm[19]~reg0.CLK clk => dtm[18]~reg0.CLK clk => dtm[17]~reg0.CLK clk => dtm[16]~reg0.CLK clk => dtm[15]~reg0.CLK clk => dtm[14]~reg0.CLK clk => dtm[13]~reg0.CLK clk => dtm[12]~reg0.CLK clk => dtm[11]~reg0.CLK clk => dtm[10]~reg0.CLK clk => dtm[9]~reg0.CLK clk => dtm[8]~reg0.CLK clk => dtm[7]~reg0.CLK clk => dtm[6]~reg0.CLK clk => dtm[5]~reg0.CLK clk => dtm[4]~reg0.CLK clk => dtm[3]~reg0.CLK clk => dtm[2]~reg0.CLK clk => dtm[1]~reg0.CLK clk => dtm[0]~reg0.CLK cpu_d_address[0] => atm[0]~reg0.DATAIN cpu_d_address[1] => atm[1]~reg0.DATAIN cpu_d_address[2] => atm[2]~reg0.DATAIN cpu_d_address[3] => atm[3]~reg0.DATAIN cpu_d_address[4] => atm[4]~reg0.DATAIN cpu_d_address[5] => atm[5]~reg0.DATAIN cpu_d_address[6] => atm[6]~reg0.DATAIN cpu_d_address[7] => atm[7]~reg0.DATAIN cpu_d_address[8] => atm[8]~reg0.DATAIN cpu_d_address[9] => atm[9]~reg0.DATAIN cpu_d_address[10] => atm[10]~reg0.DATAIN cpu_d_address[11] => atm[11]~reg0.DATAIN cpu_d_address[12] => atm[12]~reg0.DATAIN cpu_d_address[13] => atm[13]~reg0.DATAIN cpu_d_address[14] => atm[14]~reg0.DATAIN cpu_d_address[15] => atm[15]~reg0.DATAIN cpu_d_address[16] => atm[16]~reg0.DATAIN cpu_d_address[17] => atm[17]~reg0.DATAIN cpu_d_address[18] => atm[18]~reg0.DATAIN cpu_d_address[19] => atm[19]~reg0.DATAIN cpu_d_address[20] => atm[20]~reg0.DATAIN cpu_d_address[21] => atm[21]~reg0.DATAIN cpu_d_address[22] => atm[22]~reg0.DATAIN cpu_d_address[23] => atm[23]~reg0.DATAIN cpu_d_read => always0~2.IN1 cpu_d_readdata[0] => dtm~32.DATAA cpu_d_readdata[1] => dtm~31.DATAA cpu_d_readdata[2] => dtm~30.DATAA cpu_d_readdata[3] => dtm~29.DATAA cpu_d_readdata[4] => dtm~28.DATAA cpu_d_readdata[5] => dtm~27.DATAA cpu_d_readdata[6] => dtm~26.DATAA cpu_d_readdata[7] => dtm~25.DATAA cpu_d_readdata[8] => dtm~24.DATAA cpu_d_readdata[9] => dtm~23.DATAA cpu_d_readdata[10] => dtm~22.DATAA cpu_d_readdata[11] => dtm~21.DATAA cpu_d_readdata[12] => dtm~20.DATAA cpu_d_readdata[13] => dtm~19.DATAA cpu_d_readdata[14] => dtm~18.DATAA cpu_d_readdata[15] => dtm~17.DATAA cpu_d_readdata[16] => dtm~16.DATAA cpu_d_readdata[17] => dtm~15.DATAA cpu_d_readdata[18] => dtm~14.DATAA cpu_d_readdata[19] => dtm~13.DATAA cpu_d_readdata[20] => dtm~12.DATAA cpu_d_readdata[21] => dtm~11.DATAA cpu_d_readdata[22] => dtm~10.DATAA cpu_d_readdata[23] => dtm~9.DATAA cpu_d_readdata[24] => dtm~8.DATAA cpu_d_readdata[25] => dtm~7.DATAA cpu_d_readdata[26] => dtm~6.DATAA cpu_d_readdata[27] => dtm~5.DATAA cpu_d_readdata[28] => dtm~4.DATAA cpu_d_readdata[29] => dtm~3.DATAA cpu_d_readdata[30] => dtm~2.DATAA cpu_d_readdata[31] => dtm~1.DATAA cpu_d_wait => always0~0.IN0 cpu_d_wait => always0~2.IN0 cpu_d_write => always0~0.IN1 cpu_d_writedata[0] => dtm~32.DATAB cpu_d_writedata[1] => dtm~31.DATAB cpu_d_writedata[2] => dtm~30.DATAB cpu_d_writedata[3] => dtm~29.DATAB cpu_d_writedata[4] => dtm~28.DATAB cpu_d_writedata[5] => dtm~27.DATAB cpu_d_writedata[6] => dtm~26.DATAB cpu_d_writedata[7] => dtm~25.DATAB cpu_d_writedata[8] => dtm~24.DATAB cpu_d_writedata[9] => dtm~23.DATAB cpu_d_writedata[10] => dtm~22.DATAB cpu_d_writedata[11] => dtm~21.DATAB cpu_d_writedata[12] => dtm~20.DATAB cpu_d_writedata[13] => dtm~19.DATAB cpu_d_writedata[14] => dtm~18.DATAB cpu_d_writedata[15] => dtm~17.DATAB cpu_d_writedata[16] => dtm~16.DATAB cpu_d_writedata[17] => dtm~15.DATAB cpu_d_writedata[18] => dtm~14.DATAB cpu_d_writedata[19] => dtm~13.DATAB cpu_d_writedata[20] => dtm~12.DATAB cpu_d_writedata[21] => dtm~11.DATAB cpu_d_writedata[22] => dtm~10.DATAB cpu_d_writedata[23] => dtm~9.DATAB cpu_d_writedata[24] => dtm~8.DATAB cpu_d_writedata[25] => dtm~7.DATAB cpu_d_writedata[26] => dtm~6.DATAB cpu_d_writedata[27] => dtm~5.DATAB cpu_d_writedata[28] => dtm~4.DATAB cpu_d_writedata[29] => dtm~3.DATAB cpu_d_writedata[30] => dtm~2.DATAB cpu_d_writedata[31] => dtm~1.DATAB jrst_n => atm[35]~reg0.ACLR jrst_n => atm[34]~reg0.ACLR jrst_n => atm[33]~reg0.ACLR jrst_n => atm[32]~reg0.ACLR jrst_n => atm[31]~reg0.ACLR jrst_n => atm[30]~reg0.ACLR jrst_n => atm[29]~reg0.ACLR jrst_n => atm[28]~reg0.ACLR jrst_n => atm[27]~reg0.ACLR jrst_n => atm[26]~reg0.ACLR jrst_n => atm[25]~reg0.ACLR jrst_n => atm[24]~reg0.ACLR jrst_n => atm[23]~reg0.ACLR jrst_n => atm[22]~reg0.ACLR jrst_n => atm[21]~reg0.ACLR jrst_n => atm[20]~reg0.ACLR jrst_n => atm[19]~reg0.ACLR jrst_n => atm[18]~reg0.ACLR jrst_n => atm[17]~reg0.ACLR jrst_n => atm[16]~reg0.ACLR jrst_n => atm[15]~reg0.ACLR jrst_n => atm[14]~reg0.ACLR jrst_n => atm[13]~reg0.ACLR jrst_n => atm[12]~reg0.ACLR jrst_n => atm[11]~reg0.ACLR jrst_n => atm[10]~reg0.ACLR jrst_n => atm[9]~reg0.ACLR jrst_n => atm[8]~reg0.ACLR jrst_n => atm[7]~reg0.ACLR jrst_n => atm[6]~reg0.ACLR jrst_n => atm[5]~reg0.ACLR jrst_n => atm[4]~reg0.ACLR jrst_n => atm[3]~reg0.ACLR jrst_n => atm[2]~reg0.ACLR jrst_n => atm[1]~reg0.ACLR jrst_n => atm[0]~reg0.ACLR jrst_n => dtm[35]~reg0.ACLR jrst_n => dtm[34]~reg0.ACLR jrst_n => dtm[33]~reg0.ACLR jrst_n => dtm[32]~reg0.ACLR jrst_n => dtm[31]~reg0.ACLR jrst_n => dtm[30]~reg0.ACLR jrst_n => dtm[29]~reg0.ACLR jrst_n => dtm[28]~reg0.ACLR jrst_n => dtm[27]~reg0.ACLR jrst_n => dtm[26]~reg0.ACLR jrst_n => dtm[25]~reg0.ACLR jrst_n => dtm[24]~reg0.ACLR jrst_n => dtm[23]~reg0.ACLR jrst_n => dtm[22]~reg0.ACLR jrst_n => dtm[21]~reg0.ACLR jrst_n => dtm[20]~reg0.ACLR jrst_n => dtm[19]~reg0.ACLR jrst_n => dtm[18]~reg0.ACLR jrst_n => dtm[17]~reg0.ACLR jrst_n => dtm[16]~reg0.ACLR jrst_n => dtm[15]~reg0.ACLR jrst_n => dtm[14]~reg0.ACLR jrst_n => dtm[13]~reg0.ACLR jrst_n => dtm[12]~reg0.ACLR jrst_n => dtm[11]~reg0.ACLR jrst_n => dtm[10]~reg0.ACLR jrst_n => dtm[9]~reg0.ACLR jrst_n => dtm[8]~reg0.ACLR jrst_n => dtm[7]~reg0.ACLR jrst_n => dtm[6]~reg0.ACLR jrst_n => dtm[5]~reg0.ACLR jrst_n => dtm[4]~reg0.ACLR jrst_n => dtm[3]~reg0.ACLR jrst_n => dtm[2]~reg0.ACLR jrst_n => dtm[1]~reg0.ACLR jrst_n => dtm[0]~reg0.ACLR trc_ctrl[0] => trc_ctrl[0]~8.IN1 trc_ctrl[1] => trc_ctrl[1]~7.IN1 trc_ctrl[2] => trc_ctrl[2]~6.IN1 trc_ctrl[3] => trc_ctrl[3]~5.IN1 trc_ctrl[4] => trc_ctrl[4]~4.IN1 trc_ctrl[5] => trc_ctrl[5]~3.IN1 trc_ctrl[6] => trc_ctrl[6]~2.IN1 trc_ctrl[7] => trc_ctrl[7]~1.IN1 trc_ctrl[8] => trc_ctrl[8]~0.IN1 trc_ctrl[9] => ~NO_FANOUT~ trc_ctrl[10] => ~NO_FANOUT~ trc_ctrl[11] => ~NO_FANOUT~ trc_ctrl[12] => ~NO_FANOUT~ trc_ctrl[13] => ~NO_FANOUT~ trc_ctrl[14] => ~NO_FANOUT~ trc_ctrl[15] => ~NO_FANOUT~ atm[0] <= atm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[1] <= atm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[2] <= atm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[3] <= atm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[4] <= atm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[5] <= atm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[6] <= atm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[7] <= atm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[8] <= atm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[9] <= atm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[10] <= atm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[11] <= atm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[12] <= atm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[13] <= atm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[14] <= atm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[15] <= atm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[16] <= atm[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[17] <= atm[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[18] <= atm[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[19] <= atm[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[20] <= atm[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[21] <= atm[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[22] <= atm[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[23] <= atm[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[24] <= atm[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[25] <= atm[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[26] <= atm[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[27] <= atm[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[28] <= atm[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[29] <= atm[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[30] <= atm[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[31] <= atm[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[32] <= atm[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[33] <= atm[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[34] <= atm[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE atm[35] <= atm[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[0] <= dtm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[1] <= dtm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[2] <= dtm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[3] <= dtm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[4] <= dtm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[5] <= dtm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[6] <= dtm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[7] <= dtm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[8] <= dtm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[9] <= dtm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[10] <= dtm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[11] <= dtm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[12] <= dtm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[13] <= dtm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[14] <= dtm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[15] <= dtm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[16] <= dtm[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[17] <= dtm[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[18] <= dtm[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[19] <= dtm[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[20] <= dtm[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[21] <= dtm[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[22] <= dtm[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[23] <= dtm[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[24] <= dtm[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[25] <= dtm[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[26] <= dtm[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[27] <= dtm[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[28] <= dtm[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[29] <= dtm[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[30] <= dtm[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[31] <= dtm[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[32] <= dtm[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[33] <= dtm[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[34] <= dtm[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE dtm[35] <= dtm[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace|cpu_0_nios2_oci_td_mode:cpu_0_nios2_oci_trc_ctrl_td_mode ctrl[0] => ~NO_FANOUT~ ctrl[1] => ~NO_FANOUT~ ctrl[2] => ~NO_FANOUT~ ctrl[3] => ~NO_FANOUT~ ctrl[4] => ~NO_FANOUT~ ctrl[5] => Decoder0.IN2 ctrl[5] => td_mode[3].DATAIN ctrl[6] => Decoder1.IN1 ctrl[6] => Decoder0.IN1 ctrl[6] => td_mode[2].DATAIN ctrl[7] => Decoder1.IN0 ctrl[7] => Decoder0.IN0 ctrl[8] => ~NO_FANOUT~ td_mode[0] <= Decoder1.DB_MAX_OUTPUT_PORT_TYPE td_mode[1] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE td_mode[2] <= ctrl[6].DB_MAX_OUTPUT_PORT_TYPE td_mode[3] <= ctrl[5].DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo atm[0] => ~NO_FANOUT~ atm[1] => ~NO_FANOUT~ atm[2] => ~NO_FANOUT~ atm[3] => ~NO_FANOUT~ atm[4] => ~NO_FANOUT~ atm[5] => ~NO_FANOUT~ atm[6] => ~NO_FANOUT~ atm[7] => ~NO_FANOUT~ atm[8] => ~NO_FANOUT~ atm[9] => ~NO_FANOUT~ atm[10] => ~NO_FANOUT~ atm[11] => ~NO_FANOUT~ atm[12] => ~NO_FANOUT~ atm[13] => ~NO_FANOUT~ atm[14] => ~NO_FANOUT~ atm[15] => ~NO_FANOUT~ atm[16] => ~NO_FANOUT~ atm[17] => ~NO_FANOUT~ atm[18] => ~NO_FANOUT~ atm[19] => ~NO_FANOUT~ atm[20] => ~NO_FANOUT~ atm[21] => ~NO_FANOUT~ atm[22] => ~NO_FANOUT~ atm[23] => ~NO_FANOUT~ atm[24] => ~NO_FANOUT~ atm[25] => ~NO_FANOUT~ atm[26] => ~NO_FANOUT~ atm[27] => ~NO_FANOUT~ atm[28] => ~NO_FANOUT~ atm[29] => ~NO_FANOUT~ atm[30] => ~NO_FANOUT~ atm[31] => ~NO_FANOUT~ atm[32] => WideOr1.IN3 atm[33] => WideOr1.IN2 atm[34] => WideOr1.IN1 atm[35] => WideOr1.IN0 clk => fifocount[4].CLK clk => fifocount[3].CLK clk => fifocount[2].CLK clk => fifocount[1].CLK clk => fifocount[0].CLK dbrk_traceme => trc_this.IN1 dbrk_traceoff => trc_this~0.IN0 dbrk_traceon => trc_this~0.IN1 dtm[0] => ~NO_FANOUT~ dtm[1] => ~NO_FANOUT~ dtm[2] => ~NO_FANOUT~ dtm[3] => ~NO_FANOUT~ dtm[4] => ~NO_FANOUT~ dtm[5] => ~NO_FANOUT~ dtm[6] => ~NO_FANOUT~ dtm[7] => ~NO_FANOUT~ dtm[8] => ~NO_FANOUT~ dtm[9] => ~NO_FANOUT~ dtm[10] => ~NO_FANOUT~ dtm[11] => ~NO_FANOUT~ dtm[12] => ~NO_FANOUT~ dtm[13] => ~NO_FANOUT~ dtm[14] => ~NO_FANOUT~ dtm[15] => ~NO_FANOUT~ dtm[16] => ~NO_FANOUT~ dtm[17] => ~NO_FANOUT~ dtm[18] => ~NO_FANOUT~ dtm[19] => ~NO_FANOUT~ dtm[20] => ~NO_FANOUT~ dtm[21] => ~NO_FANOUT~ dtm[22] => ~NO_FANOUT~ dtm[23] => ~NO_FANOUT~ dtm[24] => ~NO_FANOUT~ dtm[25] => ~NO_FANOUT~ dtm[26] => ~NO_FANOUT~ dtm[27] => ~NO_FANOUT~ dtm[28] => ~NO_FANOUT~ dtm[29] => ~NO_FANOUT~ dtm[30] => ~NO_FANOUT~ dtm[31] => ~NO_FANOUT~ dtm[32] => WideOr2.IN3 dtm[33] => WideOr2.IN2 dtm[34] => WideOr2.IN1 dtm[35] => WideOr2.IN0 itm[0] => tw[0].DATAIN itm[1] => tw[1].DATAIN itm[2] => tw[2].DATAIN itm[3] => tw[3].DATAIN itm[4] => tw[4].DATAIN itm[5] => tw[5].DATAIN itm[6] => tw[6].DATAIN itm[7] => tw[7].DATAIN itm[8] => tw[8].DATAIN itm[9] => tw[9].DATAIN itm[10] => tw[10].DATAIN itm[11] => tw[11].DATAIN itm[12] => tw[12].DATAIN itm[13] => tw[13].DATAIN itm[14] => tw[14].DATAIN itm[15] => tw[15].DATAIN itm[16] => tw[16].DATAIN itm[17] => tw[17].DATAIN itm[18] => tw[18].DATAIN itm[19] => tw[19].DATAIN itm[20] => tw[20].DATAIN itm[21] => tw[21].DATAIN itm[22] => tw[22].DATAIN itm[23] => tw[23].DATAIN itm[24] => tw[24].DATAIN itm[25] => tw[25].DATAIN itm[26] => tw[26].DATAIN itm[27] => tw[27].DATAIN itm[28] => tw[28].DATAIN itm[29] => tw[29].DATAIN itm[30] => tw[30].DATAIN itm[31] => tw[31].DATAIN itm[32] => WideOr0.IN0 itm[32] => tw[32].DATAIN itm[33] => WideOr0.IN1 itm[33] => tw[33].DATAIN itm[34] => WideOr0.IN2 itm[34] => tw[34].DATAIN itm[35] => WideOr0.IN3 itm[35] => tw[35].DATAIN jrst_n => fifocount[4].ACLR jrst_n => fifocount[3].ACLR jrst_n => fifocount[2].ACLR jrst_n => fifocount[1].ACLR jrst_n => fifocount[0].ACLR reset_n => ~NO_FANOUT~ trc_on => trc_this~1.IN1 tw[0] <= itm[0].DB_MAX_OUTPUT_PORT_TYPE tw[1] <= itm[1].DB_MAX_OUTPUT_PORT_TYPE tw[2] <= itm[2].DB_MAX_OUTPUT_PORT_TYPE tw[3] <= itm[3].DB_MAX_OUTPUT_PORT_TYPE tw[4] <= itm[4].DB_MAX_OUTPUT_PORT_TYPE tw[5] <= itm[5].DB_MAX_OUTPUT_PORT_TYPE tw[6] <= itm[6].DB_MAX_OUTPUT_PORT_TYPE tw[7] <= itm[7].DB_MAX_OUTPUT_PORT_TYPE tw[8] <= itm[8].DB_MAX_OUTPUT_PORT_TYPE tw[9] <= itm[9].DB_MAX_OUTPUT_PORT_TYPE tw[10] <= itm[10].DB_MAX_OUTPUT_PORT_TYPE tw[11] <= itm[11].DB_MAX_OUTPUT_PORT_TYPE tw[12] <= itm[12].DB_MAX_OUTPUT_PORT_TYPE tw[13] <= itm[13].DB_MAX_OUTPUT_PORT_TYPE tw[14] <= itm[14].DB_MAX_OUTPUT_PORT_TYPE tw[15] <= itm[15].DB_MAX_OUTPUT_PORT_TYPE tw[16] <= itm[16].DB_MAX_OUTPUT_PORT_TYPE tw[17] <= itm[17].DB_MAX_OUTPUT_PORT_TYPE tw[18] <= itm[18].DB_MAX_OUTPUT_PORT_TYPE tw[19] <= itm[19].DB_MAX_OUTPUT_PORT_TYPE tw[20] <= itm[20].DB_MAX_OUTPUT_PORT_TYPE tw[21] <= itm[21].DB_MAX_OUTPUT_PORT_TYPE tw[22] <= itm[22].DB_MAX_OUTPUT_PORT_TYPE tw[23] <= itm[23].DB_MAX_OUTPUT_PORT_TYPE tw[24] <= itm[24].DB_MAX_OUTPUT_PORT_TYPE tw[25] <= itm[25].DB_MAX_OUTPUT_PORT_TYPE tw[26] <= itm[26].DB_MAX_OUTPUT_PORT_TYPE tw[27] <= itm[27].DB_MAX_OUTPUT_PORT_TYPE tw[28] <= itm[28].DB_MAX_OUTPUT_PORT_TYPE tw[29] <= itm[29].DB_MAX_OUTPUT_PORT_TYPE tw[30] <= itm[30].DB_MAX_OUTPUT_PORT_TYPE tw[31] <= itm[31].DB_MAX_OUTPUT_PORT_TYPE tw[32] <= itm[32].DB_MAX_OUTPUT_PORT_TYPE tw[33] <= itm[33].DB_MAX_OUTPUT_PORT_TYPE tw[34] <= itm[34].DB_MAX_OUTPUT_PORT_TYPE tw[35] <= itm[35].DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_compute_tm_count:cpu_0_nios2_oci_compute_tm_count_tm_count atm_valid => Decoder0.IN1 dtm_valid => Decoder0.IN2 itm_valid => Decoder0.IN0 compute_tm_count[0] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE compute_tm_count[1] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifowp_inc:cpu_0_nios2_oci_fifowp_inc_fifowp free2 => always0~1.IN1 free3 => always0~0.IN1 tm_count[0] => LessThan1.IN4 tm_count[0] => LessThan0.IN4 tm_count[0] => Equal0.IN0 tm_count[1] => LessThan1.IN3 tm_count[1] => LessThan0.IN3 tm_count[1] => Equal0.IN1 fifowp_inc[0] <= fifowp_inc~2.DB_MAX_OUTPUT_PORT_TYPE fifowp_inc[1] <= fifowp_inc~1.DB_MAX_OUTPUT_PORT_TYPE fifowp_inc[2] <= fifowp_inc[3] <= |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifocount_inc:cpu_0_nios2_oci_fifocount_inc_fifocount empty => fifocount_inc~9.OUTPUTSELECT empty => fifocount_inc~8.OUTPUTSELECT empty => fifocount_inc~7.OUTPUTSELECT empty => fifocount_inc~6.OUTPUTSELECT empty => fifocount_inc~5.OUTPUTSELECT free2 => always0~1.IN1 free3 => always0~0.IN1 tm_count[0] => fifocount_inc~9.DATAB tm_count[0] => LessThan1.IN4 tm_count[0] => LessThan0.IN4 tm_count[0] => Equal0.IN0 tm_count[1] => fifocount_inc~8.DATAB tm_count[1] => LessThan1.IN3 tm_count[1] => LessThan0.IN3 tm_count[1] => Equal0.IN1 fifocount_inc[0] <= fifocount_inc~9.DB_MAX_OUTPUT_PORT_TYPE fifocount_inc[1] <= fifocount_inc~8.DB_MAX_OUTPUT_PORT_TYPE fifocount_inc[2] <= fifocount_inc~7.DB_MAX_OUTPUT_PORT_TYPE fifocount_inc[3] <= fifocount_inc~6.DB_MAX_OUTPUT_PORT_TYPE fifocount_inc[4] <= fifocount_inc~5.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_pib:the_cpu_0_nios2_oci_pib clk => ~NO_FANOUT~ clkx2 => ~NO_FANOUT~ jrst_n => ~NO_FANOUT~ tw[0] => ~NO_FANOUT~ tw[1] => ~NO_FANOUT~ tw[2] => ~NO_FANOUT~ tw[3] => ~NO_FANOUT~ tw[4] => ~NO_FANOUT~ tw[5] => ~NO_FANOUT~ tw[6] => ~NO_FANOUT~ tw[7] => ~NO_FANOUT~ tw[8] => ~NO_FANOUT~ tw[9] => ~NO_FANOUT~ tw[10] => ~NO_FANOUT~ tw[11] => ~NO_FANOUT~ tw[12] => ~NO_FANOUT~ tw[13] => ~NO_FANOUT~ tw[14] => ~NO_FANOUT~ tw[15] => ~NO_FANOUT~ tw[16] => ~NO_FANOUT~ tw[17] => ~NO_FANOUT~ tw[18] => ~NO_FANOUT~ tw[19] => ~NO_FANOUT~ tw[20] => ~NO_FANOUT~ tw[21] => ~NO_FANOUT~ tw[22] => ~NO_FANOUT~ tw[23] => ~NO_FANOUT~ tw[24] => ~NO_FANOUT~ tw[25] => ~NO_FANOUT~ tw[26] => ~NO_FANOUT~ tw[27] => ~NO_FANOUT~ tw[28] => ~NO_FANOUT~ tw[29] => ~NO_FANOUT~ tw[30] => ~NO_FANOUT~ tw[31] => ~NO_FANOUT~ tw[32] => ~NO_FANOUT~ tw[33] => ~NO_FANOUT~ tw[34] => ~NO_FANOUT~ tw[35] => ~NO_FANOUT~ tr_clk <= tr_data[0] <= tr_data[1] <= tr_data[2] <= tr_data[3] <= tr_data[4] <= tr_data[5] <= tr_data[6] <= tr_data[7] <= tr_data[8] <= tr_data[9] <= tr_data[10] <= tr_data[11] <= tr_data[12] <= tr_data[13] <= tr_data[14] <= tr_data[15] <= tr_data[16] <= tr_data[17] <= |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im clk => clk~0.IN2 jdo[0] => ~NO_FANOUT~ jdo[1] => jdo[1]~35.IN1 jdo[2] => jdo[2]~34.IN1 jdo[3] => jdo[3]~33.IN1 jdo[4] => jdo[4]~32.IN1 jdo[5] => jdo[5]~31.IN1 jdo[6] => jdo[6]~30.IN1 jdo[7] => jdo[7]~29.IN1 jdo[8] => jdo[8]~28.IN1 jdo[9] => jdo[9]~27.IN1 jdo[10] => jdo[10]~26.IN1 jdo[11] => jdo[11]~25.IN1 jdo[12] => jdo[12]~24.IN1 jdo[13] => jdo[13]~23.IN1 jdo[14] => jdo[14]~22.IN1 jdo[15] => jdo[15]~21.IN1 jdo[16] => jdo[16]~20.IN1 jdo[17] => jdo[17]~19.IN1 jdo[18] => jdo[18]~18.IN1 jdo[19] => jdo[19]~17.IN1 jdo[20] => jdo[20]~16.IN1 jdo[21] => jdo[21]~15.IN1 jdo[22] => jdo[22]~14.IN1 jdo[23] => jdo[23]~13.IN1 jdo[24] => jdo[24]~12.IN1 jdo[25] => jdo[25]~11.IN1 jdo[26] => jdo[26]~10.IN1 jdo[27] => jdo[27]~9.IN1 jdo[28] => jdo[28]~8.IN1 jdo[29] => jdo[29]~7.IN1 jdo[30] => jdo[30]~6.IN1 jdo[31] => jdo[31]~5.IN1 jdo[32] => jdo[32]~4.IN1 jdo[33] => jdo[33]~3.IN1 jdo[34] => jdo[34]~2.IN1 jdo[35] => jdo[35]~1.IN1 jdo[36] => jdo[36]~0.IN1 jdo[37] => ~NO_FANOUT~ jrst_n => trc_im_addr[6]~reg0.ACLR jrst_n => trc_im_addr[5]~reg0.ACLR jrst_n => trc_im_addr[4]~reg0.ACLR jrst_n => trc_im_addr[3]~reg0.ACLR jrst_n => trc_im_addr[2]~reg0.ACLR jrst_n => trc_im_addr[1]~reg0.ACLR jrst_n => trc_im_addr[0]~reg0.ACLR jrst_n => trc_wrap~reg0.ACLR reset_n => trc_jtag_addr[16].ACLR reset_n => trc_jtag_addr[15].ACLR reset_n => trc_jtag_addr[14].ACLR reset_n => trc_jtag_addr[13].ACLR reset_n => trc_jtag_addr[12].ACLR reset_n => trc_jtag_addr[11].ACLR reset_n => trc_jtag_addr[10].ACLR reset_n => trc_jtag_addr[9].ACLR reset_n => trc_jtag_addr[8].ACLR reset_n => trc_jtag_addr[7].ACLR reset_n => trc_jtag_addr[6].ACLR reset_n => trc_jtag_addr[5].ACLR reset_n => trc_jtag_addr[4].ACLR reset_n => trc_jtag_addr[3].ACLR reset_n => trc_jtag_addr[2].ACLR reset_n => trc_jtag_addr[1].ACLR reset_n => trc_jtag_addr[0].ACLR take_action_tracectrl => ~NO_FANOUT~ take_action_tracemem_a => trc_jtag_addr~33.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~32.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~31.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~30.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~29.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~28.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~27.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~26.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~25.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~24.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~23.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~22.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~21.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~20.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~19.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~18.OUTPUTSELECT take_action_tracemem_a => trc_jtag_addr~17.OUTPUTSELECT take_action_tracemem_a => always1~0.IN0 take_action_tracemem_b => take_action_tracemem_b~0.IN1 take_no_action_tracemem_a => always1~0.IN1 trc_ctrl[0] => comb~0.IN0 trc_ctrl[0] => trc_enb.DATAIN trc_ctrl[0] => tracemem_on.DATAIN trc_ctrl[1] => ~NO_FANOUT~ trc_ctrl[2] => ~NO_FANOUT~ trc_ctrl[3] => ~NO_FANOUT~ trc_ctrl[4] => ~NO_FANOUT~ trc_ctrl[5] => ~NO_FANOUT~ trc_ctrl[6] => ~NO_FANOUT~ trc_ctrl[7] => ~NO_FANOUT~ trc_ctrl[8] => ~NO_FANOUT~ trc_ctrl[9] => ~NO_FANOUT~ trc_ctrl[10] => xbrk_wrap_traceoff~0.IN1 trc_ctrl[11] => ~NO_FANOUT~ trc_ctrl[12] => ~NO_FANOUT~ trc_ctrl[13] => ~NO_FANOUT~ trc_ctrl[14] => ~NO_FANOUT~ trc_ctrl[15] => ~NO_FANOUT~ tw[0] => trc_im_data[0].IN1 tw[1] => trc_im_data[1].IN1 tw[2] => trc_im_data[2].IN1 tw[3] => trc_im_data[3].IN1 tw[4] => trc_im_data[4].IN1 tw[5] => trc_im_data[5].IN1 tw[6] => trc_im_data[6].IN1 tw[7] => trc_im_data[7].IN1 tw[8] => trc_im_data[8].IN1 tw[9] => trc_im_data[9].IN1 tw[10] => trc_im_data[10].IN1 tw[11] => trc_im_data[11].IN1 tw[12] => trc_im_data[12].IN1 tw[13] => trc_im_data[13].IN1 tw[14] => trc_im_data[14].IN1 tw[15] => trc_im_data[15].IN1 tw[16] => trc_im_data[16].IN1 tw[17] => trc_im_data[17].IN1 tw[18] => trc_im_data[18].IN1 tw[19] => trc_im_data[19].IN1 tw[20] => trc_im_data[20].IN1 tw[21] => trc_im_data[21].IN1 tw[22] => trc_im_data[22].IN1 tw[23] => trc_im_data[23].IN1 tw[24] => trc_im_data[24].IN1 tw[25] => trc_im_data[25].IN1 tw[26] => trc_im_data[26].IN1 tw[27] => trc_im_data[27].IN1 tw[28] => trc_im_data[28].IN1 tw[29] => trc_im_data[29].IN1 tw[30] => trc_im_data[30].IN1 tw[31] => trc_im_data[31].IN1 tw[32] => trc_im_data[32].IN1 tw[33] => trc_im_data[33].IN1 tw[34] => trc_im_data[34].IN1 tw[35] => trc_im_data[35].IN1 tracemem_on <= trc_ctrl[0].DB_MAX_OUTPUT_PORT_TYPE tracemem_trcdata[0] <= tracemem_trcdata[1] <= tracemem_trcdata[2] <= tracemem_trcdata[3] <= tracemem_trcdata[4] <= tracemem_trcdata[5] <= tracemem_trcdata[6] <= tracemem_trcdata[7] <= tracemem_trcdata[8] <= tracemem_trcdata[9] <= tracemem_trcdata[10] <= tracemem_trcdata[11] <= tracemem_trcdata[12] <= tracemem_trcdata[13] <= tracemem_trcdata[14] <= tracemem_trcdata[15] <= tracemem_trcdata[16] <= tracemem_trcdata[17] <= tracemem_trcdata[18] <= tracemem_trcdata[19] <= tracemem_trcdata[20] <= tracemem_trcdata[21] <= tracemem_trcdata[22] <= tracemem_trcdata[23] <= tracemem_trcdata[24] <= tracemem_trcdata[25] <= tracemem_trcdata[26] <= tracemem_trcdata[27] <= tracemem_trcdata[28] <= tracemem_trcdata[29] <= tracemem_trcdata[30] <= tracemem_trcdata[31] <= tracemem_trcdata[32] <= tracemem_trcdata[33] <= tracemem_trcdata[34] <= tracemem_trcdata[35] <= tracemem_tw <= trc_wrap~reg0.DB_MAX_OUTPUT_PORT_TYPE trc_enb <= trc_ctrl[0].DB_MAX_OUTPUT_PORT_TYPE trc_im_addr[0] <= trc_im_addr[0]~6.DB_MAX_OUTPUT_PORT_TYPE trc_im_addr[1] <= trc_im_addr[1]~5.DB_MAX_OUTPUT_PORT_TYPE trc_im_addr[2] <= trc_im_addr[2]~4.DB_MAX_OUTPUT_PORT_TYPE trc_im_addr[3] <= trc_im_addr[3]~3.DB_MAX_OUTPUT_PORT_TYPE trc_im_addr[4] <= trc_im_addr[4]~2.DB_MAX_OUTPUT_PORT_TYPE trc_im_addr[5] <= trc_im_addr[5]~1.DB_MAX_OUTPUT_PORT_TYPE trc_im_addr[6] <= trc_im_addr[6]~0.DB_MAX_OUTPUT_PORT_TYPE trc_wrap <= trc_wrap~reg0.DB_MAX_OUTPUT_PORT_TYPE xbrk_wrap_traceoff <= xbrk_wrap_traceoff~0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component address_a[0] => address_a[0]~6.IN1 address_a[1] => address_a[1]~5.IN1 address_a[2] => address_a[2]~4.IN1 address_a[3] => address_a[3]~3.IN1 address_a[4] => address_a[4]~2.IN1 address_a[5] => address_a[5]~1.IN1 address_a[6] => address_a[6]~0.IN1 address_b[0] => address_b[0]~6.IN1 address_b[1] => address_b[1]~5.IN1 address_b[2] => address_b[2]~4.IN1 address_b[3] => address_b[3]~3.IN1 address_b[4] => address_b[4]~2.IN1 address_b[5] => address_b[5]~1.IN1 address_b[6] => address_b[6]~0.IN1 clock0 => clock0~0.IN1 clock1 => clock1~0.IN1 clocken0 => clocken0~0.IN1 clocken1 => clocken1~0.IN1 data_a[0] => data_a[0]~35.IN1 data_a[1] => data_a[1]~34.IN1 data_a[2] => data_a[2]~33.IN1 data_a[3] => data_a[3]~32.IN1 data_a[4] => data_a[4]~31.IN1 data_a[5] => data_a[5]~30.IN1 data_a[6] => data_a[6]~29.IN1 data_a[7] => data_a[7]~28.IN1 data_a[8] => data_a[8]~27.IN1 data_a[9] => data_a[9]~26.IN1 data_a[10] => data_a[10]~25.IN1 data_a[11] => data_a[11]~24.IN1 data_a[12] => data_a[12]~23.IN1 data_a[13] => data_a[13]~22.IN1 data_a[14] => data_a[14]~21.IN1 data_a[15] => data_a[15]~20.IN1 data_a[16] => data_a[16]~19.IN1 data_a[17] => data_a[17]~18.IN1 data_a[18] => data_a[18]~17.IN1 data_a[19] => data_a[19]~16.IN1 data_a[20] => data_a[20]~15.IN1 data_a[21] => data_a[21]~14.IN1 data_a[22] => data_a[22]~13.IN1 data_a[23] => data_a[23]~12.IN1 data_a[24] => data_a[24]~11.IN1 data_a[25] => data_a[25]~10.IN1 data_a[26] => data_a[26]~9.IN1 data_a[27] => data_a[27]~8.IN1 data_a[28] => data_a[28]~7.IN1 data_a[29] => data_a[29]~6.IN1 data_a[30] => data_a[30]~5.IN1 data_a[31] => data_a[31]~4.IN1 data_a[32] => data_a[32]~3.IN1 data_a[33] => data_a[33]~2.IN1 data_a[34] => data_a[34]~1.IN1 data_a[35] => data_a[35]~0.IN1 data_b[0] => data_b[0]~35.IN1 data_b[1] => data_b[1]~34.IN1 data_b[2] => data_b[2]~33.IN1 data_b[3] => data_b[3]~32.IN1 data_b[4] => data_b[4]~31.IN1 data_b[5] => data_b[5]~30.IN1 data_b[6] => data_b[6]~29.IN1 data_b[7] => data_b[7]~28.IN1 data_b[8] => data_b[8]~27.IN1 data_b[9] => data_b[9]~26.IN1 data_b[10] => data_b[10]~25.IN1 data_b[11] => data_b[11]~24.IN1 data_b[12] => data_b[12]~23.IN1 data_b[13] => data_b[13]~22.IN1 data_b[14] => data_b[14]~21.IN1 data_b[15] => data_b[15]~20.IN1 data_b[16] => data_b[16]~19.IN1 data_b[17] => data_b[17]~18.IN1 data_b[18] => data_b[18]~17.IN1 data_b[19] => data_b[19]~16.IN1 data_b[20] => data_b[20]~15.IN1 data_b[21] => data_b[21]~14.IN1 data_b[22] => data_b[22]~13.IN1 data_b[23] => data_b[23]~12.IN1 data_b[24] => data_b[24]~11.IN1 data_b[25] => data_b[25]~10.IN1 data_b[26] => data_b[26]~9.IN1 data_b[27] => data_b[27]~8.IN1 data_b[28] => data_b[28]~7.IN1 data_b[29] => data_b[29]~6.IN1 data_b[30] => data_b[30]~5.IN1 data_b[31] => data_b[31]~4.IN1 data_b[32] => data_b[32]~3.IN1 data_b[33] => data_b[33]~2.IN1 data_b[34] => data_b[34]~1.IN1 data_b[35] => data_b[35]~0.IN1 wren_a => wren_a~0.IN1 wren_b => wren_b~0.IN1 q_a[0] <= altsyncram:the_altsyncram.q_a q_a[1] <= altsyncram:the_altsyncram.q_a q_a[2] <= altsyncram:the_altsyncram.q_a q_a[3] <= altsyncram:the_altsyncram.q_a q_a[4] <= altsyncram:the_altsyncram.q_a q_a[5] <= altsyncram:the_altsyncram.q_a q_a[6] <= altsyncram:the_altsyncram.q_a q_a[7] <= altsyncram:the_altsyncram.q_a q_a[8] <= altsyncram:the_altsyncram.q_a q_a[9] <= altsyncram:the_altsyncram.q_a q_a[10] <= altsyncram:the_altsyncram.q_a q_a[11] <= altsyncram:the_altsyncram.q_a q_a[12] <= altsyncram:the_altsyncram.q_a q_a[13] <= altsyncram:the_altsyncram.q_a q_a[14] <= altsyncram:the_altsyncram.q_a q_a[15] <= altsyncram:the_altsyncram.q_a q_a[16] <= altsyncram:the_altsyncram.q_a q_a[17] <= altsyncram:the_altsyncram.q_a q_a[18] <= altsyncram:the_altsyncram.q_a q_a[19] <= altsyncram:the_altsyncram.q_a q_a[20] <= altsyncram:the_altsyncram.q_a q_a[21] <= altsyncram:the_altsyncram.q_a q_a[22] <= altsyncram:the_altsyncram.q_a q_a[23] <= altsyncram:the_altsyncram.q_a q_a[24] <= altsyncram:the_altsyncram.q_a q_a[25] <= altsyncram:the_altsyncram.q_a q_a[26] <= altsyncram:the_altsyncram.q_a q_a[27] <= altsyncram:the_altsyncram.q_a q_a[28] <= altsyncram:the_altsyncram.q_a q_a[29] <= altsyncram:the_altsyncram.q_a q_a[30] <= altsyncram:the_altsyncram.q_a q_a[31] <= altsyncram:the_altsyncram.q_a q_a[32] <= altsyncram:the_altsyncram.q_a q_a[33] <= altsyncram:the_altsyncram.q_a q_a[34] <= altsyncram:the_altsyncram.q_a q_a[35] <= altsyncram:the_altsyncram.q_a q_b[0] <= altsyncram:the_altsyncram.q_b q_b[1] <= altsyncram:the_altsyncram.q_b q_b[2] <= altsyncram:the_altsyncram.q_b q_b[3] <= altsyncram:the_altsyncram.q_b q_b[4] <= altsyncram:the_altsyncram.q_b q_b[5] <= altsyncram:the_altsyncram.q_b q_b[6] <= altsyncram:the_altsyncram.q_b q_b[7] <= altsyncram:the_altsyncram.q_b q_b[8] <= altsyncram:the_altsyncram.q_b q_b[9] <= altsyncram:the_altsyncram.q_b q_b[10] <= altsyncram:the_altsyncram.q_b q_b[11] <= altsyncram:the_altsyncram.q_b q_b[12] <= altsyncram:the_altsyncram.q_b q_b[13] <= altsyncram:the_altsyncram.q_b q_b[14] <= altsyncram:the_altsyncram.q_b q_b[15] <= altsyncram:the_altsyncram.q_b q_b[16] <= altsyncram:the_altsyncram.q_b q_b[17] <= altsyncram:the_altsyncram.q_b q_b[18] <= altsyncram:the_altsyncram.q_b q_b[19] <= altsyncram:the_altsyncram.q_b q_b[20] <= altsyncram:the_altsyncram.q_b q_b[21] <= altsyncram:the_altsyncram.q_b q_b[22] <= altsyncram:the_altsyncram.q_b q_b[23] <= altsyncram:the_altsyncram.q_b q_b[24] <= altsyncram:the_altsyncram.q_b q_b[25] <= altsyncram:the_altsyncram.q_b q_b[26] <= altsyncram:the_altsyncram.q_b q_b[27] <= altsyncram:the_altsyncram.q_b q_b[28] <= altsyncram:the_altsyncram.q_b q_b[29] <= altsyncram:the_altsyncram.q_b q_b[30] <= altsyncram:the_altsyncram.q_b q_b[31] <= altsyncram:the_altsyncram.q_b q_b[32] <= altsyncram:the_altsyncram.q_b q_b[33] <= altsyncram:the_altsyncram.q_b q_b[34] <= altsyncram:the_altsyncram.q_b q_b[35] <= altsyncram:the_altsyncram.q_b |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram wren_a => altsyncram_e502:auto_generated.wren_a rden_a => ~NO_FANOUT~ wren_b => altsyncram_e502:auto_generated.wren_b rden_b => ~NO_FANOUT~ data_a[0] => altsyncram_e502:auto_generated.data_a[0] data_a[1] => altsyncram_e502:auto_generated.data_a[1] data_a[2] => altsyncram_e502:auto_generated.data_a[2] data_a[3] => altsyncram_e502:auto_generated.data_a[3] data_a[4] => altsyncram_e502:auto_generated.data_a[4] data_a[5] => altsyncram_e502:auto_generated.data_a[5] data_a[6] => altsyncram_e502:auto_generated.data_a[6] data_a[7] => altsyncram_e502:auto_generated.data_a[7] data_a[8] => altsyncram_e502:auto_generated.data_a[8] data_a[9] => altsyncram_e502:auto_generated.data_a[9] data_a[10] => altsyncram_e502:auto_generated.data_a[10] data_a[11] => altsyncram_e502:auto_generated.data_a[11] data_a[12] => altsyncram_e502:auto_generated.data_a[12] data_a[13] => altsyncram_e502:auto_generated.data_a[13] data_a[14] => altsyncram_e502:auto_generated.data_a[14] data_a[15] => altsyncram_e502:auto_generated.data_a[15] data_a[16] => altsyncram_e502:auto_generated.data_a[16] data_a[17] => altsyncram_e502:auto_generated.data_a[17] data_a[18] => altsyncram_e502:auto_generated.data_a[18] data_a[19] => altsyncram_e502:auto_generated.data_a[19] data_a[20] => altsyncram_e502:auto_generated.data_a[20] data_a[21] => altsyncram_e502:auto_generated.data_a[21] data_a[22] => altsyncram_e502:auto_generated.data_a[22] data_a[23] => altsyncram_e502:auto_generated.data_a[23] data_a[24] => altsyncram_e502:auto_generated.data_a[24] data_a[25] => altsyncram_e502:auto_generated.data_a[25] data_a[26] => altsyncram_e502:auto_generated.data_a[26] data_a[27] => altsyncram_e502:auto_generated.data_a[27] data_a[28] => altsyncram_e502:auto_generated.data_a[28] data_a[29] => altsyncram_e502:auto_generated.data_a[29] data_a[30] => altsyncram_e502:auto_generated.data_a[30] data_a[31] => altsyncram_e502:auto_generated.data_a[31] data_a[32] => altsyncram_e502:auto_generated.data_a[32] data_a[33] => altsyncram_e502:auto_generated.data_a[33] data_a[34] => altsyncram_e502:auto_generated.data_a[34] data_a[35] => altsyncram_e502:auto_generated.data_a[35] data_b[0] => altsyncram_e502:auto_generated.data_b[0] data_b[1] => altsyncram_e502:auto_generated.data_b[1] data_b[2] => altsyncram_e502:auto_generated.data_b[2] data_b[3] => altsyncram_e502:auto_generated.data_b[3] data_b[4] => altsyncram_e502:auto_generated.data_b[4] data_b[5] => altsyncram_e502:auto_generated.data_b[5] data_b[6] => altsyncram_e502:auto_generated.data_b[6] data_b[7] => altsyncram_e502:auto_generated.data_b[7] data_b[8] => altsyncram_e502:auto_generated.data_b[8] data_b[9] => altsyncram_e502:auto_generated.data_b[9] data_b[10] => altsyncram_e502:auto_generated.data_b[10] data_b[11] => altsyncram_e502:auto_generated.data_b[11] data_b[12] => altsyncram_e502:auto_generated.data_b[12] data_b[13] => altsyncram_e502:auto_generated.data_b[13] data_b[14] => altsyncram_e502:auto_generated.data_b[14] data_b[15] => altsyncram_e502:auto_generated.data_b[15] data_b[16] => altsyncram_e502:auto_generated.data_b[16] data_b[17] => altsyncram_e502:auto_generated.data_b[17] data_b[18] => altsyncram_e502:auto_generated.data_b[18] data_b[19] => altsyncram_e502:auto_generated.data_b[19] data_b[20] => altsyncram_e502:auto_generated.data_b[20] data_b[21] => altsyncram_e502:auto_generated.data_b[21] data_b[22] => altsyncram_e502:auto_generated.data_b[22] data_b[23] => altsyncram_e502:auto_generated.data_b[23] data_b[24] => altsyncram_e502:auto_generated.data_b[24] data_b[25] => altsyncram_e502:auto_generated.data_b[25] data_b[26] => altsyncram_e502:auto_generated.data_b[26] data_b[27] => altsyncram_e502:auto_generated.data_b[27] data_b[28] => altsyncram_e502:auto_generated.data_b[28] data_b[29] => altsyncram_e502:auto_generated.data_b[29] data_b[30] => altsyncram_e502:auto_generated.data_b[30] data_b[31] => altsyncram_e502:auto_generated.data_b[31] data_b[32] => altsyncram_e502:auto_generated.data_b[32] data_b[33] => altsyncram_e502:auto_generated.data_b[33] data_b[34] => altsyncram_e502:auto_generated.data_b[34] data_b[35] => altsyncram_e502:auto_generated.data_b[35] address_a[0] => altsyncram_e502:auto_generated.address_a[0] address_a[1] => altsyncram_e502:auto_generated.address_a[1] address_a[2] => altsyncram_e502:auto_generated.address_a[2] address_a[3] => altsyncram_e502:auto_generated.address_a[3] address_a[4] => altsyncram_e502:auto_generated.address_a[4] address_a[5] => altsyncram_e502:auto_generated.address_a[5] address_a[6] => altsyncram_e502:auto_generated.address_a[6] address_b[0] => altsyncram_e502:auto_generated.address_b[0] address_b[1] => altsyncram_e502:auto_generated.address_b[1] address_b[2] => altsyncram_e502:auto_generated.address_b[2] address_b[3] => altsyncram_e502:auto_generated.address_b[3] address_b[4] => altsyncram_e502:auto_generated.address_b[4] address_b[5] => altsyncram_e502:auto_generated.address_b[5] address_b[6] => altsyncram_e502:auto_generated.address_b[6] addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_e502:auto_generated.clock0 clock1 => altsyncram_e502:auto_generated.clock1 clocken0 => altsyncram_e502:auto_generated.clocken0 clocken1 => altsyncram_e502:auto_generated.clocken1 clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= altsyncram_e502:auto_generated.q_a[0] q_a[1] <= altsyncram_e502:auto_generated.q_a[1] q_a[2] <= altsyncram_e502:auto_generated.q_a[2] q_a[3] <= altsyncram_e502:auto_generated.q_a[3] q_a[4] <= altsyncram_e502:auto_generated.q_a[4] q_a[5] <= altsyncram_e502:auto_generated.q_a[5] q_a[6] <= altsyncram_e502:auto_generated.q_a[6] q_a[7] <= altsyncram_e502:auto_generated.q_a[7] q_a[8] <= altsyncram_e502:auto_generated.q_a[8] q_a[9] <= altsyncram_e502:auto_generated.q_a[9] q_a[10] <= altsyncram_e502:auto_generated.q_a[10] q_a[11] <= altsyncram_e502:auto_generated.q_a[11] q_a[12] <= altsyncram_e502:auto_generated.q_a[12] q_a[13] <= altsyncram_e502:auto_generated.q_a[13] q_a[14] <= altsyncram_e502:auto_generated.q_a[14] q_a[15] <= altsyncram_e502:auto_generated.q_a[15] q_a[16] <= altsyncram_e502:auto_generated.q_a[16] q_a[17] <= altsyncram_e502:auto_generated.q_a[17] q_a[18] <= altsyncram_e502:auto_generated.q_a[18] q_a[19] <= altsyncram_e502:auto_generated.q_a[19] q_a[20] <= altsyncram_e502:auto_generated.q_a[20] q_a[21] <= altsyncram_e502:auto_generated.q_a[21] q_a[22] <= altsyncram_e502:auto_generated.q_a[22] q_a[23] <= altsyncram_e502:auto_generated.q_a[23] q_a[24] <= altsyncram_e502:auto_generated.q_a[24] q_a[25] <= altsyncram_e502:auto_generated.q_a[25] q_a[26] <= altsyncram_e502:auto_generated.q_a[26] q_a[27] <= altsyncram_e502:auto_generated.q_a[27] q_a[28] <= altsyncram_e502:auto_generated.q_a[28] q_a[29] <= altsyncram_e502:auto_generated.q_a[29] q_a[30] <= altsyncram_e502:auto_generated.q_a[30] q_a[31] <= altsyncram_e502:auto_generated.q_a[31] q_a[32] <= altsyncram_e502:auto_generated.q_a[32] q_a[33] <= altsyncram_e502:auto_generated.q_a[33] q_a[34] <= altsyncram_e502:auto_generated.q_a[34] q_a[35] <= altsyncram_e502:auto_generated.q_a[35] q_b[0] <= altsyncram_e502:auto_generated.q_b[0] q_b[1] <= altsyncram_e502:auto_generated.q_b[1] q_b[2] <= altsyncram_e502:auto_generated.q_b[2] q_b[3] <= altsyncram_e502:auto_generated.q_b[3] q_b[4] <= altsyncram_e502:auto_generated.q_b[4] q_b[5] <= altsyncram_e502:auto_generated.q_b[5] q_b[6] <= altsyncram_e502:auto_generated.q_b[6] q_b[7] <= altsyncram_e502:auto_generated.q_b[7] q_b[8] <= altsyncram_e502:auto_generated.q_b[8] q_b[9] <= altsyncram_e502:auto_generated.q_b[9] q_b[10] <= altsyncram_e502:auto_generated.q_b[10] q_b[11] <= altsyncram_e502:auto_generated.q_b[11] q_b[12] <= altsyncram_e502:auto_generated.q_b[12] q_b[13] <= altsyncram_e502:auto_generated.q_b[13] q_b[14] <= altsyncram_e502:auto_generated.q_b[14] q_b[15] <= altsyncram_e502:auto_generated.q_b[15] q_b[16] <= altsyncram_e502:auto_generated.q_b[16] q_b[17] <= altsyncram_e502:auto_generated.q_b[17] q_b[18] <= altsyncram_e502:auto_generated.q_b[18] q_b[19] <= altsyncram_e502:auto_generated.q_b[19] q_b[20] <= altsyncram_e502:auto_generated.q_b[20] q_b[21] <= altsyncram_e502:auto_generated.q_b[21] q_b[22] <= altsyncram_e502:auto_generated.q_b[22] q_b[23] <= altsyncram_e502:auto_generated.q_b[23] q_b[24] <= altsyncram_e502:auto_generated.q_b[24] q_b[25] <= altsyncram_e502:auto_generated.q_b[25] q_b[26] <= altsyncram_e502:auto_generated.q_b[26] q_b[27] <= altsyncram_e502:auto_generated.q_b[27] q_b[28] <= altsyncram_e502:auto_generated.q_b[28] q_b[29] <= altsyncram_e502:auto_generated.q_b[29] q_b[30] <= altsyncram_e502:auto_generated.q_b[30] q_b[31] <= altsyncram_e502:auto_generated.q_b[31] q_b[32] <= altsyncram_e502:auto_generated.q_b[32] q_b[33] <= altsyncram_e502:auto_generated.q_b[33] q_b[34] <= altsyncram_e502:auto_generated.q_b[34] q_b[35] <= altsyncram_e502:auto_generated.q_b[35] eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[0] => ram_block1a8.PORTAADDR address_a[0] => ram_block1a9.PORTAADDR address_a[0] => ram_block1a10.PORTAADDR address_a[0] => ram_block1a11.PORTAADDR address_a[0] => ram_block1a12.PORTAADDR address_a[0] => ram_block1a13.PORTAADDR address_a[0] => ram_block1a14.PORTAADDR address_a[0] => ram_block1a15.PORTAADDR address_a[0] => ram_block1a16.PORTAADDR address_a[0] => ram_block1a17.PORTAADDR address_a[0] => ram_block1a18.PORTAADDR address_a[0] => ram_block1a19.PORTAADDR address_a[0] => ram_block1a20.PORTAADDR address_a[0] => ram_block1a21.PORTAADDR address_a[0] => ram_block1a22.PORTAADDR address_a[0] => ram_block1a23.PORTAADDR address_a[0] => ram_block1a24.PORTAADDR address_a[0] => ram_block1a25.PORTAADDR address_a[0] => ram_block1a26.PORTAADDR address_a[0] => ram_block1a27.PORTAADDR address_a[0] => ram_block1a28.PORTAADDR address_a[0] => ram_block1a29.PORTAADDR address_a[0] => ram_block1a30.PORTAADDR address_a[0] => ram_block1a31.PORTAADDR address_a[0] => ram_block1a32.PORTAADDR address_a[0] => ram_block1a33.PORTAADDR address_a[0] => ram_block1a34.PORTAADDR address_a[0] => ram_block1a35.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[1] => ram_block1a8.PORTAADDR1 address_a[1] => ram_block1a9.PORTAADDR1 address_a[1] => ram_block1a10.PORTAADDR1 address_a[1] => ram_block1a11.PORTAADDR1 address_a[1] => ram_block1a12.PORTAADDR1 address_a[1] => ram_block1a13.PORTAADDR1 address_a[1] => ram_block1a14.PORTAADDR1 address_a[1] => ram_block1a15.PORTAADDR1 address_a[1] => ram_block1a16.PORTAADDR1 address_a[1] => ram_block1a17.PORTAADDR1 address_a[1] => ram_block1a18.PORTAADDR1 address_a[1] => ram_block1a19.PORTAADDR1 address_a[1] => ram_block1a20.PORTAADDR1 address_a[1] => ram_block1a21.PORTAADDR1 address_a[1] => ram_block1a22.PORTAADDR1 address_a[1] => ram_block1a23.PORTAADDR1 address_a[1] => ram_block1a24.PORTAADDR1 address_a[1] => ram_block1a25.PORTAADDR1 address_a[1] => ram_block1a26.PORTAADDR1 address_a[1] => ram_block1a27.PORTAADDR1 address_a[1] => ram_block1a28.PORTAADDR1 address_a[1] => ram_block1a29.PORTAADDR1 address_a[1] => ram_block1a30.PORTAADDR1 address_a[1] => ram_block1a31.PORTAADDR1 address_a[1] => ram_block1a32.PORTAADDR1 address_a[1] => ram_block1a33.PORTAADDR1 address_a[1] => ram_block1a34.PORTAADDR1 address_a[1] => ram_block1a35.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[2] => ram_block1a8.PORTAADDR2 address_a[2] => ram_block1a9.PORTAADDR2 address_a[2] => ram_block1a10.PORTAADDR2 address_a[2] => ram_block1a11.PORTAADDR2 address_a[2] => ram_block1a12.PORTAADDR2 address_a[2] => ram_block1a13.PORTAADDR2 address_a[2] => ram_block1a14.PORTAADDR2 address_a[2] => ram_block1a15.PORTAADDR2 address_a[2] => ram_block1a16.PORTAADDR2 address_a[2] => ram_block1a17.PORTAADDR2 address_a[2] => ram_block1a18.PORTAADDR2 address_a[2] => ram_block1a19.PORTAADDR2 address_a[2] => ram_block1a20.PORTAADDR2 address_a[2] => ram_block1a21.PORTAADDR2 address_a[2] => ram_block1a22.PORTAADDR2 address_a[2] => ram_block1a23.PORTAADDR2 address_a[2] => ram_block1a24.PORTAADDR2 address_a[2] => ram_block1a25.PORTAADDR2 address_a[2] => ram_block1a26.PORTAADDR2 address_a[2] => ram_block1a27.PORTAADDR2 address_a[2] => ram_block1a28.PORTAADDR2 address_a[2] => ram_block1a29.PORTAADDR2 address_a[2] => ram_block1a30.PORTAADDR2 address_a[2] => ram_block1a31.PORTAADDR2 address_a[2] => ram_block1a32.PORTAADDR2 address_a[2] => ram_block1a33.PORTAADDR2 address_a[2] => ram_block1a34.PORTAADDR2 address_a[2] => ram_block1a35.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[3] => ram_block1a8.PORTAADDR3 address_a[3] => ram_block1a9.PORTAADDR3 address_a[3] => ram_block1a10.PORTAADDR3 address_a[3] => ram_block1a11.PORTAADDR3 address_a[3] => ram_block1a12.PORTAADDR3 address_a[3] => ram_block1a13.PORTAADDR3 address_a[3] => ram_block1a14.PORTAADDR3 address_a[3] => ram_block1a15.PORTAADDR3 address_a[3] => ram_block1a16.PORTAADDR3 address_a[3] => ram_block1a17.PORTAADDR3 address_a[3] => ram_block1a18.PORTAADDR3 address_a[3] => ram_block1a19.PORTAADDR3 address_a[3] => ram_block1a20.PORTAADDR3 address_a[3] => ram_block1a21.PORTAADDR3 address_a[3] => ram_block1a22.PORTAADDR3 address_a[3] => ram_block1a23.PORTAADDR3 address_a[3] => ram_block1a24.PORTAADDR3 address_a[3] => ram_block1a25.PORTAADDR3 address_a[3] => ram_block1a26.PORTAADDR3 address_a[3] => ram_block1a27.PORTAADDR3 address_a[3] => ram_block1a28.PORTAADDR3 address_a[3] => ram_block1a29.PORTAADDR3 address_a[3] => ram_block1a30.PORTAADDR3 address_a[3] => ram_block1a31.PORTAADDR3 address_a[3] => ram_block1a32.PORTAADDR3 address_a[3] => ram_block1a33.PORTAADDR3 address_a[3] => ram_block1a34.PORTAADDR3 address_a[3] => ram_block1a35.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[4] => ram_block1a8.PORTAADDR4 address_a[4] => ram_block1a9.PORTAADDR4 address_a[4] => ram_block1a10.PORTAADDR4 address_a[4] => ram_block1a11.PORTAADDR4 address_a[4] => ram_block1a12.PORTAADDR4 address_a[4] => ram_block1a13.PORTAADDR4 address_a[4] => ram_block1a14.PORTAADDR4 address_a[4] => ram_block1a15.PORTAADDR4 address_a[4] => ram_block1a16.PORTAADDR4 address_a[4] => ram_block1a17.PORTAADDR4 address_a[4] => ram_block1a18.PORTAADDR4 address_a[4] => ram_block1a19.PORTAADDR4 address_a[4] => ram_block1a20.PORTAADDR4 address_a[4] => ram_block1a21.PORTAADDR4 address_a[4] => ram_block1a22.PORTAADDR4 address_a[4] => ram_block1a23.PORTAADDR4 address_a[4] => ram_block1a24.PORTAADDR4 address_a[4] => ram_block1a25.PORTAADDR4 address_a[4] => ram_block1a26.PORTAADDR4 address_a[4] => ram_block1a27.PORTAADDR4 address_a[4] => ram_block1a28.PORTAADDR4 address_a[4] => ram_block1a29.PORTAADDR4 address_a[4] => ram_block1a30.PORTAADDR4 address_a[4] => ram_block1a31.PORTAADDR4 address_a[4] => ram_block1a32.PORTAADDR4 address_a[4] => ram_block1a33.PORTAADDR4 address_a[4] => ram_block1a34.PORTAADDR4 address_a[4] => ram_block1a35.PORTAADDR4 address_a[5] => ram_block1a0.PORTAADDR5 address_a[5] => ram_block1a1.PORTAADDR5 address_a[5] => ram_block1a2.PORTAADDR5 address_a[5] => ram_block1a3.PORTAADDR5 address_a[5] => ram_block1a4.PORTAADDR5 address_a[5] => ram_block1a5.PORTAADDR5 address_a[5] => ram_block1a6.PORTAADDR5 address_a[5] => ram_block1a7.PORTAADDR5 address_a[5] => ram_block1a8.PORTAADDR5 address_a[5] => ram_block1a9.PORTAADDR5 address_a[5] => ram_block1a10.PORTAADDR5 address_a[5] => ram_block1a11.PORTAADDR5 address_a[5] => ram_block1a12.PORTAADDR5 address_a[5] => ram_block1a13.PORTAADDR5 address_a[5] => ram_block1a14.PORTAADDR5 address_a[5] => ram_block1a15.PORTAADDR5 address_a[5] => ram_block1a16.PORTAADDR5 address_a[5] => ram_block1a17.PORTAADDR5 address_a[5] => ram_block1a18.PORTAADDR5 address_a[5] => ram_block1a19.PORTAADDR5 address_a[5] => ram_block1a20.PORTAADDR5 address_a[5] => ram_block1a21.PORTAADDR5 address_a[5] => ram_block1a22.PORTAADDR5 address_a[5] => ram_block1a23.PORTAADDR5 address_a[5] => ram_block1a24.PORTAADDR5 address_a[5] => ram_block1a25.PORTAADDR5 address_a[5] => ram_block1a26.PORTAADDR5 address_a[5] => ram_block1a27.PORTAADDR5 address_a[5] => ram_block1a28.PORTAADDR5 address_a[5] => ram_block1a29.PORTAADDR5 address_a[5] => ram_block1a30.PORTAADDR5 address_a[5] => ram_block1a31.PORTAADDR5 address_a[5] => ram_block1a32.PORTAADDR5 address_a[5] => ram_block1a33.PORTAADDR5 address_a[5] => ram_block1a34.PORTAADDR5 address_a[5] => ram_block1a35.PORTAADDR5 address_a[6] => ram_block1a0.PORTAADDR6 address_a[6] => ram_block1a1.PORTAADDR6 address_a[6] => ram_block1a2.PORTAADDR6 address_a[6] => ram_block1a3.PORTAADDR6 address_a[6] => ram_block1a4.PORTAADDR6 address_a[6] => ram_block1a5.PORTAADDR6 address_a[6] => ram_block1a6.PORTAADDR6 address_a[6] => ram_block1a7.PORTAADDR6 address_a[6] => ram_block1a8.PORTAADDR6 address_a[6] => ram_block1a9.PORTAADDR6 address_a[6] => ram_block1a10.PORTAADDR6 address_a[6] => ram_block1a11.PORTAADDR6 address_a[6] => ram_block1a12.PORTAADDR6 address_a[6] => ram_block1a13.PORTAADDR6 address_a[6] => ram_block1a14.PORTAADDR6 address_a[6] => ram_block1a15.PORTAADDR6 address_a[6] => ram_block1a16.PORTAADDR6 address_a[6] => ram_block1a17.PORTAADDR6 address_a[6] => ram_block1a18.PORTAADDR6 address_a[6] => ram_block1a19.PORTAADDR6 address_a[6] => ram_block1a20.PORTAADDR6 address_a[6] => ram_block1a21.PORTAADDR6 address_a[6] => ram_block1a22.PORTAADDR6 address_a[6] => ram_block1a23.PORTAADDR6 address_a[6] => ram_block1a24.PORTAADDR6 address_a[6] => ram_block1a25.PORTAADDR6 address_a[6] => ram_block1a26.PORTAADDR6 address_a[6] => ram_block1a27.PORTAADDR6 address_a[6] => ram_block1a28.PORTAADDR6 address_a[6] => ram_block1a29.PORTAADDR6 address_a[6] => ram_block1a30.PORTAADDR6 address_a[6] => ram_block1a31.PORTAADDR6 address_a[6] => ram_block1a32.PORTAADDR6 address_a[6] => ram_block1a33.PORTAADDR6 address_a[6] => ram_block1a34.PORTAADDR6 address_a[6] => ram_block1a35.PORTAADDR6 address_b[0] => ram_block1a0.PORTBADDR address_b[0] => ram_block1a1.PORTBADDR address_b[0] => ram_block1a2.PORTBADDR address_b[0] => ram_block1a3.PORTBADDR address_b[0] => ram_block1a4.PORTBADDR address_b[0] => ram_block1a5.PORTBADDR address_b[0] => ram_block1a6.PORTBADDR address_b[0] => ram_block1a7.PORTBADDR address_b[0] => ram_block1a8.PORTBADDR address_b[0] => ram_block1a9.PORTBADDR address_b[0] => ram_block1a10.PORTBADDR address_b[0] => ram_block1a11.PORTBADDR address_b[0] => ram_block1a12.PORTBADDR address_b[0] => ram_block1a13.PORTBADDR address_b[0] => ram_block1a14.PORTBADDR address_b[0] => ram_block1a15.PORTBADDR address_b[0] => ram_block1a16.PORTBADDR address_b[0] => ram_block1a17.PORTBADDR address_b[0] => ram_block1a18.PORTBADDR address_b[0] => ram_block1a19.PORTBADDR address_b[0] => ram_block1a20.PORTBADDR address_b[0] => ram_block1a21.PORTBADDR address_b[0] => ram_block1a22.PORTBADDR address_b[0] => ram_block1a23.PORTBADDR address_b[0] => ram_block1a24.PORTBADDR address_b[0] => ram_block1a25.PORTBADDR address_b[0] => ram_block1a26.PORTBADDR address_b[0] => ram_block1a27.PORTBADDR address_b[0] => ram_block1a28.PORTBADDR address_b[0] => ram_block1a29.PORTBADDR address_b[0] => ram_block1a30.PORTBADDR address_b[0] => ram_block1a31.PORTBADDR address_b[0] => ram_block1a32.PORTBADDR address_b[0] => ram_block1a33.PORTBADDR address_b[0] => ram_block1a34.PORTBADDR address_b[0] => ram_block1a35.PORTBADDR address_b[1] => ram_block1a0.PORTBADDR1 address_b[1] => ram_block1a1.PORTBADDR1 address_b[1] => ram_block1a2.PORTBADDR1 address_b[1] => ram_block1a3.PORTBADDR1 address_b[1] => ram_block1a4.PORTBADDR1 address_b[1] => ram_block1a5.PORTBADDR1 address_b[1] => ram_block1a6.PORTBADDR1 address_b[1] => ram_block1a7.PORTBADDR1 address_b[1] => ram_block1a8.PORTBADDR1 address_b[1] => ram_block1a9.PORTBADDR1 address_b[1] => ram_block1a10.PORTBADDR1 address_b[1] => ram_block1a11.PORTBADDR1 address_b[1] => ram_block1a12.PORTBADDR1 address_b[1] => ram_block1a13.PORTBADDR1 address_b[1] => ram_block1a14.PORTBADDR1 address_b[1] => ram_block1a15.PORTBADDR1 address_b[1] => ram_block1a16.PORTBADDR1 address_b[1] => ram_block1a17.PORTBADDR1 address_b[1] => ram_block1a18.PORTBADDR1 address_b[1] => ram_block1a19.PORTBADDR1 address_b[1] => ram_block1a20.PORTBADDR1 address_b[1] => ram_block1a21.PORTBADDR1 address_b[1] => ram_block1a22.PORTBADDR1 address_b[1] => ram_block1a23.PORTBADDR1 address_b[1] => ram_block1a24.PORTBADDR1 address_b[1] => ram_block1a25.PORTBADDR1 address_b[1] => ram_block1a26.PORTBADDR1 address_b[1] => ram_block1a27.PORTBADDR1 address_b[1] => ram_block1a28.PORTBADDR1 address_b[1] => ram_block1a29.PORTBADDR1 address_b[1] => ram_block1a30.PORTBADDR1 address_b[1] => ram_block1a31.PORTBADDR1 address_b[1] => ram_block1a32.PORTBADDR1 address_b[1] => ram_block1a33.PORTBADDR1 address_b[1] => ram_block1a34.PORTBADDR1 address_b[1] => ram_block1a35.PORTBADDR1 address_b[2] => ram_block1a0.PORTBADDR2 address_b[2] => ram_block1a1.PORTBADDR2 address_b[2] => ram_block1a2.PORTBADDR2 address_b[2] => ram_block1a3.PORTBADDR2 address_b[2] => ram_block1a4.PORTBADDR2 address_b[2] => ram_block1a5.PORTBADDR2 address_b[2] => ram_block1a6.PORTBADDR2 address_b[2] => ram_block1a7.PORTBADDR2 address_b[2] => ram_block1a8.PORTBADDR2 address_b[2] => ram_block1a9.PORTBADDR2 address_b[2] => ram_block1a10.PORTBADDR2 address_b[2] => ram_block1a11.PORTBADDR2 address_b[2] => ram_block1a12.PORTBADDR2 address_b[2] => ram_block1a13.PORTBADDR2 address_b[2] => ram_block1a14.PORTBADDR2 address_b[2] => ram_block1a15.PORTBADDR2 address_b[2] => ram_block1a16.PORTBADDR2 address_b[2] => ram_block1a17.PORTBADDR2 address_b[2] => ram_block1a18.PORTBADDR2 address_b[2] => ram_block1a19.PORTBADDR2 address_b[2] => ram_block1a20.PORTBADDR2 address_b[2] => ram_block1a21.PORTBADDR2 address_b[2] => ram_block1a22.PORTBADDR2 address_b[2] => ram_block1a23.PORTBADDR2 address_b[2] => ram_block1a24.PORTBADDR2 address_b[2] => ram_block1a25.PORTBADDR2 address_b[2] => ram_block1a26.PORTBADDR2 address_b[2] => ram_block1a27.PORTBADDR2 address_b[2] => ram_block1a28.PORTBADDR2 address_b[2] => ram_block1a29.PORTBADDR2 address_b[2] => ram_block1a30.PORTBADDR2 address_b[2] => ram_block1a31.PORTBADDR2 address_b[2] => ram_block1a32.PORTBADDR2 address_b[2] => ram_block1a33.PORTBADDR2 address_b[2] => ram_block1a34.PORTBADDR2 address_b[2] => ram_block1a35.PORTBADDR2 address_b[3] => ram_block1a0.PORTBADDR3 address_b[3] => ram_block1a1.PORTBADDR3 address_b[3] => ram_block1a2.PORTBADDR3 address_b[3] => ram_block1a3.PORTBADDR3 address_b[3] => ram_block1a4.PORTBADDR3 address_b[3] => ram_block1a5.PORTBADDR3 address_b[3] => ram_block1a6.PORTBADDR3 address_b[3] => ram_block1a7.PORTBADDR3 address_b[3] => ram_block1a8.PORTBADDR3 address_b[3] => ram_block1a9.PORTBADDR3 address_b[3] => ram_block1a10.PORTBADDR3 address_b[3] => ram_block1a11.PORTBADDR3 address_b[3] => ram_block1a12.PORTBADDR3 address_b[3] => ram_block1a13.PORTBADDR3 address_b[3] => ram_block1a14.PORTBADDR3 address_b[3] => ram_block1a15.PORTBADDR3 address_b[3] => ram_block1a16.PORTBADDR3 address_b[3] => ram_block1a17.PORTBADDR3 address_b[3] => ram_block1a18.PORTBADDR3 address_b[3] => ram_block1a19.PORTBADDR3 address_b[3] => ram_block1a20.PORTBADDR3 address_b[3] => ram_block1a21.PORTBADDR3 address_b[3] => ram_block1a22.PORTBADDR3 address_b[3] => ram_block1a23.PORTBADDR3 address_b[3] => ram_block1a24.PORTBADDR3 address_b[3] => ram_block1a25.PORTBADDR3 address_b[3] => ram_block1a26.PORTBADDR3 address_b[3] => ram_block1a27.PORTBADDR3 address_b[3] => ram_block1a28.PORTBADDR3 address_b[3] => ram_block1a29.PORTBADDR3 address_b[3] => ram_block1a30.PORTBADDR3 address_b[3] => ram_block1a31.PORTBADDR3 address_b[3] => ram_block1a32.PORTBADDR3 address_b[3] => ram_block1a33.PORTBADDR3 address_b[3] => ram_block1a34.PORTBADDR3 address_b[3] => ram_block1a35.PORTBADDR3 address_b[4] => ram_block1a0.PORTBADDR4 address_b[4] => ram_block1a1.PORTBADDR4 address_b[4] => ram_block1a2.PORTBADDR4 address_b[4] => ram_block1a3.PORTBADDR4 address_b[4] => ram_block1a4.PORTBADDR4 address_b[4] => ram_block1a5.PORTBADDR4 address_b[4] => ram_block1a6.PORTBADDR4 address_b[4] => ram_block1a7.PORTBADDR4 address_b[4] => ram_block1a8.PORTBADDR4 address_b[4] => ram_block1a9.PORTBADDR4 address_b[4] => ram_block1a10.PORTBADDR4 address_b[4] => ram_block1a11.PORTBADDR4 address_b[4] => ram_block1a12.PORTBADDR4 address_b[4] => ram_block1a13.PORTBADDR4 address_b[4] => ram_block1a14.PORTBADDR4 address_b[4] => ram_block1a15.PORTBADDR4 address_b[4] => ram_block1a16.PORTBADDR4 address_b[4] => ram_block1a17.PORTBADDR4 address_b[4] => ram_block1a18.PORTBADDR4 address_b[4] => ram_block1a19.PORTBADDR4 address_b[4] => ram_block1a20.PORTBADDR4 address_b[4] => ram_block1a21.PORTBADDR4 address_b[4] => ram_block1a22.PORTBADDR4 address_b[4] => ram_block1a23.PORTBADDR4 address_b[4] => ram_block1a24.PORTBADDR4 address_b[4] => ram_block1a25.PORTBADDR4 address_b[4] => ram_block1a26.PORTBADDR4 address_b[4] => ram_block1a27.PORTBADDR4 address_b[4] => ram_block1a28.PORTBADDR4 address_b[4] => ram_block1a29.PORTBADDR4 address_b[4] => ram_block1a30.PORTBADDR4 address_b[4] => ram_block1a31.PORTBADDR4 address_b[4] => ram_block1a32.PORTBADDR4 address_b[4] => ram_block1a33.PORTBADDR4 address_b[4] => ram_block1a34.PORTBADDR4 address_b[4] => ram_block1a35.PORTBADDR4 address_b[5] => ram_block1a0.PORTBADDR5 address_b[5] => ram_block1a1.PORTBADDR5 address_b[5] => ram_block1a2.PORTBADDR5 address_b[5] => ram_block1a3.PORTBADDR5 address_b[5] => ram_block1a4.PORTBADDR5 address_b[5] => ram_block1a5.PORTBADDR5 address_b[5] => ram_block1a6.PORTBADDR5 address_b[5] => ram_block1a7.PORTBADDR5 address_b[5] => ram_block1a8.PORTBADDR5 address_b[5] => ram_block1a9.PORTBADDR5 address_b[5] => ram_block1a10.PORTBADDR5 address_b[5] => ram_block1a11.PORTBADDR5 address_b[5] => ram_block1a12.PORTBADDR5 address_b[5] => ram_block1a13.PORTBADDR5 address_b[5] => ram_block1a14.PORTBADDR5 address_b[5] => ram_block1a15.PORTBADDR5 address_b[5] => ram_block1a16.PORTBADDR5 address_b[5] => ram_block1a17.PORTBADDR5 address_b[5] => ram_block1a18.PORTBADDR5 address_b[5] => ram_block1a19.PORTBADDR5 address_b[5] => ram_block1a20.PORTBADDR5 address_b[5] => ram_block1a21.PORTBADDR5 address_b[5] => ram_block1a22.PORTBADDR5 address_b[5] => ram_block1a23.PORTBADDR5 address_b[5] => ram_block1a24.PORTBADDR5 address_b[5] => ram_block1a25.PORTBADDR5 address_b[5] => ram_block1a26.PORTBADDR5 address_b[5] => ram_block1a27.PORTBADDR5 address_b[5] => ram_block1a28.PORTBADDR5 address_b[5] => ram_block1a29.PORTBADDR5 address_b[5] => ram_block1a30.PORTBADDR5 address_b[5] => ram_block1a31.PORTBADDR5 address_b[5] => ram_block1a32.PORTBADDR5 address_b[5] => ram_block1a33.PORTBADDR5 address_b[5] => ram_block1a34.PORTBADDR5 address_b[5] => ram_block1a35.PORTBADDR5 address_b[6] => ram_block1a0.PORTBADDR6 address_b[6] => ram_block1a1.PORTBADDR6 address_b[6] => ram_block1a2.PORTBADDR6 address_b[6] => ram_block1a3.PORTBADDR6 address_b[6] => ram_block1a4.PORTBADDR6 address_b[6] => ram_block1a5.PORTBADDR6 address_b[6] => ram_block1a6.PORTBADDR6 address_b[6] => ram_block1a7.PORTBADDR6 address_b[6] => ram_block1a8.PORTBADDR6 address_b[6] => ram_block1a9.PORTBADDR6 address_b[6] => ram_block1a10.PORTBADDR6 address_b[6] => ram_block1a11.PORTBADDR6 address_b[6] => ram_block1a12.PORTBADDR6 address_b[6] => ram_block1a13.PORTBADDR6 address_b[6] => ram_block1a14.PORTBADDR6 address_b[6] => ram_block1a15.PORTBADDR6 address_b[6] => ram_block1a16.PORTBADDR6 address_b[6] => ram_block1a17.PORTBADDR6 address_b[6] => ram_block1a18.PORTBADDR6 address_b[6] => ram_block1a19.PORTBADDR6 address_b[6] => ram_block1a20.PORTBADDR6 address_b[6] => ram_block1a21.PORTBADDR6 address_b[6] => ram_block1a22.PORTBADDR6 address_b[6] => ram_block1a23.PORTBADDR6 address_b[6] => ram_block1a24.PORTBADDR6 address_b[6] => ram_block1a25.PORTBADDR6 address_b[6] => ram_block1a26.PORTBADDR6 address_b[6] => ram_block1a27.PORTBADDR6 address_b[6] => ram_block1a28.PORTBADDR6 address_b[6] => ram_block1a29.PORTBADDR6 address_b[6] => ram_block1a30.PORTBADDR6 address_b[6] => ram_block1a31.PORTBADDR6 address_b[6] => ram_block1a32.PORTBADDR6 address_b[6] => ram_block1a33.PORTBADDR6 address_b[6] => ram_block1a34.PORTBADDR6 address_b[6] => ram_block1a35.PORTBADDR6 clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 clock0 => ram_block1a8.CLK0 clock0 => ram_block1a9.CLK0 clock0 => ram_block1a10.CLK0 clock0 => ram_block1a11.CLK0 clock0 => ram_block1a12.CLK0 clock0 => ram_block1a13.CLK0 clock0 => ram_block1a14.CLK0 clock0 => ram_block1a15.CLK0 clock0 => ram_block1a16.CLK0 clock0 => ram_block1a17.CLK0 clock0 => ram_block1a18.CLK0 clock0 => ram_block1a19.CLK0 clock0 => ram_block1a20.CLK0 clock0 => ram_block1a21.CLK0 clock0 => ram_block1a22.CLK0 clock0 => ram_block1a23.CLK0 clock0 => ram_block1a24.CLK0 clock0 => ram_block1a25.CLK0 clock0 => ram_block1a26.CLK0 clock0 => ram_block1a27.CLK0 clock0 => ram_block1a28.CLK0 clock0 => ram_block1a29.CLK0 clock0 => ram_block1a30.CLK0 clock0 => ram_block1a31.CLK0 clock0 => ram_block1a32.CLK0 clock0 => ram_block1a33.CLK0 clock0 => ram_block1a34.CLK0 clock0 => ram_block1a35.CLK0 clock1 => ram_block1a0.CLK1 clock1 => ram_block1a1.CLK1 clock1 => ram_block1a2.CLK1 clock1 => ram_block1a3.CLK1 clock1 => ram_block1a4.CLK1 clock1 => ram_block1a5.CLK1 clock1 => ram_block1a6.CLK1 clock1 => ram_block1a7.CLK1 clock1 => ram_block1a8.CLK1 clock1 => ram_block1a9.CLK1 clock1 => ram_block1a10.CLK1 clock1 => ram_block1a11.CLK1 clock1 => ram_block1a12.CLK1 clock1 => ram_block1a13.CLK1 clock1 => ram_block1a14.CLK1 clock1 => ram_block1a15.CLK1 clock1 => ram_block1a16.CLK1 clock1 => ram_block1a17.CLK1 clock1 => ram_block1a18.CLK1 clock1 => ram_block1a19.CLK1 clock1 => ram_block1a20.CLK1 clock1 => ram_block1a21.CLK1 clock1 => ram_block1a22.CLK1 clock1 => ram_block1a23.CLK1 clock1 => ram_block1a24.CLK1 clock1 => ram_block1a25.CLK1 clock1 => ram_block1a26.CLK1 clock1 => ram_block1a27.CLK1 clock1 => ram_block1a28.CLK1 clock1 => ram_block1a29.CLK1 clock1 => ram_block1a30.CLK1 clock1 => ram_block1a31.CLK1 clock1 => ram_block1a32.CLK1 clock1 => ram_block1a33.CLK1 clock1 => ram_block1a34.CLK1 clock1 => ram_block1a35.CLK1 clocken0 => ram_block1a0.ENA0 clocken0 => ram_block1a1.ENA0 clocken0 => ram_block1a2.ENA0 clocken0 => ram_block1a3.ENA0 clocken0 => ram_block1a4.ENA0 clocken0 => ram_block1a5.ENA0 clocken0 => ram_block1a6.ENA0 clocken0 => ram_block1a7.ENA0 clocken0 => ram_block1a8.ENA0 clocken0 => ram_block1a9.ENA0 clocken0 => ram_block1a10.ENA0 clocken0 => ram_block1a11.ENA0 clocken0 => ram_block1a12.ENA0 clocken0 => ram_block1a13.ENA0 clocken0 => ram_block1a14.ENA0 clocken0 => ram_block1a15.ENA0 clocken0 => ram_block1a16.ENA0 clocken0 => ram_block1a17.ENA0 clocken0 => ram_block1a18.ENA0 clocken0 => ram_block1a19.ENA0 clocken0 => ram_block1a20.ENA0 clocken0 => ram_block1a21.ENA0 clocken0 => ram_block1a22.ENA0 clocken0 => ram_block1a23.ENA0 clocken0 => ram_block1a24.ENA0 clocken0 => ram_block1a25.ENA0 clocken0 => ram_block1a26.ENA0 clocken0 => ram_block1a27.ENA0 clocken0 => ram_block1a28.ENA0 clocken0 => ram_block1a29.ENA0 clocken0 => ram_block1a30.ENA0 clocken0 => ram_block1a31.ENA0 clocken0 => ram_block1a32.ENA0 clocken0 => ram_block1a33.ENA0 clocken0 => ram_block1a34.ENA0 clocken0 => ram_block1a35.ENA0 clocken1 => ram_block1a0.ENA1 clocken1 => ram_block1a1.ENA1 clocken1 => ram_block1a2.ENA1 clocken1 => ram_block1a3.ENA1 clocken1 => ram_block1a4.ENA1 clocken1 => ram_block1a5.ENA1 clocken1 => ram_block1a6.ENA1 clocken1 => ram_block1a7.ENA1 clocken1 => ram_block1a8.ENA1 clocken1 => ram_block1a9.ENA1 clocken1 => ram_block1a10.ENA1 clocken1 => ram_block1a11.ENA1 clocken1 => ram_block1a12.ENA1 clocken1 => ram_block1a13.ENA1 clocken1 => ram_block1a14.ENA1 clocken1 => ram_block1a15.ENA1 clocken1 => ram_block1a16.ENA1 clocken1 => ram_block1a17.ENA1 clocken1 => ram_block1a18.ENA1 clocken1 => ram_block1a19.ENA1 clocken1 => ram_block1a20.ENA1 clocken1 => ram_block1a21.ENA1 clocken1 => ram_block1a22.ENA1 clocken1 => ram_block1a23.ENA1 clocken1 => ram_block1a24.ENA1 clocken1 => ram_block1a25.ENA1 clocken1 => ram_block1a26.ENA1 clocken1 => ram_block1a27.ENA1 clocken1 => ram_block1a28.ENA1 clocken1 => ram_block1a29.ENA1 clocken1 => ram_block1a30.ENA1 clocken1 => ram_block1a31.ENA1 clocken1 => ram_block1a32.ENA1 clocken1 => ram_block1a33.ENA1 clocken1 => ram_block1a34.ENA1 clocken1 => ram_block1a35.ENA1 data_a[0] => ram_block1a0.PORTADATAIN data_a[1] => ram_block1a1.PORTADATAIN data_a[2] => ram_block1a2.PORTADATAIN data_a[3] => ram_block1a3.PORTADATAIN data_a[4] => ram_block1a4.PORTADATAIN data_a[5] => ram_block1a5.PORTADATAIN data_a[6] => ram_block1a6.PORTADATAIN data_a[7] => ram_block1a7.PORTADATAIN data_a[8] => ram_block1a8.PORTADATAIN data_a[9] => ram_block1a9.PORTADATAIN data_a[10] => ram_block1a10.PORTADATAIN data_a[11] => ram_block1a11.PORTADATAIN data_a[12] => ram_block1a12.PORTADATAIN data_a[13] => ram_block1a13.PORTADATAIN data_a[14] => ram_block1a14.PORTADATAIN data_a[15] => ram_block1a15.PORTADATAIN data_a[16] => ram_block1a16.PORTADATAIN data_a[17] => ram_block1a17.PORTADATAIN data_a[18] => ram_block1a18.PORTADATAIN data_a[19] => ram_block1a19.PORTADATAIN data_a[20] => ram_block1a20.PORTADATAIN data_a[21] => ram_block1a21.PORTADATAIN data_a[22] => ram_block1a22.PORTADATAIN data_a[23] => ram_block1a23.PORTADATAIN data_a[24] => ram_block1a24.PORTADATAIN data_a[25] => ram_block1a25.PORTADATAIN data_a[26] => ram_block1a26.PORTADATAIN data_a[27] => ram_block1a27.PORTADATAIN data_a[28] => ram_block1a28.PORTADATAIN data_a[29] => ram_block1a29.PORTADATAIN data_a[30] => ram_block1a30.PORTADATAIN data_a[31] => ram_block1a31.PORTADATAIN data_a[32] => ram_block1a32.PORTADATAIN data_a[33] => ram_block1a33.PORTADATAIN data_a[34] => ram_block1a34.PORTADATAIN data_a[35] => ram_block1a35.PORTADATAIN data_b[0] => ram_block1a0.PORTBDATAIN data_b[1] => ram_block1a1.PORTBDATAIN data_b[2] => ram_block1a2.PORTBDATAIN data_b[3] => ram_block1a3.PORTBDATAIN data_b[4] => ram_block1a4.PORTBDATAIN data_b[5] => ram_block1a5.PORTBDATAIN data_b[6] => ram_block1a6.PORTBDATAIN data_b[7] => ram_block1a7.PORTBDATAIN data_b[8] => ram_block1a8.PORTBDATAIN data_b[9] => ram_block1a9.PORTBDATAIN data_b[10] => ram_block1a10.PORTBDATAIN data_b[11] => ram_block1a11.PORTBDATAIN data_b[12] => ram_block1a12.PORTBDATAIN data_b[13] => ram_block1a13.PORTBDATAIN data_b[14] => ram_block1a14.PORTBDATAIN data_b[15] => ram_block1a15.PORTBDATAIN data_b[16] => ram_block1a16.PORTBDATAIN data_b[17] => ram_block1a17.PORTBDATAIN data_b[18] => ram_block1a18.PORTBDATAIN data_b[19] => ram_block1a19.PORTBDATAIN data_b[20] => ram_block1a20.PORTBDATAIN data_b[21] => ram_block1a21.PORTBDATAIN data_b[22] => ram_block1a22.PORTBDATAIN data_b[23] => ram_block1a23.PORTBDATAIN data_b[24] => ram_block1a24.PORTBDATAIN data_b[25] => ram_block1a25.PORTBDATAIN data_b[26] => ram_block1a26.PORTBDATAIN data_b[27] => ram_block1a27.PORTBDATAIN data_b[28] => ram_block1a28.PORTBDATAIN data_b[29] => ram_block1a29.PORTBDATAIN data_b[30] => ram_block1a30.PORTBDATAIN data_b[31] => ram_block1a31.PORTBDATAIN data_b[32] => ram_block1a32.PORTBDATAIN data_b[33] => ram_block1a33.PORTBDATAIN data_b[34] => ram_block1a34.PORTBDATAIN data_b[35] => ram_block1a35.PORTBDATAIN q_a[0] <= ram_block1a0.PORTADATAOUT q_a[1] <= ram_block1a1.PORTADATAOUT q_a[2] <= ram_block1a2.PORTADATAOUT q_a[3] <= ram_block1a3.PORTADATAOUT q_a[4] <= ram_block1a4.PORTADATAOUT q_a[5] <= ram_block1a5.PORTADATAOUT q_a[6] <= ram_block1a6.PORTADATAOUT q_a[7] <= ram_block1a7.PORTADATAOUT q_a[8] <= ram_block1a8.PORTADATAOUT q_a[9] <= ram_block1a9.PORTADATAOUT q_a[10] <= ram_block1a10.PORTADATAOUT q_a[11] <= ram_block1a11.PORTADATAOUT q_a[12] <= ram_block1a12.PORTADATAOUT q_a[13] <= ram_block1a13.PORTADATAOUT q_a[14] <= ram_block1a14.PORTADATAOUT q_a[15] <= ram_block1a15.PORTADATAOUT q_a[16] <= ram_block1a16.PORTADATAOUT q_a[17] <= ram_block1a17.PORTADATAOUT q_a[18] <= ram_block1a18.PORTADATAOUT q_a[19] <= ram_block1a19.PORTADATAOUT q_a[20] <= ram_block1a20.PORTADATAOUT q_a[21] <= ram_block1a21.PORTADATAOUT q_a[22] <= ram_block1a22.PORTADATAOUT q_a[23] <= ram_block1a23.PORTADATAOUT q_a[24] <= ram_block1a24.PORTADATAOUT q_a[25] <= ram_block1a25.PORTADATAOUT q_a[26] <= ram_block1a26.PORTADATAOUT q_a[27] <= ram_block1a27.PORTADATAOUT q_a[28] <= ram_block1a28.PORTADATAOUT q_a[29] <= ram_block1a29.PORTADATAOUT q_a[30] <= ram_block1a30.PORTADATAOUT q_a[31] <= ram_block1a31.PORTADATAOUT q_a[32] <= ram_block1a32.PORTADATAOUT q_a[33] <= ram_block1a33.PORTADATAOUT q_a[34] <= ram_block1a34.PORTADATAOUT q_a[35] <= ram_block1a35.PORTADATAOUT q_b[0] <= ram_block1a0.PORTBDATAOUT q_b[1] <= ram_block1a1.PORTBDATAOUT q_b[2] <= ram_block1a2.PORTBDATAOUT q_b[3] <= ram_block1a3.PORTBDATAOUT q_b[4] <= ram_block1a4.PORTBDATAOUT q_b[5] <= ram_block1a5.PORTBDATAOUT q_b[6] <= ram_block1a6.PORTBDATAOUT q_b[7] <= ram_block1a7.PORTBDATAOUT q_b[8] <= ram_block1a8.PORTBDATAOUT q_b[9] <= ram_block1a9.PORTBDATAOUT q_b[10] <= ram_block1a10.PORTBDATAOUT q_b[11] <= ram_block1a11.PORTBDATAOUT q_b[12] <= ram_block1a12.PORTBDATAOUT q_b[13] <= ram_block1a13.PORTBDATAOUT q_b[14] <= ram_block1a14.PORTBDATAOUT q_b[15] <= ram_block1a15.PORTBDATAOUT q_b[16] <= ram_block1a16.PORTBDATAOUT q_b[17] <= ram_block1a17.PORTBDATAOUT q_b[18] <= ram_block1a18.PORTBDATAOUT q_b[19] <= ram_block1a19.PORTBDATAOUT q_b[20] <= ram_block1a20.PORTBDATAOUT q_b[21] <= ram_block1a21.PORTBDATAOUT q_b[22] <= ram_block1a22.PORTBDATAOUT q_b[23] <= ram_block1a23.PORTBDATAOUT q_b[24] <= ram_block1a24.PORTBDATAOUT q_b[25] <= ram_block1a25.PORTBDATAOUT q_b[26] <= ram_block1a26.PORTBDATAOUT q_b[27] <= ram_block1a27.PORTBDATAOUT q_b[28] <= ram_block1a28.PORTBDATAOUT q_b[29] <= ram_block1a29.PORTBDATAOUT q_b[30] <= ram_block1a30.PORTBDATAOUT q_b[31] <= ram_block1a31.PORTBDATAOUT q_b[32] <= ram_block1a32.PORTBDATAOUT q_b[33] <= ram_block1a33.PORTBDATAOUT q_b[34] <= ram_block1a34.PORTBDATAOUT q_b[35] <= ram_block1a35.PORTBDATAOUT wren_a => ram_block1a0.PORTAWE wren_a => ram_block1a1.PORTAWE wren_a => ram_block1a2.PORTAWE wren_a => ram_block1a3.PORTAWE wren_a => ram_block1a4.PORTAWE wren_a => ram_block1a5.PORTAWE wren_a => ram_block1a6.PORTAWE wren_a => ram_block1a7.PORTAWE wren_a => ram_block1a8.PORTAWE wren_a => ram_block1a9.PORTAWE wren_a => ram_block1a10.PORTAWE wren_a => ram_block1a11.PORTAWE wren_a => ram_block1a12.PORTAWE wren_a => ram_block1a13.PORTAWE wren_a => ram_block1a14.PORTAWE wren_a => ram_block1a15.PORTAWE wren_a => ram_block1a16.PORTAWE wren_a => ram_block1a17.PORTAWE wren_a => ram_block1a18.PORTAWE wren_a => ram_block1a19.PORTAWE wren_a => ram_block1a20.PORTAWE wren_a => ram_block1a21.PORTAWE wren_a => ram_block1a22.PORTAWE wren_a => ram_block1a23.PORTAWE wren_a => ram_block1a24.PORTAWE wren_a => ram_block1a25.PORTAWE wren_a => ram_block1a26.PORTAWE wren_a => ram_block1a27.PORTAWE wren_a => ram_block1a28.PORTAWE wren_a => ram_block1a29.PORTAWE wren_a => ram_block1a30.PORTAWE wren_a => ram_block1a31.PORTAWE wren_a => ram_block1a32.PORTAWE wren_a => ram_block1a33.PORTAWE wren_a => ram_block1a34.PORTAWE wren_a => ram_block1a35.PORTAWE wren_b => ram_block1a0.PORTBRE wren_b => ram_block1a1.PORTBRE wren_b => ram_block1a2.PORTBRE wren_b => ram_block1a3.PORTBRE wren_b => ram_block1a4.PORTBRE wren_b => ram_block1a5.PORTBRE wren_b => ram_block1a6.PORTBRE wren_b => ram_block1a7.PORTBRE wren_b => ram_block1a8.PORTBRE wren_b => ram_block1a9.PORTBRE wren_b => ram_block1a10.PORTBRE wren_b => ram_block1a11.PORTBRE wren_b => ram_block1a12.PORTBRE wren_b => ram_block1a13.PORTBRE wren_b => ram_block1a14.PORTBRE wren_b => ram_block1a15.PORTBRE wren_b => ram_block1a16.PORTBRE wren_b => ram_block1a17.PORTBRE wren_b => ram_block1a18.PORTBRE wren_b => ram_block1a19.PORTBRE wren_b => ram_block1a20.PORTBRE wren_b => ram_block1a21.PORTBRE wren_b => ram_block1a22.PORTBRE wren_b => ram_block1a23.PORTBRE wren_b => ram_block1a24.PORTBRE wren_b => ram_block1a25.PORTBRE wren_b => ram_block1a26.PORTBRE wren_b => ram_block1a27.PORTBRE wren_b => ram_block1a28.PORTBRE wren_b => ram_block1a29.PORTBRE wren_b => ram_block1a30.PORTBRE wren_b => ram_block1a31.PORTBRE wren_b => ram_block1a32.PORTBRE wren_b => ram_block1a33.PORTBRE wren_b => ram_block1a34.PORTBRE wren_b => ram_block1a35.PORTBRE |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper MonDReg[0] => MonDReg[0]~31.IN1 MonDReg[1] => MonDReg[1]~30.IN1 MonDReg[2] => MonDReg[2]~29.IN1 MonDReg[3] => MonDReg[3]~28.IN1 MonDReg[4] => MonDReg[4]~27.IN1 MonDReg[5] => MonDReg[5]~26.IN1 MonDReg[6] => MonDReg[6]~25.IN1 MonDReg[7] => MonDReg[7]~24.IN1 MonDReg[8] => MonDReg[8]~23.IN1 MonDReg[9] => MonDReg[9]~22.IN1 MonDReg[10] => MonDReg[10]~21.IN1 MonDReg[11] => MonDReg[11]~20.IN1 MonDReg[12] => MonDReg[12]~19.IN1 MonDReg[13] => MonDReg[13]~18.IN1 MonDReg[14] => MonDReg[14]~17.IN1 MonDReg[15] => MonDReg[15]~16.IN1 MonDReg[16] => MonDReg[16]~15.IN1 MonDReg[17] => MonDReg[17]~14.IN1 MonDReg[18] => MonDReg[18]~13.IN1 MonDReg[19] => MonDReg[19]~12.IN1 MonDReg[20] => MonDReg[20]~11.IN1 MonDReg[21] => MonDReg[21]~10.IN1 MonDReg[22] => MonDReg[22]~9.IN1 MonDReg[23] => MonDReg[23]~8.IN1 MonDReg[24] => MonDReg[24]~7.IN1 MonDReg[25] => MonDReg[25]~6.IN1 MonDReg[26] => MonDReg[26]~5.IN1 MonDReg[27] => MonDReg[27]~4.IN1 MonDReg[28] => MonDReg[28]~3.IN1 MonDReg[29] => MonDReg[29]~2.IN1 MonDReg[30] => MonDReg[30]~1.IN1 MonDReg[31] => MonDReg[31]~0.IN1 break_readreg[0] => break_readreg[0]~31.IN1 break_readreg[1] => break_readreg[1]~30.IN1 break_readreg[2] => break_readreg[2]~29.IN1 break_readreg[3] => break_readreg[3]~28.IN1 break_readreg[4] => break_readreg[4]~27.IN1 break_readreg[5] => break_readreg[5]~26.IN1 break_readreg[6] => break_readreg[6]~25.IN1 break_readreg[7] => break_readreg[7]~24.IN1 break_readreg[8] => break_readreg[8]~23.IN1 break_readreg[9] => break_readreg[9]~22.IN1 break_readreg[10] => break_readreg[10]~21.IN1 break_readreg[11] => break_readreg[11]~20.IN1 break_readreg[12] => break_readreg[12]~19.IN1 break_readreg[13] => break_readreg[13]~18.IN1 break_readreg[14] => break_readreg[14]~17.IN1 break_readreg[15] => break_readreg[15]~16.IN1 break_readreg[16] => break_readreg[16]~15.IN1 break_readreg[17] => break_readreg[17]~14.IN1 break_readreg[18] => break_readreg[18]~13.IN1 break_readreg[19] => break_readreg[19]~12.IN1 break_readreg[20] => break_readreg[20]~11.IN1 break_readreg[21] => break_readreg[21]~10.IN1 break_readreg[22] => break_readreg[22]~9.IN1 break_readreg[23] => break_readreg[23]~8.IN1 break_readreg[24] => break_readreg[24]~7.IN1 break_readreg[25] => break_readreg[25]~6.IN1 break_readreg[26] => break_readreg[26]~5.IN1 break_readreg[27] => break_readreg[27]~4.IN1 break_readreg[28] => break_readreg[28]~3.IN1 break_readreg[29] => break_readreg[29]~2.IN1 break_readreg[30] => break_readreg[30]~1.IN1 break_readreg[31] => break_readreg[31]~0.IN1 clk => clk~0.IN1 dbrk_hit0_latch => dbrk_hit0_latch~0.IN1 dbrk_hit1_latch => dbrk_hit1_latch~0.IN1 dbrk_hit2_latch => dbrk_hit2_latch~0.IN1 dbrk_hit3_latch => dbrk_hit3_latch~0.IN1 debugack => debugack~0.IN1 monitor_error => monitor_error~0.IN1 monitor_ready => monitor_ready~0.IN1 reset_n => reset_n~0.IN1 resetlatch => resetlatch~0.IN1 tracemem_on => tracemem_on~0.IN1 tracemem_trcdata[0] => tracemem_trcdata[0]~35.IN1 tracemem_trcdata[1] => tracemem_trcdata[1]~34.IN1 tracemem_trcdata[2] => tracemem_trcdata[2]~33.IN1 tracemem_trcdata[3] => tracemem_trcdata[3]~32.IN1 tracemem_trcdata[4] => tracemem_trcdata[4]~31.IN1 tracemem_trcdata[5] => tracemem_trcdata[5]~30.IN1 tracemem_trcdata[6] => tracemem_trcdata[6]~29.IN1 tracemem_trcdata[7] => tracemem_trcdata[7]~28.IN1 tracemem_trcdata[8] => tracemem_trcdata[8]~27.IN1 tracemem_trcdata[9] => tracemem_trcdata[9]~26.IN1 tracemem_trcdata[10] => tracemem_trcdata[10]~25.IN1 tracemem_trcdata[11] => tracemem_trcdata[11]~24.IN1 tracemem_trcdata[12] => tracemem_trcdata[12]~23.IN1 tracemem_trcdata[13] => tracemem_trcdata[13]~22.IN1 tracemem_trcdata[14] => tracemem_trcdata[14]~21.IN1 tracemem_trcdata[15] => tracemem_trcdata[15]~20.IN1 tracemem_trcdata[16] => tracemem_trcdata[16]~19.IN1 tracemem_trcdata[17] => tracemem_trcdata[17]~18.IN1 tracemem_trcdata[18] => tracemem_trcdata[18]~17.IN1 tracemem_trcdata[19] => tracemem_trcdata[19]~16.IN1 tracemem_trcdata[20] => tracemem_trcdata[20]~15.IN1 tracemem_trcdata[21] => tracemem_trcdata[21]~14.IN1 tracemem_trcdata[22] => tracemem_trcdata[22]~13.IN1 tracemem_trcdata[23] => tracemem_trcdata[23]~12.IN1 tracemem_trcdata[24] => tracemem_trcdata[24]~11.IN1 tracemem_trcdata[25] => tracemem_trcdata[25]~10.IN1 tracemem_trcdata[26] => tracemem_trcdata[26]~9.IN1 tracemem_trcdata[27] => tracemem_trcdata[27]~8.IN1 tracemem_trcdata[28] => tracemem_trcdata[28]~7.IN1 tracemem_trcdata[29] => tracemem_trcdata[29]~6.IN1 tracemem_trcdata[30] => tracemem_trcdata[30]~5.IN1 tracemem_trcdata[31] => tracemem_trcdata[31]~4.IN1 tracemem_trcdata[32] => tracemem_trcdata[32]~3.IN1 tracemem_trcdata[33] => tracemem_trcdata[33]~2.IN1 tracemem_trcdata[34] => tracemem_trcdata[34]~1.IN1 tracemem_trcdata[35] => tracemem_trcdata[35]~0.IN1 tracemem_tw => tracemem_tw~0.IN1 trc_im_addr[0] => trc_im_addr[0]~6.IN1 trc_im_addr[1] => trc_im_addr[1]~5.IN1 trc_im_addr[2] => trc_im_addr[2]~4.IN1 trc_im_addr[3] => trc_im_addr[3]~3.IN1 trc_im_addr[4] => trc_im_addr[4]~2.IN1 trc_im_addr[5] => trc_im_addr[5]~1.IN1 trc_im_addr[6] => trc_im_addr[6]~0.IN1 trc_on => trc_on~0.IN1 trc_wrap => trc_wrap~0.IN1 trigbrktype => trigbrktype~0.IN1 trigger_state_1 => trigger_state_1~0.IN1 jdo[0] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[1] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[2] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[3] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[4] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[5] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[6] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[7] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[8] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[9] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[10] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[11] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[12] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[13] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[14] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[15] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[16] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[17] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[18] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[19] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[20] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[21] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[22] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[23] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[24] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[25] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[26] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[27] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[28] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[29] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[30] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[31] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[32] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[33] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[34] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[35] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[36] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jdo[37] <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jdo jrst_n <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.jrst_n st_ready_test_idle <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.st_ready_test_idle take_action_break_a <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.take_action_break_a take_action_break_b <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.take_action_break_b take_action_break_c <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.take_action_break_c take_action_ocimem_a <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.take_action_ocimem_a take_action_ocimem_b <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.take_action_ocimem_b take_action_tracectrl <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.take_action_tracectrl take_action_tracemem_a <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.take_action_tracemem_a take_action_tracemem_b <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.take_action_tracemem_b take_no_action_break_a <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.take_no_action_break_a take_no_action_break_b <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.take_no_action_break_b take_no_action_break_c <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.take_no_action_break_c take_no_action_ocimem_a <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.take_no_action_ocimem_a take_no_action_tracemem_a <= cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1.take_no_action_tracemem_a |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1 MonDReg[0] => Mux36.IN0 MonDReg[1] => Mux35.IN0 MonDReg[2] => Mux34.IN0 MonDReg[3] => Mux33.IN0 MonDReg[4] => Mux32.IN0 MonDReg[5] => Mux31.IN0 MonDReg[6] => Mux30.IN0 MonDReg[7] => Mux29.IN0 MonDReg[8] => Mux28.IN1 MonDReg[9] => Mux27.IN1 MonDReg[10] => Mux26.IN1 MonDReg[11] => Mux25.IN1 MonDReg[12] => Mux24.IN1 MonDReg[13] => Mux23.IN1 MonDReg[14] => Mux22.IN1 MonDReg[15] => Mux21.IN0 MonDReg[16] => Mux20.IN0 MonDReg[17] => Mux19.IN0 MonDReg[18] => Mux18.IN0 MonDReg[19] => Mux17.IN0 MonDReg[20] => Mux16.IN0 MonDReg[21] => Mux15.IN0 MonDReg[22] => Mux14.IN0 MonDReg[23] => Mux13.IN0 MonDReg[24] => Mux12.IN0 MonDReg[25] => Mux11.IN0 MonDReg[26] => Mux10.IN0 MonDReg[27] => Mux9.IN0 MonDReg[28] => Mux8.IN0 MonDReg[29] => Mux7.IN0 MonDReg[30] => Mux6.IN0 MonDReg[31] => Mux5.IN0 break_readreg[0] => Mux36.IN1 break_readreg[1] => Mux35.IN1 break_readreg[2] => Mux34.IN1 break_readreg[3] => Mux33.IN1 break_readreg[4] => Mux32.IN1 break_readreg[5] => Mux31.IN1 break_readreg[6] => Mux30.IN1 break_readreg[7] => Mux29.IN1 break_readreg[8] => Mux28.IN2 break_readreg[9] => Mux27.IN2 break_readreg[10] => Mux26.IN2 break_readreg[11] => Mux25.IN2 break_readreg[12] => Mux24.IN2 break_readreg[13] => Mux23.IN2 break_readreg[14] => Mux22.IN2 break_readreg[15] => Mux21.IN1 break_readreg[16] => Mux20.IN1 break_readreg[17] => Mux19.IN1 break_readreg[18] => Mux18.IN1 break_readreg[19] => Mux17.IN1 break_readreg[20] => Mux16.IN1 break_readreg[21] => Mux15.IN1 break_readreg[22] => Mux14.IN1 break_readreg[23] => Mux13.IN1 break_readreg[24] => Mux12.IN1 break_readreg[25] => Mux11.IN1 break_readreg[26] => Mux10.IN1 break_readreg[27] => Mux9.IN1 break_readreg[28] => Mux8.IN1 break_readreg[29] => Mux7.IN1 break_readreg[30] => Mux6.IN1 break_readreg[31] => Mux5.IN1 clk => dr_update1.CLK clk => dr_update2.CLK clk => jxdr.CLK clrn => jrst_n.DATAIN clrn => in_between_shiftdr_and_updatedr.ACLR clrn => ir_out[0]~reg0.ACLR clrn => ir_out[1]~reg0.ACLR clrn => sr[37].ACLR clrn => sr[36].ACLR clrn => sr[35].ACLR clrn => sr[34].ACLR clrn => sr[33].ACLR clrn => sr[32].ACLR clrn => sr[31].ACLR clrn => sr[30].ACLR clrn => sr[29].ACLR clrn => sr[28].ACLR clrn => sr[27].ACLR clrn => sr[26].ACLR clrn => sr[25].ACLR clrn => sr[24].ACLR clrn => sr[23].ACLR clrn => sr[22].ACLR clrn => sr[21].ACLR clrn => sr[20].ACLR clrn => sr[19].ACLR clrn => sr[18].ACLR clrn => sr[17].ACLR clrn => sr[16].ACLR clrn => sr[15].ACLR clrn => sr[14].ACLR clrn => sr[13].ACLR clrn => sr[12].ACLR clrn => sr[11].ACLR clrn => sr[10].ACLR clrn => sr[9].ACLR clrn => sr[8].ACLR clrn => sr[7].ACLR clrn => sr[6].ACLR clrn => sr[5].ACLR clrn => sr[4].ACLR clrn => sr[3].ACLR clrn => sr[2].ACLR clrn => sr[1].ACLR clrn => sr[0].ACLR clrn => ir[1].ENA clrn => ir[0].ENA clrn => DRsize~8.IN1 dbrk_hit0_latch => Mux4.IN0 dbrk_hit1_latch => Mux3.IN0 dbrk_hit2_latch => Mux2.IN0 dbrk_hit3_latch => Mux1.IN0 debugack => ir_out[1]~reg0.DATAIN debugack => Mux2.IN1 ena => always4~0.IN1 ena => always3~0.IN1 ena => always2~4.IN0 ena => always2~1.IN0 ir_in[0] => ir~1.DATAB ir_in[0] => Decoder0.IN1 ir_in[1] => ir~0.DATAB ir_in[1] => Decoder0.IN0 monitor_error => Mux3.IN1 monitor_ready => ir_out[0]~reg0.DATAIN monitor_ready => Mux37.IN0 raw_tck => ir_out[1]~reg0.CLK raw_tck => ir_out[0]~reg0.CLK raw_tck => sr[37].CLK raw_tck => sr[36].CLK raw_tck => sr[35].CLK raw_tck => sr[34].CLK raw_tck => sr[33].CLK raw_tck => sr[32].CLK raw_tck => sr[31].CLK raw_tck => sr[30].CLK raw_tck => sr[29].CLK raw_tck => sr[28].CLK raw_tck => sr[27].CLK raw_tck => sr[26].CLK raw_tck => sr[25].CLK raw_tck => sr[24].CLK raw_tck => sr[23].CLK raw_tck => sr[22].CLK raw_tck => sr[21].CLK raw_tck => sr[20].CLK raw_tck => sr[19].CLK raw_tck => sr[18].CLK raw_tck => sr[17].CLK raw_tck => sr[16].CLK raw_tck => sr[15].CLK raw_tck => sr[14].CLK raw_tck => sr[13].CLK raw_tck => sr[12].CLK raw_tck => sr[11].CLK raw_tck => sr[10].CLK raw_tck => sr[9].CLK raw_tck => sr[8].CLK raw_tck => sr[7].CLK raw_tck => sr[6].CLK raw_tck => sr[5].CLK raw_tck => sr[4].CLK raw_tck => sr[3].CLK raw_tck => sr[2].CLK raw_tck => sr[1].CLK raw_tck => sr[0].CLK raw_tck => ir[1].CLK raw_tck => ir[0].CLK raw_tck => st_shiftdr.CLK raw_tck => st_updateir.CLK raw_tck => st_updatedr.CLK raw_tck => in_between_shiftdr_and_updatedr.CLK raw_tck => DRsize~7.IN1 reset_n => ~NO_FANOUT~ resetlatch => Mux4.IN1 rti => st_ready_test_idle.DATAIN shift => always2~3.IN1 shift => always2~0.IN1 tdi => sr~5.DATAB tdi => sr~4.DATAB tdi => sr~3.DATAB tdi => sr~2.DATAB tdi => sr~1.DATAB tdi => sr~0.DATAB tracemem_on => Mux1.IN1 tracemem_trcdata[0] => Mux37.IN1 tracemem_trcdata[1] => Mux36.IN2 tracemem_trcdata[2] => Mux35.IN2 tracemem_trcdata[3] => Mux34.IN2 tracemem_trcdata[4] => Mux33.IN2 tracemem_trcdata[5] => Mux32.IN2 tracemem_trcdata[6] => Mux31.IN2 tracemem_trcdata[7] => Mux30.IN2 tracemem_trcdata[8] => Mux29.IN2 tracemem_trcdata[9] => Mux28.IN3 tracemem_trcdata[10] => Mux27.IN3 tracemem_trcdata[11] => Mux26.IN3 tracemem_trcdata[12] => Mux25.IN3 tracemem_trcdata[13] => Mux24.IN3 tracemem_trcdata[14] => Mux23.IN3 tracemem_trcdata[15] => Mux22.IN3 tracemem_trcdata[16] => Mux21.IN2 tracemem_trcdata[17] => Mux20.IN2 tracemem_trcdata[18] => Mux19.IN2 tracemem_trcdata[19] => Mux18.IN2 tracemem_trcdata[20] => Mux17.IN2 tracemem_trcdata[21] => Mux16.IN2 tracemem_trcdata[22] => Mux15.IN2 tracemem_trcdata[23] => Mux14.IN2 tracemem_trcdata[24] => Mux13.IN2 tracemem_trcdata[25] => Mux12.IN2 tracemem_trcdata[26] => Mux11.IN2 tracemem_trcdata[27] => Mux10.IN2 tracemem_trcdata[28] => Mux9.IN2 tracemem_trcdata[29] => Mux8.IN2 tracemem_trcdata[30] => Mux7.IN2 tracemem_trcdata[31] => Mux6.IN2 tracemem_trcdata[32] => Mux5.IN2 tracemem_trcdata[33] => Mux4.IN2 tracemem_trcdata[34] => Mux3.IN2 tracemem_trcdata[35] => Mux2.IN2 tracemem_tw => Mux0.IN0 trc_im_addr[0] => Mux35.IN3 trc_im_addr[1] => Mux34.IN3 trc_im_addr[2] => Mux33.IN3 trc_im_addr[3] => Mux32.IN3 trc_im_addr[4] => Mux31.IN3 trc_im_addr[5] => Mux30.IN3 trc_im_addr[6] => Mux29.IN3 trc_on => Mux37.IN2 trc_wrap => Mux36.IN3 trigbrktype => Mux37.IN3 trigger_state_1 => Mux0.IN1 update => jdo[37]~reg0.CLK update => jdo[36]~reg0.CLK update => jdo[35]~reg0.CLK update => jdo[34]~reg0.CLK update => jdo[33]~reg0.CLK update => jdo[32]~reg0.CLK update => jdo[31]~reg0.CLK update => jdo[30]~reg0.CLK update => jdo[29]~reg0.CLK update => jdo[28]~reg0.CLK update => jdo[27]~reg0.CLK update => jdo[26]~reg0.CLK update => jdo[25]~reg0.CLK update => jdo[24]~reg0.CLK update => jdo[23]~reg0.CLK update => jdo[22]~reg0.CLK update => jdo[21]~reg0.CLK update => jdo[20]~reg0.CLK update => jdo[19]~reg0.CLK update => jdo[18]~reg0.CLK update => jdo[17]~reg0.CLK update => jdo[16]~reg0.CLK update => jdo[15]~reg0.CLK update => jdo[14]~reg0.CLK update => jdo[13]~reg0.CLK update => jdo[12]~reg0.CLK update => jdo[11]~reg0.CLK update => jdo[10]~reg0.CLK update => jdo[9]~reg0.CLK update => jdo[8]~reg0.CLK update => jdo[7]~reg0.CLK update => jdo[6]~reg0.CLK update => jdo[5]~reg0.CLK update => jdo[4]~reg0.CLK update => jdo[3]~reg0.CLK update => jdo[2]~reg0.CLK update => jdo[1]~reg0.CLK update => jdo[0]~reg0.CLK update => st_shiftdr.ACLR update => st_updateir.ALOAD update => st_updatedr.ALOAD usr1 => always4~0.IN0 usr1 => always2~0.IN0 usr1 => always2~3.IN0 usr1 => always3~0.IN0 ir_out[0] <= ir_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE ir_out[1] <= ir_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE irq <= jdo[0] <= jdo[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[1] <= jdo[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[2] <= jdo[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[3] <= jdo[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[4] <= jdo[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[5] <= jdo[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[6] <= jdo[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[7] <= jdo[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[8] <= jdo[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[9] <= jdo[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[10] <= jdo[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[11] <= jdo[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[12] <= jdo[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[13] <= jdo[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[14] <= jdo[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[15] <= jdo[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[16] <= jdo[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[17] <= jdo[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[18] <= jdo[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[19] <= jdo[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[20] <= jdo[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[21] <= jdo[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[22] <= jdo[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[23] <= jdo[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[24] <= jdo[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[25] <= jdo[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[26] <= jdo[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[27] <= jdo[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[28] <= jdo[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[29] <= jdo[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[30] <= jdo[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[31] <= jdo[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[32] <= jdo[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[33] <= jdo[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[34] <= jdo[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[35] <= jdo[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[36] <= jdo[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE jdo[37] <= jdo[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE jrst_n <= clrn.DB_MAX_OUTPUT_PORT_TYPE st_ready_test_idle <= rti.DB_MAX_OUTPUT_PORT_TYPE take_action_break_a <= take_action_break_a~2.DB_MAX_OUTPUT_PORT_TYPE take_action_break_b <= take_action_break_b~2.DB_MAX_OUTPUT_PORT_TYPE take_action_break_c <= take_action_break_c~1.DB_MAX_OUTPUT_PORT_TYPE take_action_ocimem_a <= take_action_ocimem_a~2.DB_MAX_OUTPUT_PORT_TYPE take_action_ocimem_b <= take_action_ocimem_b~0.DB_MAX_OUTPUT_PORT_TYPE take_action_tracectrl <= take_action_tracectrl~1.DB_MAX_OUTPUT_PORT_TYPE take_action_tracemem_a <= take_action_tracemem_a~2.DB_MAX_OUTPUT_PORT_TYPE take_action_tracemem_b <= take_action_tracemem_b~0.DB_MAX_OUTPUT_PORT_TYPE take_no_action_break_a <= take_no_action_break_a~0.DB_MAX_OUTPUT_PORT_TYPE take_no_action_break_b <= take_no_action_break_b~0.DB_MAX_OUTPUT_PORT_TYPE take_no_action_break_c <= take_no_action_break_c~0.DB_MAX_OUTPUT_PORT_TYPE take_no_action_ocimem_a <= take_no_action_ocimem_a~0.DB_MAX_OUTPUT_PORT_TYPE take_no_action_tracemem_a <= take_no_action_tracemem_a~0.DB_MAX_OUTPUT_PORT_TYPE tdo <= sr[0].DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port clk => d1_reasons_to_wait.CLK clk => epcs_controller_epcs_control_port_arb_share_counter[2].CLK clk => epcs_controller_epcs_control_port_arb_share_counter[1].CLK clk => epcs_controller_epcs_control_port_arb_share_counter[0].CLK clk => epcs_controller_epcs_control_port_slavearbiterlockenable.CLK clk => last_cycle_cpu_0_instruction_master_granted_slave_epcs_controller_epcs_control_port.CLK clk => last_cycle_cpu_0_data_master_granted_slave_epcs_controller_epcs_control_port.CLK clk => epcs_controller_epcs_control_port_saved_chosen_master_vector[1].CLK clk => epcs_controller_epcs_control_port_saved_chosen_master_vector[0].CLK clk => epcs_controller_epcs_control_port_arb_addend[1].CLK clk => epcs_controller_epcs_control_port_arb_addend[0].CLK clk => d1_epcs_controller_epcs_control_port_end_xfer~reg0.CLK cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[2] => epcs_controller_epcs_control_port_address~8.DATAB cpu_0_data_master_address_to_slave[3] => epcs_controller_epcs_control_port_address~7.DATAB cpu_0_data_master_address_to_slave[4] => epcs_controller_epcs_control_port_address~6.DATAB cpu_0_data_master_address_to_slave[5] => epcs_controller_epcs_control_port_address~5.DATAB cpu_0_data_master_address_to_slave[6] => epcs_controller_epcs_control_port_address~4.DATAB cpu_0_data_master_address_to_slave[7] => epcs_controller_epcs_control_port_address~3.DATAB cpu_0_data_master_address_to_slave[8] => epcs_controller_epcs_control_port_address~2.DATAB cpu_0_data_master_address_to_slave[9] => epcs_controller_epcs_control_port_address~1.DATAB cpu_0_data_master_address_to_slave[10] => epcs_controller_epcs_control_port_address~0.DATAB cpu_0_data_master_address_to_slave[11] => Equal0.IN34 cpu_0_data_master_address_to_slave[12] => Equal0.IN9 cpu_0_data_master_address_to_slave[13] => Equal0.IN8 cpu_0_data_master_address_to_slave[14] => Equal0.IN7 cpu_0_data_master_address_to_slave[15] => Equal0.IN6 cpu_0_data_master_address_to_slave[16] => Equal0.IN5 cpu_0_data_master_address_to_slave[17] => Equal0.IN4 cpu_0_data_master_address_to_slave[18] => Equal0.IN3 cpu_0_data_master_address_to_slave[19] => Equal0.IN33 cpu_0_data_master_address_to_slave[20] => Equal0.IN2 cpu_0_data_master_address_to_slave[21] => Equal0.IN1 cpu_0_data_master_address_to_slave[22] => Equal0.IN32 cpu_0_data_master_address_to_slave[23] => Equal0.IN0 cpu_0_data_master_read => epcs_controller_epcs_control_port_in_a_read_cycle~0.IN0 cpu_0_data_master_read => cpu_0_data_master_requests_epcs_controller_epcs_control_port~0.IN0 cpu_0_data_master_write => epcs_controller_epcs_control_port_in_a_write_cycle.IN0 cpu_0_data_master_write => cpu_0_data_master_requests_epcs_controller_epcs_control_port~0.IN1 cpu_0_data_master_writedata[0] => epcs_controller_epcs_control_port_writedata[0].DATAIN cpu_0_data_master_writedata[1] => epcs_controller_epcs_control_port_writedata[1].DATAIN cpu_0_data_master_writedata[2] => epcs_controller_epcs_control_port_writedata[2].DATAIN cpu_0_data_master_writedata[3] => epcs_controller_epcs_control_port_writedata[3].DATAIN cpu_0_data_master_writedata[4] => epcs_controller_epcs_control_port_writedata[4].DATAIN cpu_0_data_master_writedata[5] => epcs_controller_epcs_control_port_writedata[5].DATAIN cpu_0_data_master_writedata[6] => epcs_controller_epcs_control_port_writedata[6].DATAIN cpu_0_data_master_writedata[7] => epcs_controller_epcs_control_port_writedata[7].DATAIN cpu_0_data_master_writedata[8] => epcs_controller_epcs_control_port_writedata[8].DATAIN cpu_0_data_master_writedata[9] => epcs_controller_epcs_control_port_writedata[9].DATAIN cpu_0_data_master_writedata[10] => epcs_controller_epcs_control_port_writedata[10].DATAIN cpu_0_data_master_writedata[11] => epcs_controller_epcs_control_port_writedata[11].DATAIN cpu_0_data_master_writedata[12] => epcs_controller_epcs_control_port_writedata[12].DATAIN cpu_0_data_master_writedata[13] => epcs_controller_epcs_control_port_writedata[13].DATAIN cpu_0_data_master_writedata[14] => epcs_controller_epcs_control_port_writedata[14].DATAIN cpu_0_data_master_writedata[15] => epcs_controller_epcs_control_port_writedata[15].DATAIN cpu_0_data_master_writedata[16] => epcs_controller_epcs_control_port_writedata[16].DATAIN cpu_0_data_master_writedata[17] => epcs_controller_epcs_control_port_writedata[17].DATAIN cpu_0_data_master_writedata[18] => epcs_controller_epcs_control_port_writedata[18].DATAIN cpu_0_data_master_writedata[19] => epcs_controller_epcs_control_port_writedata[19].DATAIN cpu_0_data_master_writedata[20] => epcs_controller_epcs_control_port_writedata[20].DATAIN cpu_0_data_master_writedata[21] => epcs_controller_epcs_control_port_writedata[21].DATAIN cpu_0_data_master_writedata[22] => epcs_controller_epcs_control_port_writedata[22].DATAIN cpu_0_data_master_writedata[23] => epcs_controller_epcs_control_port_writedata[23].DATAIN cpu_0_data_master_writedata[24] => epcs_controller_epcs_control_port_writedata[24].DATAIN cpu_0_data_master_writedata[25] => epcs_controller_epcs_control_port_writedata[25].DATAIN cpu_0_data_master_writedata[26] => epcs_controller_epcs_control_port_writedata[26].DATAIN cpu_0_data_master_writedata[27] => epcs_controller_epcs_control_port_writedata[27].DATAIN cpu_0_data_master_writedata[28] => epcs_controller_epcs_control_port_writedata[28].DATAIN cpu_0_data_master_writedata[29] => epcs_controller_epcs_control_port_writedata[29].DATAIN cpu_0_data_master_writedata[30] => epcs_controller_epcs_control_port_writedata[30].DATAIN cpu_0_data_master_writedata[31] => epcs_controller_epcs_control_port_writedata[31].DATAIN cpu_0_instruction_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_instruction_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_instruction_master_address_to_slave[2] => epcs_controller_epcs_control_port_address~8.DATAA cpu_0_instruction_master_address_to_slave[3] => epcs_controller_epcs_control_port_address~7.DATAA cpu_0_instruction_master_address_to_slave[4] => epcs_controller_epcs_control_port_address~6.DATAA cpu_0_instruction_master_address_to_slave[5] => epcs_controller_epcs_control_port_address~5.DATAA cpu_0_instruction_master_address_to_slave[6] => epcs_controller_epcs_control_port_address~4.DATAA cpu_0_instruction_master_address_to_slave[7] => epcs_controller_epcs_control_port_address~3.DATAA cpu_0_instruction_master_address_to_slave[8] => epcs_controller_epcs_control_port_address~2.DATAA cpu_0_instruction_master_address_to_slave[9] => epcs_controller_epcs_control_port_address~1.DATAA cpu_0_instruction_master_address_to_slave[10] => epcs_controller_epcs_control_port_address~0.DATAA cpu_0_instruction_master_address_to_slave[11] => Equal1.IN34 cpu_0_instruction_master_address_to_slave[12] => Equal1.IN9 cpu_0_instruction_master_address_to_slave[13] => Equal1.IN8 cpu_0_instruction_master_address_to_slave[14] => Equal1.IN7 cpu_0_instruction_master_address_to_slave[15] => Equal1.IN6 cpu_0_instruction_master_address_to_slave[16] => Equal1.IN5 cpu_0_instruction_master_address_to_slave[17] => Equal1.IN4 cpu_0_instruction_master_address_to_slave[18] => Equal1.IN3 cpu_0_instruction_master_address_to_slave[19] => Equal1.IN33 cpu_0_instruction_master_address_to_slave[20] => Equal1.IN2 cpu_0_instruction_master_address_to_slave[21] => Equal1.IN1 cpu_0_instruction_master_address_to_slave[22] => Equal1.IN32 cpu_0_instruction_master_address_to_slave[23] => Equal1.IN0 cpu_0_instruction_master_latency_counter[0] => Equal2.IN31 cpu_0_instruction_master_latency_counter[1] => Equal2.IN30 cpu_0_instruction_master_read => epcs_controller_epcs_control_port_in_a_read_cycle~1.IN0 cpu_0_instruction_master_read => cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port~1.IN0 cpu_0_instruction_master_read => cpu_0_instruction_master_requests_epcs_controller_epcs_control_port~1.IN0 cpu_0_instruction_master_read => cpu_0_instruction_master_requests_epcs_controller_epcs_control_port~0.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register => cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port~0.IN1 epcs_controller_epcs_control_port_dataavailable => epcs_controller_epcs_control_port_dataavailable_from_sa.DATAIN epcs_controller_epcs_control_port_endofpacket => epcs_controller_epcs_control_port_endofpacket_from_sa.DATAIN epcs_controller_epcs_control_port_irq => epcs_controller_epcs_control_port_irq_from_sa.DATAIN epcs_controller_epcs_control_port_readdata[0] => epcs_controller_epcs_control_port_readdata_from_sa[0].DATAIN epcs_controller_epcs_control_port_readdata[1] => epcs_controller_epcs_control_port_readdata_from_sa[1].DATAIN epcs_controller_epcs_control_port_readdata[2] => epcs_controller_epcs_control_port_readdata_from_sa[2].DATAIN epcs_controller_epcs_control_port_readdata[3] => epcs_controller_epcs_control_port_readdata_from_sa[3].DATAIN epcs_controller_epcs_control_port_readdata[4] => epcs_controller_epcs_control_port_readdata_from_sa[4].DATAIN epcs_controller_epcs_control_port_readdata[5] => epcs_controller_epcs_control_port_readdata_from_sa[5].DATAIN epcs_controller_epcs_control_port_readdata[6] => epcs_controller_epcs_control_port_readdata_from_sa[6].DATAIN epcs_controller_epcs_control_port_readdata[7] => epcs_controller_epcs_control_port_readdata_from_sa[7].DATAIN epcs_controller_epcs_control_port_readdata[8] => epcs_controller_epcs_control_port_readdata_from_sa[8].DATAIN epcs_controller_epcs_control_port_readdata[9] => epcs_controller_epcs_control_port_readdata_from_sa[9].DATAIN epcs_controller_epcs_control_port_readdata[10] => epcs_controller_epcs_control_port_readdata_from_sa[10].DATAIN epcs_controller_epcs_control_port_readdata[11] => epcs_controller_epcs_control_port_readdata_from_sa[11].DATAIN epcs_controller_epcs_control_port_readdata[12] => epcs_controller_epcs_control_port_readdata_from_sa[12].DATAIN epcs_controller_epcs_control_port_readdata[13] => epcs_controller_epcs_control_port_readdata_from_sa[13].DATAIN epcs_controller_epcs_control_port_readdata[14] => epcs_controller_epcs_control_port_readdata_from_sa[14].DATAIN epcs_controller_epcs_control_port_readdata[15] => epcs_controller_epcs_control_port_readdata_from_sa[15].DATAIN epcs_controller_epcs_control_port_readdata[16] => epcs_controller_epcs_control_port_readdata_from_sa[16].DATAIN epcs_controller_epcs_control_port_readdata[17] => epcs_controller_epcs_control_port_readdata_from_sa[17].DATAIN epcs_controller_epcs_control_port_readdata[18] => epcs_controller_epcs_control_port_readdata_from_sa[18].DATAIN epcs_controller_epcs_control_port_readdata[19] => epcs_controller_epcs_control_port_readdata_from_sa[19].DATAIN epcs_controller_epcs_control_port_readdata[20] => epcs_controller_epcs_control_port_readdata_from_sa[20].DATAIN epcs_controller_epcs_control_port_readdata[21] => epcs_controller_epcs_control_port_readdata_from_sa[21].DATAIN epcs_controller_epcs_control_port_readdata[22] => epcs_controller_epcs_control_port_readdata_from_sa[22].DATAIN epcs_controller_epcs_control_port_readdata[23] => epcs_controller_epcs_control_port_readdata_from_sa[23].DATAIN epcs_controller_epcs_control_port_readdata[24] => epcs_controller_epcs_control_port_readdata_from_sa[24].DATAIN epcs_controller_epcs_control_port_readdata[25] => epcs_controller_epcs_control_port_readdata_from_sa[25].DATAIN epcs_controller_epcs_control_port_readdata[26] => epcs_controller_epcs_control_port_readdata_from_sa[26].DATAIN epcs_controller_epcs_control_port_readdata[27] => epcs_controller_epcs_control_port_readdata_from_sa[27].DATAIN epcs_controller_epcs_control_port_readdata[28] => epcs_controller_epcs_control_port_readdata_from_sa[28].DATAIN epcs_controller_epcs_control_port_readdata[29] => epcs_controller_epcs_control_port_readdata_from_sa[29].DATAIN epcs_controller_epcs_control_port_readdata[30] => epcs_controller_epcs_control_port_readdata_from_sa[30].DATAIN epcs_controller_epcs_control_port_readdata[31] => epcs_controller_epcs_control_port_readdata_from_sa[31].DATAIN epcs_controller_epcs_control_port_readyfordata => epcs_controller_epcs_control_port_readyfordata_from_sa.DATAIN reset_n => epcs_controller_epcs_control_port_reset_n.DATAIN reset_n => epcs_controller_epcs_control_port_arb_addend[0].PRESET reset_n => epcs_controller_epcs_control_port_arb_addend[1].ACLR reset_n => epcs_controller_epcs_control_port_saved_chosen_master_vector[0].ACLR reset_n => epcs_controller_epcs_control_port_saved_chosen_master_vector[1].ACLR reset_n => last_cycle_cpu_0_data_master_granted_slave_epcs_controller_epcs_control_port.ACLR reset_n => last_cycle_cpu_0_instruction_master_granted_slave_epcs_controller_epcs_control_port.ACLR reset_n => epcs_controller_epcs_control_port_slavearbiterlockenable.ACLR reset_n => epcs_controller_epcs_control_port_arb_share_counter[0].ACLR reset_n => epcs_controller_epcs_control_port_arb_share_counter[1].ACLR reset_n => epcs_controller_epcs_control_port_arb_share_counter[2].ACLR reset_n => d1_reasons_to_wait.ACLR reset_n => d1_epcs_controller_epcs_control_port_end_xfer~reg0.PRESET cpu_0_data_master_granted_epcs_controller_epcs_control_port <= epcs_controller_epcs_control_port_grant_vector[1].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_qualified_request_epcs_controller_epcs_control_port <= cpu_0_data_master_qualified_request_epcs_controller_epcs_control_port~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_read_data_valid_epcs_controller_epcs_control_port <= cpu_0_data_master_requests_epcs_controller_epcs_control_port <= cpu_0_data_master_requests_epcs_controller_epcs_control_port~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_granted_epcs_controller_epcs_control_port <= epcs_controller_epcs_control_port_grant_vector~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port <= cpu_0_instruction_master_qualified_request_epcs_controller_epcs_control_port~3.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_read_data_valid_epcs_controller_epcs_control_port <= cpu_0_instruction_master_read_data_valid_epcs_controller_epcs_control_port~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_requests_epcs_controller_epcs_control_port <= cpu_0_instruction_master_requests_epcs_controller_epcs_control_port~1.DB_MAX_OUTPUT_PORT_TYPE d1_epcs_controller_epcs_control_port_end_xfer <= d1_epcs_controller_epcs_control_port_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_address[0] <= epcs_controller_epcs_control_port_address~8.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_address[1] <= epcs_controller_epcs_control_port_address~7.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_address[2] <= epcs_controller_epcs_control_port_address~6.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_address[3] <= epcs_controller_epcs_control_port_address~5.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_address[4] <= epcs_controller_epcs_control_port_address~4.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_address[5] <= epcs_controller_epcs_control_port_address~3.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_address[6] <= epcs_controller_epcs_control_port_address~2.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_address[7] <= epcs_controller_epcs_control_port_address~1.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_address[8] <= epcs_controller_epcs_control_port_address~0.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_chipselect <= epcs_controller_epcs_control_port_chipselect~0.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_dataavailable_from_sa <= epcs_controller_epcs_control_port_dataavailable.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_endofpacket_from_sa <= epcs_controller_epcs_control_port_endofpacket.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_irq_from_sa <= epcs_controller_epcs_control_port_irq.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_read_n <= epcs_controller_epcs_control_port_in_a_read_cycle.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[0] <= epcs_controller_epcs_control_port_readdata[0].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[1] <= epcs_controller_epcs_control_port_readdata[1].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[2] <= epcs_controller_epcs_control_port_readdata[2].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[3] <= epcs_controller_epcs_control_port_readdata[3].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[4] <= epcs_controller_epcs_control_port_readdata[4].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[5] <= epcs_controller_epcs_control_port_readdata[5].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[6] <= epcs_controller_epcs_control_port_readdata[6].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[7] <= epcs_controller_epcs_control_port_readdata[7].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[8] <= epcs_controller_epcs_control_port_readdata[8].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[9] <= epcs_controller_epcs_control_port_readdata[9].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[10] <= epcs_controller_epcs_control_port_readdata[10].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[11] <= epcs_controller_epcs_control_port_readdata[11].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[12] <= epcs_controller_epcs_control_port_readdata[12].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[13] <= epcs_controller_epcs_control_port_readdata[13].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[14] <= epcs_controller_epcs_control_port_readdata[14].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[15] <= epcs_controller_epcs_control_port_readdata[15].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[16] <= epcs_controller_epcs_control_port_readdata[16].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[17] <= epcs_controller_epcs_control_port_readdata[17].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[18] <= epcs_controller_epcs_control_port_readdata[18].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[19] <= epcs_controller_epcs_control_port_readdata[19].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[20] <= epcs_controller_epcs_control_port_readdata[20].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[21] <= epcs_controller_epcs_control_port_readdata[21].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[22] <= epcs_controller_epcs_control_port_readdata[22].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[23] <= epcs_controller_epcs_control_port_readdata[23].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[24] <= epcs_controller_epcs_control_port_readdata[24].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[25] <= epcs_controller_epcs_control_port_readdata[25].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[26] <= epcs_controller_epcs_control_port_readdata[26].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[27] <= epcs_controller_epcs_control_port_readdata[27].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[28] <= epcs_controller_epcs_control_port_readdata[28].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[29] <= epcs_controller_epcs_control_port_readdata[29].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[30] <= epcs_controller_epcs_control_port_readdata[30].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readdata_from_sa[31] <= epcs_controller_epcs_control_port_readdata[31].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_readyfordata_from_sa <= epcs_controller_epcs_control_port_readyfordata.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_reset_n <= reset_n.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_write_n <= epcs_controller_epcs_control_port_in_a_write_cycle.DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[0] <= cpu_0_data_master_writedata[0].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[1] <= cpu_0_data_master_writedata[1].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[2] <= cpu_0_data_master_writedata[2].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[3] <= cpu_0_data_master_writedata[3].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[4] <= cpu_0_data_master_writedata[4].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[5] <= cpu_0_data_master_writedata[5].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[6] <= cpu_0_data_master_writedata[6].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[7] <= cpu_0_data_master_writedata[7].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[8] <= cpu_0_data_master_writedata[8].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[9] <= cpu_0_data_master_writedata[9].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[10] <= cpu_0_data_master_writedata[10].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[11] <= cpu_0_data_master_writedata[11].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[12] <= cpu_0_data_master_writedata[12].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[13] <= cpu_0_data_master_writedata[13].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[14] <= cpu_0_data_master_writedata[14].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[15] <= cpu_0_data_master_writedata[15].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[16] <= cpu_0_data_master_writedata[16].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[17] <= cpu_0_data_master_writedata[17].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[18] <= cpu_0_data_master_writedata[18].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[19] <= cpu_0_data_master_writedata[19].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[20] <= cpu_0_data_master_writedata[20].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[21] <= cpu_0_data_master_writedata[21].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[22] <= cpu_0_data_master_writedata[22].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[23] <= cpu_0_data_master_writedata[23].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[24] <= cpu_0_data_master_writedata[24].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[25] <= cpu_0_data_master_writedata[25].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[26] <= cpu_0_data_master_writedata[26].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[27] <= cpu_0_data_master_writedata[27].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[28] <= cpu_0_data_master_writedata[28].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[29] <= cpu_0_data_master_writedata[29].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[30] <= cpu_0_data_master_writedata[30].DB_MAX_OUTPUT_PORT_TYPE epcs_controller_epcs_control_port_writedata[31] <= cpu_0_data_master_writedata[31].DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|epcs_controller:the_epcs_controller address[0] => mem_addr[0].IN2 address[1] => mem_addr[1].IN2 address[2] => mem_addr[2].IN2 address[3] => address[3]~3.IN1 address[4] => address[4]~2.IN1 address[5] => address[5]~1.IN1 address[6] => address[6]~0.IN1 address[7] => epcs_select~0.IN0 address[8] => ~NO_FANOUT~ chipselect => epcs_select~0.IN1 clk => clk~0.IN2 read_n => read_n~0.IN1 reset_n => reset_n~0.IN1 write_n => write_n~0.IN1 writedata[0] => data_from_cpu[0].IN1 writedata[1] => data_from_cpu[1].IN1 writedata[2] => data_from_cpu[2].IN1 writedata[3] => data_from_cpu[3].IN1 writedata[4] => data_from_cpu[4].IN1 writedata[5] => data_from_cpu[5].IN1 writedata[6] => data_from_cpu[6].IN1 writedata[7] => data_from_cpu[7].IN1 writedata[8] => data_from_cpu[8].IN1 writedata[9] => data_from_cpu[9].IN1 writedata[10] => data_from_cpu[10].IN1 writedata[11] => data_from_cpu[11].IN1 writedata[12] => data_from_cpu[12].IN1 writedata[13] => data_from_cpu[13].IN1 writedata[14] => data_from_cpu[14].IN1 writedata[15] => data_from_cpu[15].IN1 writedata[16] => ~NO_FANOUT~ writedata[17] => ~NO_FANOUT~ writedata[18] => ~NO_FANOUT~ writedata[19] => ~NO_FANOUT~ writedata[20] => ~NO_FANOUT~ writedata[21] => ~NO_FANOUT~ writedata[22] => ~NO_FANOUT~ writedata[23] => ~NO_FANOUT~ writedata[24] => ~NO_FANOUT~ writedata[25] => ~NO_FANOUT~ writedata[26] => ~NO_FANOUT~ writedata[27] => ~NO_FANOUT~ writedata[28] => ~NO_FANOUT~ writedata[29] => ~NO_FANOUT~ writedata[30] => ~NO_FANOUT~ writedata[31] => ~NO_FANOUT~ dataavailable <= epcs_controller_sub:the_epcs_controller_sub.dataavailable endofpacket <= epcs_controller_sub:the_epcs_controller_sub.endofpacket irq <= epcs_controller_sub:the_epcs_controller_sub.irq readdata[0] <= readdata~31.DB_MAX_OUTPUT_PORT_TYPE readdata[1] <= readdata~30.DB_MAX_OUTPUT_PORT_TYPE readdata[2] <= readdata~29.DB_MAX_OUTPUT_PORT_TYPE readdata[3] <= readdata~28.DB_MAX_OUTPUT_PORT_TYPE readdata[4] <= readdata~27.DB_MAX_OUTPUT_PORT_TYPE readdata[5] <= readdata~26.DB_MAX_OUTPUT_PORT_TYPE readdata[6] <= readdata~25.DB_MAX_OUTPUT_PORT_TYPE readdata[7] <= readdata~24.DB_MAX_OUTPUT_PORT_TYPE readdata[8] <= readdata~23.DB_MAX_OUTPUT_PORT_TYPE readdata[9] <= readdata~22.DB_MAX_OUTPUT_PORT_TYPE readdata[10] <= readdata~21.DB_MAX_OUTPUT_PORT_TYPE readdata[11] <= readdata~20.DB_MAX_OUTPUT_PORT_TYPE readdata[12] <= readdata~19.DB_MAX_OUTPUT_PORT_TYPE readdata[13] <= readdata~18.DB_MAX_OUTPUT_PORT_TYPE readdata[14] <= readdata~17.DB_MAX_OUTPUT_PORT_TYPE readdata[15] <= readdata~16.DB_MAX_OUTPUT_PORT_TYPE readdata[16] <= readdata~15.DB_MAX_OUTPUT_PORT_TYPE readdata[17] <= readdata~14.DB_MAX_OUTPUT_PORT_TYPE readdata[18] <= readdata~13.DB_MAX_OUTPUT_PORT_TYPE readdata[19] <= readdata~12.DB_MAX_OUTPUT_PORT_TYPE readdata[20] <= readdata~11.DB_MAX_OUTPUT_PORT_TYPE readdata[21] <= readdata~10.DB_MAX_OUTPUT_PORT_TYPE readdata[22] <= readdata~9.DB_MAX_OUTPUT_PORT_TYPE readdata[23] <= readdata~8.DB_MAX_OUTPUT_PORT_TYPE readdata[24] <= readdata~7.DB_MAX_OUTPUT_PORT_TYPE readdata[25] <= readdata~6.DB_MAX_OUTPUT_PORT_TYPE readdata[26] <= readdata~5.DB_MAX_OUTPUT_PORT_TYPE readdata[27] <= readdata~4.DB_MAX_OUTPUT_PORT_TYPE readdata[28] <= readdata~3.DB_MAX_OUTPUT_PORT_TYPE readdata[29] <= readdata~2.DB_MAX_OUTPUT_PORT_TYPE readdata[30] <= readdata~1.DB_MAX_OUTPUT_PORT_TYPE readdata[31] <= readdata~0.DB_MAX_OUTPUT_PORT_TYPE readyfordata <= epcs_controller_sub:the_epcs_controller_sub.readyfordata |DE1_NIOS|system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub MISO => MISO_reg~0.DATAA clk => rd_strobe.CLK clk => data_rd_strobe.CLK clk => wr_strobe.CLK clk => data_wr_strobe.CLK clk => iEOP_reg.CLK clk => iE_reg.CLK clk => iRRDY_reg.CLK clk => iTRDY_reg.CLK clk => iTOE_reg.CLK clk => iROE_reg.CLK clk => SSO_reg.CLK clk => irq_reg.CLK clk => epcs_slave_select_reg[15].CLK clk => epcs_slave_select_reg[14].CLK clk => epcs_slave_select_reg[13].CLK clk => epcs_slave_select_reg[12].CLK clk => epcs_slave_select_reg[11].CLK clk => epcs_slave_select_reg[10].CLK clk => epcs_slave_select_reg[9].CLK clk => epcs_slave_select_reg[8].CLK clk => epcs_slave_select_reg[7].CLK clk => epcs_slave_select_reg[6].CLK clk => epcs_slave_select_reg[5].CLK clk => epcs_slave_select_reg[4].CLK clk => epcs_slave_select_reg[3].CLK clk => epcs_slave_select_reg[2].CLK clk => epcs_slave_select_reg[1].CLK clk => epcs_slave_select_reg[0].CLK clk => epcs_slave_select_holding_reg[15].CLK clk => epcs_slave_select_holding_reg[14].CLK clk => epcs_slave_select_holding_reg[13].CLK clk => epcs_slave_select_holding_reg[12].CLK clk => epcs_slave_select_holding_reg[11].CLK clk => epcs_slave_select_holding_reg[10].CLK clk => epcs_slave_select_holding_reg[9].CLK clk => epcs_slave_select_holding_reg[8].CLK clk => epcs_slave_select_holding_reg[7].CLK clk => epcs_slave_select_holding_reg[6].CLK clk => epcs_slave_select_holding_reg[5].CLK clk => epcs_slave_select_holding_reg[4].CLK clk => epcs_slave_select_holding_reg[3].CLK clk => epcs_slave_select_holding_reg[2].CLK clk => epcs_slave_select_holding_reg[1].CLK clk => epcs_slave_select_holding_reg[0].CLK clk => slowcount[1].CLK clk => slowcount[0].CLK clk => endofpacketvalue_reg[15].CLK clk => endofpacketvalue_reg[14].CLK clk => endofpacketvalue_reg[13].CLK clk => endofpacketvalue_reg[12].CLK clk => endofpacketvalue_reg[11].CLK clk => endofpacketvalue_reg[10].CLK clk => endofpacketvalue_reg[9].CLK clk => endofpacketvalue_reg[8].CLK clk => endofpacketvalue_reg[7].CLK clk => endofpacketvalue_reg[6].CLK clk => endofpacketvalue_reg[5].CLK clk => endofpacketvalue_reg[4].CLK clk => endofpacketvalue_reg[3].CLK clk => endofpacketvalue_reg[2].CLK clk => endofpacketvalue_reg[1].CLK clk => endofpacketvalue_reg[0].CLK clk => data_to_cpu[15]~reg0.CLK clk => data_to_cpu[14]~reg0.CLK clk => data_to_cpu[13]~reg0.CLK clk => data_to_cpu[12]~reg0.CLK clk => data_to_cpu[11]~reg0.CLK clk => data_to_cpu[10]~reg0.CLK clk => data_to_cpu[9]~reg0.CLK clk => data_to_cpu[8]~reg0.CLK clk => data_to_cpu[7]~reg0.CLK clk => data_to_cpu[6]~reg0.CLK clk => data_to_cpu[5]~reg0.CLK clk => data_to_cpu[4]~reg0.CLK clk => data_to_cpu[3]~reg0.CLK clk => data_to_cpu[2]~reg0.CLK clk => data_to_cpu[1]~reg0.CLK clk => data_to_cpu[0]~reg0.CLK clk => state[4].CLK clk => state[3].CLK clk => state[2].CLK clk => state[1].CLK clk => state[0].CLK clk => stateZero.CLK clk => shift_reg[7].CLK clk => shift_reg[6].CLK clk => shift_reg[5].CLK clk => shift_reg[4].CLK clk => shift_reg[3].CLK clk => shift_reg[2].CLK clk => shift_reg[1].CLK clk => shift_reg[0].CLK clk => rx_holding_reg[7].CLK clk => rx_holding_reg[6].CLK clk => rx_holding_reg[5].CLK clk => rx_holding_reg[4].CLK clk => rx_holding_reg[3].CLK clk => rx_holding_reg[2].CLK clk => rx_holding_reg[1].CLK clk => rx_holding_reg[0].CLK clk => EOP.CLK clk => RRDY.CLK clk => ROE.CLK clk => TOE.CLK clk => tx_holding_reg[7].CLK clk => tx_holding_reg[6].CLK clk => tx_holding_reg[5].CLK clk => tx_holding_reg[4].CLK clk => tx_holding_reg[3].CLK clk => tx_holding_reg[2].CLK clk => tx_holding_reg[1].CLK clk => tx_holding_reg[0].CLK clk => tx_holding_primed.CLK clk => transmitting.CLK clk => SCLK_reg.CLK clk => MISO_reg.CLK data_from_cpu[0] => Equal8.IN15 data_from_cpu[0] => epcs_slave_select_holding_reg[0].DATAIN data_from_cpu[0] => endofpacketvalue_reg[0].DATAIN data_from_cpu[0] => tx_holding_reg[0].DATAIN data_from_cpu[1] => Equal8.IN14 data_from_cpu[1] => epcs_slave_select_holding_reg[1].DATAIN data_from_cpu[1] => endofpacketvalue_reg[1].DATAIN data_from_cpu[1] => tx_holding_reg[1].DATAIN data_from_cpu[2] => Equal8.IN13 data_from_cpu[2] => epcs_slave_select_holding_reg[2].DATAIN data_from_cpu[2] => endofpacketvalue_reg[2].DATAIN data_from_cpu[2] => tx_holding_reg[2].DATAIN data_from_cpu[3] => Equal8.IN12 data_from_cpu[3] => iROE_reg.DATAIN data_from_cpu[3] => epcs_slave_select_holding_reg[3].DATAIN data_from_cpu[3] => endofpacketvalue_reg[3].DATAIN data_from_cpu[3] => tx_holding_reg[3].DATAIN data_from_cpu[4] => Equal8.IN11 data_from_cpu[4] => iTOE_reg.DATAIN data_from_cpu[4] => epcs_slave_select_holding_reg[4].DATAIN data_from_cpu[4] => endofpacketvalue_reg[4].DATAIN data_from_cpu[4] => tx_holding_reg[4].DATAIN data_from_cpu[5] => Equal8.IN10 data_from_cpu[5] => epcs_slave_select_holding_reg[5].DATAIN data_from_cpu[5] => endofpacketvalue_reg[5].DATAIN data_from_cpu[5] => tx_holding_reg[5].DATAIN data_from_cpu[6] => Equal8.IN9 data_from_cpu[6] => iTRDY_reg.DATAIN data_from_cpu[6] => epcs_slave_select_holding_reg[6].DATAIN data_from_cpu[6] => endofpacketvalue_reg[6].DATAIN data_from_cpu[6] => tx_holding_reg[6].DATAIN data_from_cpu[7] => Equal8.IN8 data_from_cpu[7] => iRRDY_reg.DATAIN data_from_cpu[7] => epcs_slave_select_holding_reg[7].DATAIN data_from_cpu[7] => endofpacketvalue_reg[7].DATAIN data_from_cpu[7] => tx_holding_reg[7].DATAIN data_from_cpu[8] => iE_reg.DATAIN data_from_cpu[8] => epcs_slave_select_holding_reg[8].DATAIN data_from_cpu[8] => endofpacketvalue_reg[8].DATAIN data_from_cpu[9] => iEOP_reg.DATAIN data_from_cpu[9] => epcs_slave_select_holding_reg[9].DATAIN data_from_cpu[9] => endofpacketvalue_reg[9].DATAIN data_from_cpu[10] => always6~0.IN1 data_from_cpu[10] => SSO_reg.DATAIN data_from_cpu[10] => epcs_slave_select_holding_reg[10].DATAIN data_from_cpu[10] => endofpacketvalue_reg[10].DATAIN data_from_cpu[11] => epcs_slave_select_holding_reg[11].DATAIN data_from_cpu[11] => endofpacketvalue_reg[11].DATAIN data_from_cpu[12] => epcs_slave_select_holding_reg[12].DATAIN data_from_cpu[12] => endofpacketvalue_reg[12].DATAIN data_from_cpu[13] => epcs_slave_select_holding_reg[13].DATAIN data_from_cpu[13] => endofpacketvalue_reg[13].DATAIN data_from_cpu[14] => epcs_slave_select_holding_reg[14].DATAIN data_from_cpu[14] => endofpacketvalue_reg[14].DATAIN data_from_cpu[15] => epcs_slave_select_holding_reg[15].DATAIN data_from_cpu[15] => endofpacketvalue_reg[15].DATAIN epcs_select => p1_wr_strobe~0.IN1 epcs_select => p1_rd_strobe~0.IN1 mem_addr[0] => Equal0.IN31 mem_addr[0] => Equal1.IN0 mem_addr[0] => Equal3.IN31 mem_addr[0] => Equal4.IN0 mem_addr[0] => Equal5.IN31 mem_addr[0] => Equal6.IN0 mem_addr[1] => Equal0.IN30 mem_addr[1] => Equal1.IN31 mem_addr[1] => Equal3.IN0 mem_addr[1] => Equal4.IN1 mem_addr[1] => Equal5.IN0 mem_addr[1] => Equal6.IN31 mem_addr[2] => Equal0.IN29 mem_addr[2] => Equal1.IN30 mem_addr[2] => Equal3.IN30 mem_addr[2] => Equal4.IN31 mem_addr[2] => Equal5.IN1 mem_addr[2] => Equal6.IN1 read_n => p1_rd_strobe.IN1 reset_n => stateZero.PRESET reset_n => state[0].ACLR reset_n => state[1].ACLR reset_n => state[2].ACLR reset_n => state[3].ACLR reset_n => state[4].ACLR reset_n => endofpacketvalue_reg[0].ACLR reset_n => endofpacketvalue_reg[1].ACLR reset_n => endofpacketvalue_reg[2].ACLR reset_n => endofpacketvalue_reg[3].ACLR reset_n => endofpacketvalue_reg[4].ACLR reset_n => endofpacketvalue_reg[5].ACLR reset_n => endofpacketvalue_reg[6].ACLR reset_n => endofpacketvalue_reg[7].ACLR reset_n => endofpacketvalue_reg[8].ACLR reset_n => endofpacketvalue_reg[9].ACLR reset_n => endofpacketvalue_reg[10].ACLR reset_n => endofpacketvalue_reg[11].ACLR reset_n => endofpacketvalue_reg[12].ACLR reset_n => endofpacketvalue_reg[13].ACLR reset_n => endofpacketvalue_reg[14].ACLR reset_n => endofpacketvalue_reg[15].ACLR reset_n => slowcount[0].ACLR reset_n => slowcount[1].ACLR reset_n => epcs_slave_select_holding_reg[0].PRESET reset_n => epcs_slave_select_holding_reg[1].ACLR reset_n => epcs_slave_select_holding_reg[2].ACLR reset_n => epcs_slave_select_holding_reg[3].ACLR reset_n => epcs_slave_select_holding_reg[4].ACLR reset_n => epcs_slave_select_holding_reg[5].ACLR reset_n => epcs_slave_select_holding_reg[6].ACLR reset_n => epcs_slave_select_holding_reg[7].ACLR reset_n => epcs_slave_select_holding_reg[8].ACLR reset_n => epcs_slave_select_holding_reg[9].ACLR reset_n => epcs_slave_select_holding_reg[10].ACLR reset_n => epcs_slave_select_holding_reg[11].ACLR reset_n => epcs_slave_select_holding_reg[12].ACLR reset_n => epcs_slave_select_holding_reg[13].ACLR reset_n => epcs_slave_select_holding_reg[14].ACLR reset_n => epcs_slave_select_holding_reg[15].ACLR reset_n => epcs_slave_select_reg[0].PRESET reset_n => epcs_slave_select_reg[1].ACLR reset_n => epcs_slave_select_reg[2].ACLR reset_n => epcs_slave_select_reg[3].ACLR reset_n => epcs_slave_select_reg[4].ACLR reset_n => epcs_slave_select_reg[5].ACLR reset_n => epcs_slave_select_reg[6].ACLR reset_n => epcs_slave_select_reg[7].ACLR reset_n => epcs_slave_select_reg[8].ACLR reset_n => epcs_slave_select_reg[9].ACLR reset_n => epcs_slave_select_reg[10].ACLR reset_n => epcs_slave_select_reg[11].ACLR reset_n => epcs_slave_select_reg[12].ACLR reset_n => epcs_slave_select_reg[13].ACLR reset_n => epcs_slave_select_reg[14].ACLR reset_n => epcs_slave_select_reg[15].ACLR reset_n => SSO_reg.ACLR reset_n => iROE_reg.ACLR reset_n => iTOE_reg.ACLR reset_n => iTRDY_reg.ACLR reset_n => iRRDY_reg.ACLR reset_n => iE_reg.ACLR reset_n => iEOP_reg.ACLR reset_n => data_wr_strobe.ACLR reset_n => wr_strobe.ACLR reset_n => data_rd_strobe.ACLR reset_n => rd_strobe.ACLR reset_n => irq_reg.ACLR reset_n => data_to_cpu[0]~reg0.ACLR reset_n => data_to_cpu[1]~reg0.ACLR reset_n => data_to_cpu[2]~reg0.ACLR reset_n => data_to_cpu[3]~reg0.ACLR reset_n => data_to_cpu[4]~reg0.ACLR reset_n => data_to_cpu[5]~reg0.ACLR reset_n => data_to_cpu[6]~reg0.ACLR reset_n => data_to_cpu[7]~reg0.ACLR reset_n => data_to_cpu[8]~reg0.ACLR reset_n => data_to_cpu[9]~reg0.ACLR reset_n => data_to_cpu[10]~reg0.ACLR reset_n => data_to_cpu[11]~reg0.ACLR reset_n => data_to_cpu[12]~reg0.ACLR reset_n => data_to_cpu[13]~reg0.ACLR reset_n => data_to_cpu[14]~reg0.ACLR reset_n => data_to_cpu[15]~reg0.ACLR reset_n => shift_reg[7].ACLR reset_n => shift_reg[6].ACLR reset_n => shift_reg[5].ACLR reset_n => shift_reg[4].ACLR reset_n => shift_reg[3].ACLR reset_n => shift_reg[2].ACLR reset_n => shift_reg[1].ACLR reset_n => shift_reg[0].ACLR reset_n => rx_holding_reg[7].ACLR reset_n => rx_holding_reg[6].ACLR reset_n => rx_holding_reg[5].ACLR reset_n => rx_holding_reg[4].ACLR reset_n => rx_holding_reg[3].ACLR reset_n => rx_holding_reg[2].ACLR reset_n => rx_holding_reg[1].ACLR reset_n => rx_holding_reg[0].ACLR reset_n => EOP.ACLR reset_n => RRDY.ACLR reset_n => ROE.ACLR reset_n => TOE.ACLR reset_n => tx_holding_reg[7].ACLR reset_n => tx_holding_reg[6].ACLR reset_n => tx_holding_reg[5].ACLR reset_n => tx_holding_reg[4].ACLR reset_n => tx_holding_reg[3].ACLR reset_n => tx_holding_reg[2].ACLR reset_n => tx_holding_reg[1].ACLR reset_n => tx_holding_reg[0].ACLR reset_n => tx_holding_primed.ACLR reset_n => transmitting.ACLR reset_n => SCLK_reg.ACLR reset_n => MISO_reg.ACLR write_n => p1_wr_strobe.IN1 MOSI <= shift_reg[7].DB_MAX_OUTPUT_PORT_TYPE SCLK <= SCLK_reg.DB_MAX_OUTPUT_PORT_TYPE SS_n <= SS_n~1.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[0] <= data_to_cpu[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[1] <= data_to_cpu[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[2] <= data_to_cpu[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[3] <= data_to_cpu[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[4] <= data_to_cpu[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[5] <= data_to_cpu[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[6] <= data_to_cpu[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[7] <= data_to_cpu[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[8] <= data_to_cpu[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[9] <= data_to_cpu[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[10] <= data_to_cpu[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[11] <= data_to_cpu[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[12] <= data_to_cpu[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[13] <= data_to_cpu[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[14] <= data_to_cpu[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_to_cpu[15] <= data_to_cpu[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE dataavailable <= RRDY.DB_MAX_OUTPUT_PORT_TYPE endofpacket <= EOP.DB_MAX_OUTPUT_PORT_TYPE irq <= irq_reg.DB_MAX_OUTPUT_PORT_TYPE readyfordata <= TRDY~0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|epcs_controller:the_epcs_controller|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom dclkin => the_tornado_spiblock.CLK oe => the_tornado_spiblock.OE scein => the_tornado_spiblock.SCEIN sdoin => the_tornado_spiblock.SDOIN data0out <= the_tornado_spiblock.DATAOUT |DE1_NIOS|system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom wren_a => ~NO_FANOUT~ rden_a => ~NO_FANOUT~ wren_b => ~NO_FANOUT~ rden_b => ~NO_FANOUT~ data_a[0] => ~NO_FANOUT~ data_a[1] => ~NO_FANOUT~ data_a[2] => ~NO_FANOUT~ data_a[3] => ~NO_FANOUT~ data_a[4] => ~NO_FANOUT~ data_a[5] => ~NO_FANOUT~ data_a[6] => ~NO_FANOUT~ data_a[7] => ~NO_FANOUT~ data_a[8] => ~NO_FANOUT~ data_a[9] => ~NO_FANOUT~ data_a[10] => ~NO_FANOUT~ data_a[11] => ~NO_FANOUT~ data_a[12] => ~NO_FANOUT~ data_a[13] => ~NO_FANOUT~ data_a[14] => ~NO_FANOUT~ data_a[15] => ~NO_FANOUT~ data_a[16] => ~NO_FANOUT~ data_a[17] => ~NO_FANOUT~ data_a[18] => ~NO_FANOUT~ data_a[19] => ~NO_FANOUT~ data_a[20] => ~NO_FANOUT~ data_a[21] => ~NO_FANOUT~ data_a[22] => ~NO_FANOUT~ data_a[23] => ~NO_FANOUT~ data_a[24] => ~NO_FANOUT~ data_a[25] => ~NO_FANOUT~ data_a[26] => ~NO_FANOUT~ data_a[27] => ~NO_FANOUT~ data_a[28] => ~NO_FANOUT~ data_a[29] => ~NO_FANOUT~ data_a[30] => ~NO_FANOUT~ data_a[31] => ~NO_FANOUT~ data_b[0] => ~NO_FANOUT~ address_a[0] => altsyncram_lo31:auto_generated.address_a[0] address_a[1] => altsyncram_lo31:auto_generated.address_a[1] address_a[2] => altsyncram_lo31:auto_generated.address_a[2] address_a[3] => altsyncram_lo31:auto_generated.address_a[3] address_a[4] => altsyncram_lo31:auto_generated.address_a[4] address_a[5] => altsyncram_lo31:auto_generated.address_a[5] address_a[6] => altsyncram_lo31:auto_generated.address_a[6] address_b[0] => ~NO_FANOUT~ addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_lo31:auto_generated.clock0 clock1 => ~NO_FANOUT~ clocken0 => ~NO_FANOUT~ clocken1 => ~NO_FANOUT~ clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= altsyncram_lo31:auto_generated.q_a[0] q_a[1] <= altsyncram_lo31:auto_generated.q_a[1] q_a[2] <= altsyncram_lo31:auto_generated.q_a[2] q_a[3] <= altsyncram_lo31:auto_generated.q_a[3] q_a[4] <= altsyncram_lo31:auto_generated.q_a[4] q_a[5] <= altsyncram_lo31:auto_generated.q_a[5] q_a[6] <= altsyncram_lo31:auto_generated.q_a[6] q_a[7] <= altsyncram_lo31:auto_generated.q_a[7] q_a[8] <= altsyncram_lo31:auto_generated.q_a[8] q_a[9] <= altsyncram_lo31:auto_generated.q_a[9] q_a[10] <= altsyncram_lo31:auto_generated.q_a[10] q_a[11] <= altsyncram_lo31:auto_generated.q_a[11] q_a[12] <= altsyncram_lo31:auto_generated.q_a[12] q_a[13] <= altsyncram_lo31:auto_generated.q_a[13] q_a[14] <= altsyncram_lo31:auto_generated.q_a[14] q_a[15] <= altsyncram_lo31:auto_generated.q_a[15] q_a[16] <= altsyncram_lo31:auto_generated.q_a[16] q_a[17] <= altsyncram_lo31:auto_generated.q_a[17] q_a[18] <= altsyncram_lo31:auto_generated.q_a[18] q_a[19] <= altsyncram_lo31:auto_generated.q_a[19] q_a[20] <= altsyncram_lo31:auto_generated.q_a[20] q_a[21] <= altsyncram_lo31:auto_generated.q_a[21] q_a[22] <= altsyncram_lo31:auto_generated.q_a[22] q_a[23] <= altsyncram_lo31:auto_generated.q_a[23] q_a[24] <= altsyncram_lo31:auto_generated.q_a[24] q_a[25] <= altsyncram_lo31:auto_generated.q_a[25] q_a[26] <= altsyncram_lo31:auto_generated.q_a[26] q_a[27] <= altsyncram_lo31:auto_generated.q_a[27] q_a[28] <= altsyncram_lo31:auto_generated.q_a[28] q_a[29] <= altsyncram_lo31:auto_generated.q_a[29] q_a[30] <= altsyncram_lo31:auto_generated.q_a[30] q_a[31] <= altsyncram_lo31:auto_generated.q_a[31] q_b[0] <= eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |DE1_NIOS|system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_lo31:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[0] => ram_block1a8.PORTAADDR address_a[0] => ram_block1a9.PORTAADDR address_a[0] => ram_block1a10.PORTAADDR address_a[0] => ram_block1a11.PORTAADDR address_a[0] => ram_block1a12.PORTAADDR address_a[0] => ram_block1a13.PORTAADDR address_a[0] => ram_block1a14.PORTAADDR address_a[0] => ram_block1a15.PORTAADDR address_a[0] => ram_block1a16.PORTAADDR address_a[0] => ram_block1a17.PORTAADDR address_a[0] => ram_block1a18.PORTAADDR address_a[0] => ram_block1a19.PORTAADDR address_a[0] => ram_block1a20.PORTAADDR address_a[0] => ram_block1a21.PORTAADDR address_a[0] => ram_block1a22.PORTAADDR address_a[0] => ram_block1a23.PORTAADDR address_a[0] => ram_block1a24.PORTAADDR address_a[0] => ram_block1a25.PORTAADDR address_a[0] => ram_block1a26.PORTAADDR address_a[0] => ram_block1a27.PORTAADDR address_a[0] => ram_block1a28.PORTAADDR address_a[0] => ram_block1a29.PORTAADDR address_a[0] => ram_block1a30.PORTAADDR address_a[0] => ram_block1a31.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[1] => ram_block1a8.PORTAADDR1 address_a[1] => ram_block1a9.PORTAADDR1 address_a[1] => ram_block1a10.PORTAADDR1 address_a[1] => ram_block1a11.PORTAADDR1 address_a[1] => ram_block1a12.PORTAADDR1 address_a[1] => ram_block1a13.PORTAADDR1 address_a[1] => ram_block1a14.PORTAADDR1 address_a[1] => ram_block1a15.PORTAADDR1 address_a[1] => ram_block1a16.PORTAADDR1 address_a[1] => ram_block1a17.PORTAADDR1 address_a[1] => ram_block1a18.PORTAADDR1 address_a[1] => ram_block1a19.PORTAADDR1 address_a[1] => ram_block1a20.PORTAADDR1 address_a[1] => ram_block1a21.PORTAADDR1 address_a[1] => ram_block1a22.PORTAADDR1 address_a[1] => ram_block1a23.PORTAADDR1 address_a[1] => ram_block1a24.PORTAADDR1 address_a[1] => ram_block1a25.PORTAADDR1 address_a[1] => ram_block1a26.PORTAADDR1 address_a[1] => ram_block1a27.PORTAADDR1 address_a[1] => ram_block1a28.PORTAADDR1 address_a[1] => ram_block1a29.PORTAADDR1 address_a[1] => ram_block1a30.PORTAADDR1 address_a[1] => ram_block1a31.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[2] => ram_block1a8.PORTAADDR2 address_a[2] => ram_block1a9.PORTAADDR2 address_a[2] => ram_block1a10.PORTAADDR2 address_a[2] => ram_block1a11.PORTAADDR2 address_a[2] => ram_block1a12.PORTAADDR2 address_a[2] => ram_block1a13.PORTAADDR2 address_a[2] => ram_block1a14.PORTAADDR2 address_a[2] => ram_block1a15.PORTAADDR2 address_a[2] => ram_block1a16.PORTAADDR2 address_a[2] => ram_block1a17.PORTAADDR2 address_a[2] => ram_block1a18.PORTAADDR2 address_a[2] => ram_block1a19.PORTAADDR2 address_a[2] => ram_block1a20.PORTAADDR2 address_a[2] => ram_block1a21.PORTAADDR2 address_a[2] => ram_block1a22.PORTAADDR2 address_a[2] => ram_block1a23.PORTAADDR2 address_a[2] => ram_block1a24.PORTAADDR2 address_a[2] => ram_block1a25.PORTAADDR2 address_a[2] => ram_block1a26.PORTAADDR2 address_a[2] => ram_block1a27.PORTAADDR2 address_a[2] => ram_block1a28.PORTAADDR2 address_a[2] => ram_block1a29.PORTAADDR2 address_a[2] => ram_block1a30.PORTAADDR2 address_a[2] => ram_block1a31.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[3] => ram_block1a8.PORTAADDR3 address_a[3] => ram_block1a9.PORTAADDR3 address_a[3] => ram_block1a10.PORTAADDR3 address_a[3] => ram_block1a11.PORTAADDR3 address_a[3] => ram_block1a12.PORTAADDR3 address_a[3] => ram_block1a13.PORTAADDR3 address_a[3] => ram_block1a14.PORTAADDR3 address_a[3] => ram_block1a15.PORTAADDR3 address_a[3] => ram_block1a16.PORTAADDR3 address_a[3] => ram_block1a17.PORTAADDR3 address_a[3] => ram_block1a18.PORTAADDR3 address_a[3] => ram_block1a19.PORTAADDR3 address_a[3] => ram_block1a20.PORTAADDR3 address_a[3] => ram_block1a21.PORTAADDR3 address_a[3] => ram_block1a22.PORTAADDR3 address_a[3] => ram_block1a23.PORTAADDR3 address_a[3] => ram_block1a24.PORTAADDR3 address_a[3] => ram_block1a25.PORTAADDR3 address_a[3] => ram_block1a26.PORTAADDR3 address_a[3] => ram_block1a27.PORTAADDR3 address_a[3] => ram_block1a28.PORTAADDR3 address_a[3] => ram_block1a29.PORTAADDR3 address_a[3] => ram_block1a30.PORTAADDR3 address_a[3] => ram_block1a31.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[4] => ram_block1a8.PORTAADDR4 address_a[4] => ram_block1a9.PORTAADDR4 address_a[4] => ram_block1a10.PORTAADDR4 address_a[4] => ram_block1a11.PORTAADDR4 address_a[4] => ram_block1a12.PORTAADDR4 address_a[4] => ram_block1a13.PORTAADDR4 address_a[4] => ram_block1a14.PORTAADDR4 address_a[4] => ram_block1a15.PORTAADDR4 address_a[4] => ram_block1a16.PORTAADDR4 address_a[4] => ram_block1a17.PORTAADDR4 address_a[4] => ram_block1a18.PORTAADDR4 address_a[4] => ram_block1a19.PORTAADDR4 address_a[4] => ram_block1a20.PORTAADDR4 address_a[4] => ram_block1a21.PORTAADDR4 address_a[4] => ram_block1a22.PORTAADDR4 address_a[4] => ram_block1a23.PORTAADDR4 address_a[4] => ram_block1a24.PORTAADDR4 address_a[4] => ram_block1a25.PORTAADDR4 address_a[4] => ram_block1a26.PORTAADDR4 address_a[4] => ram_block1a27.PORTAADDR4 address_a[4] => ram_block1a28.PORTAADDR4 address_a[4] => ram_block1a29.PORTAADDR4 address_a[4] => ram_block1a30.PORTAADDR4 address_a[4] => ram_block1a31.PORTAADDR4 address_a[5] => ram_block1a0.PORTAADDR5 address_a[5] => ram_block1a1.PORTAADDR5 address_a[5] => ram_block1a2.PORTAADDR5 address_a[5] => ram_block1a3.PORTAADDR5 address_a[5] => ram_block1a4.PORTAADDR5 address_a[5] => ram_block1a5.PORTAADDR5 address_a[5] => ram_block1a6.PORTAADDR5 address_a[5] => ram_block1a7.PORTAADDR5 address_a[5] => ram_block1a8.PORTAADDR5 address_a[5] => ram_block1a9.PORTAADDR5 address_a[5] => ram_block1a10.PORTAADDR5 address_a[5] => ram_block1a11.PORTAADDR5 address_a[5] => ram_block1a12.PORTAADDR5 address_a[5] => ram_block1a13.PORTAADDR5 address_a[5] => ram_block1a14.PORTAADDR5 address_a[5] => ram_block1a15.PORTAADDR5 address_a[5] => ram_block1a16.PORTAADDR5 address_a[5] => ram_block1a17.PORTAADDR5 address_a[5] => ram_block1a18.PORTAADDR5 address_a[5] => ram_block1a19.PORTAADDR5 address_a[5] => ram_block1a20.PORTAADDR5 address_a[5] => ram_block1a21.PORTAADDR5 address_a[5] => ram_block1a22.PORTAADDR5 address_a[5] => ram_block1a23.PORTAADDR5 address_a[5] => ram_block1a24.PORTAADDR5 address_a[5] => ram_block1a25.PORTAADDR5 address_a[5] => ram_block1a26.PORTAADDR5 address_a[5] => ram_block1a27.PORTAADDR5 address_a[5] => ram_block1a28.PORTAADDR5 address_a[5] => ram_block1a29.PORTAADDR5 address_a[5] => ram_block1a30.PORTAADDR5 address_a[5] => ram_block1a31.PORTAADDR5 address_a[6] => ram_block1a0.PORTAADDR6 address_a[6] => ram_block1a1.PORTAADDR6 address_a[6] => ram_block1a2.PORTAADDR6 address_a[6] => ram_block1a3.PORTAADDR6 address_a[6] => ram_block1a4.PORTAADDR6 address_a[6] => ram_block1a5.PORTAADDR6 address_a[6] => ram_block1a6.PORTAADDR6 address_a[6] => ram_block1a7.PORTAADDR6 address_a[6] => ram_block1a8.PORTAADDR6 address_a[6] => ram_block1a9.PORTAADDR6 address_a[6] => ram_block1a10.PORTAADDR6 address_a[6] => ram_block1a11.PORTAADDR6 address_a[6] => ram_block1a12.PORTAADDR6 address_a[6] => ram_block1a13.PORTAADDR6 address_a[6] => ram_block1a14.PORTAADDR6 address_a[6] => ram_block1a15.PORTAADDR6 address_a[6] => ram_block1a16.PORTAADDR6 address_a[6] => ram_block1a17.PORTAADDR6 address_a[6] => ram_block1a18.PORTAADDR6 address_a[6] => ram_block1a19.PORTAADDR6 address_a[6] => ram_block1a20.PORTAADDR6 address_a[6] => ram_block1a21.PORTAADDR6 address_a[6] => ram_block1a22.PORTAADDR6 address_a[6] => ram_block1a23.PORTAADDR6 address_a[6] => ram_block1a24.PORTAADDR6 address_a[6] => ram_block1a25.PORTAADDR6 address_a[6] => ram_block1a26.PORTAADDR6 address_a[6] => ram_block1a27.PORTAADDR6 address_a[6] => ram_block1a28.PORTAADDR6 address_a[6] => ram_block1a29.PORTAADDR6 address_a[6] => ram_block1a30.PORTAADDR6 address_a[6] => ram_block1a31.PORTAADDR6 clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 clock0 => ram_block1a8.CLK0 clock0 => ram_block1a9.CLK0 clock0 => ram_block1a10.CLK0 clock0 => ram_block1a11.CLK0 clock0 => ram_block1a12.CLK0 clock0 => ram_block1a13.CLK0 clock0 => ram_block1a14.CLK0 clock0 => ram_block1a15.CLK0 clock0 => ram_block1a16.CLK0 clock0 => ram_block1a17.CLK0 clock0 => ram_block1a18.CLK0 clock0 => ram_block1a19.CLK0 clock0 => ram_block1a20.CLK0 clock0 => ram_block1a21.CLK0 clock0 => ram_block1a22.CLK0 clock0 => ram_block1a23.CLK0 clock0 => ram_block1a24.CLK0 clock0 => ram_block1a25.CLK0 clock0 => ram_block1a26.CLK0 clock0 => ram_block1a27.CLK0 clock0 => ram_block1a28.CLK0 clock0 => ram_block1a29.CLK0 clock0 => ram_block1a30.CLK0 clock0 => ram_block1a31.CLK0 q_a[0] <= ram_block1a0.PORTADATAOUT q_a[1] <= ram_block1a1.PORTADATAOUT q_a[2] <= ram_block1a2.PORTADATAOUT q_a[3] <= ram_block1a3.PORTADATAOUT q_a[4] <= ram_block1a4.PORTADATAOUT q_a[5] <= ram_block1a5.PORTADATAOUT q_a[6] <= ram_block1a6.PORTADATAOUT q_a[7] <= ram_block1a7.PORTADATAOUT q_a[8] <= ram_block1a8.PORTADATAOUT q_a[9] <= ram_block1a9.PORTADATAOUT q_a[10] <= ram_block1a10.PORTADATAOUT q_a[11] <= ram_block1a11.PORTADATAOUT q_a[12] <= ram_block1a12.PORTADATAOUT q_a[13] <= ram_block1a13.PORTADATAOUT q_a[14] <= ram_block1a14.PORTADATAOUT q_a[15] <= ram_block1a15.PORTADATAOUT q_a[16] <= ram_block1a16.PORTADATAOUT q_a[17] <= ram_block1a17.PORTADATAOUT q_a[18] <= ram_block1a18.PORTADATAOUT q_a[19] <= ram_block1a19.PORTADATAOUT q_a[20] <= ram_block1a20.PORTADATAOUT q_a[21] <= ram_block1a21.PORTADATAOUT q_a[22] <= ram_block1a22.PORTADATAOUT q_a[23] <= ram_block1a23.PORTADATAOUT q_a[24] <= ram_block1a24.PORTADATAOUT q_a[25] <= ram_block1a25.PORTADATAOUT q_a[26] <= ram_block1a26.PORTADATAOUT q_a[27] <= ram_block1a27.PORTADATAOUT q_a[28] <= ram_block1a28.PORTADATAOUT q_a[29] <= ram_block1a29.PORTADATAOUT q_a[30] <= ram_block1a30.PORTADATAOUT q_a[31] <= ram_block1a31.PORTADATAOUT |DE1_NIOS|system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave clk => d1_jtag_uart_0_avalon_jtag_slave_end_xfer~reg0.CLK cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[2] => jtag_uart_0_avalon_jtag_slave_address.DATAIN cpu_0_data_master_address_to_slave[3] => Equal0.IN11 cpu_0_data_master_address_to_slave[4] => Equal0.IN12 cpu_0_data_master_address_to_slave[5] => Equal0.IN0 cpu_0_data_master_address_to_slave[6] => Equal0.IN1 cpu_0_data_master_address_to_slave[7] => Equal0.IN13 cpu_0_data_master_address_to_slave[8] => Equal0.IN14 cpu_0_data_master_address_to_slave[9] => Equal0.IN15 cpu_0_data_master_address_to_slave[10] => Equal0.IN16 cpu_0_data_master_address_to_slave[11] => Equal0.IN17 cpu_0_data_master_address_to_slave[12] => Equal0.IN2 cpu_0_data_master_address_to_slave[13] => Equal0.IN18 cpu_0_data_master_address_to_slave[14] => Equal0.IN19 cpu_0_data_master_address_to_slave[15] => Equal0.IN20 cpu_0_data_master_address_to_slave[16] => Equal0.IN21 cpu_0_data_master_address_to_slave[17] => Equal0.IN22 cpu_0_data_master_address_to_slave[18] => Equal0.IN23 cpu_0_data_master_address_to_slave[19] => Equal0.IN3 cpu_0_data_master_address_to_slave[20] => Equal0.IN24 cpu_0_data_master_address_to_slave[21] => Equal0.IN25 cpu_0_data_master_address_to_slave[22] => Equal0.IN4 cpu_0_data_master_address_to_slave[23] => Equal0.IN26 cpu_0_data_master_read => jtag_uart_0_avalon_jtag_slave_in_a_read_cycle.IN0 cpu_0_data_master_read => cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave~0.IN0 cpu_0_data_master_read => cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave~0.IN0 cpu_0_data_master_waitrequest => cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave~0.IN1 cpu_0_data_master_waitrequest => cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave~1.IN0 cpu_0_data_master_write => jtag_uart_0_avalon_jtag_slave_in_a_write_cycle.IN0 cpu_0_data_master_write => cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave~1.IN1 cpu_0_data_master_write => cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave~0.IN1 cpu_0_data_master_writedata[0] => jtag_uart_0_avalon_jtag_slave_writedata[0].DATAIN cpu_0_data_master_writedata[1] => jtag_uart_0_avalon_jtag_slave_writedata[1].DATAIN cpu_0_data_master_writedata[2] => jtag_uart_0_avalon_jtag_slave_writedata[2].DATAIN cpu_0_data_master_writedata[3] => jtag_uart_0_avalon_jtag_slave_writedata[3].DATAIN cpu_0_data_master_writedata[4] => jtag_uart_0_avalon_jtag_slave_writedata[4].DATAIN cpu_0_data_master_writedata[5] => jtag_uart_0_avalon_jtag_slave_writedata[5].DATAIN cpu_0_data_master_writedata[6] => jtag_uart_0_avalon_jtag_slave_writedata[6].DATAIN cpu_0_data_master_writedata[7] => jtag_uart_0_avalon_jtag_slave_writedata[7].DATAIN cpu_0_data_master_writedata[8] => jtag_uart_0_avalon_jtag_slave_writedata[8].DATAIN cpu_0_data_master_writedata[9] => jtag_uart_0_avalon_jtag_slave_writedata[9].DATAIN cpu_0_data_master_writedata[10] => jtag_uart_0_avalon_jtag_slave_writedata[10].DATAIN cpu_0_data_master_writedata[11] => jtag_uart_0_avalon_jtag_slave_writedata[11].DATAIN cpu_0_data_master_writedata[12] => jtag_uart_0_avalon_jtag_slave_writedata[12].DATAIN cpu_0_data_master_writedata[13] => jtag_uart_0_avalon_jtag_slave_writedata[13].DATAIN cpu_0_data_master_writedata[14] => jtag_uart_0_avalon_jtag_slave_writedata[14].DATAIN cpu_0_data_master_writedata[15] => jtag_uart_0_avalon_jtag_slave_writedata[15].DATAIN cpu_0_data_master_writedata[16] => jtag_uart_0_avalon_jtag_slave_writedata[16].DATAIN cpu_0_data_master_writedata[17] => jtag_uart_0_avalon_jtag_slave_writedata[17].DATAIN cpu_0_data_master_writedata[18] => jtag_uart_0_avalon_jtag_slave_writedata[18].DATAIN cpu_0_data_master_writedata[19] => jtag_uart_0_avalon_jtag_slave_writedata[19].DATAIN cpu_0_data_master_writedata[20] => jtag_uart_0_avalon_jtag_slave_writedata[20].DATAIN cpu_0_data_master_writedata[21] => jtag_uart_0_avalon_jtag_slave_writedata[21].DATAIN cpu_0_data_master_writedata[22] => jtag_uart_0_avalon_jtag_slave_writedata[22].DATAIN cpu_0_data_master_writedata[23] => jtag_uart_0_avalon_jtag_slave_writedata[23].DATAIN cpu_0_data_master_writedata[24] => jtag_uart_0_avalon_jtag_slave_writedata[24].DATAIN cpu_0_data_master_writedata[25] => jtag_uart_0_avalon_jtag_slave_writedata[25].DATAIN cpu_0_data_master_writedata[26] => jtag_uart_0_avalon_jtag_slave_writedata[26].DATAIN cpu_0_data_master_writedata[27] => jtag_uart_0_avalon_jtag_slave_writedata[27].DATAIN cpu_0_data_master_writedata[28] => jtag_uart_0_avalon_jtag_slave_writedata[28].DATAIN cpu_0_data_master_writedata[29] => jtag_uart_0_avalon_jtag_slave_writedata[29].DATAIN cpu_0_data_master_writedata[30] => jtag_uart_0_avalon_jtag_slave_writedata[30].DATAIN cpu_0_data_master_writedata[31] => jtag_uart_0_avalon_jtag_slave_writedata[31].DATAIN jtag_uart_0_avalon_jtag_slave_dataavailable => jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa.DATAIN jtag_uart_0_avalon_jtag_slave_irq => jtag_uart_0_avalon_jtag_slave_irq_from_sa.DATAIN jtag_uart_0_avalon_jtag_slave_readdata[0] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[0].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[1] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[1].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[2] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[2].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[3] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[3].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[4] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[4].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[5] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[5].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[6] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[6].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[7] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[7].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[8] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[8].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[9] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[9].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[10] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[10].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[11] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[11].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[12] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[12].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[13] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[13].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[14] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[14].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[15] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[15].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[16] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[16].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[17] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[17].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[18] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[18].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[19] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[19].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[20] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[20].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[21] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[21].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[22] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[22].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[23] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[23].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[24] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[24].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[25] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[25].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[26] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[26].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[27] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[27].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[28] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[28].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[29] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[29].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[30] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[30].DATAIN jtag_uart_0_avalon_jtag_slave_readdata[31] => jtag_uart_0_avalon_jtag_slave_readdata_from_sa[31].DATAIN jtag_uart_0_avalon_jtag_slave_readyfordata => jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa.DATAIN jtag_uart_0_avalon_jtag_slave_waitrequest => jtag_uart_0_avalon_jtag_slave_waits_for_write.IN0 jtag_uart_0_avalon_jtag_slave_waitrequest => jtag_uart_0_avalon_jtag_slave_waits_for_read.IN0 jtag_uart_0_avalon_jtag_slave_waitrequest => jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa.DATAIN reset_n => jtag_uart_0_avalon_jtag_slave_reset_n.DATAIN reset_n => d1_jtag_uart_0_avalon_jtag_slave_end_xfer~reg0.PRESET cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave <= cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave~3.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave <= cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave~3.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave <= cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave <= cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave~1.DB_MAX_OUTPUT_PORT_TYPE d1_jtag_uart_0_avalon_jtag_slave_end_xfer <= d1_jtag_uart_0_avalon_jtag_slave_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_address <= cpu_0_data_master_address_to_slave[2].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_chipselect <= cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave~3.DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa <= jtag_uart_0_avalon_jtag_slave_dataavailable.DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_irq_from_sa <= jtag_uart_0_avalon_jtag_slave_irq.DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_read_n <= jtag_uart_0_avalon_jtag_slave_in_a_read_cycle.DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[0] <= jtag_uart_0_avalon_jtag_slave_readdata[0].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[1] <= jtag_uart_0_avalon_jtag_slave_readdata[1].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[2] <= jtag_uart_0_avalon_jtag_slave_readdata[2].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[3] <= jtag_uart_0_avalon_jtag_slave_readdata[3].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[4] <= jtag_uart_0_avalon_jtag_slave_readdata[4].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[5] <= jtag_uart_0_avalon_jtag_slave_readdata[5].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[6] <= jtag_uart_0_avalon_jtag_slave_readdata[6].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[7] <= jtag_uart_0_avalon_jtag_slave_readdata[7].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[8] <= jtag_uart_0_avalon_jtag_slave_readdata[8].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[9] <= jtag_uart_0_avalon_jtag_slave_readdata[9].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[10] <= jtag_uart_0_avalon_jtag_slave_readdata[10].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[11] <= jtag_uart_0_avalon_jtag_slave_readdata[11].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[12] <= jtag_uart_0_avalon_jtag_slave_readdata[12].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[13] <= jtag_uart_0_avalon_jtag_slave_readdata[13].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[14] <= jtag_uart_0_avalon_jtag_slave_readdata[14].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[15] <= jtag_uart_0_avalon_jtag_slave_readdata[15].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[16] <= jtag_uart_0_avalon_jtag_slave_readdata[16].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[17] <= jtag_uart_0_avalon_jtag_slave_readdata[17].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[18] <= jtag_uart_0_avalon_jtag_slave_readdata[18].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[19] <= jtag_uart_0_avalon_jtag_slave_readdata[19].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[20] <= jtag_uart_0_avalon_jtag_slave_readdata[20].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[21] <= jtag_uart_0_avalon_jtag_slave_readdata[21].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[22] <= jtag_uart_0_avalon_jtag_slave_readdata[22].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[23] <= jtag_uart_0_avalon_jtag_slave_readdata[23].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[24] <= jtag_uart_0_avalon_jtag_slave_readdata[24].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[25] <= jtag_uart_0_avalon_jtag_slave_readdata[25].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[26] <= jtag_uart_0_avalon_jtag_slave_readdata[26].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[27] <= jtag_uart_0_avalon_jtag_slave_readdata[27].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[28] <= jtag_uart_0_avalon_jtag_slave_readdata[28].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[29] <= jtag_uart_0_avalon_jtag_slave_readdata[29].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[30] <= jtag_uart_0_avalon_jtag_slave_readdata[30].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readdata_from_sa[31] <= jtag_uart_0_avalon_jtag_slave_readdata[31].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa <= jtag_uart_0_avalon_jtag_slave_readyfordata.DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_reset_n <= reset_n.DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa <= jtag_uart_0_avalon_jtag_slave_waitrequest.DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_write_n <= jtag_uart_0_avalon_jtag_slave_in_a_write_cycle.DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[0] <= cpu_0_data_master_writedata[0].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[1] <= cpu_0_data_master_writedata[1].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[2] <= cpu_0_data_master_writedata[2].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[3] <= cpu_0_data_master_writedata[3].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[4] <= cpu_0_data_master_writedata[4].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[5] <= cpu_0_data_master_writedata[5].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[6] <= cpu_0_data_master_writedata[6].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[7] <= cpu_0_data_master_writedata[7].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[8] <= cpu_0_data_master_writedata[8].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[9] <= cpu_0_data_master_writedata[9].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[10] <= cpu_0_data_master_writedata[10].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[11] <= cpu_0_data_master_writedata[11].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[12] <= cpu_0_data_master_writedata[12].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[13] <= cpu_0_data_master_writedata[13].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[14] <= cpu_0_data_master_writedata[14].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[15] <= cpu_0_data_master_writedata[15].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[16] <= cpu_0_data_master_writedata[16].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[17] <= cpu_0_data_master_writedata[17].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[18] <= cpu_0_data_master_writedata[18].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[19] <= cpu_0_data_master_writedata[19].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[20] <= cpu_0_data_master_writedata[20].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[21] <= cpu_0_data_master_writedata[21].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[22] <= cpu_0_data_master_writedata[22].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[23] <= cpu_0_data_master_writedata[23].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[24] <= cpu_0_data_master_writedata[24].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[25] <= cpu_0_data_master_writedata[25].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[26] <= cpu_0_data_master_writedata[26].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[27] <= cpu_0_data_master_writedata[27].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[28] <= cpu_0_data_master_writedata[28].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[29] <= cpu_0_data_master_writedata[29].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[30] <= cpu_0_data_master_writedata[30].DB_MAX_OUTPUT_PORT_TYPE jtag_uart_0_avalon_jtag_slave_writedata[31] <= cpu_0_data_master_writedata[31].DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0 av_address => rvalid~0.OUTPUTSELECT av_address => woverflow~0.OUTPUTSELECT av_address => fifo_wr~0.OUTPUTSELECT av_address => ac~2.OUTPUTSELECT av_address => ien_AE~0.OUTPUTSELECT av_address => ien_AF~0.OUTPUTSELECT av_address => read_0~0.DATAB av_address => fifo_rd~2.IN0 av_chipselect => fifo_rd~0.IN0 av_chipselect => always2~3.IN0 av_chipselect => always2~0.IN1 av_chipselect => av_waitrequest~1.IN0 av_read_n => av_waitrequest~0.IN1 av_read_n => always2~3.IN1 av_read_n => fifo_rd~0.IN1 av_write_n => av_waitrequest~0.IN0 av_write_n => always2~0.IN0 av_writedata[0] => fifo_wdata[0].IN1 av_writedata[1] => fifo_wdata[1].IN1 av_writedata[2] => fifo_wdata[2].IN1 av_writedata[3] => fifo_wdata[3].IN1 av_writedata[4] => fifo_wdata[4].IN1 av_writedata[5] => fifo_wdata[5].IN1 av_writedata[6] => fifo_wdata[6].IN1 av_writedata[7] => fifo_wdata[7].IN1 av_writedata[8] => ~NO_FANOUT~ av_writedata[9] => ~NO_FANOUT~ av_writedata[10] => always2~2.IN1 av_writedata[11] => ~NO_FANOUT~ av_writedata[12] => ~NO_FANOUT~ av_writedata[13] => ~NO_FANOUT~ av_writedata[14] => ~NO_FANOUT~ av_writedata[15] => ~NO_FANOUT~ av_writedata[16] => ~NO_FANOUT~ av_writedata[17] => ~NO_FANOUT~ av_writedata[18] => ~NO_FANOUT~ av_writedata[19] => ~NO_FANOUT~ av_writedata[20] => ~NO_FANOUT~ av_writedata[21] => ~NO_FANOUT~ av_writedata[22] => ~NO_FANOUT~ av_writedata[23] => ~NO_FANOUT~ av_writedata[24] => ~NO_FANOUT~ av_writedata[25] => ~NO_FANOUT~ av_writedata[26] => ~NO_FANOUT~ av_writedata[27] => ~NO_FANOUT~ av_writedata[28] => ~NO_FANOUT~ av_writedata[29] => ~NO_FANOUT~ av_writedata[30] => ~NO_FANOUT~ av_writedata[31] => ~NO_FANOUT~ clk => clk~0.IN3 rst_n => rst_n~0.IN2 av_irq <= av_irq~0.DB_MAX_OUTPUT_PORT_TYPE av_readdata[0] <= av_readdata~14.DB_MAX_OUTPUT_PORT_TYPE av_readdata[1] <= av_readdata~13.DB_MAX_OUTPUT_PORT_TYPE av_readdata[2] <= av_readdata~12.DB_MAX_OUTPUT_PORT_TYPE av_readdata[3] <= av_readdata~11.DB_MAX_OUTPUT_PORT_TYPE av_readdata[4] <= av_readdata~10.DB_MAX_OUTPUT_PORT_TYPE av_readdata[5] <= av_readdata~9.DB_MAX_OUTPUT_PORT_TYPE av_readdata[6] <= av_readdata~8.DB_MAX_OUTPUT_PORT_TYPE av_readdata[7] <= av_readdata~7.DB_MAX_OUTPUT_PORT_TYPE av_readdata[8] <= ipen_AF~1.DB_MAX_OUTPUT_PORT_TYPE av_readdata[9] <= ipen_AE~0.DB_MAX_OUTPUT_PORT_TYPE av_readdata[10] <= ac.DB_MAX_OUTPUT_PORT_TYPE av_readdata[11] <= av_readdata[12] <= jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r.fifo_EF av_readdata[13] <= jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w.fifo_FF av_readdata[14] <= woverflow.DB_MAX_OUTPUT_PORT_TYPE av_readdata[15] <= rvalid.DB_MAX_OUTPUT_PORT_TYPE av_readdata[16] <= av_readdata~6.DB_MAX_OUTPUT_PORT_TYPE av_readdata[17] <= av_readdata~5.DB_MAX_OUTPUT_PORT_TYPE av_readdata[18] <= av_readdata~4.DB_MAX_OUTPUT_PORT_TYPE av_readdata[19] <= av_readdata~3.DB_MAX_OUTPUT_PORT_TYPE av_readdata[20] <= av_readdata~2.DB_MAX_OUTPUT_PORT_TYPE av_readdata[21] <= av_readdata~1.DB_MAX_OUTPUT_PORT_TYPE av_readdata[22] <= av_readdata~0.DB_MAX_OUTPUT_PORT_TYPE av_readdata[23] <= av_readdata[24] <= av_readdata[25] <= av_readdata[26] <= av_readdata[27] <= av_readdata[28] <= av_readdata[29] <= av_readdata[30] <= av_readdata[31] <= av_waitrequest <= av_waitrequest~reg0.DB_MAX_OUTPUT_PORT_TYPE dataavailable <= dataavailable~reg0.DB_MAX_OUTPUT_PORT_TYPE readyfordata <= readyfordata~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w clk => clk~0.IN1 fifo_clear => fifo_clear~0.IN1 fifo_wdata[0] => fifo_wdata[0]~7.IN1 fifo_wdata[1] => fifo_wdata[1]~6.IN1 fifo_wdata[2] => fifo_wdata[2]~5.IN1 fifo_wdata[3] => fifo_wdata[3]~4.IN1 fifo_wdata[4] => fifo_wdata[4]~3.IN1 fifo_wdata[5] => fifo_wdata[5]~2.IN1 fifo_wdata[6] => fifo_wdata[6]~1.IN1 fifo_wdata[7] => fifo_wdata[7]~0.IN1 fifo_wr => fifo_wr~0.IN1 rd_wfifo => rd_wfifo~0.IN1 fifo_FF <= scfifo:wfifo.full r_dat[0] <= scfifo:wfifo.q r_dat[1] <= scfifo:wfifo.q r_dat[2] <= scfifo:wfifo.q r_dat[3] <= scfifo:wfifo.q r_dat[4] <= scfifo:wfifo.q r_dat[5] <= scfifo:wfifo.q r_dat[6] <= scfifo:wfifo.q r_dat[7] <= scfifo:wfifo.q wfifo_empty <= scfifo:wfifo.empty wfifo_used[0] <= scfifo:wfifo.usedw wfifo_used[1] <= scfifo:wfifo.usedw wfifo_used[2] <= scfifo:wfifo.usedw wfifo_used[3] <= scfifo:wfifo.usedw wfifo_used[4] <= scfifo:wfifo.usedw wfifo_used[5] <= scfifo:wfifo.usedw |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo data[0] => scfifo_1n21:auto_generated.data[0] data[1] => scfifo_1n21:auto_generated.data[1] data[2] => scfifo_1n21:auto_generated.data[2] data[3] => scfifo_1n21:auto_generated.data[3] data[4] => scfifo_1n21:auto_generated.data[4] data[5] => scfifo_1n21:auto_generated.data[5] data[6] => scfifo_1n21:auto_generated.data[6] data[7] => scfifo_1n21:auto_generated.data[7] q[0] <= scfifo_1n21:auto_generated.q[0] q[1] <= scfifo_1n21:auto_generated.q[1] q[2] <= scfifo_1n21:auto_generated.q[2] q[3] <= scfifo_1n21:auto_generated.q[3] q[4] <= scfifo_1n21:auto_generated.q[4] q[5] <= scfifo_1n21:auto_generated.q[5] q[6] <= scfifo_1n21:auto_generated.q[6] q[7] <= scfifo_1n21:auto_generated.q[7] wrreq => scfifo_1n21:auto_generated.wrreq rdreq => scfifo_1n21:auto_generated.rdreq clock => scfifo_1n21:auto_generated.clock aclr => scfifo_1n21:auto_generated.aclr sclr => ~NO_FANOUT~ empty <= scfifo_1n21:auto_generated.empty full <= scfifo_1n21:auto_generated.full almost_full <= almost_empty <= usedw[0] <= scfifo_1n21:auto_generated.usedw[0] usedw[1] <= scfifo_1n21:auto_generated.usedw[1] usedw[2] <= scfifo_1n21:auto_generated.usedw[2] usedw[3] <= scfifo_1n21:auto_generated.usedw[3] usedw[4] <= scfifo_1n21:auto_generated.usedw[4] usedw[5] <= scfifo_1n21:auto_generated.usedw[5] |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated aclr => a_dpfifo_8t21:dpfifo.aclr clock => a_dpfifo_8t21:dpfifo.clock data[0] => a_dpfifo_8t21:dpfifo.data[0] data[1] => a_dpfifo_8t21:dpfifo.data[1] data[2] => a_dpfifo_8t21:dpfifo.data[2] data[3] => a_dpfifo_8t21:dpfifo.data[3] data[4] => a_dpfifo_8t21:dpfifo.data[4] data[5] => a_dpfifo_8t21:dpfifo.data[5] data[6] => a_dpfifo_8t21:dpfifo.data[6] data[7] => a_dpfifo_8t21:dpfifo.data[7] empty <= a_dpfifo_8t21:dpfifo.empty full <= a_dpfifo_8t21:dpfifo.full q[0] <= a_dpfifo_8t21:dpfifo.q[0] q[1] <= a_dpfifo_8t21:dpfifo.q[1] q[2] <= a_dpfifo_8t21:dpfifo.q[2] q[3] <= a_dpfifo_8t21:dpfifo.q[3] q[4] <= a_dpfifo_8t21:dpfifo.q[4] q[5] <= a_dpfifo_8t21:dpfifo.q[5] q[6] <= a_dpfifo_8t21:dpfifo.q[6] q[7] <= a_dpfifo_8t21:dpfifo.q[7] rdreq => a_dpfifo_8t21:dpfifo.rreq usedw[0] <= a_dpfifo_8t21:dpfifo.usedw[0] usedw[1] <= a_dpfifo_8t21:dpfifo.usedw[1] usedw[2] <= a_dpfifo_8t21:dpfifo.usedw[2] usedw[3] <= a_dpfifo_8t21:dpfifo.usedw[3] usedw[4] <= a_dpfifo_8t21:dpfifo.usedw[4] usedw[5] <= a_dpfifo_8t21:dpfifo.usedw[5] wrreq => a_dpfifo_8t21:dpfifo.wreq |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo aclr => a_fefifo_7cf:fifo_state.aclr aclr => cntr_fjb:rd_ptr_count.aclr aclr => cntr_fjb:wr_ptr.aclr clock => a_fefifo_7cf:fifo_state.clock clock => dpram_5h21:FIFOram.inclock clock => dpram_5h21:FIFOram.outclock clock => cntr_fjb:rd_ptr_count.clock clock => cntr_fjb:wr_ptr.clock data[0] => dpram_5h21:FIFOram.data[0] data[1] => dpram_5h21:FIFOram.data[1] data[2] => dpram_5h21:FIFOram.data[2] data[3] => dpram_5h21:FIFOram.data[3] data[4] => dpram_5h21:FIFOram.data[4] data[5] => dpram_5h21:FIFOram.data[5] data[6] => dpram_5h21:FIFOram.data[6] data[7] => dpram_5h21:FIFOram.data[7] empty <= a_fefifo_7cf:fifo_state.empty full <= a_fefifo_7cf:fifo_state.full q[0] <= dpram_5h21:FIFOram.q[0] q[1] <= dpram_5h21:FIFOram.q[1] q[2] <= dpram_5h21:FIFOram.q[2] q[3] <= dpram_5h21:FIFOram.q[3] q[4] <= dpram_5h21:FIFOram.q[4] q[5] <= dpram_5h21:FIFOram.q[5] q[6] <= dpram_5h21:FIFOram.q[6] q[7] <= dpram_5h21:FIFOram.q[7] rreq => a_fefifo_7cf:fifo_state.rreq rreq => cntr_fjb:rd_ptr_count.cnt_en sclr => a_fefifo_7cf:fifo_state.sclr sclr => cntr_fjb:rd_ptr_count.sclr sclr => cntr_fjb:wr_ptr.sclr usedw[0] <= a_fefifo_7cf:fifo_state.usedw_out[0] usedw[1] <= a_fefifo_7cf:fifo_state.usedw_out[1] usedw[2] <= a_fefifo_7cf:fifo_state.usedw_out[2] usedw[3] <= a_fefifo_7cf:fifo_state.usedw_out[3] usedw[4] <= a_fefifo_7cf:fifo_state.usedw_out[4] usedw[5] <= a_fefifo_7cf:fifo_state.usedw_out[5] wreq => a_fefifo_7cf:fifo_state.wreq wreq => dpram_5h21:FIFOram.wren wreq => cntr_fjb:wr_ptr.cnt_en |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state aclr => cntr_rj7:count_usedw.aclr clock => cntr_rj7:count_usedw.clock clock => b_full.CLK clock => b_non_empty.CLK full <= b_full.DB_MAX_OUTPUT_PORT_TYPE sclr => cntr_rj7:count_usedw.sclr usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE usedw_out[3] <= usedw[3].DB_MAX_OUTPUT_PORT_TYPE usedw_out[4] <= usedw[4].DB_MAX_OUTPUT_PORT_TYPE usedw_out[5] <= usedw[5].DB_MAX_OUTPUT_PORT_TYPE wreq => cntr_rj7:count_usedw.updown |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw aclr => counter_reg_bit1a[5].ACLR aclr => counter_reg_bit1a[4].ACLR aclr => counter_reg_bit1a[3].ACLR aclr => counter_reg_bit1a[2].ACLR aclr => counter_reg_bit1a[1].ACLR aclr => counter_reg_bit1a[0].ACLR clock => counter_reg_bit1a[5].CLK clock => counter_reg_bit1a[4].CLK clock => counter_reg_bit1a[3].CLK clock => counter_reg_bit1a[2].CLK clock => counter_reg_bit1a[1].CLK clock => counter_reg_bit1a[0].CLK q[0] <= counter_reg_bit1a[0].REGOUT q[1] <= counter_reg_bit1a[1].REGOUT q[2] <= counter_reg_bit1a[2].REGOUT q[3] <= counter_reg_bit1a[3].REGOUT q[4] <= counter_reg_bit1a[4].REGOUT q[5] <= counter_reg_bit1a[5].REGOUT updown => counter_comb_bita0.DATAB updown => counter_comb_bita1.DATAB updown => counter_comb_bita2.DATAB updown => counter_comb_bita3.DATAB updown => counter_comb_bita4.DATAB updown => counter_comb_bita5.DATAB |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram data[0] => altsyncram_9tl1:altsyncram2.data_a[0] data[1] => altsyncram_9tl1:altsyncram2.data_a[1] data[2] => altsyncram_9tl1:altsyncram2.data_a[2] data[3] => altsyncram_9tl1:altsyncram2.data_a[3] data[4] => altsyncram_9tl1:altsyncram2.data_a[4] data[5] => altsyncram_9tl1:altsyncram2.data_a[5] data[6] => altsyncram_9tl1:altsyncram2.data_a[6] data[7] => altsyncram_9tl1:altsyncram2.data_a[7] inclock => altsyncram_9tl1:altsyncram2.clock0 outclock => altsyncram_9tl1:altsyncram2.clock1 outclocken => altsyncram_9tl1:altsyncram2.clocken1 q[0] <= altsyncram_9tl1:altsyncram2.q_b[0] q[1] <= altsyncram_9tl1:altsyncram2.q_b[1] q[2] <= altsyncram_9tl1:altsyncram2.q_b[2] q[3] <= altsyncram_9tl1:altsyncram2.q_b[3] q[4] <= altsyncram_9tl1:altsyncram2.q_b[4] q[5] <= altsyncram_9tl1:altsyncram2.q_b[5] q[6] <= altsyncram_9tl1:altsyncram2.q_b[6] q[7] <= altsyncram_9tl1:altsyncram2.q_b[7] rdaddress[0] => altsyncram_9tl1:altsyncram2.address_b[0] rdaddress[1] => altsyncram_9tl1:altsyncram2.address_b[1] rdaddress[2] => altsyncram_9tl1:altsyncram2.address_b[2] rdaddress[3] => altsyncram_9tl1:altsyncram2.address_b[3] rdaddress[4] => altsyncram_9tl1:altsyncram2.address_b[4] rdaddress[5] => altsyncram_9tl1:altsyncram2.address_b[5] wraddress[0] => altsyncram_9tl1:altsyncram2.address_a[0] wraddress[1] => altsyncram_9tl1:altsyncram2.address_a[1] wraddress[2] => altsyncram_9tl1:altsyncram2.address_a[2] wraddress[3] => altsyncram_9tl1:altsyncram2.address_a[3] wraddress[4] => altsyncram_9tl1:altsyncram2.address_a[4] wraddress[5] => altsyncram_9tl1:altsyncram2.address_a[5] wren => altsyncram_9tl1:altsyncram2.wren_a |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 address_a[0] => ram_block3a0.PORTAADDR address_a[0] => ram_block3a1.PORTAADDR address_a[0] => ram_block3a2.PORTAADDR address_a[0] => ram_block3a3.PORTAADDR address_a[0] => ram_block3a4.PORTAADDR address_a[0] => ram_block3a5.PORTAADDR address_a[0] => ram_block3a6.PORTAADDR address_a[0] => ram_block3a7.PORTAADDR address_a[1] => ram_block3a0.PORTAADDR1 address_a[1] => ram_block3a1.PORTAADDR1 address_a[1] => ram_block3a2.PORTAADDR1 address_a[1] => ram_block3a3.PORTAADDR1 address_a[1] => ram_block3a4.PORTAADDR1 address_a[1] => ram_block3a5.PORTAADDR1 address_a[1] => ram_block3a6.PORTAADDR1 address_a[1] => ram_block3a7.PORTAADDR1 address_a[2] => ram_block3a0.PORTAADDR2 address_a[2] => ram_block3a1.PORTAADDR2 address_a[2] => ram_block3a2.PORTAADDR2 address_a[2] => ram_block3a3.PORTAADDR2 address_a[2] => ram_block3a4.PORTAADDR2 address_a[2] => ram_block3a5.PORTAADDR2 address_a[2] => ram_block3a6.PORTAADDR2 address_a[2] => ram_block3a7.PORTAADDR2 address_a[3] => ram_block3a0.PORTAADDR3 address_a[3] => ram_block3a1.PORTAADDR3 address_a[3] => ram_block3a2.PORTAADDR3 address_a[3] => ram_block3a3.PORTAADDR3 address_a[3] => ram_block3a4.PORTAADDR3 address_a[3] => ram_block3a5.PORTAADDR3 address_a[3] => ram_block3a6.PORTAADDR3 address_a[3] => ram_block3a7.PORTAADDR3 address_a[4] => ram_block3a0.PORTAADDR4 address_a[4] => ram_block3a1.PORTAADDR4 address_a[4] => ram_block3a2.PORTAADDR4 address_a[4] => ram_block3a3.PORTAADDR4 address_a[4] => ram_block3a4.PORTAADDR4 address_a[4] => ram_block3a5.PORTAADDR4 address_a[4] => ram_block3a6.PORTAADDR4 address_a[4] => ram_block3a7.PORTAADDR4 address_a[5] => ram_block3a0.PORTAADDR5 address_a[5] => ram_block3a1.PORTAADDR5 address_a[5] => ram_block3a2.PORTAADDR5 address_a[5] => ram_block3a3.PORTAADDR5 address_a[5] => ram_block3a4.PORTAADDR5 address_a[5] => ram_block3a5.PORTAADDR5 address_a[5] => ram_block3a6.PORTAADDR5 address_a[5] => ram_block3a7.PORTAADDR5 address_b[0] => ram_block3a0.PORTBADDR address_b[0] => ram_block3a1.PORTBADDR address_b[0] => ram_block3a2.PORTBADDR address_b[0] => ram_block3a3.PORTBADDR address_b[0] => ram_block3a4.PORTBADDR address_b[0] => ram_block3a5.PORTBADDR address_b[0] => ram_block3a6.PORTBADDR address_b[0] => ram_block3a7.PORTBADDR address_b[1] => ram_block3a0.PORTBADDR1 address_b[1] => ram_block3a1.PORTBADDR1 address_b[1] => ram_block3a2.PORTBADDR1 address_b[1] => ram_block3a3.PORTBADDR1 address_b[1] => ram_block3a4.PORTBADDR1 address_b[1] => ram_block3a5.PORTBADDR1 address_b[1] => ram_block3a6.PORTBADDR1 address_b[1] => ram_block3a7.PORTBADDR1 address_b[2] => ram_block3a0.PORTBADDR2 address_b[2] => ram_block3a1.PORTBADDR2 address_b[2] => ram_block3a2.PORTBADDR2 address_b[2] => ram_block3a3.PORTBADDR2 address_b[2] => ram_block3a4.PORTBADDR2 address_b[2] => ram_block3a5.PORTBADDR2 address_b[2] => ram_block3a6.PORTBADDR2 address_b[2] => ram_block3a7.PORTBADDR2 address_b[3] => ram_block3a0.PORTBADDR3 address_b[3] => ram_block3a1.PORTBADDR3 address_b[3] => ram_block3a2.PORTBADDR3 address_b[3] => ram_block3a3.PORTBADDR3 address_b[3] => ram_block3a4.PORTBADDR3 address_b[3] => ram_block3a5.PORTBADDR3 address_b[3] => ram_block3a6.PORTBADDR3 address_b[3] => ram_block3a7.PORTBADDR3 address_b[4] => ram_block3a0.PORTBADDR4 address_b[4] => ram_block3a1.PORTBADDR4 address_b[4] => ram_block3a2.PORTBADDR4 address_b[4] => ram_block3a3.PORTBADDR4 address_b[4] => ram_block3a4.PORTBADDR4 address_b[4] => ram_block3a5.PORTBADDR4 address_b[4] => ram_block3a6.PORTBADDR4 address_b[4] => ram_block3a7.PORTBADDR4 address_b[5] => ram_block3a0.PORTBADDR5 address_b[5] => ram_block3a1.PORTBADDR5 address_b[5] => ram_block3a2.PORTBADDR5 address_b[5] => ram_block3a3.PORTBADDR5 address_b[5] => ram_block3a4.PORTBADDR5 address_b[5] => ram_block3a5.PORTBADDR5 address_b[5] => ram_block3a6.PORTBADDR5 address_b[5] => ram_block3a7.PORTBADDR5 clock0 => ram_block3a0.CLK0 clock0 => ram_block3a1.CLK0 clock0 => ram_block3a2.CLK0 clock0 => ram_block3a3.CLK0 clock0 => ram_block3a4.CLK0 clock0 => ram_block3a5.CLK0 clock0 => ram_block3a6.CLK0 clock0 => ram_block3a7.CLK0 clock1 => ram_block3a0.CLK1 clock1 => ram_block3a1.CLK1 clock1 => ram_block3a2.CLK1 clock1 => ram_block3a3.CLK1 clock1 => ram_block3a4.CLK1 clock1 => ram_block3a5.CLK1 clock1 => ram_block3a6.CLK1 clock1 => ram_block3a7.CLK1 clocken1 => ram_block3a0.ENA1 clocken1 => ram_block3a1.ENA1 clocken1 => ram_block3a2.ENA1 clocken1 => ram_block3a3.ENA1 clocken1 => ram_block3a4.ENA1 clocken1 => ram_block3a5.ENA1 clocken1 => ram_block3a6.ENA1 clocken1 => ram_block3a7.ENA1 data_a[0] => ram_block3a0.PORTADATAIN data_a[1] => ram_block3a1.PORTADATAIN data_a[2] => ram_block3a2.PORTADATAIN data_a[3] => ram_block3a3.PORTADATAIN data_a[4] => ram_block3a4.PORTADATAIN data_a[5] => ram_block3a5.PORTADATAIN data_a[6] => ram_block3a6.PORTADATAIN data_a[7] => ram_block3a7.PORTADATAIN q_b[0] <= ram_block3a0.PORTBDATAOUT q_b[1] <= ram_block3a1.PORTBDATAOUT q_b[2] <= ram_block3a2.PORTBDATAOUT q_b[3] <= ram_block3a3.PORTBDATAOUT q_b[4] <= ram_block3a4.PORTBDATAOUT q_b[5] <= ram_block3a5.PORTBDATAOUT q_b[6] <= ram_block3a6.PORTBDATAOUT q_b[7] <= ram_block3a7.PORTBDATAOUT wren_a => ram_block3a0.ENA0 wren_a => ram_block3a1.ENA0 wren_a => ram_block3a2.ENA0 wren_a => ram_block3a3.ENA0 wren_a => ram_block3a4.ENA0 wren_a => ram_block3a5.ENA0 wren_a => ram_block3a6.ENA0 wren_a => ram_block3a7.ENA0 |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:rd_ptr_count aclr => counter_reg_bit4a[5].ACLR aclr => counter_reg_bit4a[4].ACLR aclr => counter_reg_bit4a[3].ACLR aclr => counter_reg_bit4a[2].ACLR aclr => counter_reg_bit4a[1].ACLR aclr => counter_reg_bit4a[0].ACLR clock => counter_reg_bit4a[5].CLK clock => counter_reg_bit4a[4].CLK clock => counter_reg_bit4a[3].CLK clock => counter_reg_bit4a[2].CLK clock => counter_reg_bit4a[1].CLK clock => counter_reg_bit4a[0].CLK q[0] <= counter_reg_bit4a[0].REGOUT q[1] <= counter_reg_bit4a[1].REGOUT q[2] <= counter_reg_bit4a[2].REGOUT q[3] <= counter_reg_bit4a[3].REGOUT q[4] <= counter_reg_bit4a[4].REGOUT q[5] <= counter_reg_bit4a[5].REGOUT |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:wr_ptr aclr => counter_reg_bit4a[5].ACLR aclr => counter_reg_bit4a[4].ACLR aclr => counter_reg_bit4a[3].ACLR aclr => counter_reg_bit4a[2].ACLR aclr => counter_reg_bit4a[1].ACLR aclr => counter_reg_bit4a[0].ACLR clock => counter_reg_bit4a[5].CLK clock => counter_reg_bit4a[4].CLK clock => counter_reg_bit4a[3].CLK clock => counter_reg_bit4a[2].CLK clock => counter_reg_bit4a[1].CLK clock => counter_reg_bit4a[0].CLK q[0] <= counter_reg_bit4a[0].REGOUT q[1] <= counter_reg_bit4a[1].REGOUT q[2] <= counter_reg_bit4a[2].REGOUT q[3] <= counter_reg_bit4a[3].REGOUT q[4] <= counter_reg_bit4a[4].REGOUT q[5] <= counter_reg_bit4a[5].REGOUT |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r clk => clk~0.IN1 fifo_clear => fifo_clear~0.IN1 fifo_rd => fifo_rd~0.IN1 rst_n => ~NO_FANOUT~ t_dat[0] => t_dat[0]~7.IN1 t_dat[1] => t_dat[1]~6.IN1 t_dat[2] => t_dat[2]~5.IN1 t_dat[3] => t_dat[3]~4.IN1 t_dat[4] => t_dat[4]~3.IN1 t_dat[5] => t_dat[5]~2.IN1 t_dat[6] => t_dat[6]~1.IN1 t_dat[7] => t_dat[7]~0.IN1 wr_rfifo => wr_rfifo~0.IN1 fifo_EF <= scfifo:rfifo.empty fifo_rdata[0] <= scfifo:rfifo.q fifo_rdata[1] <= scfifo:rfifo.q fifo_rdata[2] <= scfifo:rfifo.q fifo_rdata[3] <= scfifo:rfifo.q fifo_rdata[4] <= scfifo:rfifo.q fifo_rdata[5] <= scfifo:rfifo.q fifo_rdata[6] <= scfifo:rfifo.q fifo_rdata[7] <= scfifo:rfifo.q rfifo_full <= scfifo:rfifo.full rfifo_used[0] <= scfifo:rfifo.usedw rfifo_used[1] <= scfifo:rfifo.usedw rfifo_used[2] <= scfifo:rfifo.usedw rfifo_used[3] <= scfifo:rfifo.usedw rfifo_used[4] <= scfifo:rfifo.usedw rfifo_used[5] <= scfifo:rfifo.usedw |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo data[0] => scfifo_1n21:auto_generated.data[0] data[1] => scfifo_1n21:auto_generated.data[1] data[2] => scfifo_1n21:auto_generated.data[2] data[3] => scfifo_1n21:auto_generated.data[3] data[4] => scfifo_1n21:auto_generated.data[4] data[5] => scfifo_1n21:auto_generated.data[5] data[6] => scfifo_1n21:auto_generated.data[6] data[7] => scfifo_1n21:auto_generated.data[7] q[0] <= scfifo_1n21:auto_generated.q[0] q[1] <= scfifo_1n21:auto_generated.q[1] q[2] <= scfifo_1n21:auto_generated.q[2] q[3] <= scfifo_1n21:auto_generated.q[3] q[4] <= scfifo_1n21:auto_generated.q[4] q[5] <= scfifo_1n21:auto_generated.q[5] q[6] <= scfifo_1n21:auto_generated.q[6] q[7] <= scfifo_1n21:auto_generated.q[7] wrreq => scfifo_1n21:auto_generated.wrreq rdreq => scfifo_1n21:auto_generated.rdreq clock => scfifo_1n21:auto_generated.clock aclr => scfifo_1n21:auto_generated.aclr sclr => ~NO_FANOUT~ empty <= scfifo_1n21:auto_generated.empty full <= scfifo_1n21:auto_generated.full almost_full <= almost_empty <= usedw[0] <= scfifo_1n21:auto_generated.usedw[0] usedw[1] <= scfifo_1n21:auto_generated.usedw[1] usedw[2] <= scfifo_1n21:auto_generated.usedw[2] usedw[3] <= scfifo_1n21:auto_generated.usedw[3] usedw[4] <= scfifo_1n21:auto_generated.usedw[4] usedw[5] <= scfifo_1n21:auto_generated.usedw[5] |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated aclr => a_dpfifo_8t21:dpfifo.aclr clock => a_dpfifo_8t21:dpfifo.clock data[0] => a_dpfifo_8t21:dpfifo.data[0] data[1] => a_dpfifo_8t21:dpfifo.data[1] data[2] => a_dpfifo_8t21:dpfifo.data[2] data[3] => a_dpfifo_8t21:dpfifo.data[3] data[4] => a_dpfifo_8t21:dpfifo.data[4] data[5] => a_dpfifo_8t21:dpfifo.data[5] data[6] => a_dpfifo_8t21:dpfifo.data[6] data[7] => a_dpfifo_8t21:dpfifo.data[7] empty <= a_dpfifo_8t21:dpfifo.empty full <= a_dpfifo_8t21:dpfifo.full q[0] <= a_dpfifo_8t21:dpfifo.q[0] q[1] <= a_dpfifo_8t21:dpfifo.q[1] q[2] <= a_dpfifo_8t21:dpfifo.q[2] q[3] <= a_dpfifo_8t21:dpfifo.q[3] q[4] <= a_dpfifo_8t21:dpfifo.q[4] q[5] <= a_dpfifo_8t21:dpfifo.q[5] q[6] <= a_dpfifo_8t21:dpfifo.q[6] q[7] <= a_dpfifo_8t21:dpfifo.q[7] rdreq => a_dpfifo_8t21:dpfifo.rreq usedw[0] <= a_dpfifo_8t21:dpfifo.usedw[0] usedw[1] <= a_dpfifo_8t21:dpfifo.usedw[1] usedw[2] <= a_dpfifo_8t21:dpfifo.usedw[2] usedw[3] <= a_dpfifo_8t21:dpfifo.usedw[3] usedw[4] <= a_dpfifo_8t21:dpfifo.usedw[4] usedw[5] <= a_dpfifo_8t21:dpfifo.usedw[5] wrreq => a_dpfifo_8t21:dpfifo.wreq |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo aclr => a_fefifo_7cf:fifo_state.aclr aclr => cntr_fjb:rd_ptr_count.aclr aclr => cntr_fjb:wr_ptr.aclr clock => a_fefifo_7cf:fifo_state.clock clock => dpram_5h21:FIFOram.inclock clock => dpram_5h21:FIFOram.outclock clock => cntr_fjb:rd_ptr_count.clock clock => cntr_fjb:wr_ptr.clock data[0] => dpram_5h21:FIFOram.data[0] data[1] => dpram_5h21:FIFOram.data[1] data[2] => dpram_5h21:FIFOram.data[2] data[3] => dpram_5h21:FIFOram.data[3] data[4] => dpram_5h21:FIFOram.data[4] data[5] => dpram_5h21:FIFOram.data[5] data[6] => dpram_5h21:FIFOram.data[6] data[7] => dpram_5h21:FIFOram.data[7] empty <= a_fefifo_7cf:fifo_state.empty full <= a_fefifo_7cf:fifo_state.full q[0] <= dpram_5h21:FIFOram.q[0] q[1] <= dpram_5h21:FIFOram.q[1] q[2] <= dpram_5h21:FIFOram.q[2] q[3] <= dpram_5h21:FIFOram.q[3] q[4] <= dpram_5h21:FIFOram.q[4] q[5] <= dpram_5h21:FIFOram.q[5] q[6] <= dpram_5h21:FIFOram.q[6] q[7] <= dpram_5h21:FIFOram.q[7] rreq => a_fefifo_7cf:fifo_state.rreq rreq => cntr_fjb:rd_ptr_count.cnt_en sclr => a_fefifo_7cf:fifo_state.sclr sclr => cntr_fjb:rd_ptr_count.sclr sclr => cntr_fjb:wr_ptr.sclr usedw[0] <= a_fefifo_7cf:fifo_state.usedw_out[0] usedw[1] <= a_fefifo_7cf:fifo_state.usedw_out[1] usedw[2] <= a_fefifo_7cf:fifo_state.usedw_out[2] usedw[3] <= a_fefifo_7cf:fifo_state.usedw_out[3] usedw[4] <= a_fefifo_7cf:fifo_state.usedw_out[4] usedw[5] <= a_fefifo_7cf:fifo_state.usedw_out[5] wreq => a_fefifo_7cf:fifo_state.wreq wreq => dpram_5h21:FIFOram.wren wreq => cntr_fjb:wr_ptr.cnt_en |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state aclr => cntr_rj7:count_usedw.aclr clock => cntr_rj7:count_usedw.clock clock => b_full.CLK clock => b_non_empty.CLK full <= b_full.DB_MAX_OUTPUT_PORT_TYPE sclr => cntr_rj7:count_usedw.sclr usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE usedw_out[3] <= usedw[3].DB_MAX_OUTPUT_PORT_TYPE usedw_out[4] <= usedw[4].DB_MAX_OUTPUT_PORT_TYPE usedw_out[5] <= usedw[5].DB_MAX_OUTPUT_PORT_TYPE wreq => cntr_rj7:count_usedw.updown |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw aclr => counter_reg_bit1a[5].ACLR aclr => counter_reg_bit1a[4].ACLR aclr => counter_reg_bit1a[3].ACLR aclr => counter_reg_bit1a[2].ACLR aclr => counter_reg_bit1a[1].ACLR aclr => counter_reg_bit1a[0].ACLR clock => counter_reg_bit1a[5].CLK clock => counter_reg_bit1a[4].CLK clock => counter_reg_bit1a[3].CLK clock => counter_reg_bit1a[2].CLK clock => counter_reg_bit1a[1].CLK clock => counter_reg_bit1a[0].CLK q[0] <= counter_reg_bit1a[0].REGOUT q[1] <= counter_reg_bit1a[1].REGOUT q[2] <= counter_reg_bit1a[2].REGOUT q[3] <= counter_reg_bit1a[3].REGOUT q[4] <= counter_reg_bit1a[4].REGOUT q[5] <= counter_reg_bit1a[5].REGOUT updown => counter_comb_bita0.DATAB updown => counter_comb_bita1.DATAB updown => counter_comb_bita2.DATAB updown => counter_comb_bita3.DATAB updown => counter_comb_bita4.DATAB updown => counter_comb_bita5.DATAB |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram data[0] => altsyncram_9tl1:altsyncram2.data_a[0] data[1] => altsyncram_9tl1:altsyncram2.data_a[1] data[2] => altsyncram_9tl1:altsyncram2.data_a[2] data[3] => altsyncram_9tl1:altsyncram2.data_a[3] data[4] => altsyncram_9tl1:altsyncram2.data_a[4] data[5] => altsyncram_9tl1:altsyncram2.data_a[5] data[6] => altsyncram_9tl1:altsyncram2.data_a[6] data[7] => altsyncram_9tl1:altsyncram2.data_a[7] inclock => altsyncram_9tl1:altsyncram2.clock0 outclock => altsyncram_9tl1:altsyncram2.clock1 outclocken => altsyncram_9tl1:altsyncram2.clocken1 q[0] <= altsyncram_9tl1:altsyncram2.q_b[0] q[1] <= altsyncram_9tl1:altsyncram2.q_b[1] q[2] <= altsyncram_9tl1:altsyncram2.q_b[2] q[3] <= altsyncram_9tl1:altsyncram2.q_b[3] q[4] <= altsyncram_9tl1:altsyncram2.q_b[4] q[5] <= altsyncram_9tl1:altsyncram2.q_b[5] q[6] <= altsyncram_9tl1:altsyncram2.q_b[6] q[7] <= altsyncram_9tl1:altsyncram2.q_b[7] rdaddress[0] => altsyncram_9tl1:altsyncram2.address_b[0] rdaddress[1] => altsyncram_9tl1:altsyncram2.address_b[1] rdaddress[2] => altsyncram_9tl1:altsyncram2.address_b[2] rdaddress[3] => altsyncram_9tl1:altsyncram2.address_b[3] rdaddress[4] => altsyncram_9tl1:altsyncram2.address_b[4] rdaddress[5] => altsyncram_9tl1:altsyncram2.address_b[5] wraddress[0] => altsyncram_9tl1:altsyncram2.address_a[0] wraddress[1] => altsyncram_9tl1:altsyncram2.address_a[1] wraddress[2] => altsyncram_9tl1:altsyncram2.address_a[2] wraddress[3] => altsyncram_9tl1:altsyncram2.address_a[3] wraddress[4] => altsyncram_9tl1:altsyncram2.address_a[4] wraddress[5] => altsyncram_9tl1:altsyncram2.address_a[5] wren => altsyncram_9tl1:altsyncram2.wren_a |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 address_a[0] => ram_block3a0.PORTAADDR address_a[0] => ram_block3a1.PORTAADDR address_a[0] => ram_block3a2.PORTAADDR address_a[0] => ram_block3a3.PORTAADDR address_a[0] => ram_block3a4.PORTAADDR address_a[0] => ram_block3a5.PORTAADDR address_a[0] => ram_block3a6.PORTAADDR address_a[0] => ram_block3a7.PORTAADDR address_a[1] => ram_block3a0.PORTAADDR1 address_a[1] => ram_block3a1.PORTAADDR1 address_a[1] => ram_block3a2.PORTAADDR1 address_a[1] => ram_block3a3.PORTAADDR1 address_a[1] => ram_block3a4.PORTAADDR1 address_a[1] => ram_block3a5.PORTAADDR1 address_a[1] => ram_block3a6.PORTAADDR1 address_a[1] => ram_block3a7.PORTAADDR1 address_a[2] => ram_block3a0.PORTAADDR2 address_a[2] => ram_block3a1.PORTAADDR2 address_a[2] => ram_block3a2.PORTAADDR2 address_a[2] => ram_block3a3.PORTAADDR2 address_a[2] => ram_block3a4.PORTAADDR2 address_a[2] => ram_block3a5.PORTAADDR2 address_a[2] => ram_block3a6.PORTAADDR2 address_a[2] => ram_block3a7.PORTAADDR2 address_a[3] => ram_block3a0.PORTAADDR3 address_a[3] => ram_block3a1.PORTAADDR3 address_a[3] => ram_block3a2.PORTAADDR3 address_a[3] => ram_block3a3.PORTAADDR3 address_a[3] => ram_block3a4.PORTAADDR3 address_a[3] => ram_block3a5.PORTAADDR3 address_a[3] => ram_block3a6.PORTAADDR3 address_a[3] => ram_block3a7.PORTAADDR3 address_a[4] => ram_block3a0.PORTAADDR4 address_a[4] => ram_block3a1.PORTAADDR4 address_a[4] => ram_block3a2.PORTAADDR4 address_a[4] => ram_block3a3.PORTAADDR4 address_a[4] => ram_block3a4.PORTAADDR4 address_a[4] => ram_block3a5.PORTAADDR4 address_a[4] => ram_block3a6.PORTAADDR4 address_a[4] => ram_block3a7.PORTAADDR4 address_a[5] => ram_block3a0.PORTAADDR5 address_a[5] => ram_block3a1.PORTAADDR5 address_a[5] => ram_block3a2.PORTAADDR5 address_a[5] => ram_block3a3.PORTAADDR5 address_a[5] => ram_block3a4.PORTAADDR5 address_a[5] => ram_block3a5.PORTAADDR5 address_a[5] => ram_block3a6.PORTAADDR5 address_a[5] => ram_block3a7.PORTAADDR5 address_b[0] => ram_block3a0.PORTBADDR address_b[0] => ram_block3a1.PORTBADDR address_b[0] => ram_block3a2.PORTBADDR address_b[0] => ram_block3a3.PORTBADDR address_b[0] => ram_block3a4.PORTBADDR address_b[0] => ram_block3a5.PORTBADDR address_b[0] => ram_block3a6.PORTBADDR address_b[0] => ram_block3a7.PORTBADDR address_b[1] => ram_block3a0.PORTBADDR1 address_b[1] => ram_block3a1.PORTBADDR1 address_b[1] => ram_block3a2.PORTBADDR1 address_b[1] => ram_block3a3.PORTBADDR1 address_b[1] => ram_block3a4.PORTBADDR1 address_b[1] => ram_block3a5.PORTBADDR1 address_b[1] => ram_block3a6.PORTBADDR1 address_b[1] => ram_block3a7.PORTBADDR1 address_b[2] => ram_block3a0.PORTBADDR2 address_b[2] => ram_block3a1.PORTBADDR2 address_b[2] => ram_block3a2.PORTBADDR2 address_b[2] => ram_block3a3.PORTBADDR2 address_b[2] => ram_block3a4.PORTBADDR2 address_b[2] => ram_block3a5.PORTBADDR2 address_b[2] => ram_block3a6.PORTBADDR2 address_b[2] => ram_block3a7.PORTBADDR2 address_b[3] => ram_block3a0.PORTBADDR3 address_b[3] => ram_block3a1.PORTBADDR3 address_b[3] => ram_block3a2.PORTBADDR3 address_b[3] => ram_block3a3.PORTBADDR3 address_b[3] => ram_block3a4.PORTBADDR3 address_b[3] => ram_block3a5.PORTBADDR3 address_b[3] => ram_block3a6.PORTBADDR3 address_b[3] => ram_block3a7.PORTBADDR3 address_b[4] => ram_block3a0.PORTBADDR4 address_b[4] => ram_block3a1.PORTBADDR4 address_b[4] => ram_block3a2.PORTBADDR4 address_b[4] => ram_block3a3.PORTBADDR4 address_b[4] => ram_block3a4.PORTBADDR4 address_b[4] => ram_block3a5.PORTBADDR4 address_b[4] => ram_block3a6.PORTBADDR4 address_b[4] => ram_block3a7.PORTBADDR4 address_b[5] => ram_block3a0.PORTBADDR5 address_b[5] => ram_block3a1.PORTBADDR5 address_b[5] => ram_block3a2.PORTBADDR5 address_b[5] => ram_block3a3.PORTBADDR5 address_b[5] => ram_block3a4.PORTBADDR5 address_b[5] => ram_block3a5.PORTBADDR5 address_b[5] => ram_block3a6.PORTBADDR5 address_b[5] => ram_block3a7.PORTBADDR5 clock0 => ram_block3a0.CLK0 clock0 => ram_block3a1.CLK0 clock0 => ram_block3a2.CLK0 clock0 => ram_block3a3.CLK0 clock0 => ram_block3a4.CLK0 clock0 => ram_block3a5.CLK0 clock0 => ram_block3a6.CLK0 clock0 => ram_block3a7.CLK0 clock1 => ram_block3a0.CLK1 clock1 => ram_block3a1.CLK1 clock1 => ram_block3a2.CLK1 clock1 => ram_block3a3.CLK1 clock1 => ram_block3a4.CLK1 clock1 => ram_block3a5.CLK1 clock1 => ram_block3a6.CLK1 clock1 => ram_block3a7.CLK1 clocken1 => ram_block3a0.ENA1 clocken1 => ram_block3a1.ENA1 clocken1 => ram_block3a2.ENA1 clocken1 => ram_block3a3.ENA1 clocken1 => ram_block3a4.ENA1 clocken1 => ram_block3a5.ENA1 clocken1 => ram_block3a6.ENA1 clocken1 => ram_block3a7.ENA1 data_a[0] => ram_block3a0.PORTADATAIN data_a[1] => ram_block3a1.PORTADATAIN data_a[2] => ram_block3a2.PORTADATAIN data_a[3] => ram_block3a3.PORTADATAIN data_a[4] => ram_block3a4.PORTADATAIN data_a[5] => ram_block3a5.PORTADATAIN data_a[6] => ram_block3a6.PORTADATAIN data_a[7] => ram_block3a7.PORTADATAIN q_b[0] <= ram_block3a0.PORTBDATAOUT q_b[1] <= ram_block3a1.PORTBDATAOUT q_b[2] <= ram_block3a2.PORTBDATAOUT q_b[3] <= ram_block3a3.PORTBDATAOUT q_b[4] <= ram_block3a4.PORTBDATAOUT q_b[5] <= ram_block3a5.PORTBDATAOUT q_b[6] <= ram_block3a6.PORTBDATAOUT q_b[7] <= ram_block3a7.PORTBDATAOUT wren_a => ram_block3a0.ENA0 wren_a => ram_block3a1.ENA0 wren_a => ram_block3a2.ENA0 wren_a => ram_block3a3.ENA0 wren_a => ram_block3a4.ENA0 wren_a => ram_block3a5.ENA0 wren_a => ram_block3a6.ENA0 wren_a => ram_block3a7.ENA0 |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:rd_ptr_count aclr => counter_reg_bit4a[5].ACLR aclr => counter_reg_bit4a[4].ACLR aclr => counter_reg_bit4a[3].ACLR aclr => counter_reg_bit4a[2].ACLR aclr => counter_reg_bit4a[1].ACLR aclr => counter_reg_bit4a[0].ACLR clock => counter_reg_bit4a[5].CLK clock => counter_reg_bit4a[4].CLK clock => counter_reg_bit4a[3].CLK clock => counter_reg_bit4a[2].CLK clock => counter_reg_bit4a[1].CLK clock => counter_reg_bit4a[0].CLK q[0] <= counter_reg_bit4a[0].REGOUT q[1] <= counter_reg_bit4a[1].REGOUT q[2] <= counter_reg_bit4a[2].REGOUT q[3] <= counter_reg_bit4a[3].REGOUT q[4] <= counter_reg_bit4a[4].REGOUT q[5] <= counter_reg_bit4a[5].REGOUT |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:wr_ptr aclr => counter_reg_bit4a[5].ACLR aclr => counter_reg_bit4a[4].ACLR aclr => counter_reg_bit4a[3].ACLR aclr => counter_reg_bit4a[2].ACLR aclr => counter_reg_bit4a[1].ACLR aclr => counter_reg_bit4a[0].ACLR clock => counter_reg_bit4a[5].CLK clock => counter_reg_bit4a[4].CLK clock => counter_reg_bit4a[3].CLK clock => counter_reg_bit4a[2].CLK clock => counter_reg_bit4a[1].CLK clock => counter_reg_bit4a[0].CLK q[0] <= counter_reg_bit4a[0].REGOUT q[1] <= counter_reg_bit4a[1].REGOUT q[2] <= counter_reg_bit4a[2].REGOUT q[3] <= counter_reg_bit4a[3].REGOUT q[4] <= counter_reg_bit4a[4].REGOUT q[5] <= counter_reg_bit4a[5].REGOUT |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic raw_tck => td_shift[10].CLK raw_tck => td_shift[9].CLK raw_tck => td_shift[8].CLK raw_tck => td_shift[7].CLK raw_tck => td_shift[6].CLK raw_tck => td_shift[5].CLK raw_tck => td_shift[4].CLK raw_tck => td_shift[3].CLK raw_tck => td_shift[2].CLK raw_tck => td_shift[1].CLK raw_tck => td_shift[0].CLK raw_tck => user_saw_rvalid.CLK raw_tck => state.CLK raw_tck => count[9].CLK raw_tck => count[8].CLK raw_tck => count[7].CLK raw_tck => count[6].CLK raw_tck => count[5].CLK raw_tck => count[4].CLK raw_tck => count[3].CLK raw_tck => count[2].CLK raw_tck => count[1].CLK raw_tck => count[0].CLK raw_tck => write_valid.CLK raw_tck => read_req.CLK raw_tck => read_write.CLK raw_tck => wdata[7].CLK raw_tck => wdata[6].CLK raw_tck => wdata[5].CLK raw_tck => wdata[4].CLK raw_tck => wdata[3].CLK raw_tck => wdata[2].CLK raw_tck => wdata[1].CLK raw_tck => wdata[0].CLK raw_tck => write_stalled.CLK raw_tck => jupdate.CLK tck => ~NO_FANOUT~ tdi => td_shift~54.DATAB tdi => wdata~7.DATAB tdi => always0~2.IN1 tdi => wdata~0.DATAB tdi => state~1.OUTPUTSELECT tdi => count~10.OUTPUTSELECT tdi => td_shift~21.OUTPUTSELECT rti => ~NO_FANOUT~ shift => ~NO_FANOUT~ update => ~NO_FANOUT~ usr1 => always0~0.IN0 clrn => jupdate.ACLR clrn => td_shift[10].ACLR clrn => td_shift[9].ACLR clrn => td_shift[8].ACLR clrn => td_shift[7].ACLR clrn => td_shift[6].ACLR clrn => td_shift[5].ACLR clrn => td_shift[4].ACLR clrn => td_shift[3].ACLR clrn => td_shift[2].ACLR clrn => td_shift[1].ACLR clrn => td_shift[0].ACLR clrn => user_saw_rvalid.ACLR clrn => state.ACLR clrn => count[9].PRESET clrn => count[8].ACLR clrn => count[7].ACLR clrn => count[6].ACLR clrn => count[5].ACLR clrn => count[4].ACLR clrn => count[3].ACLR clrn => count[2].ACLR clrn => count[1].ACLR clrn => count[0].ACLR clrn => write_valid.ACLR clrn => read_req.ACLR clrn => read_write.ACLR clrn => wdata[7].ACLR clrn => wdata[6].ACLR clrn => wdata[5].ACLR clrn => wdata[4].ACLR clrn => wdata[3].ACLR clrn => wdata[2].ACLR clrn => wdata[1].ACLR clrn => wdata[0].ACLR clrn => write_stalled.ACLR ena => always0~0.IN1 ir_in[0] => Decoder1.IN0 ir_in[0] => ir_out[0].DATAIN tdo <= td_shift[0].DB_MAX_OUTPUT_PORT_TYPE irq <= ir_out[0] <= ir_in[0].DB_MAX_OUTPUT_PORT_TYPE jtag_state_cdr => td_shift~10.OUTPUTSELECT jtag_state_cdr => td_shift~9.OUTPUTSELECT jtag_state_cdr => td_shift~8.OUTPUTSELECT jtag_state_cdr => td_shift~7.OUTPUTSELECT jtag_state_cdr => td_shift~6.OUTPUTSELECT jtag_state_cdr => td_shift~5.OUTPUTSELECT jtag_state_cdr => td_shift~4.OUTPUTSELECT jtag_state_cdr => td_shift~3.OUTPUTSELECT jtag_state_cdr => td_shift~2.OUTPUTSELECT jtag_state_cdr => td_shift~1.OUTPUTSELECT jtag_state_cdr => td_shift~0.OUTPUTSELECT jtag_state_cdr => count~9.OUTPUTSELECT jtag_state_cdr => count~8.OUTPUTSELECT jtag_state_cdr => count~7.OUTPUTSELECT jtag_state_cdr => count~6.OUTPUTSELECT jtag_state_cdr => count~5.OUTPUTSELECT jtag_state_cdr => count~4.OUTPUTSELECT jtag_state_cdr => count~3.OUTPUTSELECT jtag_state_cdr => count~2.OUTPUTSELECT jtag_state_cdr => count~1.OUTPUTSELECT jtag_state_cdr => count~0.OUTPUTSELECT jtag_state_cdr => state~0.OUTPUTSELECT jtag_state_sdr => state~4.OUTPUTSELECT jtag_state_sdr => write_stalled~5.OUTPUTSELECT jtag_state_sdr => read_req~3.OUTPUTSELECT jtag_state_sdr => write_valid~3.OUTPUTSELECT jtag_state_sdr => user_saw_rvalid~3.OUTPUTSELECT jtag_state_sdr => wdata~31.OUTPUTSELECT jtag_state_sdr => wdata~30.OUTPUTSELECT jtag_state_sdr => wdata~29.OUTPUTSELECT jtag_state_sdr => wdata~28.OUTPUTSELECT jtag_state_sdr => wdata~27.OUTPUTSELECT jtag_state_sdr => wdata~26.OUTPUTSELECT jtag_state_sdr => wdata~25.OUTPUTSELECT jtag_state_sdr => wdata~24.OUTPUTSELECT jtag_state_sdr => read_write~3.OUTPUTSELECT jtag_state_sdr => td_shift~64.OUTPUTSELECT jtag_state_sdr => td_shift~63.OUTPUTSELECT jtag_state_sdr => td_shift~62.OUTPUTSELECT jtag_state_sdr => td_shift~61.OUTPUTSELECT jtag_state_sdr => td_shift~60.OUTPUTSELECT jtag_state_sdr => td_shift~59.OUTPUTSELECT jtag_state_sdr => td_shift~58.OUTPUTSELECT jtag_state_sdr => td_shift~57.OUTPUTSELECT jtag_state_sdr => td_shift~56.OUTPUTSELECT jtag_state_sdr => td_shift~55.OUTPUTSELECT jtag_state_sdr => td_shift~54.OUTPUTSELECT jtag_state_sdr => count~22.OUTPUTSELECT jtag_state_sdr => count~21.OUTPUTSELECT jtag_state_sdr => count~20.OUTPUTSELECT jtag_state_sdr => count~19.OUTPUTSELECT jtag_state_sdr => count~18.OUTPUTSELECT jtag_state_sdr => count~17.OUTPUTSELECT jtag_state_sdr => count~16.OUTPUTSELECT jtag_state_sdr => count~15.OUTPUTSELECT jtag_state_sdr => count~14.OUTPUTSELECT jtag_state_sdr => count~13.OUTPUTSELECT jtag_state_udr => jupdate~1.OUTPUTSELECT clk => rst1.CLK clk => rst2.CLK clk => read_write1.CLK clk => read_write2.CLK clk => jupdate1.CLK clk => jupdate2.CLK clk => r_ena1.CLK clk => rvalid0.CLK clk => rvalid.CLK clk => rdata[7].CLK clk => rdata[6].CLK clk => rdata[5].CLK clk => rdata[4].CLK clk => rdata[3].CLK clk => rdata[2].CLK clk => rdata[1].CLK clk => rdata[0].CLK clk => t_ena~reg0.CLK clk => t_pause~reg0.CLK rst_n => rst1.PRESET rst_n => rst2.PRESET rst_n => read_write1.ACLR rst_n => read_write2.ACLR rst_n => jupdate1.ACLR rst_n => jupdate2.ACLR rst_n => r_ena1.ACLR rst_n => rvalid0.ACLR rst_n => rvalid.ACLR rst_n => rdata[7].ACLR rst_n => rdata[6].ACLR rst_n => rdata[5].ACLR rst_n => rdata[4].ACLR rst_n => rdata[3].ACLR rst_n => rdata[2].ACLR rst_n => rdata[1].ACLR rst_n => rdata[0].ACLR rst_n => t_ena~reg0.ACLR rst_n => t_pause~reg0.ACLR r_ena <= r_ena~1.DB_MAX_OUTPUT_PORT_TYPE r_val => r_ena~0.IN1 r_dat[0] => rdata[0].DATAIN r_dat[1] => rdata[1].DATAIN r_dat[2] => rdata[2].DATAIN r_dat[3] => rdata[3].DATAIN r_dat[4] => rdata[4].DATAIN r_dat[5] => rdata[5].DATAIN r_dat[6] => rdata[6].DATAIN r_dat[7] => rdata[7].DATAIN t_dav => always2~5.IN1 t_dav => td_shift~29.DATAB t_dav => always0~1.IN1 t_ena <= t_ena~reg0.DB_MAX_OUTPUT_PORT_TYPE t_dat[0] <= wdata[0].DB_MAX_OUTPUT_PORT_TYPE t_dat[1] <= wdata[1].DB_MAX_OUTPUT_PORT_TYPE t_dat[2] <= wdata[2].DB_MAX_OUTPUT_PORT_TYPE t_dat[3] <= wdata[3].DB_MAX_OUTPUT_PORT_TYPE t_dat[4] <= wdata[4].DB_MAX_OUTPUT_PORT_TYPE t_dat[5] <= wdata[5].DB_MAX_OUTPUT_PORT_TYPE t_dat[6] <= wdata[6].DB_MAX_OUTPUT_PORT_TYPE t_dat[7] <= wdata[7].DB_MAX_OUTPUT_PORT_TYPE t_pause <= t_pause~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1 clk => clk~0.IN2 cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[2] => sdram_0_s1_address~20.DATAB cpu_0_data_master_address_to_slave[3] => sdram_0_s1_address~19.DATAB cpu_0_data_master_address_to_slave[4] => sdram_0_s1_address~18.DATAB cpu_0_data_master_address_to_slave[5] => sdram_0_s1_address~17.DATAB cpu_0_data_master_address_to_slave[6] => sdram_0_s1_address~16.DATAB cpu_0_data_master_address_to_slave[7] => sdram_0_s1_address~15.DATAB cpu_0_data_master_address_to_slave[8] => sdram_0_s1_address~14.DATAB cpu_0_data_master_address_to_slave[9] => sdram_0_s1_address~13.DATAB cpu_0_data_master_address_to_slave[10] => sdram_0_s1_address~12.DATAB cpu_0_data_master_address_to_slave[11] => sdram_0_s1_address~11.DATAB cpu_0_data_master_address_to_slave[12] => sdram_0_s1_address~10.DATAB cpu_0_data_master_address_to_slave[13] => sdram_0_s1_address~9.DATAB cpu_0_data_master_address_to_slave[14] => sdram_0_s1_address~8.DATAB cpu_0_data_master_address_to_slave[15] => sdram_0_s1_address~7.DATAB cpu_0_data_master_address_to_slave[16] => sdram_0_s1_address~6.DATAB cpu_0_data_master_address_to_slave[17] => sdram_0_s1_address~5.DATAB cpu_0_data_master_address_to_slave[18] => sdram_0_s1_address~4.DATAB cpu_0_data_master_address_to_slave[19] => sdram_0_s1_address~3.DATAB cpu_0_data_master_address_to_slave[20] => sdram_0_s1_address~2.DATAB cpu_0_data_master_address_to_slave[21] => sdram_0_s1_address~1.DATAB cpu_0_data_master_address_to_slave[22] => sdram_0_s1_address~0.DATAB cpu_0_data_master_address_to_slave[23] => cpu_0_data_master_requests_sdram_0_s1~1.IN1 cpu_0_data_master_byteenable[0] => cpu_0_data_master_byteenable_sdram_0_s1~1.DATAB cpu_0_data_master_byteenable[1] => cpu_0_data_master_byteenable_sdram_0_s1~0.DATAB cpu_0_data_master_byteenable[2] => cpu_0_data_master_byteenable_sdram_0_s1~1.DATAA cpu_0_data_master_byteenable[3] => cpu_0_data_master_byteenable_sdram_0_s1~0.DATAA cpu_0_data_master_dbs_address[0] => ~NO_FANOUT~ cpu_0_data_master_dbs_address[1] => sdram_0_s1_address~21.DATAB cpu_0_data_master_dbs_address[1] => cpu_0_data_master_byteenable_sdram_0_s1~1.OUTPUTSELECT cpu_0_data_master_dbs_address[1] => cpu_0_data_master_byteenable_sdram_0_s1~0.OUTPUTSELECT cpu_0_data_master_dbs_write_16[0] => sdram_0_s1_writedata[0].DATAIN cpu_0_data_master_dbs_write_16[1] => sdram_0_s1_writedata[1].DATAIN cpu_0_data_master_dbs_write_16[2] => sdram_0_s1_writedata[2].DATAIN cpu_0_data_master_dbs_write_16[3] => sdram_0_s1_writedata[3].DATAIN cpu_0_data_master_dbs_write_16[4] => sdram_0_s1_writedata[4].DATAIN cpu_0_data_master_dbs_write_16[5] => sdram_0_s1_writedata[5].DATAIN cpu_0_data_master_dbs_write_16[6] => sdram_0_s1_writedata[6].DATAIN cpu_0_data_master_dbs_write_16[7] => sdram_0_s1_writedata[7].DATAIN cpu_0_data_master_dbs_write_16[8] => sdram_0_s1_writedata[8].DATAIN cpu_0_data_master_dbs_write_16[9] => sdram_0_s1_writedata[9].DATAIN cpu_0_data_master_dbs_write_16[10] => sdram_0_s1_writedata[10].DATAIN cpu_0_data_master_dbs_write_16[11] => sdram_0_s1_writedata[11].DATAIN cpu_0_data_master_dbs_write_16[12] => sdram_0_s1_writedata[12].DATAIN cpu_0_data_master_dbs_write_16[13] => sdram_0_s1_writedata[13].DATAIN cpu_0_data_master_dbs_write_16[14] => sdram_0_s1_writedata[14].DATAIN cpu_0_data_master_dbs_write_16[15] => sdram_0_s1_writedata[15].DATAIN cpu_0_data_master_no_byte_enables_and_last_term => cpu_0_data_master_qualified_request_sdram_0_s1~2.IN1 cpu_0_data_master_read => sdram_0_s1_in_a_read_cycle~0.IN1 cpu_0_data_master_read => cpu_0_data_master_qualified_request_sdram_0_s1~1.IN0 cpu_0_data_master_read => cpu_0_data_master_requests_sdram_0_s1~0.IN0 cpu_0_data_master_waitrequest => cpu_0_data_master_qualified_request_sdram_0_s1~0.IN1 cpu_0_data_master_waitrequest => cpu_0_data_master_qualified_request_sdram_0_s1~2.IN0 cpu_0_data_master_write => sdram_0_s1_in_a_write_cycle.IN1 cpu_0_data_master_write => cpu_0_data_master_qualified_request_sdram_0_s1~4.IN0 cpu_0_data_master_write => cpu_0_data_master_requests_sdram_0_s1~0.IN1 cpu_0_instruction_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_instruction_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_instruction_master_address_to_slave[2] => sdram_0_s1_address~20.DATAA cpu_0_instruction_master_address_to_slave[3] => sdram_0_s1_address~19.DATAA cpu_0_instruction_master_address_to_slave[4] => sdram_0_s1_address~18.DATAA cpu_0_instruction_master_address_to_slave[5] => sdram_0_s1_address~17.DATAA cpu_0_instruction_master_address_to_slave[6] => sdram_0_s1_address~16.DATAA cpu_0_instruction_master_address_to_slave[7] => sdram_0_s1_address~15.DATAA cpu_0_instruction_master_address_to_slave[8] => sdram_0_s1_address~14.DATAA cpu_0_instruction_master_address_to_slave[9] => sdram_0_s1_address~13.DATAA cpu_0_instruction_master_address_to_slave[10] => sdram_0_s1_address~12.DATAA cpu_0_instruction_master_address_to_slave[11] => sdram_0_s1_address~11.DATAA cpu_0_instruction_master_address_to_slave[12] => sdram_0_s1_address~10.DATAA cpu_0_instruction_master_address_to_slave[13] => sdram_0_s1_address~9.DATAA cpu_0_instruction_master_address_to_slave[14] => sdram_0_s1_address~8.DATAA cpu_0_instruction_master_address_to_slave[15] => sdram_0_s1_address~7.DATAA cpu_0_instruction_master_address_to_slave[16] => sdram_0_s1_address~6.DATAA cpu_0_instruction_master_address_to_slave[17] => sdram_0_s1_address~5.DATAA cpu_0_instruction_master_address_to_slave[18] => sdram_0_s1_address~4.DATAA cpu_0_instruction_master_address_to_slave[19] => sdram_0_s1_address~3.DATAA cpu_0_instruction_master_address_to_slave[20] => sdram_0_s1_address~2.DATAA cpu_0_instruction_master_address_to_slave[21] => sdram_0_s1_address~1.DATAA cpu_0_instruction_master_address_to_slave[22] => sdram_0_s1_address~0.DATAA cpu_0_instruction_master_address_to_slave[23] => cpu_0_instruction_master_requests_sdram_0_s1~0.IN1 cpu_0_instruction_master_dbs_address[0] => ~NO_FANOUT~ cpu_0_instruction_master_dbs_address[1] => sdram_0_s1_address~21.DATAA cpu_0_instruction_master_latency_counter[0] => LessThan0.IN4 cpu_0_instruction_master_latency_counter[0] => Equal0.IN31 cpu_0_instruction_master_latency_counter[1] => LessThan0.IN3 cpu_0_instruction_master_latency_counter[1] => Equal0.IN30 cpu_0_instruction_master_read => sdram_0_s1_in_a_read_cycle~1.IN1 cpu_0_instruction_master_read => cpu_0_instruction_master_qualified_request_sdram_0_s1~1.IN0 cpu_0_instruction_master_read => cpu_0_instruction_master_requests_sdram_0_s1~1.IN0 cpu_0_instruction_master_read => cpu_0_instruction_master_requests_sdram_0_s1~0.IN0 reset_n => reset_n~0.IN2 sdram_0_s1_readdata[0] => sdram_0_s1_readdata_from_sa[0].DATAIN sdram_0_s1_readdata[1] => sdram_0_s1_readdata_from_sa[1].DATAIN sdram_0_s1_readdata[2] => sdram_0_s1_readdata_from_sa[2].DATAIN sdram_0_s1_readdata[3] => sdram_0_s1_readdata_from_sa[3].DATAIN sdram_0_s1_readdata[4] => sdram_0_s1_readdata_from_sa[4].DATAIN sdram_0_s1_readdata[5] => sdram_0_s1_readdata_from_sa[5].DATAIN sdram_0_s1_readdata[6] => sdram_0_s1_readdata_from_sa[6].DATAIN sdram_0_s1_readdata[7] => sdram_0_s1_readdata_from_sa[7].DATAIN sdram_0_s1_readdata[8] => sdram_0_s1_readdata_from_sa[8].DATAIN sdram_0_s1_readdata[9] => sdram_0_s1_readdata_from_sa[9].DATAIN sdram_0_s1_readdata[10] => sdram_0_s1_readdata_from_sa[10].DATAIN sdram_0_s1_readdata[11] => sdram_0_s1_readdata_from_sa[11].DATAIN sdram_0_s1_readdata[12] => sdram_0_s1_readdata_from_sa[12].DATAIN sdram_0_s1_readdata[13] => sdram_0_s1_readdata_from_sa[13].DATAIN sdram_0_s1_readdata[14] => sdram_0_s1_readdata_from_sa[14].DATAIN sdram_0_s1_readdata[15] => sdram_0_s1_readdata_from_sa[15].DATAIN sdram_0_s1_readdatavalid => sdram_0_s1_move_on_to_next_transaction.IN2 sdram_0_s1_waitrequest => sdram_0_s1_waits_for_write.IN0 sdram_0_s1_waitrequest => sdram_0_s1_waits_for_read.IN0 sdram_0_s1_waitrequest => sdram_0_s1_waitrequest_from_sa.DATAIN cpu_0_data_master_byteenable_sdram_0_s1[0] <= cpu_0_data_master_byteenable_sdram_0_s1~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_byteenable_sdram_0_s1[1] <= cpu_0_data_master_byteenable_sdram_0_s1~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_granted_sdram_0_s1 <= cpu_0_data_master_granted_sdram_0_s1~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_qualified_request_sdram_0_s1 <= cpu_0_data_master_qualified_request_sdram_0_s1~7.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_read_data_valid_sdram_0_s1 <= cpu_0_data_master_read_data_valid_sdram_0_s1~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register <= rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1.fifo_contains_ones_n cpu_0_data_master_requests_sdram_0_s1 <= cpu_0_data_master_requests_sdram_0_s1~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_granted_sdram_0_s1 <= cpu_0_instruction_master_granted_sdram_0_s1~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_qualified_request_sdram_0_s1 <= cpu_0_instruction_master_qualified_request_sdram_0_s1~3.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_read_data_valid_sdram_0_s1 <= cpu_0_instruction_master_read_data_valid_sdram_0_s1~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register <= rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1.fifo_contains_ones_n cpu_0_instruction_master_requests_sdram_0_s1 <= cpu_0_instruction_master_requests_sdram_0_s1~1.DB_MAX_OUTPUT_PORT_TYPE d1_sdram_0_s1_end_xfer <= d1_sdram_0_s1_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[0] <= sdram_0_s1_address~21.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[1] <= sdram_0_s1_address~20.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[2] <= sdram_0_s1_address~19.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[3] <= sdram_0_s1_address~18.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[4] <= sdram_0_s1_address~17.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[5] <= sdram_0_s1_address~16.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[6] <= sdram_0_s1_address~15.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[7] <= sdram_0_s1_address~14.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[8] <= sdram_0_s1_address~13.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[9] <= sdram_0_s1_address~12.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[10] <= sdram_0_s1_address~11.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[11] <= sdram_0_s1_address~10.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[12] <= sdram_0_s1_address~9.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[13] <= sdram_0_s1_address~8.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[14] <= sdram_0_s1_address~7.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[15] <= sdram_0_s1_address~6.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[16] <= sdram_0_s1_address~5.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[17] <= sdram_0_s1_address~4.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[18] <= sdram_0_s1_address~3.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[19] <= sdram_0_s1_address~2.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[20] <= sdram_0_s1_address~1.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_address[21] <= sdram_0_s1_address~0.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_byteenable_n[0] <= sdram_0_s1_byteenable_n~1.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_byteenable_n[1] <= sdram_0_s1_byteenable_n~0.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_chipselect <= sdram_0_s1_chipselect~0.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_read_n <= sdram_0_s1_in_a_read_cycle.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[0] <= sdram_0_s1_readdata[0].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[1] <= sdram_0_s1_readdata[1].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[2] <= sdram_0_s1_readdata[2].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[3] <= sdram_0_s1_readdata[3].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[4] <= sdram_0_s1_readdata[4].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[5] <= sdram_0_s1_readdata[5].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[6] <= sdram_0_s1_readdata[6].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[7] <= sdram_0_s1_readdata[7].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[8] <= sdram_0_s1_readdata[8].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[9] <= sdram_0_s1_readdata[9].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[10] <= sdram_0_s1_readdata[10].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[11] <= sdram_0_s1_readdata[11].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[12] <= sdram_0_s1_readdata[12].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[13] <= sdram_0_s1_readdata[13].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[14] <= sdram_0_s1_readdata[14].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_readdata_from_sa[15] <= sdram_0_s1_readdata[15].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_reset_n <= reset_n~0.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_waitrequest_from_sa <= sdram_0_s1_waitrequest.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_write_n <= sdram_0_s1_in_a_write_cycle.DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[0] <= cpu_0_data_master_dbs_write_16[0].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[1] <= cpu_0_data_master_dbs_write_16[1].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[2] <= cpu_0_data_master_dbs_write_16[2].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[3] <= cpu_0_data_master_dbs_write_16[3].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[4] <= cpu_0_data_master_dbs_write_16[4].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[5] <= cpu_0_data_master_dbs_write_16[5].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[6] <= cpu_0_data_master_dbs_write_16[6].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[7] <= cpu_0_data_master_dbs_write_16[7].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[8] <= cpu_0_data_master_dbs_write_16[8].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[9] <= cpu_0_data_master_dbs_write_16[9].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[10] <= cpu_0_data_master_dbs_write_16[10].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[11] <= cpu_0_data_master_dbs_write_16[11].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[12] <= cpu_0_data_master_dbs_write_16[12].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[13] <= cpu_0_data_master_dbs_write_16[13].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[14] <= cpu_0_data_master_dbs_write_16[14].DB_MAX_OUTPUT_PORT_TYPE sdram_0_s1_writedata[15] <= cpu_0_data_master_dbs_write_16[15].DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1 clear_fifo => always13~0.IN1 clear_fifo => always12~0.IN1 clear_fifo => full_1~0.OUTPUTSELECT clear_fifo => full_2~0.OUTPUTSELECT clear_fifo => full_3~0.OUTPUTSELECT clear_fifo => full_4~0.OUTPUTSELECT clear_fifo => full_5~0.OUTPUTSELECT clear_fifo => full_6~0.OUTPUTSELECT clear_fifo => always1~1.IN0 clear_fifo => p1_stage_1~0.IN1 clear_fifo => p2_stage_2~0.IN1 clear_fifo => p3_stage_3~0.IN1 clear_fifo => p4_stage_4~0.IN1 clear_fifo => p5_stage_5~0.IN1 clear_fifo => p0_stage_0~0.IN1 clk => stage_6.CLK clk => full_6.CLK clk => stage_5.CLK clk => full_5.CLK clk => stage_4.CLK clk => full_4.CLK clk => stage_3.CLK clk => full_3.CLK clk => stage_2.CLK clk => full_2.CLK clk => stage_1.CLK clk => full_1.CLK clk => stage_0.CLK clk => full_0.CLK clk => how_many_ones[3].CLK clk => how_many_ones[2].CLK clk => how_many_ones[1].CLK clk => how_many_ones[0].CLK clk => fifo_contains_ones_n~reg0.CLK data_in => stage_6~0.DATAA data_in => updated_one_count~22.DATAB data_in => updated_one_count~5.IN0 data_in => updated_one_count~2.IN0 data_in => p0_stage_0.DATAB data_in => p1_stage_1.DATAB data_in => p2_stage_2.DATAB data_in => p3_stage_3.DATAB data_in => p4_stage_4.DATAB data_in => p5_stage_5.DATAB read => always0~3.IN0 read => updated_one_count~6.IN1 read => updated_one_count~2.IN1 read => always12~5.IN1 read => always12~1.IN0 read => always10~3.IN1 read => always8~3.IN1 read => always6~3.IN1 read => always4~3.IN1 read => always2~3.IN1 read => always1~0.IN0 read => p6_full_6~0.IN0 reset_n => how_many_ones[0].ACLR reset_n => how_many_ones[1].ACLR reset_n => how_many_ones[2].ACLR reset_n => how_many_ones[3].ACLR reset_n => full_0.ACLR reset_n => full_1.ACLR reset_n => full_2.ACLR reset_n => full_3.ACLR reset_n => full_4.ACLR reset_n => full_5.ACLR reset_n => full_6.ACLR reset_n => fifo_contains_ones_n~reg0.PRESET sync_reset => always12~4.IN1 sync_reset => always12~0.IN0 sync_reset => always10~2.IN1 sync_reset => always8~2.IN1 sync_reset => always6~2.IN1 sync_reset => always4~2.IN1 sync_reset => always2~2.IN1 sync_reset => always0~2.IN1 write => always15~0.IN0 write => updated_one_count~5.IN1 write => updated_one_count~3.IN0 write => updated_one_count~1.IN0 write => always12~6.IN0 write => always12~2.IN1 write => always10~4.IN0 write => always10~0.IN1 write => always8~4.IN0 write => always8~0.IN1 write => always6~4.IN0 write => always6~0.IN1 write => always4~4.IN0 write => always4~0.IN1 write => always2~4.IN0 write => always2~0.IN1 write => always1~2.IN1 write => always1~0.IN1 write => always0~3.IN1 write => always0~0.IN1 write => always13~0.IN0 write => p6_full_6~0.IN1 write => updated_one_count~0.IN0 data_out <= stage_0.DB_MAX_OUTPUT_PORT_TYPE empty <= full_0.DB_MAX_OUTPUT_PORT_TYPE fifo_contains_ones_n <= fifo_contains_ones_n~reg0.DB_MAX_OUTPUT_PORT_TYPE full <= full_6.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1 clear_fifo => always13~0.IN1 clear_fifo => always12~0.IN1 clear_fifo => full_1~0.OUTPUTSELECT clear_fifo => full_2~0.OUTPUTSELECT clear_fifo => full_3~0.OUTPUTSELECT clear_fifo => full_4~0.OUTPUTSELECT clear_fifo => full_5~0.OUTPUTSELECT clear_fifo => full_6~0.OUTPUTSELECT clear_fifo => always1~1.IN0 clear_fifo => p1_stage_1~0.IN1 clear_fifo => p2_stage_2~0.IN1 clear_fifo => p3_stage_3~0.IN1 clear_fifo => p4_stage_4~0.IN1 clear_fifo => p5_stage_5~0.IN1 clear_fifo => p0_stage_0~0.IN1 clk => stage_6.CLK clk => full_6.CLK clk => stage_5.CLK clk => full_5.CLK clk => stage_4.CLK clk => full_4.CLK clk => stage_3.CLK clk => full_3.CLK clk => stage_2.CLK clk => full_2.CLK clk => stage_1.CLK clk => full_1.CLK clk => stage_0.CLK clk => full_0.CLK clk => how_many_ones[3].CLK clk => how_many_ones[2].CLK clk => how_many_ones[1].CLK clk => how_many_ones[0].CLK clk => fifo_contains_ones_n~reg0.CLK data_in => stage_6~0.DATAA data_in => updated_one_count~22.DATAB data_in => updated_one_count~5.IN0 data_in => updated_one_count~2.IN0 data_in => p0_stage_0.DATAB data_in => p1_stage_1.DATAB data_in => p2_stage_2.DATAB data_in => p3_stage_3.DATAB data_in => p4_stage_4.DATAB data_in => p5_stage_5.DATAB read => always0~3.IN0 read => updated_one_count~6.IN1 read => updated_one_count~2.IN1 read => always12~5.IN1 read => always12~1.IN0 read => always10~3.IN1 read => always8~3.IN1 read => always6~3.IN1 read => always4~3.IN1 read => always2~3.IN1 read => always1~0.IN0 read => p6_full_6~0.IN0 reset_n => how_many_ones[0].ACLR reset_n => how_many_ones[1].ACLR reset_n => how_many_ones[2].ACLR reset_n => how_many_ones[3].ACLR reset_n => full_0.ACLR reset_n => full_1.ACLR reset_n => full_2.ACLR reset_n => full_3.ACLR reset_n => full_4.ACLR reset_n => full_5.ACLR reset_n => full_6.ACLR reset_n => fifo_contains_ones_n~reg0.PRESET sync_reset => always12~4.IN1 sync_reset => always12~0.IN0 sync_reset => always10~2.IN1 sync_reset => always8~2.IN1 sync_reset => always6~2.IN1 sync_reset => always4~2.IN1 sync_reset => always2~2.IN1 sync_reset => always0~2.IN1 write => always15~0.IN0 write => updated_one_count~5.IN1 write => updated_one_count~3.IN0 write => updated_one_count~1.IN0 write => always12~6.IN0 write => always12~2.IN1 write => always10~4.IN0 write => always10~0.IN1 write => always8~4.IN0 write => always8~0.IN1 write => always6~4.IN0 write => always6~0.IN1 write => always4~4.IN0 write => always4~0.IN1 write => always2~4.IN0 write => always2~0.IN1 write => always1~2.IN1 write => always1~0.IN1 write => always0~3.IN1 write => always0~0.IN1 write => always13~0.IN0 write => p6_full_6~0.IN1 write => updated_one_count~0.IN0 data_out <= stage_0.DB_MAX_OUTPUT_PORT_TYPE empty <= full_0.DB_MAX_OUTPUT_PORT_TYPE fifo_contains_ones_n <= fifo_contains_ones_n~reg0.DB_MAX_OUTPUT_PORT_TYPE full <= full_6.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0 az_addr[0] => az_addr[0]~21.IN1 az_addr[1] => az_addr[1]~20.IN1 az_addr[2] => az_addr[2]~19.IN1 az_addr[3] => az_addr[3]~18.IN1 az_addr[4] => az_addr[4]~17.IN1 az_addr[5] => az_addr[5]~16.IN1 az_addr[6] => az_addr[6]~15.IN1 az_addr[7] => az_addr[7]~14.IN1 az_addr[8] => az_addr[8]~13.IN1 az_addr[9] => az_addr[9]~12.IN1 az_addr[10] => az_addr[10]~11.IN1 az_addr[11] => az_addr[11]~10.IN1 az_addr[12] => az_addr[12]~9.IN1 az_addr[13] => az_addr[13]~8.IN1 az_addr[14] => az_addr[14]~7.IN1 az_addr[15] => az_addr[15]~6.IN1 az_addr[16] => az_addr[16]~5.IN1 az_addr[17] => az_addr[17]~4.IN1 az_addr[18] => az_addr[18]~3.IN1 az_addr[19] => az_addr[19]~2.IN1 az_addr[20] => az_addr[20]~1.IN1 az_addr[21] => az_addr[21]~0.IN1 az_be_n[0] => comb~3.DATAA az_be_n[1] => comb~2.DATAA az_cs => ~NO_FANOUT~ az_data[0] => az_data[0]~15.IN1 az_data[1] => az_data[1]~14.IN1 az_data[2] => az_data[2]~13.IN1 az_data[3] => az_data[3]~12.IN1 az_data[4] => az_data[4]~11.IN1 az_data[5] => az_data[5]~10.IN1 az_data[6] => az_data[6]~9.IN1 az_data[7] => az_data[7]~8.IN1 az_data[8] => az_data[8]~7.IN1 az_data[9] => az_data[9]~6.IN1 az_data[10] => az_data[10]~5.IN1 az_data[11] => az_data[11]~4.IN1 az_data[12] => az_data[12]~3.IN1 az_data[13] => az_data[13]~2.IN1 az_data[14] => az_data[14]~1.IN1 az_data[15] => az_data[15]~0.IN1 az_rd_n => comb~0.IN1 az_wr_n => az_wr_n~0.IN1 clk => clk~0.IN1 reset_n => reset_n~0.IN1 za_data[0] <= za_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_data[1] <= za_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_data[2] <= za_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_data[3] <= za_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_data[4] <= za_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_data[5] <= za_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_data[6] <= za_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_data[7] <= za_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_data[8] <= za_data[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_data[9] <= za_data[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_data[10] <= za_data[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_data[11] <= za_data[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_data[12] <= za_data[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_data[13] <= za_data[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_data[14] <= za_data[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_data[15] <= za_data[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE za_valid <= za_valid~reg0.DB_MAX_OUTPUT_PORT_TYPE za_waitrequest <= sdram_0_input_efifo_module:the_sdram_0_input_efifo_module.full zs_addr[0] <= zs_addr~11.DB_MAX_OUTPUT_PORT_TYPE zs_addr[1] <= zs_addr~10.DB_MAX_OUTPUT_PORT_TYPE zs_addr[2] <= zs_addr~9.DB_MAX_OUTPUT_PORT_TYPE zs_addr[3] <= zs_addr~8.DB_MAX_OUTPUT_PORT_TYPE zs_addr[4] <= zs_addr~7.DB_MAX_OUTPUT_PORT_TYPE zs_addr[5] <= zs_addr~6.DB_MAX_OUTPUT_PORT_TYPE zs_addr[6] <= zs_addr~5.DB_MAX_OUTPUT_PORT_TYPE zs_addr[7] <= zs_addr~4.DB_MAX_OUTPUT_PORT_TYPE zs_addr[8] <= zs_addr~3.DB_MAX_OUTPUT_PORT_TYPE zs_addr[9] <= zs_addr~2.DB_MAX_OUTPUT_PORT_TYPE zs_addr[10] <= zs_addr~1.DB_MAX_OUTPUT_PORT_TYPE zs_addr[11] <= zs_addr~0.DB_MAX_OUTPUT_PORT_TYPE zs_ba[0] <= zs_ba~1.DB_MAX_OUTPUT_PORT_TYPE zs_ba[1] <= zs_ba~0.DB_MAX_OUTPUT_PORT_TYPE zs_cas_n <= concat~2.DB_MAX_OUTPUT_PORT_TYPE zs_cke <= zs_cs_n <= concat~0.DB_MAX_OUTPUT_PORT_TYPE zs_dq[0] <= zs_dq[0]~0 zs_dq[1] <= zs_dq[1]~1 zs_dq[2] <= zs_dq[2]~2 zs_dq[3] <= zs_dq[3]~3 zs_dq[4] <= zs_dq[4]~4 zs_dq[5] <= zs_dq[5]~5 zs_dq[6] <= zs_dq[6]~6 zs_dq[7] <= zs_dq[7]~7 zs_dq[8] <= zs_dq[8]~8 zs_dq[9] <= zs_dq[9]~9 zs_dq[10] <= zs_dq[10]~10 zs_dq[11] <= zs_dq[11]~11 zs_dq[12] <= zs_dq[12]~12 zs_dq[13] <= zs_dq[13]~13 zs_dq[14] <= zs_dq[14]~14 zs_dq[15] <= zs_dq[15]~15 zs_dqm[0] <= zs_dqm~1.DB_MAX_OUTPUT_PORT_TYPE zs_dqm[1] <= zs_dqm~0.DB_MAX_OUTPUT_PORT_TYPE zs_ras_n <= concat~1.DB_MAX_OUTPUT_PORT_TYPE zs_we_n <= concat~3.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module clk => wr_address.CLK clk => rd_address.CLK clk => entries[1].CLK clk => entries[0].CLK clk => entry_1[40].CLK clk => entry_1[39].CLK clk => entry_1[38].CLK clk => entry_1[37].CLK clk => entry_1[36].CLK clk => entry_1[35].CLK clk => entry_1[34].CLK clk => entry_1[33].CLK clk => entry_1[32].CLK clk => entry_1[31].CLK clk => entry_1[30].CLK clk => entry_1[29].CLK clk => entry_1[28].CLK clk => entry_1[27].CLK clk => entry_1[26].CLK clk => entry_1[25].CLK clk => entry_1[24].CLK clk => entry_1[23].CLK clk => entry_1[22].CLK clk => entry_1[21].CLK clk => entry_1[20].CLK clk => entry_1[19].CLK clk => entry_1[18].CLK clk => entry_1[17].CLK clk => entry_1[16].CLK clk => entry_1[15].CLK clk => entry_1[14].CLK clk => entry_1[13].CLK clk => entry_1[12].CLK clk => entry_1[11].CLK clk => entry_1[10].CLK clk => entry_1[9].CLK clk => entry_1[8].CLK clk => entry_1[7].CLK clk => entry_1[6].CLK clk => entry_1[5].CLK clk => entry_1[4].CLK clk => entry_1[3].CLK clk => entry_1[2].CLK clk => entry_1[1].CLK clk => entry_1[0].CLK clk => entry_0[40].CLK clk => entry_0[39].CLK clk => entry_0[38].CLK clk => entry_0[37].CLK clk => entry_0[36].CLK clk => entry_0[35].CLK clk => entry_0[34].CLK clk => entry_0[33].CLK clk => entry_0[32].CLK clk => entry_0[31].CLK clk => entry_0[30].CLK clk => entry_0[29].CLK clk => entry_0[28].CLK clk => entry_0[27].CLK clk => entry_0[26].CLK clk => entry_0[25].CLK clk => entry_0[24].CLK clk => entry_0[23].CLK clk => entry_0[22].CLK clk => entry_0[21].CLK clk => entry_0[20].CLK clk => entry_0[19].CLK clk => entry_0[18].CLK clk => entry_0[17].CLK clk => entry_0[16].CLK clk => entry_0[15].CLK clk => entry_0[14].CLK clk => entry_0[13].CLK clk => entry_0[12].CLK clk => entry_0[11].CLK clk => entry_0[10].CLK clk => entry_0[9].CLK clk => entry_0[8].CLK clk => entry_0[7].CLK clk => entry_0[6].CLK clk => entry_0[5].CLK clk => entry_0[4].CLK clk => entry_0[3].CLK clk => entry_0[2].CLK clk => entry_0[1].CLK clk => entry_0[0].CLK rd => Mux3.IN4 rd => Mux2.IN4 rd => Mux1.IN4 rd => Mux0.IN2 reset_n => wr_address.ACLR reset_n => rd_address.ACLR reset_n => entries[1].ACLR reset_n => entries[0].ACLR wr => always2~0.IN1 wr => Mux3.IN5 wr => Mux2.IN5 wr => Mux1.IN5 wr => Mux0.IN3 wr_data[0] => entry_0~40.DATAA wr_data[0] => entry_1~40.DATAB wr_data[1] => entry_0~39.DATAA wr_data[1] => entry_1~39.DATAB wr_data[2] => entry_0~38.DATAA wr_data[2] => entry_1~38.DATAB wr_data[3] => entry_0~37.DATAA wr_data[3] => entry_1~37.DATAB wr_data[4] => entry_0~36.DATAA wr_data[4] => entry_1~36.DATAB wr_data[5] => entry_0~35.DATAA wr_data[5] => entry_1~35.DATAB wr_data[6] => entry_0~34.DATAA wr_data[6] => entry_1~34.DATAB wr_data[7] => entry_0~33.DATAA wr_data[7] => entry_1~33.DATAB wr_data[8] => entry_0~32.DATAA wr_data[8] => entry_1~32.DATAB wr_data[9] => entry_0~31.DATAA wr_data[9] => entry_1~31.DATAB wr_data[10] => entry_0~30.DATAA wr_data[10] => entry_1~30.DATAB wr_data[11] => entry_0~29.DATAA wr_data[11] => entry_1~29.DATAB wr_data[12] => entry_0~28.DATAA wr_data[12] => entry_1~28.DATAB wr_data[13] => entry_0~27.DATAA wr_data[13] => entry_1~27.DATAB wr_data[14] => entry_0~26.DATAA wr_data[14] => entry_1~26.DATAB wr_data[15] => entry_0~25.DATAA wr_data[15] => entry_1~25.DATAB wr_data[16] => entry_0~24.DATAA wr_data[16] => entry_1~24.DATAB wr_data[17] => entry_0~23.DATAA wr_data[17] => entry_1~23.DATAB wr_data[18] => entry_0~22.DATAA wr_data[18] => entry_1~22.DATAB wr_data[19] => entry_0~21.DATAA wr_data[19] => entry_1~21.DATAB wr_data[20] => entry_0~20.DATAA wr_data[20] => entry_1~20.DATAB wr_data[21] => entry_0~19.DATAA wr_data[21] => entry_1~19.DATAB wr_data[22] => entry_0~18.DATAA wr_data[22] => entry_1~18.DATAB wr_data[23] => entry_0~17.DATAA wr_data[23] => entry_1~17.DATAB wr_data[24] => entry_0~16.DATAA wr_data[24] => entry_1~16.DATAB wr_data[25] => entry_0~15.DATAA wr_data[25] => entry_1~15.DATAB wr_data[26] => entry_0~14.DATAA wr_data[26] => entry_1~14.DATAB wr_data[27] => entry_0~13.DATAA wr_data[27] => entry_1~13.DATAB wr_data[28] => entry_0~12.DATAA wr_data[28] => entry_1~12.DATAB wr_data[29] => entry_0~11.DATAA wr_data[29] => entry_1~11.DATAB wr_data[30] => entry_0~10.DATAA wr_data[30] => entry_1~10.DATAB wr_data[31] => entry_0~9.DATAA wr_data[31] => entry_1~9.DATAB wr_data[32] => entry_0~8.DATAA wr_data[32] => entry_1~8.DATAB wr_data[33] => entry_0~7.DATAA wr_data[33] => entry_1~7.DATAB wr_data[34] => entry_0~6.DATAA wr_data[34] => entry_1~6.DATAB wr_data[35] => entry_0~5.DATAA wr_data[35] => entry_1~5.DATAB wr_data[36] => entry_0~4.DATAA wr_data[36] => entry_1~4.DATAB wr_data[37] => entry_0~3.DATAA wr_data[37] => entry_1~3.DATAB wr_data[38] => entry_0~2.DATAA wr_data[38] => entry_1~2.DATAB wr_data[39] => entry_0~1.DATAA wr_data[39] => entry_1~1.DATAB wr_data[40] => entry_0~0.DATAA wr_data[40] => entry_1~0.DATAB almost_empty <= LessThan1.DB_MAX_OUTPUT_PORT_TYPE almost_full <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE empty <= Equal1.DB_MAX_OUTPUT_PORT_TYPE full <= Equal0.DB_MAX_OUTPUT_PORT_TYPE rd_data[0] <= rd_data~40.DB_MAX_OUTPUT_PORT_TYPE rd_data[1] <= rd_data~39.DB_MAX_OUTPUT_PORT_TYPE rd_data[2] <= rd_data~38.DB_MAX_OUTPUT_PORT_TYPE rd_data[3] <= rd_data~37.DB_MAX_OUTPUT_PORT_TYPE rd_data[4] <= rd_data~36.DB_MAX_OUTPUT_PORT_TYPE rd_data[5] <= rd_data~35.DB_MAX_OUTPUT_PORT_TYPE rd_data[6] <= rd_data~34.DB_MAX_OUTPUT_PORT_TYPE rd_data[7] <= rd_data~33.DB_MAX_OUTPUT_PORT_TYPE rd_data[8] <= rd_data~32.DB_MAX_OUTPUT_PORT_TYPE rd_data[9] <= rd_data~31.DB_MAX_OUTPUT_PORT_TYPE rd_data[10] <= rd_data~30.DB_MAX_OUTPUT_PORT_TYPE rd_data[11] <= rd_data~29.DB_MAX_OUTPUT_PORT_TYPE rd_data[12] <= rd_data~28.DB_MAX_OUTPUT_PORT_TYPE rd_data[13] <= rd_data~27.DB_MAX_OUTPUT_PORT_TYPE rd_data[14] <= rd_data~26.DB_MAX_OUTPUT_PORT_TYPE rd_data[15] <= rd_data~25.DB_MAX_OUTPUT_PORT_TYPE rd_data[16] <= rd_data~24.DB_MAX_OUTPUT_PORT_TYPE rd_data[17] <= rd_data~23.DB_MAX_OUTPUT_PORT_TYPE rd_data[18] <= rd_data~22.DB_MAX_OUTPUT_PORT_TYPE rd_data[19] <= rd_data~21.DB_MAX_OUTPUT_PORT_TYPE rd_data[20] <= rd_data~20.DB_MAX_OUTPUT_PORT_TYPE rd_data[21] <= rd_data~19.DB_MAX_OUTPUT_PORT_TYPE rd_data[22] <= rd_data~18.DB_MAX_OUTPUT_PORT_TYPE rd_data[23] <= rd_data~17.DB_MAX_OUTPUT_PORT_TYPE rd_data[24] <= rd_data~16.DB_MAX_OUTPUT_PORT_TYPE rd_data[25] <= rd_data~15.DB_MAX_OUTPUT_PORT_TYPE rd_data[26] <= rd_data~14.DB_MAX_OUTPUT_PORT_TYPE rd_data[27] <= rd_data~13.DB_MAX_OUTPUT_PORT_TYPE rd_data[28] <= rd_data~12.DB_MAX_OUTPUT_PORT_TYPE rd_data[29] <= rd_data~11.DB_MAX_OUTPUT_PORT_TYPE rd_data[30] <= rd_data~10.DB_MAX_OUTPUT_PORT_TYPE rd_data[31] <= rd_data~9.DB_MAX_OUTPUT_PORT_TYPE rd_data[32] <= rd_data~8.DB_MAX_OUTPUT_PORT_TYPE rd_data[33] <= rd_data~7.DB_MAX_OUTPUT_PORT_TYPE rd_data[34] <= rd_data~6.DB_MAX_OUTPUT_PORT_TYPE rd_data[35] <= rd_data~5.DB_MAX_OUTPUT_PORT_TYPE rd_data[36] <= rd_data~4.DB_MAX_OUTPUT_PORT_TYPE rd_data[37] <= rd_data~3.DB_MAX_OUTPUT_PORT_TYPE rd_data[38] <= rd_data~2.DB_MAX_OUTPUT_PORT_TYPE rd_data[39] <= rd_data~1.DB_MAX_OUTPUT_PORT_TYPE rd_data[40] <= rd_data~0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS clk => d1_reasons_to_wait.CLK clk => sram_0_avalonS_arb_share_counter[2].CLK clk => sram_0_avalonS_arb_share_counter[1].CLK clk => sram_0_avalonS_arb_share_counter[0].CLK clk => sram_0_avalonS_slavearbiterlockenable.CLK clk => last_cycle_cpu_0_instruction_master_granted_slave_sram_0_avalonS.CLK clk => last_cycle_cpu_0_data_master_granted_slave_sram_0_avalonS.CLK clk => sram_0_avalonS_saved_chosen_master_vector[1].CLK clk => sram_0_avalonS_saved_chosen_master_vector[0].CLK clk => sram_0_avalonS_arb_addend[1].CLK clk => sram_0_avalonS_arb_addend[0].CLK clk => d1_sram_0_avalonS_end_xfer~reg0.CLK clk => sram_0_avalonS_wait_counter[2].CLK clk => sram_0_avalonS_wait_counter[1].CLK clk => sram_0_avalonS_wait_counter[0].CLK cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[2] => sram_0_avalonS_address~16.DATAB cpu_0_data_master_address_to_slave[3] => sram_0_avalonS_address~15.DATAB cpu_0_data_master_address_to_slave[4] => sram_0_avalonS_address~14.DATAB cpu_0_data_master_address_to_slave[5] => sram_0_avalonS_address~13.DATAB cpu_0_data_master_address_to_slave[6] => sram_0_avalonS_address~12.DATAB cpu_0_data_master_address_to_slave[7] => sram_0_avalonS_address~11.DATAB cpu_0_data_master_address_to_slave[8] => sram_0_avalonS_address~10.DATAB cpu_0_data_master_address_to_slave[9] => sram_0_avalonS_address~9.DATAB cpu_0_data_master_address_to_slave[10] => sram_0_avalonS_address~8.DATAB cpu_0_data_master_address_to_slave[11] => sram_0_avalonS_address~7.DATAB cpu_0_data_master_address_to_slave[12] => sram_0_avalonS_address~6.DATAB cpu_0_data_master_address_to_slave[13] => sram_0_avalonS_address~5.DATAB cpu_0_data_master_address_to_slave[14] => sram_0_avalonS_address~4.DATAB cpu_0_data_master_address_to_slave[15] => sram_0_avalonS_address~3.DATAB cpu_0_data_master_address_to_slave[16] => sram_0_avalonS_address~2.DATAB cpu_0_data_master_address_to_slave[17] => sram_0_avalonS_address~1.DATAB cpu_0_data_master_address_to_slave[18] => sram_0_avalonS_address~0.DATAB cpu_0_data_master_address_to_slave[19] => Equal0.IN4 cpu_0_data_master_address_to_slave[20] => Equal0.IN3 cpu_0_data_master_address_to_slave[21] => Equal0.IN2 cpu_0_data_master_address_to_slave[22] => Equal0.IN0 cpu_0_data_master_address_to_slave[23] => Equal0.IN1 cpu_0_data_master_byteenable[0] => cpu_0_data_master_byteenable_sram_0_avalonS~1.DATAB cpu_0_data_master_byteenable[1] => cpu_0_data_master_byteenable_sram_0_avalonS~0.DATAB cpu_0_data_master_byteenable[2] => cpu_0_data_master_byteenable_sram_0_avalonS~1.DATAA cpu_0_data_master_byteenable[3] => cpu_0_data_master_byteenable_sram_0_avalonS~0.DATAA cpu_0_data_master_dbs_address[0] => ~NO_FANOUT~ cpu_0_data_master_dbs_address[1] => sram_0_avalonS_address~17.DATAB cpu_0_data_master_dbs_address[1] => cpu_0_data_master_byteenable_sram_0_avalonS~1.OUTPUTSELECT cpu_0_data_master_dbs_address[1] => cpu_0_data_master_byteenable_sram_0_avalonS~0.OUTPUTSELECT cpu_0_data_master_dbs_write_16[0] => sram_0_avalonS_writedata[0].DATAIN cpu_0_data_master_dbs_write_16[1] => sram_0_avalonS_writedata[1].DATAIN cpu_0_data_master_dbs_write_16[2] => sram_0_avalonS_writedata[2].DATAIN cpu_0_data_master_dbs_write_16[3] => sram_0_avalonS_writedata[3].DATAIN cpu_0_data_master_dbs_write_16[4] => sram_0_avalonS_writedata[4].DATAIN cpu_0_data_master_dbs_write_16[5] => sram_0_avalonS_writedata[5].DATAIN cpu_0_data_master_dbs_write_16[6] => sram_0_avalonS_writedata[6].DATAIN cpu_0_data_master_dbs_write_16[7] => sram_0_avalonS_writedata[7].DATAIN cpu_0_data_master_dbs_write_16[8] => sram_0_avalonS_writedata[8].DATAIN cpu_0_data_master_dbs_write_16[9] => sram_0_avalonS_writedata[9].DATAIN cpu_0_data_master_dbs_write_16[10] => sram_0_avalonS_writedata[10].DATAIN cpu_0_data_master_dbs_write_16[11] => sram_0_avalonS_writedata[11].DATAIN cpu_0_data_master_dbs_write_16[12] => sram_0_avalonS_writedata[12].DATAIN cpu_0_data_master_dbs_write_16[13] => sram_0_avalonS_writedata[13].DATAIN cpu_0_data_master_dbs_write_16[14] => sram_0_avalonS_writedata[14].DATAIN cpu_0_data_master_dbs_write_16[15] => sram_0_avalonS_writedata[15].DATAIN cpu_0_data_master_no_byte_enables_and_last_term => cpu_0_data_master_qualified_request_sram_0_avalonS~0.IN1 cpu_0_data_master_read => sram_0_avalonS_in_a_read_cycle~0.IN0 cpu_0_data_master_read => cpu_0_data_master_requests_sram_0_avalonS~0.IN0 cpu_0_data_master_write => sram_0_avalonS_in_a_write_cycle.IN0 cpu_0_data_master_write => cpu_0_data_master_qualified_request_sram_0_avalonS~1.IN1 cpu_0_data_master_write => cpu_0_data_master_requests_sram_0_avalonS~0.IN1 cpu_0_instruction_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_instruction_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_instruction_master_address_to_slave[2] => sram_0_avalonS_address~16.DATAA cpu_0_instruction_master_address_to_slave[3] => sram_0_avalonS_address~15.DATAA cpu_0_instruction_master_address_to_slave[4] => sram_0_avalonS_address~14.DATAA cpu_0_instruction_master_address_to_slave[5] => sram_0_avalonS_address~13.DATAA cpu_0_instruction_master_address_to_slave[6] => sram_0_avalonS_address~12.DATAA cpu_0_instruction_master_address_to_slave[7] => sram_0_avalonS_address~11.DATAA cpu_0_instruction_master_address_to_slave[8] => sram_0_avalonS_address~10.DATAA cpu_0_instruction_master_address_to_slave[9] => sram_0_avalonS_address~9.DATAA cpu_0_instruction_master_address_to_slave[10] => sram_0_avalonS_address~8.DATAA cpu_0_instruction_master_address_to_slave[11] => sram_0_avalonS_address~7.DATAA cpu_0_instruction_master_address_to_slave[12] => sram_0_avalonS_address~6.DATAA cpu_0_instruction_master_address_to_slave[13] => sram_0_avalonS_address~5.DATAA cpu_0_instruction_master_address_to_slave[14] => sram_0_avalonS_address~4.DATAA cpu_0_instruction_master_address_to_slave[15] => sram_0_avalonS_address~3.DATAA cpu_0_instruction_master_address_to_slave[16] => sram_0_avalonS_address~2.DATAA cpu_0_instruction_master_address_to_slave[17] => sram_0_avalonS_address~1.DATAA cpu_0_instruction_master_address_to_slave[18] => sram_0_avalonS_address~0.DATAA cpu_0_instruction_master_address_to_slave[19] => Equal1.IN4 cpu_0_instruction_master_address_to_slave[20] => Equal1.IN3 cpu_0_instruction_master_address_to_slave[21] => Equal1.IN2 cpu_0_instruction_master_address_to_slave[22] => Equal1.IN0 cpu_0_instruction_master_address_to_slave[23] => Equal1.IN1 cpu_0_instruction_master_dbs_address[0] => ~NO_FANOUT~ cpu_0_instruction_master_dbs_address[1] => sram_0_avalonS_address~17.DATAA cpu_0_instruction_master_latency_counter[0] => Equal2.IN31 cpu_0_instruction_master_latency_counter[1] => Equal2.IN30 cpu_0_instruction_master_read => sram_0_avalonS_in_a_read_cycle~1.IN0 cpu_0_instruction_master_read => cpu_0_instruction_master_qualified_request_sram_0_avalonS~1.IN0 cpu_0_instruction_master_read => cpu_0_instruction_master_requests_sram_0_avalonS~1.IN0 cpu_0_instruction_master_read => cpu_0_instruction_master_requests_sram_0_avalonS~0.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register => cpu_0_instruction_master_qualified_request_sram_0_avalonS~0.IN1 reset_n => sram_0_avalonS_reset_n.DATAIN reset_n => sram_0_avalonS_wait_counter[0].ACLR reset_n => sram_0_avalonS_wait_counter[1].ACLR reset_n => sram_0_avalonS_wait_counter[2].ACLR reset_n => sram_0_avalonS_arb_addend[0].PRESET reset_n => sram_0_avalonS_arb_addend[1].ACLR reset_n => sram_0_avalonS_saved_chosen_master_vector[0].ACLR reset_n => sram_0_avalonS_saved_chosen_master_vector[1].ACLR reset_n => last_cycle_cpu_0_data_master_granted_slave_sram_0_avalonS.ACLR reset_n => last_cycle_cpu_0_instruction_master_granted_slave_sram_0_avalonS.ACLR reset_n => sram_0_avalonS_slavearbiterlockenable.ACLR reset_n => sram_0_avalonS_arb_share_counter[0].ACLR reset_n => sram_0_avalonS_arb_share_counter[1].ACLR reset_n => sram_0_avalonS_arb_share_counter[2].ACLR reset_n => d1_reasons_to_wait.ACLR reset_n => d1_sram_0_avalonS_end_xfer~reg0.PRESET sram_0_avalonS_readdata[0] => sram_0_avalonS_readdata_from_sa[0].DATAIN sram_0_avalonS_readdata[1] => sram_0_avalonS_readdata_from_sa[1].DATAIN sram_0_avalonS_readdata[2] => sram_0_avalonS_readdata_from_sa[2].DATAIN sram_0_avalonS_readdata[3] => sram_0_avalonS_readdata_from_sa[3].DATAIN sram_0_avalonS_readdata[4] => sram_0_avalonS_readdata_from_sa[4].DATAIN sram_0_avalonS_readdata[5] => sram_0_avalonS_readdata_from_sa[5].DATAIN sram_0_avalonS_readdata[6] => sram_0_avalonS_readdata_from_sa[6].DATAIN sram_0_avalonS_readdata[7] => sram_0_avalonS_readdata_from_sa[7].DATAIN sram_0_avalonS_readdata[8] => sram_0_avalonS_readdata_from_sa[8].DATAIN sram_0_avalonS_readdata[9] => sram_0_avalonS_readdata_from_sa[9].DATAIN sram_0_avalonS_readdata[10] => sram_0_avalonS_readdata_from_sa[10].DATAIN sram_0_avalonS_readdata[11] => sram_0_avalonS_readdata_from_sa[11].DATAIN sram_0_avalonS_readdata[12] => sram_0_avalonS_readdata_from_sa[12].DATAIN sram_0_avalonS_readdata[13] => sram_0_avalonS_readdata_from_sa[13].DATAIN sram_0_avalonS_readdata[14] => sram_0_avalonS_readdata_from_sa[14].DATAIN sram_0_avalonS_readdata[15] => sram_0_avalonS_readdata_from_sa[15].DATAIN cpu_0_data_master_byteenable_sram_0_avalonS[0] <= cpu_0_data_master_byteenable_sram_0_avalonS~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_byteenable_sram_0_avalonS[1] <= cpu_0_data_master_byteenable_sram_0_avalonS~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_granted_sram_0_avalonS <= sram_0_avalonS_grant_vector[1].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_qualified_request_sram_0_avalonS <= cpu_0_data_master_qualified_request_sram_0_avalonS~3.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_read_data_valid_sram_0_avalonS <= cpu_0_data_master_requests_sram_0_avalonS <= cpu_0_data_master_requests_sram_0_avalonS~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_granted_sram_0_avalonS <= sram_0_avalonS_grant_vector~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_qualified_request_sram_0_avalonS <= cpu_0_instruction_master_qualified_request_sram_0_avalonS~3.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_read_data_valid_sram_0_avalonS <= cpu_0_instruction_master_read_data_valid_sram_0_avalonS~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_requests_sram_0_avalonS <= cpu_0_instruction_master_requests_sram_0_avalonS~1.DB_MAX_OUTPUT_PORT_TYPE d1_sram_0_avalonS_end_xfer <= d1_sram_0_avalonS_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[0] <= sram_0_avalonS_address~17.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[1] <= sram_0_avalonS_address~16.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[2] <= sram_0_avalonS_address~15.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[3] <= sram_0_avalonS_address~14.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[4] <= sram_0_avalonS_address~13.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[5] <= sram_0_avalonS_address~12.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[6] <= sram_0_avalonS_address~11.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[7] <= sram_0_avalonS_address~10.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[8] <= sram_0_avalonS_address~9.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[9] <= sram_0_avalonS_address~8.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[10] <= sram_0_avalonS_address~7.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[11] <= sram_0_avalonS_address~6.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[12] <= sram_0_avalonS_address~5.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[13] <= sram_0_avalonS_address~4.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[14] <= sram_0_avalonS_address~3.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[15] <= sram_0_avalonS_address~2.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[16] <= sram_0_avalonS_address~1.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_address[17] <= sram_0_avalonS_address~0.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_byteenable_n[0] <= sram_0_avalonS_byteenable_n~1.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_byteenable_n[1] <= sram_0_avalonS_byteenable_n~0.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_chipselect_n <= sram_0_avalonS_chipselect_n~0.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_outputenable_n <= sram_0_avalonS_in_a_read_cycle.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[0] <= sram_0_avalonS_readdata[0].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[1] <= sram_0_avalonS_readdata[1].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[2] <= sram_0_avalonS_readdata[2].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[3] <= sram_0_avalonS_readdata[3].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[4] <= sram_0_avalonS_readdata[4].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[5] <= sram_0_avalonS_readdata[5].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[6] <= sram_0_avalonS_readdata[6].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[7] <= sram_0_avalonS_readdata[7].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[8] <= sram_0_avalonS_readdata[8].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[9] <= sram_0_avalonS_readdata[9].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[10] <= sram_0_avalonS_readdata[10].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[11] <= sram_0_avalonS_readdata[11].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[12] <= sram_0_avalonS_readdata[12].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[13] <= sram_0_avalonS_readdata[13].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[14] <= sram_0_avalonS_readdata[14].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_readdata_from_sa[15] <= sram_0_avalonS_readdata[15].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_reset_n <= reset_n.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_wait_counter_eq_0 <= Equal4.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_wait_counter_eq_1 <= Equal3.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_write_n <= sram_0_avalonS_write_n~2.DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[0] <= cpu_0_data_master_dbs_write_16[0].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[1] <= cpu_0_data_master_dbs_write_16[1].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[2] <= cpu_0_data_master_dbs_write_16[2].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[3] <= cpu_0_data_master_dbs_write_16[3].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[4] <= cpu_0_data_master_dbs_write_16[4].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[5] <= cpu_0_data_master_dbs_write_16[5].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[6] <= cpu_0_data_master_dbs_write_16[6].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[7] <= cpu_0_data_master_dbs_write_16[7].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[8] <= cpu_0_data_master_dbs_write_16[8].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[9] <= cpu_0_data_master_dbs_write_16[9].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[10] <= cpu_0_data_master_dbs_write_16[10].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[11] <= cpu_0_data_master_dbs_write_16[11].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[12] <= cpu_0_data_master_dbs_write_16[12].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[13] <= cpu_0_data_master_dbs_write_16[13].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[14] <= cpu_0_data_master_dbs_write_16[14].DB_MAX_OUTPUT_PORT_TYPE sram_0_avalonS_writedata[15] <= cpu_0_data_master_dbs_write_16[15].DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|sram_0:the_sram_0 iADDR[0] => iADDR[0]~17.IN1 iADDR[1] => iADDR[1]~16.IN1 iADDR[2] => iADDR[2]~15.IN1 iADDR[3] => iADDR[3]~14.IN1 iADDR[4] => iADDR[4]~13.IN1 iADDR[5] => iADDR[5]~12.IN1 iADDR[6] => iADDR[6]~11.IN1 iADDR[7] => iADDR[7]~10.IN1 iADDR[8] => iADDR[8]~9.IN1 iADDR[9] => iADDR[9]~8.IN1 iADDR[10] => iADDR[10]~7.IN1 iADDR[11] => iADDR[11]~6.IN1 iADDR[12] => iADDR[12]~5.IN1 iADDR[13] => iADDR[13]~4.IN1 iADDR[14] => iADDR[14]~3.IN1 iADDR[15] => iADDR[15]~2.IN1 iADDR[16] => iADDR[16]~1.IN1 iADDR[17] => iADDR[17]~0.IN1 iCE_N => iCE_N~0.IN1 iDATA[0] => iDATA[0]~15.IN1 iDATA[1] => iDATA[1]~14.IN1 iDATA[2] => iDATA[2]~13.IN1 iDATA[3] => iDATA[3]~12.IN1 iDATA[4] => iDATA[4]~11.IN1 iDATA[5] => iDATA[5]~10.IN1 iDATA[6] => iDATA[6]~9.IN1 iDATA[7] => iDATA[7]~8.IN1 iDATA[8] => iDATA[8]~7.IN1 iDATA[9] => iDATA[9]~6.IN1 iDATA[10] => iDATA[10]~5.IN1 iDATA[11] => iDATA[11]~4.IN1 iDATA[12] => iDATA[12]~3.IN1 iDATA[13] => iDATA[13]~2.IN1 iDATA[14] => iDATA[14]~1.IN1 iDATA[15] => iDATA[15]~0.IN1 iLB_N => iLB_N~0.IN1 iOE_N => iOE_N~0.IN1 iRST_N => iRST_N~0.IN1 iUB_N => iUB_N~0.IN1 iWE_N => iWE_N~0.IN1 SRAM_ADDR[0] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[1] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[2] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[3] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[4] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[5] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[6] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[7] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[8] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[9] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[10] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[11] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[12] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[13] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[14] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[15] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[16] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_ADDR[17] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR SRAM_CE_N <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_CE_N SRAM_DQ[0] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_DQ[1] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_DQ[2] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_DQ[3] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_DQ[4] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_DQ[5] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_DQ[6] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_DQ[7] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_DQ[8] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_DQ[9] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_DQ[10] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_DQ[11] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_DQ[12] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_DQ[13] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_DQ[14] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_DQ[15] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ SRAM_LB_N <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_LB_N SRAM_OE_N <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_OE_N SRAM_UB_N <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_UB_N SRAM_WE_N <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_WE_N oDATA[0] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA oDATA[1] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA oDATA[2] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA oDATA[3] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA oDATA[4] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA oDATA[5] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA oDATA[6] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA oDATA[7] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA oDATA[8] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA oDATA[9] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA oDATA[10] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA oDATA[11] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA oDATA[12] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA oDATA[13] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA oDATA[14] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA oDATA[15] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.oDATA |DE1_NIOS|system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K oDATA[0] <= oDATA~15.DB_MAX_OUTPUT_PORT_TYPE oDATA[1] <= oDATA~14.DB_MAX_OUTPUT_PORT_TYPE oDATA[2] <= oDATA~13.DB_MAX_OUTPUT_PORT_TYPE oDATA[3] <= oDATA~12.DB_MAX_OUTPUT_PORT_TYPE oDATA[4] <= oDATA~11.DB_MAX_OUTPUT_PORT_TYPE oDATA[5] <= oDATA~10.DB_MAX_OUTPUT_PORT_TYPE oDATA[6] <= oDATA~9.DB_MAX_OUTPUT_PORT_TYPE oDATA[7] <= oDATA~8.DB_MAX_OUTPUT_PORT_TYPE oDATA[8] <= oDATA~7.DB_MAX_OUTPUT_PORT_TYPE oDATA[9] <= oDATA~6.DB_MAX_OUTPUT_PORT_TYPE oDATA[10] <= oDATA~5.DB_MAX_OUTPUT_PORT_TYPE oDATA[11] <= oDATA~4.DB_MAX_OUTPUT_PORT_TYPE oDATA[12] <= oDATA~3.DB_MAX_OUTPUT_PORT_TYPE oDATA[13] <= oDATA~2.DB_MAX_OUTPUT_PORT_TYPE oDATA[14] <= oDATA~1.DB_MAX_OUTPUT_PORT_TYPE oDATA[15] <= oDATA~0.DB_MAX_OUTPUT_PORT_TYPE iDATA[0] => SRAM_DQ[0]~0.DATAIN iDATA[1] => SRAM_DQ[1]~1.DATAIN iDATA[2] => SRAM_DQ[2]~2.DATAIN iDATA[3] => SRAM_DQ[3]~3.DATAIN iDATA[4] => SRAM_DQ[4]~4.DATAIN iDATA[5] => SRAM_DQ[5]~5.DATAIN iDATA[6] => SRAM_DQ[6]~6.DATAIN iDATA[7] => SRAM_DQ[7]~7.DATAIN iDATA[8] => SRAM_DQ[8]~8.DATAIN iDATA[9] => SRAM_DQ[9]~9.DATAIN iDATA[10] => SRAM_DQ[10]~10.DATAIN iDATA[11] => SRAM_DQ[11]~11.DATAIN iDATA[12] => SRAM_DQ[12]~12.DATAIN iDATA[13] => SRAM_DQ[13]~13.DATAIN iDATA[14] => SRAM_DQ[14]~14.DATAIN iDATA[15] => SRAM_DQ[15]~15.DATAIN iADDR[0] => SRAM_ADDR[0].DATAIN iADDR[1] => SRAM_ADDR[1].DATAIN iADDR[2] => SRAM_ADDR[2].DATAIN iADDR[3] => SRAM_ADDR[3].DATAIN iADDR[4] => SRAM_ADDR[4].DATAIN iADDR[5] => SRAM_ADDR[5].DATAIN iADDR[6] => SRAM_ADDR[6].DATAIN iADDR[7] => SRAM_ADDR[7].DATAIN iADDR[8] => SRAM_ADDR[8].DATAIN iADDR[9] => SRAM_ADDR[9].DATAIN iADDR[10] => SRAM_ADDR[10].DATAIN iADDR[11] => SRAM_ADDR[11].DATAIN iADDR[12] => SRAM_ADDR[12].DATAIN iADDR[13] => SRAM_ADDR[13].DATAIN iADDR[14] => SRAM_ADDR[14].DATAIN iADDR[15] => SRAM_ADDR[15].DATAIN iADDR[16] => SRAM_ADDR[16].DATAIN iADDR[17] => SRAM_ADDR[17].DATAIN iWE_N => SRAM_WE_N.DATAIN iWE_N => SRAM_DQ[0]~0.OE iWE_N => SRAM_DQ[1]~1.OE iWE_N => SRAM_DQ[2]~2.OE iWE_N => SRAM_DQ[3]~3.OE iWE_N => SRAM_DQ[4]~4.OE iWE_N => SRAM_DQ[5]~5.OE iWE_N => SRAM_DQ[6]~6.OE iWE_N => SRAM_DQ[7]~7.OE iWE_N => SRAM_DQ[8]~8.OE iWE_N => SRAM_DQ[9]~9.OE iWE_N => SRAM_DQ[10]~10.OE iWE_N => SRAM_DQ[11]~11.OE iWE_N => SRAM_DQ[12]~12.OE iWE_N => SRAM_DQ[13]~13.OE iWE_N => SRAM_DQ[14]~14.OE iWE_N => SRAM_DQ[15]~15.OE iOE_N => SRAM_OE_N.DATAIN iCE_N => SRAM_CE_N.DATAIN iRST_N => ~NO_FANOUT~ iUB_N => SRAM_UB_N.DATAIN iLB_N => SRAM_LB_N.DATAIN SRAM_DQ[0] <= SRAM_DQ[0]~0 SRAM_DQ[1] <= SRAM_DQ[1]~1 SRAM_DQ[2] <= SRAM_DQ[2]~2 SRAM_DQ[3] <= SRAM_DQ[3]~3 SRAM_DQ[4] <= SRAM_DQ[4]~4 SRAM_DQ[5] <= SRAM_DQ[5]~5 SRAM_DQ[6] <= SRAM_DQ[6]~6 SRAM_DQ[7] <= SRAM_DQ[7]~7 SRAM_DQ[8] <= SRAM_DQ[8]~8 SRAM_DQ[9] <= SRAM_DQ[9]~9 SRAM_DQ[10] <= SRAM_DQ[10]~10 SRAM_DQ[11] <= SRAM_DQ[11]~11 SRAM_DQ[12] <= SRAM_DQ[12]~12 SRAM_DQ[13] <= SRAM_DQ[13]~13 SRAM_DQ[14] <= SRAM_DQ[14]~14 SRAM_DQ[15] <= SRAM_DQ[15]~15 SRAM_ADDR[0] <= iADDR[0].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[1] <= iADDR[1].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[2] <= iADDR[2].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[3] <= iADDR[3].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[4] <= iADDR[4].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[5] <= iADDR[5].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[6] <= iADDR[6].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[7] <= iADDR[7].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[8] <= iADDR[8].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[9] <= iADDR[9].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[10] <= iADDR[10].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[11] <= iADDR[11].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[12] <= iADDR[12].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[13] <= iADDR[13].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[14] <= iADDR[14].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[15] <= iADDR[15].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[16] <= iADDR[16].DB_MAX_OUTPUT_PORT_TYPE SRAM_ADDR[17] <= iADDR[17].DB_MAX_OUTPUT_PORT_TYPE SRAM_UB_N <= iUB_N.DB_MAX_OUTPUT_PORT_TYPE SRAM_LB_N <= iLB_N.DB_MAX_OUTPUT_PORT_TYPE SRAM_WE_N <= iWE_N.DB_MAX_OUTPUT_PORT_TYPE SRAM_CE_N <= iCE_N.DB_MAX_OUTPUT_PORT_TYPE SRAM_OE_N <= iOE_N.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave clk => d1_reasons_to_wait.CLK clk => select_n_to_the_cfi_flash_0~reg0.CLK clk => tri_state_bridge_0_avalon_slave_arb_share_counter[2].CLK clk => tri_state_bridge_0_avalon_slave_arb_share_counter[1].CLK clk => tri_state_bridge_0_avalon_slave_arb_share_counter[0].CLK clk => tri_state_bridge_0_avalon_slave_slavearbiterlockenable.CLK clk => last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1.CLK clk => cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1].CLK clk => cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0].CLK clk => incoming_tri_state_bridge_0_data[7]~reg0.CLK clk => incoming_tri_state_bridge_0_data[6]~reg0.CLK clk => incoming_tri_state_bridge_0_data[5]~reg0.CLK clk => incoming_tri_state_bridge_0_data[4]~reg0.CLK clk => incoming_tri_state_bridge_0_data[3]~reg0.CLK clk => incoming_tri_state_bridge_0_data[2]~reg0.CLK clk => incoming_tri_state_bridge_0_data[1]~reg0.CLK clk => incoming_tri_state_bridge_0_data[0]~reg0.CLK clk => d1_outgoing_tri_state_bridge_0_data[7].CLK clk => d1_outgoing_tri_state_bridge_0_data[6].CLK clk => d1_outgoing_tri_state_bridge_0_data[5].CLK clk => d1_outgoing_tri_state_bridge_0_data[4].CLK clk => d1_outgoing_tri_state_bridge_0_data[3].CLK clk => d1_outgoing_tri_state_bridge_0_data[2].CLK clk => d1_outgoing_tri_state_bridge_0_data[1].CLK clk => d1_outgoing_tri_state_bridge_0_data[0].CLK clk => d1_in_a_write_cycle.CLK clk => last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1.CLK clk => cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1].CLK clk => cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0].CLK clk => tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1].CLK clk => tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0].CLK clk => tri_state_bridge_0_avalon_slave_arb_addend[1].CLK clk => tri_state_bridge_0_avalon_slave_arb_addend[0].CLK clk => tri_state_bridge_0_readn~reg0.CLK clk => write_n_to_the_cfi_flash_0~reg0.CLK clk => tri_state_bridge_0_address[21]~reg0.CLK clk => tri_state_bridge_0_address[20]~reg0.CLK clk => tri_state_bridge_0_address[19]~reg0.CLK clk => tri_state_bridge_0_address[18]~reg0.CLK clk => tri_state_bridge_0_address[17]~reg0.CLK clk => tri_state_bridge_0_address[16]~reg0.CLK clk => tri_state_bridge_0_address[15]~reg0.CLK clk => tri_state_bridge_0_address[14]~reg0.CLK clk => tri_state_bridge_0_address[13]~reg0.CLK clk => tri_state_bridge_0_address[12]~reg0.CLK clk => tri_state_bridge_0_address[11]~reg0.CLK clk => tri_state_bridge_0_address[10]~reg0.CLK clk => tri_state_bridge_0_address[9]~reg0.CLK clk => tri_state_bridge_0_address[8]~reg0.CLK clk => tri_state_bridge_0_address[7]~reg0.CLK clk => tri_state_bridge_0_address[6]~reg0.CLK clk => tri_state_bridge_0_address[5]~reg0.CLK clk => tri_state_bridge_0_address[4]~reg0.CLK clk => tri_state_bridge_0_address[3]~reg0.CLK clk => tri_state_bridge_0_address[2]~reg0.CLK clk => tri_state_bridge_0_address[1]~reg0.CLK clk => tri_state_bridge_0_address[0]~reg0.CLK clk => d1_tri_state_bridge_0_avalon_slave_end_xfer~reg0.CLK clk => cfi_flash_0_s1_wait_counter[4].CLK clk => cfi_flash_0_s1_wait_counter[3].CLK clk => cfi_flash_0_s1_wait_counter[2].CLK clk => cfi_flash_0_s1_wait_counter[1].CLK clk => cfi_flash_0_s1_wait_counter[0].CLK cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[2] => p1_tri_state_bridge_0_address[2].DATAB cpu_0_data_master_address_to_slave[3] => p1_tri_state_bridge_0_address[3].DATAB cpu_0_data_master_address_to_slave[4] => p1_tri_state_bridge_0_address[4].DATAB cpu_0_data_master_address_to_slave[5] => p1_tri_state_bridge_0_address[5].DATAB cpu_0_data_master_address_to_slave[6] => p1_tri_state_bridge_0_address[6].DATAB cpu_0_data_master_address_to_slave[7] => p1_tri_state_bridge_0_address[7].DATAB cpu_0_data_master_address_to_slave[8] => p1_tri_state_bridge_0_address[8].DATAB cpu_0_data_master_address_to_slave[9] => p1_tri_state_bridge_0_address[9].DATAB cpu_0_data_master_address_to_slave[10] => p1_tri_state_bridge_0_address[10].DATAB cpu_0_data_master_address_to_slave[11] => p1_tri_state_bridge_0_address[11].DATAB cpu_0_data_master_address_to_slave[12] => p1_tri_state_bridge_0_address[12].DATAB cpu_0_data_master_address_to_slave[13] => p1_tri_state_bridge_0_address[13].DATAB cpu_0_data_master_address_to_slave[14] => p1_tri_state_bridge_0_address[14].DATAB cpu_0_data_master_address_to_slave[15] => p1_tri_state_bridge_0_address[15].DATAB cpu_0_data_master_address_to_slave[16] => p1_tri_state_bridge_0_address[16].DATAB cpu_0_data_master_address_to_slave[17] => p1_tri_state_bridge_0_address[17].DATAB cpu_0_data_master_address_to_slave[18] => p1_tri_state_bridge_0_address[18].DATAB cpu_0_data_master_address_to_slave[19] => p1_tri_state_bridge_0_address[19].DATAB cpu_0_data_master_address_to_slave[20] => p1_tri_state_bridge_0_address[20].DATAB cpu_0_data_master_address_to_slave[21] => p1_tri_state_bridge_0_address[21].DATAB cpu_0_data_master_address_to_slave[22] => Equal0.IN1 cpu_0_data_master_address_to_slave[23] => Equal0.IN0 cpu_0_data_master_byteenable[0] => cpu_0_data_master_byteenable_cfi_flash_0_s1~2.DATAB cpu_0_data_master_byteenable[1] => cpu_0_data_master_byteenable_cfi_flash_0_s1~1.DATAB cpu_0_data_master_byteenable[2] => cpu_0_data_master_byteenable_cfi_flash_0_s1~0.DATAB cpu_0_data_master_byteenable[3] => cpu_0_data_master_byteenable_cfi_flash_0_s1~0.DATAA cpu_0_data_master_dbs_address[0] => p1_tri_state_bridge_0_address[0].DATAB cpu_0_data_master_dbs_address[0] => Equal4.IN31 cpu_0_data_master_dbs_address[0] => Equal5.IN0 cpu_0_data_master_dbs_address[0] => Equal6.IN31 cpu_0_data_master_dbs_address[1] => p1_tri_state_bridge_0_address[1].DATAB cpu_0_data_master_dbs_address[1] => Equal4.IN30 cpu_0_data_master_dbs_address[1] => Equal5.IN31 cpu_0_data_master_dbs_address[1] => Equal6.IN0 cpu_0_data_master_dbs_write_8[0] => d1_outgoing_tri_state_bridge_0_data[0].DATAIN cpu_0_data_master_dbs_write_8[1] => d1_outgoing_tri_state_bridge_0_data[1].DATAIN cpu_0_data_master_dbs_write_8[2] => d1_outgoing_tri_state_bridge_0_data[2].DATAIN cpu_0_data_master_dbs_write_8[3] => d1_outgoing_tri_state_bridge_0_data[3].DATAIN cpu_0_data_master_dbs_write_8[4] => d1_outgoing_tri_state_bridge_0_data[4].DATAIN cpu_0_data_master_dbs_write_8[5] => d1_outgoing_tri_state_bridge_0_data[5].DATAIN cpu_0_data_master_dbs_write_8[6] => d1_outgoing_tri_state_bridge_0_data[6].DATAIN cpu_0_data_master_dbs_write_8[7] => d1_outgoing_tri_state_bridge_0_data[7].DATAIN cpu_0_data_master_no_byte_enables_and_last_term => cpu_0_data_master_qualified_request_cfi_flash_0_s1~1.IN1 cpu_0_data_master_read => cfi_flash_0_s1_in_a_read_cycle~0.IN0 cpu_0_data_master_read => cpu_0_data_master_qualified_request_cfi_flash_0_s1~0.IN0 cpu_0_data_master_read => cpu_0_data_master_requests_cfi_flash_0_s1~0.IN0 cpu_0_data_master_write => in_a_write_cycle.IN0 cpu_0_data_master_write => cpu_0_data_master_qualified_request_cfi_flash_0_s1~2.IN1 cpu_0_data_master_write => cpu_0_data_master_requests_cfi_flash_0_s1~0.IN1 cpu_0_instruction_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_instruction_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_instruction_master_address_to_slave[2] => p1_tri_state_bridge_0_address[2].DATAA cpu_0_instruction_master_address_to_slave[3] => p1_tri_state_bridge_0_address[3].DATAA cpu_0_instruction_master_address_to_slave[4] => p1_tri_state_bridge_0_address[4].DATAA cpu_0_instruction_master_address_to_slave[5] => p1_tri_state_bridge_0_address[5].DATAA cpu_0_instruction_master_address_to_slave[6] => p1_tri_state_bridge_0_address[6].DATAA cpu_0_instruction_master_address_to_slave[7] => p1_tri_state_bridge_0_address[7].DATAA cpu_0_instruction_master_address_to_slave[8] => p1_tri_state_bridge_0_address[8].DATAA cpu_0_instruction_master_address_to_slave[9] => p1_tri_state_bridge_0_address[9].DATAA cpu_0_instruction_master_address_to_slave[10] => p1_tri_state_bridge_0_address[10].DATAA cpu_0_instruction_master_address_to_slave[11] => p1_tri_state_bridge_0_address[11].DATAA cpu_0_instruction_master_address_to_slave[12] => p1_tri_state_bridge_0_address[12].DATAA cpu_0_instruction_master_address_to_slave[13] => p1_tri_state_bridge_0_address[13].DATAA cpu_0_instruction_master_address_to_slave[14] => p1_tri_state_bridge_0_address[14].DATAA cpu_0_instruction_master_address_to_slave[15] => p1_tri_state_bridge_0_address[15].DATAA cpu_0_instruction_master_address_to_slave[16] => p1_tri_state_bridge_0_address[16].DATAA cpu_0_instruction_master_address_to_slave[17] => p1_tri_state_bridge_0_address[17].DATAA cpu_0_instruction_master_address_to_slave[18] => p1_tri_state_bridge_0_address[18].DATAA cpu_0_instruction_master_address_to_slave[19] => p1_tri_state_bridge_0_address[19].DATAA cpu_0_instruction_master_address_to_slave[20] => p1_tri_state_bridge_0_address[20].DATAA cpu_0_instruction_master_address_to_slave[21] => p1_tri_state_bridge_0_address[21].DATAA cpu_0_instruction_master_address_to_slave[22] => Equal1.IN1 cpu_0_instruction_master_address_to_slave[23] => Equal1.IN0 cpu_0_instruction_master_dbs_address[0] => p1_tri_state_bridge_0_address[0].DATAA cpu_0_instruction_master_dbs_address[1] => p1_tri_state_bridge_0_address[1].DATAA cpu_0_instruction_master_latency_counter[0] => LessThan0.IN4 cpu_0_instruction_master_latency_counter[1] => LessThan0.IN3 cpu_0_instruction_master_read => cfi_flash_0_s1_in_a_read_cycle~1.IN0 cpu_0_instruction_master_read => cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~1.IN0 cpu_0_instruction_master_read => cpu_0_instruction_master_requests_cfi_flash_0_s1~1.IN0 cpu_0_instruction_master_read => cpu_0_instruction_master_requests_cfi_flash_0_s1~0.IN0 cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register => cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~0.IN1 reset_n => cfi_flash_0_s1_wait_counter[0].ACLR reset_n => cfi_flash_0_s1_wait_counter[1].ACLR reset_n => cfi_flash_0_s1_wait_counter[2].ACLR reset_n => cfi_flash_0_s1_wait_counter[3].ACLR reset_n => cfi_flash_0_s1_wait_counter[4].ACLR reset_n => tri_state_bridge_0_avalon_slave_arb_addend[0].PRESET reset_n => tri_state_bridge_0_avalon_slave_arb_addend[1].ACLR reset_n => tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0].ACLR reset_n => tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1].ACLR reset_n => last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1.ACLR reset_n => d1_in_a_write_cycle.ACLR reset_n => d1_outgoing_tri_state_bridge_0_data[0].ACLR reset_n => d1_outgoing_tri_state_bridge_0_data[1].ACLR reset_n => d1_outgoing_tri_state_bridge_0_data[2].ACLR reset_n => d1_outgoing_tri_state_bridge_0_data[3].ACLR reset_n => d1_outgoing_tri_state_bridge_0_data[4].ACLR reset_n => d1_outgoing_tri_state_bridge_0_data[5].ACLR reset_n => d1_outgoing_tri_state_bridge_0_data[6].ACLR reset_n => d1_outgoing_tri_state_bridge_0_data[7].ACLR reset_n => last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1.ACLR reset_n => tri_state_bridge_0_avalon_slave_slavearbiterlockenable.ACLR reset_n => tri_state_bridge_0_avalon_slave_arb_share_counter[0].ACLR reset_n => tri_state_bridge_0_avalon_slave_arb_share_counter[1].ACLR reset_n => tri_state_bridge_0_avalon_slave_arb_share_counter[2].ACLR reset_n => d1_reasons_to_wait.ACLR reset_n => write_n_to_the_cfi_flash_0~reg0.PRESET reset_n => tri_state_bridge_0_readn~reg0.PRESET reset_n => incoming_tri_state_bridge_0_data[0]~reg0.ACLR reset_n => incoming_tri_state_bridge_0_data[1]~reg0.ACLR reset_n => incoming_tri_state_bridge_0_data[2]~reg0.ACLR reset_n => incoming_tri_state_bridge_0_data[3]~reg0.ACLR reset_n => incoming_tri_state_bridge_0_data[4]~reg0.ACLR reset_n => incoming_tri_state_bridge_0_data[5]~reg0.ACLR reset_n => incoming_tri_state_bridge_0_data[6]~reg0.ACLR reset_n => incoming_tri_state_bridge_0_data[7]~reg0.ACLR reset_n => d1_tri_state_bridge_0_avalon_slave_end_xfer~reg0.PRESET reset_n => cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0].ACLR reset_n => cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1].ACLR reset_n => cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1].ACLR reset_n => cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0].ACLR reset_n => select_n_to_the_cfi_flash_0~reg0.PRESET reset_n => tri_state_bridge_0_address[21]~reg0.ACLR reset_n => tri_state_bridge_0_address[20]~reg0.ACLR reset_n => tri_state_bridge_0_address[19]~reg0.ACLR reset_n => tri_state_bridge_0_address[18]~reg0.ACLR reset_n => tri_state_bridge_0_address[17]~reg0.ACLR reset_n => tri_state_bridge_0_address[16]~reg0.ACLR reset_n => tri_state_bridge_0_address[15]~reg0.ACLR reset_n => tri_state_bridge_0_address[14]~reg0.ACLR reset_n => tri_state_bridge_0_address[13]~reg0.ACLR reset_n => tri_state_bridge_0_address[12]~reg0.ACLR reset_n => tri_state_bridge_0_address[11]~reg0.ACLR reset_n => tri_state_bridge_0_address[10]~reg0.ACLR reset_n => tri_state_bridge_0_address[9]~reg0.ACLR reset_n => tri_state_bridge_0_address[8]~reg0.ACLR reset_n => tri_state_bridge_0_address[7]~reg0.ACLR reset_n => tri_state_bridge_0_address[6]~reg0.ACLR reset_n => tri_state_bridge_0_address[5]~reg0.ACLR reset_n => tri_state_bridge_0_address[4]~reg0.ACLR reset_n => tri_state_bridge_0_address[3]~reg0.ACLR reset_n => tri_state_bridge_0_address[2]~reg0.ACLR reset_n => tri_state_bridge_0_address[1]~reg0.ACLR reset_n => tri_state_bridge_0_address[0]~reg0.ACLR cfi_flash_0_s1_wait_counter_eq_0 <= Equal3.DB_MAX_OUTPUT_PORT_TYPE cfi_flash_0_s1_wait_counter_eq_1 <= Equal2.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_byteenable_cfi_flash_0_s1 <= cpu_0_data_master_byteenable_cfi_flash_0_s1~2.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_granted_cfi_flash_0_s1 <= tri_state_bridge_0_avalon_slave_grant_vector[1].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_qualified_request_cfi_flash_0_s1 <= cpu_0_data_master_qualified_request_cfi_flash_0_s1~5.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_read_data_valid_cfi_flash_0_s1 <= cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1].DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_requests_cfi_flash_0_s1 <= cpu_0_data_master_requests_cfi_flash_0_s1~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_granted_cfi_flash_0_s1 <= tri_state_bridge_0_avalon_slave_grant_vector~0.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_qualified_request_cfi_flash_0_s1 <= cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~3.DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 <= cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1].DB_MAX_OUTPUT_PORT_TYPE cpu_0_instruction_master_requests_cfi_flash_0_s1 <= cpu_0_instruction_master_requests_cfi_flash_0_s1~1.DB_MAX_OUTPUT_PORT_TYPE d1_tri_state_bridge_0_avalon_slave_end_xfer <= d1_tri_state_bridge_0_avalon_slave_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data[0] <= incoming_tri_state_bridge_0_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data[1] <= incoming_tri_state_bridge_0_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data[2] <= incoming_tri_state_bridge_0_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data[3] <= incoming_tri_state_bridge_0_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data[4] <= incoming_tri_state_bridge_0_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data[5] <= incoming_tri_state_bridge_0_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data[6] <= incoming_tri_state_bridge_0_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data[7] <= incoming_tri_state_bridge_0_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[0] <= incoming_tri_state_bridge_0_data_with_Xs_converted_to_0~7.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[1] <= incoming_tri_state_bridge_0_data_with_Xs_converted_to_0~6.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[2] <= incoming_tri_state_bridge_0_data_with_Xs_converted_to_0~5.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[3] <= incoming_tri_state_bridge_0_data_with_Xs_converted_to_0~4.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[4] <= incoming_tri_state_bridge_0_data_with_Xs_converted_to_0~3.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[5] <= incoming_tri_state_bridge_0_data_with_Xs_converted_to_0~2.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[6] <= incoming_tri_state_bridge_0_data_with_Xs_converted_to_0~1.DB_MAX_OUTPUT_PORT_TYPE incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[7] <= incoming_tri_state_bridge_0_data_with_Xs_converted_to_0~0.DB_MAX_OUTPUT_PORT_TYPE registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1 <= cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0].DB_MAX_OUTPUT_PORT_TYPE select_n_to_the_cfi_flash_0 <= select_n_to_the_cfi_flash_0~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[0] <= tri_state_bridge_0_address[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[1] <= tri_state_bridge_0_address[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[2] <= tri_state_bridge_0_address[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[3] <= tri_state_bridge_0_address[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[4] <= tri_state_bridge_0_address[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[5] <= tri_state_bridge_0_address[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[6] <= tri_state_bridge_0_address[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[7] <= tri_state_bridge_0_address[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[8] <= tri_state_bridge_0_address[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[9] <= tri_state_bridge_0_address[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[10] <= tri_state_bridge_0_address[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[11] <= tri_state_bridge_0_address[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[12] <= tri_state_bridge_0_address[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[13] <= tri_state_bridge_0_address[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[14] <= tri_state_bridge_0_address[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[15] <= tri_state_bridge_0_address[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[16] <= tri_state_bridge_0_address[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[17] <= tri_state_bridge_0_address[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[18] <= tri_state_bridge_0_address[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[19] <= tri_state_bridge_0_address[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[20] <= tri_state_bridge_0_address[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_address[21] <= tri_state_bridge_0_address[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE tri_state_bridge_0_data[0] <= tri_state_bridge_0_data[0]~0 tri_state_bridge_0_data[1] <= tri_state_bridge_0_data[1]~7 tri_state_bridge_0_data[2] <= tri_state_bridge_0_data[2]~6 tri_state_bridge_0_data[3] <= tri_state_bridge_0_data[3]~5 tri_state_bridge_0_data[4] <= tri_state_bridge_0_data[4]~4 tri_state_bridge_0_data[5] <= tri_state_bridge_0_data[5]~3 tri_state_bridge_0_data[6] <= tri_state_bridge_0_data[6]~2 tri_state_bridge_0_data[7] <= tri_state_bridge_0_data[7]~1 tri_state_bridge_0_readn <= tri_state_bridge_0_readn~reg0.DB_MAX_OUTPUT_PORT_TYPE write_n_to_the_cfi_flash_0 <= write_n_to_the_cfi_flash_0~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|uart_0_s1_arbitrator:the_uart_0_s1 clk => d1_reasons_to_wait.CLK clk => d1_uart_0_s1_end_xfer~reg0.CLK cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~ cpu_0_data_master_address_to_slave[2] => uart_0_s1_address[0].DATAIN cpu_0_data_master_address_to_slave[3] => uart_0_s1_address[1].DATAIN cpu_0_data_master_address_to_slave[4] => uart_0_s1_address[2].DATAIN cpu_0_data_master_address_to_slave[5] => Equal0.IN13 cpu_0_data_master_address_to_slave[6] => Equal0.IN14 cpu_0_data_master_address_to_slave[7] => Equal0.IN15 cpu_0_data_master_address_to_slave[8] => Equal0.IN16 cpu_0_data_master_address_to_slave[9] => Equal0.IN17 cpu_0_data_master_address_to_slave[10] => Equal0.IN18 cpu_0_data_master_address_to_slave[11] => Equal0.IN19 cpu_0_data_master_address_to_slave[12] => Equal0.IN0 cpu_0_data_master_address_to_slave[13] => Equal0.IN20 cpu_0_data_master_address_to_slave[14] => Equal0.IN21 cpu_0_data_master_address_to_slave[15] => Equal0.IN22 cpu_0_data_master_address_to_slave[16] => Equal0.IN23 cpu_0_data_master_address_to_slave[17] => Equal0.IN24 cpu_0_data_master_address_to_slave[18] => Equal0.IN25 cpu_0_data_master_address_to_slave[19] => Equal0.IN1 cpu_0_data_master_address_to_slave[20] => Equal0.IN26 cpu_0_data_master_address_to_slave[21] => Equal0.IN27 cpu_0_data_master_address_to_slave[22] => Equal0.IN2 cpu_0_data_master_address_to_slave[23] => Equal0.IN28 cpu_0_data_master_read => uart_0_s1_in_a_read_cycle.IN0 cpu_0_data_master_read => cpu_0_data_master_requests_uart_0_s1~0.IN0 cpu_0_data_master_write => uart_0_s1_in_a_write_cycle.IN0 cpu_0_data_master_write => cpu_0_data_master_requests_uart_0_s1~0.IN1 cpu_0_data_master_writedata[0] => uart_0_s1_writedata[0].DATAIN cpu_0_data_master_writedata[1] => uart_0_s1_writedata[1].DATAIN cpu_0_data_master_writedata[2] => uart_0_s1_writedata[2].DATAIN cpu_0_data_master_writedata[3] => uart_0_s1_writedata[3].DATAIN cpu_0_data_master_writedata[4] => uart_0_s1_writedata[4].DATAIN cpu_0_data_master_writedata[5] => uart_0_s1_writedata[5].DATAIN cpu_0_data_master_writedata[6] => uart_0_s1_writedata[6].DATAIN cpu_0_data_master_writedata[7] => uart_0_s1_writedata[7].DATAIN cpu_0_data_master_writedata[8] => uart_0_s1_writedata[8].DATAIN cpu_0_data_master_writedata[9] => uart_0_s1_writedata[9].DATAIN cpu_0_data_master_writedata[10] => uart_0_s1_writedata[10].DATAIN cpu_0_data_master_writedata[11] => uart_0_s1_writedata[11].DATAIN cpu_0_data_master_writedata[12] => uart_0_s1_writedata[12].DATAIN cpu_0_data_master_writedata[13] => uart_0_s1_writedata[13].DATAIN cpu_0_data_master_writedata[14] => uart_0_s1_writedata[14].DATAIN cpu_0_data_master_writedata[15] => uart_0_s1_writedata[15].DATAIN cpu_0_data_master_writedata[16] => ~NO_FANOUT~ cpu_0_data_master_writedata[17] => ~NO_FANOUT~ cpu_0_data_master_writedata[18] => ~NO_FANOUT~ cpu_0_data_master_writedata[19] => ~NO_FANOUT~ cpu_0_data_master_writedata[20] => ~NO_FANOUT~ cpu_0_data_master_writedata[21] => ~NO_FANOUT~ cpu_0_data_master_writedata[22] => ~NO_FANOUT~ cpu_0_data_master_writedata[23] => ~NO_FANOUT~ cpu_0_data_master_writedata[24] => ~NO_FANOUT~ cpu_0_data_master_writedata[25] => ~NO_FANOUT~ cpu_0_data_master_writedata[26] => ~NO_FANOUT~ cpu_0_data_master_writedata[27] => ~NO_FANOUT~ cpu_0_data_master_writedata[28] => ~NO_FANOUT~ cpu_0_data_master_writedata[29] => ~NO_FANOUT~ cpu_0_data_master_writedata[30] => ~NO_FANOUT~ cpu_0_data_master_writedata[31] => ~NO_FANOUT~ reset_n => uart_0_s1_reset_n.DATAIN reset_n => d1_reasons_to_wait.ACLR reset_n => d1_uart_0_s1_end_xfer~reg0.PRESET uart_0_s1_dataavailable => uart_0_s1_dataavailable_from_sa.DATAIN uart_0_s1_irq => uart_0_s1_irq_from_sa.DATAIN uart_0_s1_readdata[0] => uart_0_s1_readdata_from_sa[0].DATAIN uart_0_s1_readdata[1] => uart_0_s1_readdata_from_sa[1].DATAIN uart_0_s1_readdata[2] => uart_0_s1_readdata_from_sa[2].DATAIN uart_0_s1_readdata[3] => uart_0_s1_readdata_from_sa[3].DATAIN uart_0_s1_readdata[4] => uart_0_s1_readdata_from_sa[4].DATAIN uart_0_s1_readdata[5] => uart_0_s1_readdata_from_sa[5].DATAIN uart_0_s1_readdata[6] => uart_0_s1_readdata_from_sa[6].DATAIN uart_0_s1_readdata[7] => uart_0_s1_readdata_from_sa[7].DATAIN uart_0_s1_readdata[8] => uart_0_s1_readdata_from_sa[8].DATAIN uart_0_s1_readdata[9] => uart_0_s1_readdata_from_sa[9].DATAIN uart_0_s1_readdata[10] => uart_0_s1_readdata_from_sa[10].DATAIN uart_0_s1_readdata[11] => uart_0_s1_readdata_from_sa[11].DATAIN uart_0_s1_readdata[12] => uart_0_s1_readdata_from_sa[12].DATAIN uart_0_s1_readdata[13] => uart_0_s1_readdata_from_sa[13].DATAIN uart_0_s1_readdata[14] => uart_0_s1_readdata_from_sa[14].DATAIN uart_0_s1_readdata[15] => uart_0_s1_readdata_from_sa[15].DATAIN uart_0_s1_readyfordata => uart_0_s1_readyfordata_from_sa.DATAIN cpu_0_data_master_granted_uart_0_s1 <= cpu_0_data_master_requests_uart_0_s1~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_qualified_request_uart_0_s1 <= cpu_0_data_master_requests_uart_0_s1~1.DB_MAX_OUTPUT_PORT_TYPE cpu_0_data_master_read_data_valid_uart_0_s1 <= cpu_0_data_master_requests_uart_0_s1 <= cpu_0_data_master_requests_uart_0_s1~1.DB_MAX_OUTPUT_PORT_TYPE d1_uart_0_s1_end_xfer <= d1_uart_0_s1_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_address[0] <= cpu_0_data_master_address_to_slave[2].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_address[1] <= cpu_0_data_master_address_to_slave[3].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_address[2] <= cpu_0_data_master_address_to_slave[4].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_begintransfer <= uart_0_s1_begins_xfer~0.DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_chipselect <= cpu_0_data_master_requests_uart_0_s1~1.DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_dataavailable_from_sa <= uart_0_s1_dataavailable.DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_irq_from_sa <= uart_0_s1_irq.DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_read_n <= uart_0_s1_in_a_read_cycle.DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[0] <= uart_0_s1_readdata[0].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[1] <= uart_0_s1_readdata[1].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[2] <= uart_0_s1_readdata[2].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[3] <= uart_0_s1_readdata[3].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[4] <= uart_0_s1_readdata[4].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[5] <= uart_0_s1_readdata[5].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[6] <= uart_0_s1_readdata[6].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[7] <= uart_0_s1_readdata[7].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[8] <= uart_0_s1_readdata[8].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[9] <= uart_0_s1_readdata[9].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[10] <= uart_0_s1_readdata[10].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[11] <= uart_0_s1_readdata[11].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[12] <= uart_0_s1_readdata[12].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[13] <= uart_0_s1_readdata[13].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[14] <= uart_0_s1_readdata[14].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readdata_from_sa[15] <= uart_0_s1_readdata[15].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_readyfordata_from_sa <= uart_0_s1_readyfordata.DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_reset_n <= reset_n.DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_write_n <= uart_0_s1_in_a_write_cycle.DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[0] <= cpu_0_data_master_writedata[0].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[1] <= cpu_0_data_master_writedata[1].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[2] <= cpu_0_data_master_writedata[2].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[3] <= cpu_0_data_master_writedata[3].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[4] <= cpu_0_data_master_writedata[4].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[5] <= cpu_0_data_master_writedata[5].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[6] <= cpu_0_data_master_writedata[6].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[7] <= cpu_0_data_master_writedata[7].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[8] <= cpu_0_data_master_writedata[8].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[9] <= cpu_0_data_master_writedata[9].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[10] <= cpu_0_data_master_writedata[10].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[11] <= cpu_0_data_master_writedata[11].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[12] <= cpu_0_data_master_writedata[12].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[13] <= cpu_0_data_master_writedata[13].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[14] <= cpu_0_data_master_writedata[14].DB_MAX_OUTPUT_PORT_TYPE uart_0_s1_writedata[15] <= cpu_0_data_master_writedata[15].DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|uart_0:the_uart_0 address[0] => address[0]~2.IN1 address[1] => address[1]~1.IN1 address[2] => address[2]~0.IN1 begintransfer => begintransfer~0.IN2 chipselect => chipselect~0.IN1 clk => clk~0.IN3 read_n => read_n~0.IN1 reset_n => reset_n~0.IN3 rxd => rxd~0.IN1 write_n => write_n~0.IN1 writedata[0] => writedata[0]~15.IN1 writedata[1] => writedata[1]~14.IN1 writedata[2] => writedata[2]~13.IN1 writedata[3] => writedata[3]~12.IN1 writedata[4] => writedata[4]~11.IN1 writedata[5] => writedata[5]~10.IN1 writedata[6] => writedata[6]~9.IN1 writedata[7] => writedata[7]~8.IN1 writedata[8] => writedata[8]~7.IN1 writedata[9] => writedata[9]~6.IN1 writedata[10] => writedata[10]~5.IN1 writedata[11] => writedata[11]~4.IN1 writedata[12] => writedata[12]~3.IN1 writedata[13] => writedata[13]~2.IN1 writedata[14] => writedata[14]~1.IN1 writedata[15] => writedata[15]~0.IN1 dataavailable <= uart_0_regs:the_uart_0_regs.dataavailable irq <= uart_0_regs:the_uart_0_regs.irq readdata[0] <= uart_0_regs:the_uart_0_regs.readdata readdata[1] <= uart_0_regs:the_uart_0_regs.readdata readdata[2] <= uart_0_regs:the_uart_0_regs.readdata readdata[3] <= uart_0_regs:the_uart_0_regs.readdata readdata[4] <= uart_0_regs:the_uart_0_regs.readdata readdata[5] <= uart_0_regs:the_uart_0_regs.readdata readdata[6] <= uart_0_regs:the_uart_0_regs.readdata readdata[7] <= uart_0_regs:the_uart_0_regs.readdata readdata[8] <= uart_0_regs:the_uart_0_regs.readdata readdata[9] <= uart_0_regs:the_uart_0_regs.readdata readdata[10] <= uart_0_regs:the_uart_0_regs.readdata readdata[11] <= uart_0_regs:the_uart_0_regs.readdata readdata[12] <= uart_0_regs:the_uart_0_regs.readdata readdata[13] <= uart_0_regs:the_uart_0_regs.readdata readdata[14] <= uart_0_regs:the_uart_0_regs.readdata readdata[15] <= uart_0_regs:the_uart_0_regs.readdata readyfordata <= uart_0_regs:the_uart_0_regs.readyfordata txd <= uart_0_tx:the_uart_0_tx.txd |DE1_NIOS|system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx baud_divisor[0] => baud_rate_counter~9.DATAB baud_divisor[1] => baud_rate_counter~8.DATAB baud_divisor[2] => baud_rate_counter~7.DATAB baud_divisor[3] => baud_rate_counter~6.DATAB baud_divisor[4] => baud_rate_counter~5.DATAB baud_divisor[5] => baud_rate_counter~4.DATAB baud_divisor[6] => baud_rate_counter~3.DATAB baud_divisor[7] => baud_rate_counter~2.DATAB baud_divisor[8] => baud_rate_counter~1.DATAB baud_divisor[9] => baud_rate_counter~0.DATAB begintransfer => tx_wr_strobe_onset.IN0 clk => do_load_shifter.CLK clk => tx_ready~reg0.CLK clk => tx_overrun~reg0.CLK clk => tx_shift_empty~reg0.CLK clk => baud_rate_counter[9].CLK clk => baud_rate_counter[8].CLK clk => baud_rate_counter[7].CLK clk => baud_rate_counter[6].CLK clk => baud_rate_counter[5].CLK clk => baud_rate_counter[4].CLK clk => baud_rate_counter[3].CLK clk => baud_rate_counter[2].CLK clk => baud_rate_counter[1].CLK clk => baud_rate_counter[0].CLK clk => baud_clk_en.CLK clk => pre_txd.CLK clk => txd~reg0.CLK clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9].CLK clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8].CLK clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7].CLK clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6].CLK clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5].CLK clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4].CLK clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3].CLK clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2].CLK clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1].CLK clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0].CLK clk_en => do_load_shifter.ENA clk_en => tx_ready~reg0.ENA clk_en => tx_overrun~reg0.ENA clk_en => tx_shift_empty~reg0.ENA clk_en => baud_rate_counter[9].ENA clk_en => baud_rate_counter[8].ENA clk_en => baud_rate_counter[7].ENA clk_en => baud_rate_counter[6].ENA clk_en => baud_rate_counter[5].ENA clk_en => baud_rate_counter[4].ENA clk_en => baud_rate_counter[3].ENA clk_en => baud_rate_counter[2].ENA clk_en => baud_rate_counter[1].ENA clk_en => baud_rate_counter[0].ENA clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0].ENA clk_en => baud_clk_en.ENA clk_en => txd~reg0.ENA clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9].ENA clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8].ENA clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7].ENA clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6].ENA clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5].ENA clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4].ENA clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3].ENA clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2].ENA clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1].ENA do_force_break => txd~0.IN1 reset_n => pre_txd.PRESET reset_n => baud_clk_en.ACLR reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0].ACLR reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1].ACLR reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2].ACLR reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3].ACLR reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4].ACLR reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5].ACLR reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6].ACLR reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7].ACLR reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8].ACLR reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9].ACLR reset_n => tx_overrun~reg0.ACLR reset_n => tx_ready~reg0.PRESET reset_n => tx_shift_empty~reg0.PRESET reset_n => txd~reg0.PRESET reset_n => do_load_shifter.ACLR reset_n => baud_rate_counter[9].ACLR reset_n => baud_rate_counter[8].ACLR reset_n => baud_rate_counter[7].ACLR reset_n => baud_rate_counter[6].ACLR reset_n => baud_rate_counter[5].ACLR reset_n => baud_rate_counter[4].ACLR reset_n => baud_rate_counter[3].ACLR reset_n => baud_rate_counter[2].ACLR reset_n => baud_rate_counter[1].ACLR reset_n => baud_rate_counter[0].ACLR status_wr_strobe => tx_overrun~1.OUTPUTSELECT tx_data[0] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[1].DATAB tx_data[1] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[2].DATAB tx_data[2] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[3].DATAB tx_data[3] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[4].DATAB tx_data[4] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[5].DATAB tx_data[5] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[6].DATAB tx_data[6] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[7].DATAB tx_data[7] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[8].DATAB tx_wr_strobe => tx_wr_strobe_onset.IN1 tx_overrun <= tx_overrun~reg0.DB_MAX_OUTPUT_PORT_TYPE tx_ready <= tx_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE tx_shift_empty <= tx_shift_empty~reg0.DB_MAX_OUTPUT_PORT_TYPE txd <= txd~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx baud_divisor[0] => baud_divisor[0]~9.IN1 baud_divisor[1] => baud_divisor[1]~8.IN1 baud_divisor[2] => baud_divisor[2]~7.IN1 baud_divisor[3] => baud_divisor[3]~6.IN1 baud_divisor[4] => baud_divisor[4]~5.IN1 baud_divisor[5] => baud_divisor[5]~4.IN1 baud_divisor[6] => baud_divisor[6]~3.IN1 baud_divisor[7] => baud_divisor[7]~2.IN1 baud_divisor[8] => baud_divisor[8]~1.IN1 baud_divisor[9] => baud_divisor[9]~0.IN1 begintransfer => rx_rd_strobe_onset.IN0 clk => clk~0.IN1 clk_en => clk_en~0.IN1 reset_n => reset_n~0.IN1 rx_rd_strobe => rx_rd_strobe_onset.IN1 rxd => rxd~0.IN1 status_wr_strobe => rx_overrun~1.OUTPUTSELECT status_wr_strobe => break_detect~1.OUTPUTSELECT status_wr_strobe => framing_error~1.OUTPUTSELECT break_detect <= break_detect~reg0.DB_MAX_OUTPUT_PORT_TYPE framing_error <= framing_error~reg0.DB_MAX_OUTPUT_PORT_TYPE parity_error <= rx_char_ready <= rx_char_ready~3.DB_MAX_OUTPUT_PORT_TYPE rx_data[0] <= rx_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE rx_data[1] <= rx_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE rx_data[2] <= rx_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE rx_data[3] <= rx_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE rx_data[4] <= rx_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE rx_data[5] <= rx_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE rx_data[6] <= rx_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE rx_data[7] <= rx_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE rx_overrun <= rx_overrun~reg0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|uart_0_rx_stimulus_source:the_uart_0_rx_stimulus_source baud_divisor[0] => ~NO_FANOUT~ baud_divisor[1] => ~NO_FANOUT~ baud_divisor[2] => ~NO_FANOUT~ baud_divisor[3] => ~NO_FANOUT~ baud_divisor[4] => ~NO_FANOUT~ baud_divisor[5] => ~NO_FANOUT~ baud_divisor[6] => ~NO_FANOUT~ baud_divisor[7] => ~NO_FANOUT~ baud_divisor[8] => ~NO_FANOUT~ baud_divisor[9] => ~NO_FANOUT~ clk => ~NO_FANOUT~ clk_en => ~NO_FANOUT~ reset_n => ~NO_FANOUT~ rx_char_ready => ~NO_FANOUT~ rxd => source_rxd.DATAIN source_rxd <= rxd.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs address[0] => Equal0.IN2 address[0] => Equal1.IN2 address[0] => Equal2.IN2 address[0] => Equal3.IN1 address[1] => Equal0.IN1 address[1] => Equal1.IN1 address[1] => Equal2.IN1 address[1] => Equal3.IN2 address[2] => Equal0.IN0 address[2] => Equal1.IN0 address[2] => Equal2.IN0 address[2] => Equal3.IN0 break_detect => selected_read_data~26.IN1 break_detect => qualified_irq~7.IN1 break_detect => status_reg[8].IN1 chipselect => control_wr_strobe~0.IN1 chipselect => rx_rd_strobe~0.IN0 clk => readdata[15]~reg0.CLK clk => readdata[14]~reg0.CLK clk => readdata[13]~reg0.CLK clk => readdata[12]~reg0.CLK clk => readdata[11]~reg0.CLK clk => readdata[10]~reg0.CLK clk => readdata[9]~reg0.CLK clk => readdata[8]~reg0.CLK clk => readdata[7]~reg0.CLK clk => readdata[6]~reg0.CLK clk => readdata[5]~reg0.CLK clk => readdata[4]~reg0.CLK clk => readdata[3]~reg0.CLK clk => readdata[2]~reg0.CLK clk => readdata[1]~reg0.CLK clk => readdata[0]~reg0.CLK clk => irq~reg0.CLK clk => tx_data[7]~reg0.CLK clk => tx_data[6]~reg0.CLK clk => tx_data[5]~reg0.CLK clk => tx_data[4]~reg0.CLK clk => tx_data[3]~reg0.CLK clk => tx_data[2]~reg0.CLK clk => tx_data[1]~reg0.CLK clk => tx_data[0]~reg0.CLK clk => control_reg[9].CLK clk => control_reg[8].CLK clk => control_reg[7].CLK clk => control_reg[6].CLK clk => control_reg[5].CLK clk => control_reg[4].CLK clk => control_reg[3].CLK clk => control_reg[2].CLK clk => control_reg[1].CLK clk => control_reg[0].CLK clk => d1_rx_char_ready.CLK clk => d1_tx_ready.CLK clk_en => readdata[15]~reg0.ENA clk_en => readdata[14]~reg0.ENA clk_en => readdata[13]~reg0.ENA clk_en => readdata[12]~reg0.ENA clk_en => readdata[11]~reg0.ENA clk_en => readdata[10]~reg0.ENA clk_en => readdata[9]~reg0.ENA clk_en => readdata[8]~reg0.ENA clk_en => readdata[7]~reg0.ENA clk_en => readdata[6]~reg0.ENA clk_en => readdata[5]~reg0.ENA clk_en => readdata[4]~reg0.ENA clk_en => readdata[3]~reg0.ENA clk_en => readdata[2]~reg0.ENA clk_en => readdata[1]~reg0.ENA clk_en => readdata[0]~reg0.ENA clk_en => irq~reg0.ENA clk_en => d1_rx_char_ready.ENA clk_en => d1_tx_ready.ENA framing_error => selected_read_data~25.IN1 framing_error => qualified_irq~9.IN1 framing_error => any_error~2.IN1 parity_error => selected_read_data~24.IN1 parity_error => qualified_irq~11.IN1 parity_error => any_error~1.IN1 read_n => rx_rd_strobe~0.IN1 reset_n => tx_data[0]~reg0.ACLR reset_n => tx_data[1]~reg0.ACLR reset_n => tx_data[2]~reg0.ACLR reset_n => tx_data[3]~reg0.ACLR reset_n => tx_data[4]~reg0.ACLR reset_n => tx_data[5]~reg0.ACLR reset_n => tx_data[6]~reg0.ACLR reset_n => tx_data[7]~reg0.ACLR reset_n => d1_tx_ready.ACLR reset_n => control_reg[0].ACLR reset_n => control_reg[1].ACLR reset_n => control_reg[2].ACLR reset_n => control_reg[3].ACLR reset_n => control_reg[4].ACLR reset_n => control_reg[5].ACLR reset_n => control_reg[6].ACLR reset_n => control_reg[7].ACLR reset_n => control_reg[8].ACLR reset_n => control_reg[9].ACLR reset_n => d1_rx_char_ready.ACLR reset_n => irq~reg0.ACLR reset_n => readdata[15]~reg0.ACLR reset_n => readdata[14]~reg0.ACLR reset_n => readdata[13]~reg0.ACLR reset_n => readdata[12]~reg0.ACLR reset_n => readdata[11]~reg0.ACLR reset_n => readdata[10]~reg0.ACLR reset_n => readdata[9]~reg0.ACLR reset_n => readdata[8]~reg0.ACLR reset_n => readdata[7]~reg0.ACLR reset_n => readdata[6]~reg0.ACLR reset_n => readdata[5]~reg0.ACLR reset_n => readdata[4]~reg0.ACLR reset_n => readdata[3]~reg0.ACLR reset_n => readdata[2]~reg0.ACLR reset_n => readdata[1]~reg0.ACLR reset_n => readdata[0]~reg0.ACLR rx_char_ready => selected_read_data~31.IN1 rx_char_ready => qualified_irq~13.IN1 rx_char_ready => d1_rx_char_ready.DATAIN rx_data[0] => selected_read_data~0.IN1 rx_data[1] => selected_read_data~1.IN1 rx_data[2] => selected_read_data~2.IN1 rx_data[3] => selected_read_data~3.IN1 rx_data[4] => selected_read_data~4.IN1 rx_data[5] => selected_read_data~5.IN1 rx_data[6] => selected_read_data~6.IN1 rx_data[7] => selected_read_data~7.IN1 rx_overrun => selected_read_data~27.IN1 rx_overrun => qualified_irq~5.IN1 rx_overrun => any_error~0.IN0 tx_overrun => selected_read_data~28.IN1 tx_overrun => qualified_irq~3.IN1 tx_overrun => any_error~0.IN1 tx_ready => selected_read_data~30.IN1 tx_ready => qualified_irq~15.IN1 tx_ready => d1_tx_ready.DATAIN tx_shift_empty => qualified_irq~1.IN1 tx_shift_empty => selected_read_data~29.IN1 write_n => control_wr_strobe~0.IN0 writedata[0] => tx_data[0]~reg0.DATAIN writedata[0] => control_reg[0].DATAIN writedata[1] => tx_data[1]~reg0.DATAIN writedata[1] => control_reg[1].DATAIN writedata[2] => tx_data[2]~reg0.DATAIN writedata[2] => control_reg[2].DATAIN writedata[3] => tx_data[3]~reg0.DATAIN writedata[3] => control_reg[3].DATAIN writedata[4] => tx_data[4]~reg0.DATAIN writedata[4] => control_reg[4].DATAIN writedata[5] => tx_data[5]~reg0.DATAIN writedata[5] => control_reg[5].DATAIN writedata[6] => tx_data[6]~reg0.DATAIN writedata[6] => control_reg[6].DATAIN writedata[7] => tx_data[7]~reg0.DATAIN writedata[7] => control_reg[7].DATAIN writedata[8] => control_reg[8].DATAIN writedata[9] => control_reg[9].DATAIN writedata[10] => ~NO_FANOUT~ writedata[11] => ~NO_FANOUT~ writedata[12] => ~NO_FANOUT~ writedata[13] => ~NO_FANOUT~ writedata[14] => ~NO_FANOUT~ writedata[15] => ~NO_FANOUT~ baud_divisor[0] <= baud_divisor[1] <= baud_divisor[2] <= baud_divisor[3] <= baud_divisor[4] <= baud_divisor[5] <= baud_divisor[6] <= baud_divisor[7] <= baud_divisor[8] <= baud_divisor[9] <= dataavailable <= d1_rx_char_ready.DB_MAX_OUTPUT_PORT_TYPE do_force_break <= control_reg[9].DB_MAX_OUTPUT_PORT_TYPE irq <= irq~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE readyfordata <= d1_tx_ready.DB_MAX_OUTPUT_PORT_TYPE rx_rd_strobe <= rx_rd_strobe~1.DB_MAX_OUTPUT_PORT_TYPE status_wr_strobe <= status_wr_strobe~0.DB_MAX_OUTPUT_PORT_TYPE tx_data[0] <= tx_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE tx_data[1] <= tx_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE tx_data[2] <= tx_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE tx_data[3] <= tx_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE tx_data[4] <= tx_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE tx_data[5] <= tx_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE tx_data[6] <= tx_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE tx_data[7] <= tx_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE tx_wr_strobe <= tx_wr_strobe~0.DB_MAX_OUTPUT_PORT_TYPE |DE1_NIOS|system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch clk => data_in_d1.CLK clk => data_out~reg0.CLK data_in => data_in_d1.DATAIN reset_n => data_in_d1.ACLR reset_n => data_out~reg0.ACLR data_out <= data_out~reg0.DB_MAX_OUTPUT_PORT_TYPE