{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version " "Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 30 15:46:22 2007 " "Info: Processing started: Thu Aug 30 15:46:22 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DE1_NIOS -c DE1_NIOS " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DE1_NIOS -c DE1_NIOS" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "DE1_NIOS EP2C20F484C7 " "Info: Selected device EP2C20F484C7 for design \"DE1_NIOS\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "SDRAM_PLL:PLL1\|altpll:altpll_component\|pll Cyclone II " "Info: Implemented PLL \"SDRAM_PLL:PLL1\|altpll:altpll_component\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk0 2 1 -108 -3000 " "Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of -108 degrees (-3000 ps) for SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk0 port" {  } { { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 2 1 0 0 " "Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 port" {  } { { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 877 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0}  } { { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } }  } 0 0 "Implemented PLL \"%1!s!\" as %2!s! PLL type" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Info: Device EP2C15AF484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Info: Device EP2C35F484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Info: Device EP2C50F484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Info: Pin ~ASDO~ is reserved at location C4" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Info: Pin ~nCSO~ is reserved at location C3" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Info: Pin ~LVDS91p/nCEO~ is reserved at location W20" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "4 283 " "Warning: No exact pin location assignment(s) for 4 pins of 283 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_CLK " "Info: Pin SD_CLK not assigned to an exact location on the device" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 179 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_DAT3 " "Info: Pin SD_DAT3 not assigned to an exact location on the device" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 177 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_CMD " "Info: Pin SD_CMD not assigned to an exact location on the device" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 178 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_DAT " "Info: Pin SD_DAT not assigned to an exact location on the device" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 176 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 130 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk0 (placed in counter C2 of PLL_1) " "Info: Automatically promoted node SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk0 (placed in counter C2 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations External Clock Output CLKCTRL_X0_Y1_N1 " "Info: Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_X0_Y1_N1" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 504 3 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 (placed in counter C0 of PLL_1) " "Info: Automatically promoted node SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 504 3 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Info: Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~UPDATEUSER  " "Info: Automatically promoted node altera_internal_jtag~UPDATEUSER " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updateir~112 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updateir~112" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" 139 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir~112 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir~112 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updatedr~99 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updatedr~99" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" 138 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr~99 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr~99 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out  " "Info: Automatically promoted node system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|sdram_0:the_sdram_0\|active_addr\[20\]~478 " "Info: Destination node system_0:u0\|sdram_0:the_sdram_0\|active_addr\[20\]~478" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 647 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|active_addr[20]~478 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|active_addr[20]~478 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|sdram_0:the_sdram_0\|active_cs_n~186 " "Info: Destination node system_0:u0\|sdram_0:the_sdram_0\|active_cs_n~186" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 207 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|active_cs_n~186 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|active_cs_n~186 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wren " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wren" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 5696 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wren } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wren } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wraddress\[0\]~946 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wraddress\[0\]~946" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 5693 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[0]~946 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[0]~946 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wraddress\[1\]~947 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wraddress\[1\]~947" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 5693 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[1]~947 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[1]~947 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wraddress\[2\]~948 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wraddress\[2\]~948" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 5693 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[2]~948 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[2]~948 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wraddress\[3\]~949 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wraddress\[3\]~949" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 5693 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[3]~949 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[3]~949 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wraddress\[4\]~950 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wraddress\[4\]~950" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 5693 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[4]~950 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[4]~950 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wraddress\[5\]~951 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wraddress\[5\]~951" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 5693 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[5]~951 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[5]~951 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wraddress\[6\]~952 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|ic_tag_wraddress\[6\]~952" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 5693 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[6]~952 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[6]~952 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" {  } {  } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 5522 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_out } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_out } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|CLR_SIGNAL  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|CLR_SIGNAL " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|ir\[1\]~717 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|ir\[1\]~717" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v" 225 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|ir[1]~717 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|ir[1]~717 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch~182 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch~182" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 747 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch~182 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch~182 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch~183 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch~183" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 747 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch~183 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch~183 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|CLR_SIGNAL" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~433 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~433" {  } { { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 1140 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~433 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~433 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5" {  } { { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 1140 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 1155 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|reset_n_sources~1  " "Info: Automatically promoted node system_0:u0\|reset_n_sources~1 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 5843 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|reset_n_sources~1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|reset_n_sources~1 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_IGNORED_FAST_REGISTER_IO_ASSIGNMENTS" "" "Info: Ignoring invalid fast I/O register assignments" {  } {  } 0 0 "Ignoring invalid fast I/O register assignments" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:03 " "Info: Finished register packing: elapsed time is 00:00:03" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "2 EC " "Extra Info: Packed 2 registers into blocks of type EC" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "117 I/O " "Extra Info: Packed 117 registers into blocks of type I/O" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "64 Embedded multiplier block " "Extra Info: Packed 64 registers into blocks of type Embedded multiplier block" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "73 " "Extra Info: Created 73 register duplicates" {  } {  } 1 0 "Created %1!d! register duplicates" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "4 unused 3.30 0 1 3 " "Info: Number of I/O pins in group: 4 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 3 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 40 1 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 40 total pin(s) used --  1 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.30V 36 1 " "Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 36 total pin(s) used --  1 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 28 15 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 28 total pin(s) used --  15 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 38 2 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 38 total pin(s) used --  2 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.30V 36 3 " "Info: I/O bank number 5 does not use VREF pins and has 3.30V VCCIO pins. 36 total pin(s) used --  3 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.30V 31 5 " "Info: I/O bank number 6 does not use VREF pins and has 3.30V VCCIO pins. 31 total pin(s) used --  5 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 3.30V 36 4 " "Info: I/O bank number 7 does not use VREF pins and has 3.30V VCCIO pins. 36 total pin(s) used --  4 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 3.30V 41 2 " "Info: I/O bank number 8 does not use VREF pins and has 3.30V VCCIO pins. 41 total pin(s) used --  2 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0}
{ "Warning" "WCUT_PLL_NON_ZDB_COMP_CLK_FEEDING_IO" "SDRAM_PLL:PLL1\|altpll:altpll_component\|pll compensate_clock 0 " "Warning: PLL \"SDRAM_PLL:PLL1\|altpll:altpll_component\|pll\" is in normal or source synchronous mode with output clock \"compensate_clock\" set to clk\[0\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" {  } { { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SDRAM_PLL.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SDRAM_PLL.v" 83 0 0 } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 224 0 0 } }  } 0 0 "PLL \"%1!s!\" is in normal or source synchronous mode with output clock \"%2!s!\" set to clk\[%3!d!\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:12 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:12" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:01:05 " "Info: Fitter placement operations ending: elapsed time is 00:01:05" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.258 ns register register " "Info: Estimated most critical path is register to register delay of 9.258 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns system_0:u0\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|rd_address 1 REG LAB_X7_Y6 42 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y6; Fanout = 42; REG Node = 'system_0:u0\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|rd_address'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(0.178 ns) 1.278 ns system_0:u0\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|rd_data\[36\]~438 2 COMB LAB_X10_Y6 2 " "Info: 2: + IC(1.100 ns) + CELL(0.178 ns) = 1.278 ns; Loc. = LAB_X10_Y6; Fanout = 2; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|rd_data\[36\]~438'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.278 ns" { system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_data[36]~438 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.178 ns) 2.188 ns system_0:u0\|sdram_0:the_sdram_0\|pending~273 3 COMB LAB_X9_Y6 1 " "Info: 3: + IC(0.732 ns) + CELL(0.178 ns) = 2.188 ns; Loc. = LAB_X9_Y6; Fanout = 1; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|pending~273'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.910 ns" { system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_data[36]~438 system_0:u0|sdram_0:the_sdram_0|pending~273 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 247 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.689 ns) + CELL(0.544 ns) 3.421 ns system_0:u0\|sdram_0:the_sdram_0\|pending~274 4 COMB LAB_X5_Y6 1 " "Info: 4: + IC(0.689 ns) + CELL(0.544 ns) = 3.421 ns; Loc. = LAB_X5_Y6; Fanout = 1; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|pending~274'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.233 ns" { system_0:u0|sdram_0:the_sdram_0|pending~273 system_0:u0|sdram_0:the_sdram_0|pending~274 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 247 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.178 ns) 4.097 ns system_0:u0\|sdram_0:the_sdram_0\|pending~275 5 COMB LAB_X5_Y6 12 " "Info: 5: + IC(0.498 ns) + CELL(0.178 ns) = 4.097 ns; Loc. = LAB_X5_Y6; Fanout = 12; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|pending~275'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { system_0:u0|sdram_0:the_sdram_0|pending~274 system_0:u0|sdram_0:the_sdram_0|pending~275 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 247 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.178 ns) 4.773 ns system_0:u0\|sdram_0:the_sdram_0\|pending 6 COMB LAB_X5_Y6 5 " "Info: 6: + IC(0.498 ns) + CELL(0.178 ns) = 4.773 ns; Loc. = LAB_X5_Y6; Fanout = 5; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|pending'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { system_0:u0|sdram_0:the_sdram_0|pending~275 system_0:u0|sdram_0:the_sdram_0|pending } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 247 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.178 ns) 5.449 ns system_0:u0\|sdram_0:the_sdram_0\|m_addr\[0\]~122 7 COMB LAB_X5_Y6 11 " "Info: 7: + IC(0.498 ns) + CELL(0.178 ns) = 5.449 ns; Loc. = LAB_X5_Y6; Fanout = 11; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|m_addr\[0\]~122'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { system_0:u0|sdram_0:the_sdram_0|pending system_0:u0|sdram_0:the_sdram_0|m_addr[0]~122 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 647 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.542 ns) 6.713 ns system_0:u0\|sdram_0:the_sdram_0\|Selector88~16 8 COMB LAB_X4_Y3 1 " "Info: 8: + IC(0.722 ns) + CELL(0.542 ns) = 6.713 ns; Loc. = LAB_X4_Y3; Fanout = 1; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|Selector88~16'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { system_0:u0|sdram_0:the_sdram_0|m_addr[0]~122 system_0:u0|sdram_0:the_sdram_0|Selector88~16 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 439 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.319 ns) 7.386 ns system_0:u0\|sdram_0:the_sdram_0\|Selector88~17 9 COMB LAB_X4_Y3 1 " "Info: 9: + IC(0.354 ns) + CELL(0.319 ns) = 7.386 ns; Loc. = LAB_X4_Y3; Fanout = 1; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|Selector88~17'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.673 ns" { system_0:u0|sdram_0:the_sdram_0|Selector88~16 system_0:u0|sdram_0:the_sdram_0|Selector88~17 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 439 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.560 ns) + CELL(0.312 ns) 9.258 ns system_0:u0\|sdram_0:the_sdram_0\|m_addr\[6\] 10 REG IOC_X0_Y9_N3 1 " "Info: 10: + IC(1.560 ns) + CELL(0.312 ns) = 9.258 ns; Loc. = IOC_X0_Y9_N3; Fanout = 1; REG Node = 'system_0:u0\|sdram_0:the_sdram_0\|m_addr\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.872 ns" { system_0:u0|sdram_0:the_sdram_0|Selector88~17 system_0:u0|sdram_0:the_sdram_0|m_addr[6] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v" 647 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.607 ns ( 28.16 % ) " "Info: Total cell delay = 2.607 ns ( 28.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.651 ns ( 71.84 % ) " "Info: Total interconnect delay = 6.651 ns ( 71.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.258 ns" { system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_data[36]~438 system_0:u0|sdram_0:the_sdram_0|pending~273 system_0:u0|sdram_0:the_sdram_0|pending~274 system_0:u0|sdram_0:the_sdram_0|pending~275 system_0:u0|sdram_0:the_sdram_0|pending system_0:u0|sdram_0:the_sdram_0|m_addr[0]~122 system_0:u0|sdram_0:the_sdram_0|Selector88~16 system_0:u0|sdram_0:the_sdram_0|Selector88~17 system_0:u0|sdram_0:the_sdram_0|m_addr[6] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "9 32 " "Info: Average interconnect usage is 9% of the available device resources. Peak interconnect usage is 32%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X12_Y0 X24_Y13 " "Info: The peak interconnect region extends from location X12_Y0 to location X24_Y13" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:17 " "Info: Fitter routing operations ending: elapsed time is 00:00:17" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." {  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "256 " "Warning: Found 256 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[0\] 0 " "Info: Pin \"HEX0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[1\] 0 " "Info: Pin \"HEX0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[2\] 0 " "Info: Pin \"HEX0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[3\] 0 " "Info: Pin \"HEX0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[4\] 0 " "Info: Pin \"HEX0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[5\] 0 " "Info: Pin \"HEX0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[6\] 0 " "Info: Pin \"HEX0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[0\] 0 " "Info: Pin \"HEX1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[1\] 0 " "Info: Pin \"HEX1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[2\] 0 " "Info: Pin \"HEX1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[3\] 0 " "Info: Pin \"HEX1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[4\] 0 " "Info: Pin \"HEX1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[5\] 0 " "Info: Pin \"HEX1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[6\] 0 " "Info: Pin \"HEX1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[0\] 0 " "Info: Pin \"HEX2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[1\] 0 " "Info: Pin \"HEX2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[2\] 0 " "Info: Pin \"HEX2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[3\] 0 " "Info: Pin \"HEX2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[4\] 0 " "Info: Pin \"HEX2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[5\] 0 " "Info: Pin \"HEX2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[6\] 0 " "Info: Pin \"HEX2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[0\] 0 " "Info: Pin \"HEX3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[1\] 0 " "Info: Pin \"HEX3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[2\] 0 " "Info: Pin \"HEX3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[3\] 0 " "Info: Pin \"HEX3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[4\] 0 " "Info: Pin \"HEX3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[5\] 0 " "Info: Pin \"HEX3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[6\] 0 " "Info: Pin \"HEX3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[0\] 0 " "Info: Pin \"LEDG\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[1\] 0 " "Info: Pin \"LEDG\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[2\] 0 " "Info: Pin \"LEDG\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[3\] 0 " "Info: Pin \"LEDG\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[4\] 0 " "Info: Pin \"LEDG\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[5\] 0 " "Info: Pin \"LEDG\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[6\] 0 " "Info: Pin \"LEDG\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[7\] 0 " "Info: Pin \"LEDG\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[0\] 0 " "Info: Pin \"LEDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[1\] 0 " "Info: Pin \"LEDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[2\] 0 " "Info: Pin \"LEDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[3\] 0 " "Info: Pin \"LEDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[4\] 0 " "Info: Pin \"LEDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[5\] 0 " "Info: Pin \"LEDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[6\] 0 " "Info: Pin \"LEDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[7\] 0 " "Info: Pin \"LEDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[8\] 0 " "Info: Pin \"LEDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[9\] 0 " "Info: Pin \"LEDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "UART_TXD 0 " "Info: Pin \"UART_TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[0\] 0 " "Info: Pin \"DRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[1\] 0 " "Info: Pin \"DRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[2\] 0 " "Info: Pin \"DRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[3\] 0 " "Info: Pin \"DRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[4\] 0 " "Info: Pin \"DRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[5\] 0 " "Info: Pin \"DRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[6\] 0 " "Info: Pin \"DRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[7\] 0 " "Info: Pin \"DRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[8\] 0 " "Info: Pin \"DRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[9\] 0 " "Info: Pin \"DRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[10\] 0 " "Info: Pin \"DRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[11\] 0 " "Info: Pin \"DRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_LDQM 0 " "Info: Pin \"DRAM_LDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_UDQM 0 " "Info: Pin \"DRAM_UDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_WE_N 0 " "Info: Pin \"DRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CAS_N 0 " "Info: Pin \"DRAM_CAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_RAS_N 0 " "Info: Pin \"DRAM_RAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CS_N 0 " "Info: Pin \"DRAM_CS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_0 0 " "Info: Pin \"DRAM_BA_0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_1 0 " "Info: Pin \"DRAM_BA_1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CLK 0 " "Info: Pin \"DRAM_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CKE 0 " "Info: Pin \"DRAM_CKE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[0\] 0 " "Info: Pin \"FL_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[1\] 0 " "Info: Pin \"FL_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[2\] 0 " "Info: Pin \"FL_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[3\] 0 " "Info: Pin \"FL_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[4\] 0 " "Info: Pin \"FL_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[5\] 0 " "Info: Pin \"FL_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[6\] 0 " "Info: Pin \"FL_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[7\] 0 " "Info: Pin \"FL_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[8\] 0 " "Info: Pin \"FL_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[9\] 0 " "Info: Pin \"FL_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[10\] 0 " "Info: Pin \"FL_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[11\] 0 " "Info: Pin \"FL_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[12\] 0 " "Info: Pin \"FL_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[13\] 0 " "Info: Pin \"FL_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[14\] 0 " "Info: Pin \"FL_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[15\] 0 " "Info: Pin \"FL_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[16\] 0 " "Info: Pin \"FL_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[17\] 0 " "Info: Pin \"FL_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[18\] 0 " "Info: Pin \"FL_ADDR\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[19\] 0 " "Info: Pin \"FL_ADDR\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[20\] 0 " "Info: Pin \"FL_ADDR\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[21\] 0 " "Info: Pin \"FL_ADDR\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_WE_N 0 " "Info: Pin \"FL_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_RST_N 0 " "Info: Pin \"FL_RST_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_OE_N 0 " "Info: Pin \"FL_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_CE_N 0 " "Info: Pin \"FL_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[0\] 0 " "Info: Pin \"SRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[1\] 0 " "Info: Pin \"SRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[2\] 0 " "Info: Pin \"SRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[3\] 0 " "Info: Pin \"SRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[4\] 0 " "Info: Pin \"SRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[5\] 0 " "Info: Pin \"SRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[6\] 0 " "Info: Pin \"SRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[7\] 0 " "Info: Pin \"SRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[8\] 0 " "Info: Pin \"SRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[9\] 0 " "Info: Pin \"SRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[10\] 0 " "Info: Pin \"SRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[11\] 0 " "Info: Pin \"SRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[12\] 0 " "Info: Pin \"SRAM_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[13\] 0 " "Info: Pin \"SRAM_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[14\] 0 " "Info: Pin \"SRAM_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[15\] 0 " "Info: Pin \"SRAM_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[16\] 0 " "Info: Pin \"SRAM_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[17\] 0 " "Info: Pin \"SRAM_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_UB_N 0 " "Info: Pin \"SRAM_UB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_LB_N 0 " "Info: Pin \"SRAM_LB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_WE_N 0 " "Info: Pin \"SRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_CE_N 0 " "Info: Pin \"SRAM_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_OE_N 0 " "Info: Pin \"SRAM_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CLK 0 " "Info: Pin \"SD_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TDO 0 " "Info: Pin \"TDO\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SCLK 0 " "Info: Pin \"I2C_SCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_HS 0 " "Info: Pin \"VGA_HS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_VS 0 " "Info: Pin \"VGA_VS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[0\] 0 " "Info: Pin \"VGA_R\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[1\] 0 " "Info: Pin \"VGA_R\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[2\] 0 " "Info: Pin \"VGA_R\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[3\] 0 " "Info: Pin \"VGA_R\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[0\] 0 " "Info: Pin \"VGA_G\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[1\] 0 " "Info: Pin \"VGA_G\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[2\] 0 " "Info: Pin \"VGA_G\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[3\] 0 " "Info: Pin \"VGA_G\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[0\] 0 " "Info: Pin \"VGA_B\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[1\] 0 " "Info: Pin \"VGA_B\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[2\] 0 " "Info: Pin \"VGA_B\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[3\] 0 " "Info: Pin \"VGA_B\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACDAT 0 " "Info: Pin \"AUD_DACDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_XCK 0 " "Info: Pin \"AUD_XCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT3 0 " "Info: Pin \"SD_DAT3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CMD 0 " "Info: Pin \"SD_CMD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[0\] 0 " "Info: Pin \"DRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[1\] 0 " "Info: Pin \"DRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[2\] 0 " "Info: Pin \"DRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[3\] 0 " "Info: Pin \"DRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[4\] 0 " "Info: Pin \"DRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[5\] 0 " "Info: Pin \"DRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[6\] 0 " "Info: Pin \"DRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[7\] 0 " "Info: Pin \"DRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[8\] 0 " "Info: Pin \"DRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[9\] 0 " "Info: Pin \"DRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[10\] 0 " "Info: Pin \"DRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[11\] 0 " "Info: Pin \"DRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[12\] 0 " "Info: Pin \"DRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[13\] 0 " "Info: Pin \"DRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[14\] 0 " "Info: Pin \"DRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[15\] 0 " "Info: Pin \"DRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[0\] 0 " "Info: Pin \"FL_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[1\] 0 " "Info: Pin \"FL_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[2\] 0 " "Info: Pin \"FL_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[3\] 0 " "Info: Pin \"FL_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[4\] 0 " "Info: Pin \"FL_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[5\] 0 " "Info: Pin \"FL_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[6\] 0 " "Info: Pin \"FL_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[7\] 0 " "Info: Pin \"FL_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[0\] 0 " "Info: Pin \"SRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[1\] 0 " "Info: Pin \"SRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[2\] 0 " "Info: Pin \"SRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[3\] 0 " "Info: Pin \"SRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[4\] 0 " "Info: Pin \"SRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[5\] 0 " "Info: Pin \"SRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[6\] 0 " "Info: Pin \"SRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[7\] 0 " "Info: Pin \"SRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[8\] 0 " "Info: Pin \"SRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[9\] 0 " "Info: Pin \"SRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[10\] 0 " "Info: Pin \"SRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[11\] 0 " "Info: Pin \"SRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[12\] 0 " "Info: Pin \"SRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[13\] 0 " "Info: Pin \"SRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[14\] 0 " "Info: Pin \"SRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[15\] 0 " "Info: Pin \"SRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT 0 " "Info: Pin \"SD_DAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SDAT 0 " "Info: Pin \"I2C_SDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_ADCLRCK 0 " "Info: Pin \"AUD_ADCLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACLRCK 0 " "Info: Pin \"AUD_DACLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_BCLK 0 " "Info: Pin \"AUD_BCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[0\] 0 " "Info: Pin \"GPIO_0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[1\] 0 " "Info: Pin \"GPIO_0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[2\] 0 " "Info: Pin \"GPIO_0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[3\] 0 " "Info: Pin \"GPIO_0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[4\] 0 " "Info: Pin \"GPIO_0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[5\] 0 " "Info: Pin \"GPIO_0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[6\] 0 " "Info: Pin \"GPIO_0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[7\] 0 " "Info: Pin \"GPIO_0\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[8\] 0 " "Info: Pin \"GPIO_0\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[9\] 0 " "Info: Pin \"GPIO_0\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[10\] 0 " "Info: Pin \"GPIO_0\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[11\] 0 " "Info: Pin \"GPIO_0\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[12\] 0 " "Info: Pin \"GPIO_0\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[13\] 0 " "Info: Pin \"GPIO_0\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[14\] 0 " "Info: Pin \"GPIO_0\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[15\] 0 " "Info: Pin \"GPIO_0\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[16\] 0 " "Info: Pin \"GPIO_0\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[17\] 0 " "Info: Pin \"GPIO_0\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[18\] 0 " "Info: Pin \"GPIO_0\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[19\] 0 " "Info: Pin \"GPIO_0\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[20\] 0 " "Info: Pin \"GPIO_0\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[21\] 0 " "Info: Pin \"GPIO_0\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[22\] 0 " "Info: Pin \"GPIO_0\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[23\] 0 " "Info: Pin \"GPIO_0\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[24\] 0 " "Info: Pin \"GPIO_0\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[25\] 0 " "Info: Pin \"GPIO_0\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[26\] 0 " "Info: Pin \"GPIO_0\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[27\] 0 " "Info: Pin \"GPIO_0\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[28\] 0 " "Info: Pin \"GPIO_0\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[29\] 0 " "Info: Pin \"GPIO_0\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[30\] 0 " "Info: Pin \"GPIO_0\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[31\] 0 " "Info: Pin \"GPIO_0\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[32\] 0 " "Info: Pin \"GPIO_0\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[33\] 0 " "Info: Pin \"GPIO_0\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[34\] 0 " "Info: Pin \"GPIO_0\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[35\] 0 " "Info: Pin \"GPIO_0\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[0\] 0 " "Info: Pin \"GPIO_1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[1\] 0 " "Info: Pin \"GPIO_1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[2\] 0 " "Info: Pin \"GPIO_1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[3\] 0 " "Info: Pin \"GPIO_1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[4\] 0 " "Info: Pin \"GPIO_1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[5\] 0 " "Info: Pin \"GPIO_1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[6\] 0 " "Info: Pin \"GPIO_1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[7\] 0 " "Info: Pin \"GPIO_1\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[8\] 0 " "Info: Pin \"GPIO_1\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[9\] 0 " "Info: Pin \"GPIO_1\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[10\] 0 " "Info: Pin \"GPIO_1\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[11\] 0 " "Info: Pin \"GPIO_1\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[12\] 0 " "Info: Pin \"GPIO_1\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[13\] 0 " "Info: Pin \"GPIO_1\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[14\] 0 " "Info: Pin \"GPIO_1\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[15\] 0 " "Info: Pin \"GPIO_1\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[16\] 0 " "Info: Pin \"GPIO_1\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[17\] 0 " "Info: Pin \"GPIO_1\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[18\] 0 " "Info: Pin \"GPIO_1\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[19\] 0 " "Info: Pin \"GPIO_1\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[20\] 0 " "Info: Pin \"GPIO_1\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[21\] 0 " "Info: Pin \"GPIO_1\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[22\] 0 " "Info: Pin \"GPIO_1\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[23\] 0 " "Info: Pin \"GPIO_1\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[24\] 0 " "Info: Pin \"GPIO_1\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[25\] 0 " "Info: Pin \"GPIO_1\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[26\] 0 " "Info: Pin \"GPIO_1\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[27\] 0 " "Info: Pin \"GPIO_1\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[28\] 0 " "Info: Pin \"GPIO_1\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[29\] 0 " "Info: Pin \"GPIO_1\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[30\] 0 " "Info: Pin \"GPIO_1\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[31\] 0 " "Info: Pin \"GPIO_1\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[32\] 0 " "Info: Pin \"GPIO_1\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[33\] 0 " "Info: Pin \"GPIO_1\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[34\] 0 " "Info: Pin \"GPIO_1\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[35\] 0 " "Info: Pin \"GPIO_1\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out~clkctrl " "Info: Node system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out~clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|cpu_0:the_cpu_0\|ic_fill_valid_bits\[5\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|cpu_0:the_cpu_0\|ic_fill_valid_bits\[5\] -- routed using non-global resources" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[5] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 6907 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[5] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|cpu_0:the_cpu_0\|ic_fill_valid_bits\[4\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|cpu_0:the_cpu_0\|ic_fill_valid_bits\[4\] -- routed using non-global resources" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[4] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 6907 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[4] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|cpu_0:the_cpu_0\|ic_fill_valid_bits\[1\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|cpu_0:the_cpu_0\|ic_fill_valid_bits\[1\] -- routed using non-global resources" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[1] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 6907 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|cpu_0:the_cpu_0\|ic_fill_valid_bits\[0\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|cpu_0:the_cpu_0\|ic_fill_valid_bits\[0\] -- routed using non-global resources" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[0] } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 6907 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|ic_fill_valid_bits[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_out~clkctrl } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v" 5522 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_out~clkctrl } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|CLR_SIGNAL~clkctrl " "Info: Node sld_hub:sld_hub_inst\|CLR_SIGNAL~clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|write_valid " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|write_valid -- routed using non-global resources" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_valid } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 238 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_valid } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[0\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[0\] -- routed using non-global resources" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[0] } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 407 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|write_stalled " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|write_stalled -- routed using non-global resources" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_stalled } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 223 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_stalled } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[3\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[3\] -- routed using non-global resources" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[3] } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 407 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[3] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[1\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[1\] -- routed using non-global resources" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[1] } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 407 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write -- routed using non-global resources" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 227 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[7\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[7\] -- routed using non-global resources" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[7] } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 407 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[7] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem\|MonRd1 " "Info: Port clear -- assigned as a global for destination node system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem\|MonRd1 -- routed using non-global resources" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonRd1 } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 965 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonRd1 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem\|MonRd " "Info: Port clear -- assigned as a global for destination node system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem\|MonRd -- routed using non-global resources" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonRd } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 964 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonRd } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetrequest " "Info: Port clear -- assigned as a global for destination node system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetrequest -- routed using non-global resources" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetrequest } "NODE_NAME" } } { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v" 748 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetrequest } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~clkctrl } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~clkctrl } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "79 " "Warning: Following 79 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SD_DAT3 a permanently disabled " "Info: Pin SD_DAT3 has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 177 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SD_CMD a permanently disabled " "Info: Pin SD_CMD has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 178 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SD_DAT a permanently disabled " "Info: Pin SD_DAT has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 176 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "I2C_SDAT a permanently disabled " "Info: Pin I2C_SDAT has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 181 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_ADCLRCK a permanently disabled " "Info: Pin AUD_ADCLRCK has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 198 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_DACLRCK a permanently disabled " "Info: Pin AUD_DACLRCK has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 200 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_BCLK a permanently disabled " "Info: Pin AUD_BCLK has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 202 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[0\] a permanently disabled " "Info: Pin GPIO_0\[0\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[1\] a permanently disabled " "Info: Pin GPIO_0\[1\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[2\] a permanently disabled " "Info: Pin GPIO_0\[2\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[3\] a permanently disabled " "Info: Pin GPIO_0\[3\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[4\] a permanently disabled " "Info: Pin GPIO_0\[4\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[5\] a permanently disabled " "Info: Pin GPIO_0\[5\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[6\] a permanently disabled " "Info: Pin GPIO_0\[6\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[7\] a permanently disabled " "Info: Pin GPIO_0\[7\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[8\] a permanently disabled " "Info: Pin GPIO_0\[8\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[9\] a permanently disabled " "Info: Pin GPIO_0\[9\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[10\] a permanently disabled " "Info: Pin GPIO_0\[10\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[11\] a permanently disabled " "Info: Pin GPIO_0\[11\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[12\] a permanently disabled " "Info: Pin GPIO_0\[12\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[13\] a permanently disabled " "Info: Pin GPIO_0\[13\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[14\] a permanently disabled " "Info: Pin GPIO_0\[14\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[15\] a permanently disabled " "Info: Pin GPIO_0\[15\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[16\] a permanently disabled " "Info: Pin GPIO_0\[16\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[17\] a permanently disabled " "Info: Pin GPIO_0\[17\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[18\] a permanently disabled " "Info: Pin GPIO_0\[18\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[19\] a permanently disabled " "Info: Pin GPIO_0\[19\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[20\] a permanently disabled " "Info: Pin GPIO_0\[20\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[21\] a permanently disabled " "Info: Pin GPIO_0\[21\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[22\] a permanently disabled " "Info: Pin GPIO_0\[22\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[23\] a permanently disabled " "Info: Pin GPIO_0\[23\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[24\] a permanently disabled " "Info: Pin GPIO_0\[24\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[25\] a permanently disabled " "Info: Pin GPIO_0\[25\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[26\] a permanently disabled " "Info: Pin GPIO_0\[26\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[27\] a permanently disabled " "Info: Pin GPIO_0\[27\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[28\] a permanently disabled " "Info: Pin GPIO_0\[28\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[29\] a permanently disabled " "Info: Pin GPIO_0\[29\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[30\] a permanently disabled " "Info: Pin GPIO_0\[30\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[31\] a permanently disabled " "Info: Pin GPIO_0\[31\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[32\] a permanently disabled " "Info: Pin GPIO_0\[32\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[33\] a permanently disabled " "Info: Pin GPIO_0\[33\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[34\] a permanently disabled " "Info: Pin GPIO_0\[34\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[35\] a permanently disabled " "Info: Pin GPIO_0\[35\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Info: Pin GPIO_1\[0\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Info: Pin GPIO_1\[1\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Info: Pin GPIO_1\[2\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Info: Pin GPIO_1\[3\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Info: Pin GPIO_1\[4\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Info: Pin GPIO_1\[5\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Info: Pin GPIO_1\[6\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Info: Pin GPIO_1\[7\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Info: Pin GPIO_1\[8\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Info: Pin GPIO_1\[9\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Info: Pin GPIO_1\[10\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Info: Pin GPIO_1\[11\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Info: Pin GPIO_1\[12\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Info: Pin GPIO_1\[13\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Info: Pin GPIO_1\[14\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Info: Pin GPIO_1\[15\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Info: Pin GPIO_1\[16\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Info: Pin GPIO_1\[17\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Info: Pin GPIO_1\[18\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Info: Pin GPIO_1\[19\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Info: Pin GPIO_1\[20\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Info: Pin GPIO_1\[21\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Info: Pin GPIO_1\[22\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Info: Pin GPIO_1\[23\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Info: Pin GPIO_1\[24\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Info: Pin GPIO_1\[25\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Info: Pin GPIO_1\[26\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Info: Pin GPIO_1\[27\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Info: Pin GPIO_1\[28\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Info: Pin GPIO_1\[29\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Info: Pin GPIO_1\[30\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Info: Pin GPIO_1\[31\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Info: Pin GPIO_1\[32\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently disabled " "Info: Pin GPIO_1\[33\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[34\] a permanently disabled " "Info: Pin GPIO_1\[34\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[35\] a permanently disabled " "Info: Pin GPIO_1\[35\] has a permanently disabled output enable" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "100 " "Warning: Following 100 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CKE VCC " "Info: Pin DRAM_CKE has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 159 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CKE } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CKE } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_RST_N VCC " "Info: Pin FL_RST_N has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 164 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_RST_N } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_RST_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_CLK GND " "Info: Pin SD_CLK has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 179 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TDO GND " "Info: Pin TDO has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 190 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "TDO" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { TDO } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { TDO } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "I2C_SCLK GND " "Info: Pin I2C_SCLK has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 182 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_HS GND " "Info: Pin VGA_HS has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 192 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_HS } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_HS } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_VS GND " "Info: Pin VGA_VS has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 193 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_VS } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_VS } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[0\] GND " "Info: Pin VGA_R\[0\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 194 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[1\] GND " "Info: Pin VGA_R\[1\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 194 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[2\] GND " "Info: Pin VGA_R\[2\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 194 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[3\] GND " "Info: Pin VGA_R\[3\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 194 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[0\] GND " "Info: Pin VGA_G\[0\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 195 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[1\] GND " "Info: Pin VGA_G\[1\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 195 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[2\] GND " "Info: Pin VGA_G\[2\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 195 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[3\] GND " "Info: Pin VGA_G\[3\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 195 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[0\] GND " "Info: Pin VGA_B\[0\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 196 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[1\] GND " "Info: Pin VGA_B\[1\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 196 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[2\] GND " "Info: Pin VGA_B\[2\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 196 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[3\] GND " "Info: Pin VGA_B\[3\] has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 196 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_DACDAT GND " "Info: Pin AUD_DACDAT has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 201 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACDAT } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACDAT } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_XCK GND " "Info: Pin AUD_XCK has GND driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 203 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_XCK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_XCK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_DAT3 VCC " "Info: Pin SD_DAT3 has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 177 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_CMD VCC " "Info: Pin SD_CMD has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 178 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_DAT VCC " "Info: Pin SD_DAT has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 176 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "I2C_SDAT VCC " "Info: Pin I2C_SDAT has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 181 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_ADCLRCK VCC " "Info: Pin AUD_ADCLRCK has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 198 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_DACLRCK VCC " "Info: Pin AUD_DACLRCK has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 200 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_BCLK VCC " "Info: Pin AUD_BCLK has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 202 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[0\] VCC " "Info: Pin GPIO_0\[0\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[1\] VCC " "Info: Pin GPIO_0\[1\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[2\] VCC " "Info: Pin GPIO_0\[2\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[3\] VCC " "Info: Pin GPIO_0\[3\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[4\] VCC " "Info: Pin GPIO_0\[4\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[5\] VCC " "Info: Pin GPIO_0\[5\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[6\] VCC " "Info: Pin GPIO_0\[6\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[7\] VCC " "Info: Pin GPIO_0\[7\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[8\] VCC " "Info: Pin GPIO_0\[8\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[9\] VCC " "Info: Pin GPIO_0\[9\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[10\] VCC " "Info: Pin GPIO_0\[10\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[11\] VCC " "Info: Pin GPIO_0\[11\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[12\] VCC " "Info: Pin GPIO_0\[12\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[13\] VCC " "Info: Pin GPIO_0\[13\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[14\] VCC " "Info: Pin GPIO_0\[14\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[15\] VCC " "Info: Pin GPIO_0\[15\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[16\] VCC " "Info: Pin GPIO_0\[16\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[17\] VCC " "Info: Pin GPIO_0\[17\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[18\] VCC " "Info: Pin GPIO_0\[18\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[19\] VCC " "Info: Pin GPIO_0\[19\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[20\] VCC " "Info: Pin GPIO_0\[20\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[21\] VCC " "Info: Pin GPIO_0\[21\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[22\] VCC " "Info: Pin GPIO_0\[22\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[23\] VCC " "Info: Pin GPIO_0\[23\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[24\] VCC " "Info: Pin GPIO_0\[24\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[25\] VCC " "Info: Pin GPIO_0\[25\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[26\] VCC " "Info: Pin GPIO_0\[26\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[27\] VCC " "Info: Pin GPIO_0\[27\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[28\] VCC " "Info: Pin GPIO_0\[28\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[29\] VCC " "Info: Pin GPIO_0\[29\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[30\] VCC " "Info: Pin GPIO_0\[30\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[31\] VCC " "Info: Pin GPIO_0\[31\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[32\] VCC " "Info: Pin GPIO_0\[32\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[33\] VCC " "Info: Pin GPIO_0\[33\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[34\] VCC " "Info: Pin GPIO_0\[34\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[35\] VCC " "Info: Pin GPIO_0\[35\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 205 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[0\] VCC " "Info: Pin GPIO_1\[0\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[1\] VCC " "Info: Pin GPIO_1\[1\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[2\] VCC " "Info: Pin GPIO_1\[2\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[3\] VCC " "Info: Pin GPIO_1\[3\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[4\] VCC " "Info: Pin GPIO_1\[4\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[5\] VCC " "Info: Pin GPIO_1\[5\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[6\] VCC " "Info: Pin GPIO_1\[6\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[7\] VCC " "Info: Pin GPIO_1\[7\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[8\] VCC " "Info: Pin GPIO_1\[8\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[9\] VCC " "Info: Pin GPIO_1\[9\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[10\] VCC " "Info: Pin GPIO_1\[10\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[11\] VCC " "Info: Pin GPIO_1\[11\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[12\] VCC " "Info: Pin GPIO_1\[12\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[13\] VCC " "Info: Pin GPIO_1\[13\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[14\] VCC " "Info: Pin GPIO_1\[14\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[15\] VCC " "Info: Pin GPIO_1\[15\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[16\] VCC " "Info: Pin GPIO_1\[16\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[17\] VCC " "Info: Pin GPIO_1\[17\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[18\] VCC " "Info: Pin GPIO_1\[18\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[19\] VCC " "Info: Pin GPIO_1\[19\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[20\] VCC " "Info: Pin GPIO_1\[20\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[21\] VCC " "Info: Pin GPIO_1\[21\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[22\] VCC " "Info: Pin GPIO_1\[22\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[23\] VCC " "Info: Pin GPIO_1\[23\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[24\] VCC " "Info: Pin GPIO_1\[24\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[25\] VCC " "Info: Pin GPIO_1\[25\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[26\] VCC " "Info: Pin GPIO_1\[26\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[27\] VCC " "Info: Pin GPIO_1\[27\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[28\] VCC " "Info: Pin GPIO_1\[28\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[29\] VCC " "Info: Pin GPIO_1\[29\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[30\] VCC " "Info: Pin GPIO_1\[30\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[31\] VCC " "Info: Pin GPIO_1\[31\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[32\] VCC " "Info: Pin GPIO_1\[32\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[33\] VCC " "Info: Pin GPIO_1\[33\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[34\] VCC " "Info: Pin GPIO_1\[34\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[35\] VCC " "Info: Pin GPIO_1\[35\] has VCC driving its datain port" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 206 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "system_0:u0\|sdram_0:the_sdram_0\|always5~0 " "Info: Following pins have the same output enable: system_0:u0\|sdram_0:the_sdram_0\|always5~0" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[9\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[9\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[0\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[0\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[7\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[7\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[15\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[15\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[6\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[6\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[14\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[14\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[5\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[5\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[13\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[13\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[4\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[4\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[12\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[12\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[3\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[3\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[11\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[11\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[2\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[2\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[10\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[10\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[1\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[1\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[8\] 3.3-V LVTTL " "Info: Type bidirectional pin DRAM_DQ\[8\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 148 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "system_0:u0\|sram_0_avalonS_arbitrator:the_sram_0_avalonS\|sram_0_avalonS_write_n~29 " "Info: Following pins have the same output enable: system_0:u0\|sram_0_avalonS_arbitrator:the_sram_0_avalonS\|sram_0_avalonS_write_n~29" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[1\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[1\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[8\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[8\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[8] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[7\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[7\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[15\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[15\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[15] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[6\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[6\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[14\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[14\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[5\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[5\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[13\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[13\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[13] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[13] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[4\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[4\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[12\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[12\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[12] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[12] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[3\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[3\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[11\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[11\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[11] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[11] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[2\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[2\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[10\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[10\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[10] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[9\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[9\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[9] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[0\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_DQ\[0\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 168 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|in_a_write_cycle " "Info: Following pins have the same output enable: system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|in_a_write_cycle" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[0\] 3.3-V LVTTL " "Info: Type bidirectional pin FL_DQ\[0\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[7\] 3.3-V LVTTL " "Info: Type bidirectional pin FL_DQ\[7\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[6\] 3.3-V LVTTL " "Info: Type bidirectional pin FL_DQ\[6\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[5\] 3.3-V LVTTL " "Info: Type bidirectional pin FL_DQ\[5\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[4\] 3.3-V LVTTL " "Info: Type bidirectional pin FL_DQ\[4\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[3\] 3.3-V LVTTL " "Info: Type bidirectional pin FL_DQ\[3\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[2\] 3.3-V LVTTL " "Info: Type bidirectional pin FL_DQ\[2\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[1\] 3.3-V LVTTL " "Info: Type bidirectional pin FL_DQ\[1\] uses the 3.3-V LVTTL I/O standard" {  } { { "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" "" { Text "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v" 161 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "//file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.fit.smsg " "Info: Generated suppressed messages file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "240 " "Info: Allocated 240 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 30 15:48:37 2007 " "Info: Processing ended: Thu Aug 30 15:48:37 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:02:15 " "Info: Elapsed time: 00:02:15" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}