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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 11.184 ns
From           : SRAM_DQ[14]
To             : system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[30]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.580 ns
From           : system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1]
To             : SRAM_ADDR[11]
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.810 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.311 ns
From           : altera_internal_jtag
To             : sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'SDRAM_PLL:PLL1|altpll:altpll_component|_clk1'
Slack          : 0.516 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 105.44 MHz ( period = 9.484 ns )
From           : system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[9]
To             : system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[11]
From Clock     : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
To Clock       : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK_50'
Slack          : 15.086 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 203.50 MHz ( period = 4.914 ns )
From           : Reset_Delay:delay1|Cont[15]
To             : Reset_Delay:delay1|Cont[12]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 102.24 MHz ( period = 9.781 ns )
From           : sld_hub:sld_hub_inst|jtag_debug_mode_usr1
To             : system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[9]
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'SDRAM_PLL:PLL1|altpll:altpll_component|_clk1'
Slack          : 0.445 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : system_0:u0|sdram_0:the_sdram_0|i_cmd[3]
To             : system_0:u0|sdram_0:the_sdram_0|i_cmd[3]
From Clock     : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
To Clock       : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Hold: 'CLOCK_50'
Slack          : 0.445 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : Reset_Delay:delay1|Cont[0]
To             : Reset_Delay:delay1|Cont[0]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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