Analysis & Synthesis report for DE1_NIOS Thu Aug 30 15:46:17 2007 Quartus II Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Analysis & Synthesis Source Files Read 5. Analysis & Synthesis Resource Usage Summary 6. Analysis & Synthesis Resource Utilization by Entity 7. Analysis & Synthesis RAM Summary 8. Analysis & Synthesis DSP Block Usage Summary 9. State Machine - |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_next 10. State Machine - |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_state 11. State Machine - |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_next 12. State Machine - |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_state 13. State Machine - |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize 14. Registers Protected by Synthesis 15. Logic Cells Representing Combinational Loops 16. Registers Removed During Synthesis 17. Removed Registers Triggering Further Register Optimizations 18. General Register Statistics 19. Inverted Register Statistics 20. Multiplexer Restructuring Statistics (Restructuring Performed) 21. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated 22. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1 23. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_73e1:auto_generated 24. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_4nd1:auto_generated 25. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_4nd1:auto_generated|altsyncram_3um1:altsyncram1 26. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_epd1:auto_generated 27. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_fpd1:auto_generated 28. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_9u12:auto_generated 29. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated 30. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result 31. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result 32. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated 33. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated 34. Source assignments for system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_lo31:auto_generated 35. Source assignments for system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 36. Source assignments for system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 37. Source assignments for system_0:u0|sdram_0:the_sdram_0 38. Source assignments for system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave 39. Source assignments for system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch 40. Source assignments for sld_hub:sld_hub_inst 41. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG 42. Parameter Settings for User Entity Instance: SDRAM_PLL:PLL1|altpll:altpll_component 43. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data 44. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram 45. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1 46. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag 47. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram 48. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht 49. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram 50. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_4nd1:auto_generated|altsyncram_3um1:altsyncram1 51. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a 52. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram 53. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b 54. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram 55. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag 56. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram 57. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data 58. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram 59. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1 60. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1 61. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2 62. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1 63. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component 64. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram 65. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component 66. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram 67. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1 68. Parameter Settings for User Entity Instance: system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom 69. Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo 70. Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 71. Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo 72. Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 73. Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic 74. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst 75. altmult_add Parameter Settings by Entity Instance 76. scfifo Parameter Settings by Entity Instance 77. Analysis & Synthesis INI Usage 78. Analysis & Synthesis Messages 79. Analysis & Synthesis Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2007 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +------------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+-----------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Thu Aug 30 15:46:16 2007 ; ; Quartus II Version ; 7.1 Build 178 06/25/2007 SP 1 SJ Full Version ; ; Revision Name ; DE1_NIOS ; ; Top-level Entity Name ; DE1_NIOS ; ; Family ; Cyclone II ; ; Total logic elements ; 3,539 ; ; Total combinational functions ; 3,539 ; ; Dedicated logic registers ; 2,479 ; ; Total registers ; 2479 ; ; Total pins ; 287 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 75,264 ; ; Embedded Multiplier 9-bit elements ; 4 ; ; Total PLLs ; 1 ; +------------------------------------+-----------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +--------------------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +--------------------------------------------------------------------------------+--------------------+--------------------+ ; Device ; EP2C20F484C7 ; ; ; Top-level entity name ; DE1_NIOS ; DE1_NIOS ; ; Family name ; Cyclone II ; Stratix ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL93 ; VHDL93 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; DSP Block Balancing ; Auto ; Auto ; ; Maximum DSP Block Usage ; Unlimited ; Unlimited ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique -- Cyclone II/Cyclone III ; Balanced ; Balanced ; ; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Perform gate-level register retiming ; Off ; Off ; ; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto RAM to Logic Cell Conversion ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Maximum Number of M4K/M9K Memory Blocks ; Unlimited ; Unlimited ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Show Parameter Settings Tables in Synthesis Report ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ; ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Use smart compilation ; Off ; Off ; +--------------------------------------------------------------------------------+--------------------+--------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------------------------------------------------------------------------+-----------------+----------------------------------+----------------------------------------------------------------------------------------------------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; +----------------------------------------------------------------------------------------------------+-----------------+----------------------------------+----------------------------------------------------------------------------------------------------+ ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v ; yes ; Encrypted User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module_wrapper.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module_wrapper.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_mult_cell.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_mult_cell.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_test_bench.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_test_bench.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/epcs_controller.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/epcs_controller.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/jtag_uart_0.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/jtag_uart_0.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/KEY.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/KEY.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/LEDG.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/LEDG.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/LEDR.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/LEDR.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SDRAM_PLL.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SDRAM_PLL.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SEG7.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SEG7.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SEG7_LUT.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SEG7_LUT.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SEG7_LUT_4.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SEG7_LUT_4.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sram_0.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sram_0.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SRAM_16Bit_512K.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SRAM_16Bit_512K.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Switch.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Switch.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v ; ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/uart_0.v ; yes ; User Verilog HDL File ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/uart_0.v ; ; altpll.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altpll.tdf ; ; aglobal71.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/aglobal71.inc ; ; stratix_pll.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/stratix_pll.inc ; ; stratixii_pll.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/stratixii_pll.inc ; ; cycloneii_pll.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/cycloneii_pll.inc ; ; altsyncram.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf ; ; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; lpm_mux.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_mux.inc ; ; lpm_decode.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_decode.inc ; ; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/a_rdenreg.inc ; ; altrom.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altrom.inc ; ; altram.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altram.inc ; ; altdpram.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altdpram.inc ; ; altqpram.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altqpram.inc ; ; altsyncram_cub1.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_cub1.tdf ; ; altsyncram_k1l1.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_k1l1.tdf ; ; altsyncram_73e1.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_73e1.tdf ; ; altsyncram_4nd1.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_4nd1.tdf ; ; altsyncram_3um1.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_3um1.tdf ; ; altsyncram_epd1.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_epd1.tdf ; ; altsyncram_fpd1.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_fpd1.tdf ; ; altsyncram_9u12.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_9u12.tdf ; ; altsyncram_a422.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_a422.tdf ; ; altmult_add.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altmult_add.tdf ; ; stratix_mac_mult.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/stratix_mac_mult.inc ; ; stratix_mac_out.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/stratix_mac_out.inc ; ; mult_add_4cr2.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/mult_add_4cr2.tdf ; ; ded_mult_2o81.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/ded_mult_2o81.tdf ; ; dffpipe_93c.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/dffpipe_93c.tdf ; ; mult_add_6cr2.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/mult_add_6cr2.tdf ; ; altsyncram_c572.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_c572.tdf ; ; altsyncram_e502.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_e502.tdf ; ; altsyncram_lo31.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_lo31.tdf ; ; scfifo.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/scfifo.tdf ; ; a_regfifo.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/a_regfifo.inc ; ; a_dpfifo.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/a_dpfifo.inc ; ; a_i2fifo.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/a_i2fifo.inc ; ; a_fffifo.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/a_fffifo.inc ; ; a_f2fifo.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/a_f2fifo.inc ; ; scfifo_1n21.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/scfifo_1n21.tdf ; ; a_dpfifo_8t21.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/a_dpfifo_8t21.tdf ; ; a_fefifo_7cf.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/a_fefifo_7cf.tdf ; ; cntr_rj7.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/cntr_rj7.tdf ; ; dpram_5h21.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/dpram_5h21.tdf ; ; altsyncram_9tl1.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_9tl1.tdf ; ; cntr_fjb.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/cntr_fjb.tdf ; ; alt_jtag_atlantic.v ; yes ; Encrypted Megafunction ; c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v ; ; sld_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd ; ; lpm_shiftreg.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf ; ; lpm_constant.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_constant.inc ; ; dffeea.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/dffeea.inc ; ; lpm_decode.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_decode.tdf ; ; declut.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/declut.inc ; ; altshift.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altshift.inc ; ; lpm_compare.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_compare.inc ; ; decode_aoi.tdf ; yes ; Other ; //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/decode_aoi.tdf ; ; sld_dffex.vhd ; yes ; Encrypted Megafunction ; c:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd ; ; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; c:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd ; +----------------------------------------------------------------------------------------------------+-----------------+----------------------------------+----------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +---------------------------------------------+----------------------------------------------+ ; Resource ; Usage ; +---------------------------------------------+----------------------------------------------+ ; Estimated Total logic elements ; 3,539 ; ; ; ; ; Total combinational functions ; 3539 ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 1899 ; ; -- 3 input functions ; 1132 ; ; -- <=2 input functions ; 508 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 3261 ; ; -- arithmetic mode ; 278 ; ; ; ; ; Total registers ; 2479 ; ; -- Dedicated logic registers ; 2479 ; ; -- I/O registers ; 0 ; ; ; ; ; I/O pins ; 287 ; ; Total memory bits ; 75264 ; ; Embedded Multiplier 9-bit elements ; 4 ; ; Total PLLs ; 1 ; ; Maximum fan-out node ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk0 ; ; Maximum fan-out ; 2511 ; ; Total fan-out ; 26011 ; ; Average fan-out ; 3.97 ; +---------------------------------------------+----------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +---------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; +---------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ ; |DE1_NIOS ; 3539 (1) ; 2479 (0) ; 75264 ; 4 ; 0 ; 2 ; 287 ; 0 ; |DE1_NIOS ; work ; ; |Reset_Delay:delay1| ; 33 (33) ; 25 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|Reset_Delay:delay1 ; work ; ; |SDRAM_PLL:PLL1| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|SDRAM_PLL:PLL1 ; work ; ; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|SDRAM_PLL:PLL1|altpll:altpll_component ; work ; ; |sld_hub:sld_hub_inst| ; 91 (37) ; 68 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|sld_hub:sld_hub_inst ; work ; ; |lpm_decode:instruction_decoder| ; 5 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder ; work ; ; |decode_aoi:auto_generated| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated ; work ; ; |lpm_shiftreg:jtag_ir_register| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register ; work ; ; |sld_dffex:BROADCAST| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|sld_hub:sld_hub_inst|sld_dffex:BROADCAST ; work ; ; |sld_dffex:IRF_ENA_0| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0 ; work ; ; |sld_dffex:IRF_ENA| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA ; work ; ; |sld_dffex:IRSR| ; 4 (4) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|sld_hub:sld_hub_inst|sld_dffex:IRSR ; work ; ; |sld_dffex:RESET| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|sld_hub:sld_hub_inst|sld_dffex:RESET ; work ; ; |sld_dffex:\GEN_IRF:1:IRF| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF ; work ; ; |sld_dffex:\GEN_IRF:2:IRF| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF ; work ; ; |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF ; work ; ; |sld_dffex:\GEN_SHADOW_IRF:2:S_IRF| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:2:S_IRF ; work ; ; |sld_jtag_state_machine:jtag_state_machine| ; 19 (19) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine ; work ; ; |sld_rom_sr:HUB_INFO_REG| ; 21 (21) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ; work ; ; |system_0:u0| ; 3414 (1) ; 2386 (0) ; 75264 ; 4 ; 0 ; 2 ; 0 ; 0 ; |DE1_NIOS|system_0:u0 ; work ; ; |KEY:the_KEY| ; 16 (16) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|KEY:the_KEY ; work ; ; |KEY_s1_arbitrator:the_KEY_s1| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|KEY_s1_arbitrator:the_KEY_s1 ; work ; ; |LEDG:the_LEDG| ; 2 (2) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|LEDG:the_LEDG ; work ; ; |LEDR:the_LEDR| ; 1 (1) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|LEDR:the_LEDR ; work ; ; |SEG7:the_SEG7| ; 28 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|SEG7:the_SEG7 ; work ; ; |SEG7_LUT_4:the_SEG7_LUT_4| ; 28 (0) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4 ; work ; ; |SEG7_LUT:u0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u0 ; work ; ; |SEG7_LUT:u1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u1 ; work ; ; |SEG7_LUT:u2| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u2 ; work ; ; |SEG7_LUT:u3| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u3 ; work ; ; |SEG7_avalonS_arbitrator:the_SEG7_avalonS| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|SEG7_avalonS_arbitrator:the_SEG7_avalonS ; work ; ; |Switch:the_Switch| ; 10 (10) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|Switch:the_Switch ; work ; ; |Switch_s1_arbitrator:the_Switch_s1| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|Switch_s1_arbitrator:the_Switch_s1 ; work ; ; |cpu_0:the_cpu_0| ; 1920 (1688) ; 1497 (1319) ; 70144 ; 4 ; 0 ; 2 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0 ; work ; ; |cpu_0_bht_module:cpu_0_bht| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht ; work ; ; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram ; work ; ; |altsyncram_4nd1:auto_generated| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_4nd1:auto_generated ; work ; ; |altsyncram_3um1:altsyncram1| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_4nd1:auto_generated|altsyncram_3um1:altsyncram1 ; work ; ; |cpu_0_dc_data_module:cpu_0_dc_data| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data ; work ; ; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram ; work ; ; |altsyncram_a422:auto_generated| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated ; work ; ; |cpu_0_dc_tag_module:cpu_0_dc_tag| ; 0 (0) ; 0 (0) ; 7680 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag ; work ; ; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 7680 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram ; work ; ; |altsyncram_9u12:auto_generated| ; 0 (0) ; 0 (0) ; 7680 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_9u12:auto_generated ; work ; ; |cpu_0_ic_data_module:cpu_0_ic_data| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data ; work ; ; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram ; work ; ; |altsyncram_cub1:auto_generated| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated ; work ; ; |altsyncram_k1l1:altsyncram1| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1 ; work ; ; |cpu_0_ic_tag_module:cpu_0_ic_tag| ; 0 (0) ; 0 (0) ; 2560 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag ; work ; ; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 2560 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram ; work ; ; |altsyncram_73e1:auto_generated| ; 0 (0) ; 0 (0) ; 2560 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_73e1:auto_generated ; work ; ; |cpu_0_mult_cell:the_cpu_0_mult_cell| ; 0 (0) ; 0 (0) ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell ; work ; ; |altmult_add:the_altmult_add_part_1| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1 ; work ; ; |mult_add_4cr2:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated ; work ; ; |ded_mult_2o81:ded_mult1| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1 ; work ; ; |altmult_add:the_altmult_add_part_2| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2 ; work ; ; |mult_add_6cr2:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated ; work ; ; |ded_mult_2o81:ded_mult1| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1 ; work ; ; |cpu_0_nios2_oci:the_cpu_0_nios2_oci| ; 221 (8) ; 178 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci ; work ; ; |cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper| ; 106 (0) ; 90 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper ; work ; ; |cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1| ; 106 (106) ; 90 (90) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1 ; work ; ; |cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg| ; 10 (10) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg ; work ; ; |cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break| ; 33 (33) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break ; work ; ; |cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug| ; 11 (11) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug ; work ; ; |cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem| ; 53 (53) ; 44 (44) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem ; work ; ; |cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component ; work ; ; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram ; work ; ; |altsyncram_c572:auto_generated| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated ; work ; ; |cpu_0_register_bank_a_module:cpu_0_register_bank_a| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a ; work ; ; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram ; work ; ; |altsyncram_epd1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_epd1:auto_generated ; work ; ; |cpu_0_register_bank_b_module:cpu_0_register_bank_b| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b ; work ; ; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram ; work ; ; |altsyncram_fpd1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_fpd1:auto_generated ; work ; ; |cpu_0_test_bench:the_cpu_0_test_bench| ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench ; work ; ; |cpu_0_data_master_arbitrator:the_cpu_0_data_master| ; 293 (293) ; 76 (76) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master ; work ; ; |cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master| ; 180 (180) ; 63 (63) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master ; work ; ; |cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module| ; 24 (24) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module ; work ; ; |epcs_controller:the_epcs_controller| ; 109 (1) ; 116 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|epcs_controller:the_epcs_controller ; work ; ; |altsyncram:the_boot_copier_rom| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom ; work ; ; |altsyncram_lo31:auto_generated| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_lo31:auto_generated ; work ; ; |epcs_controller_sub:the_epcs_controller_sub| ; 108 (108) ; 116 (116) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub ; work ; ; |tornado_epcs_controller_atom:the_tornado_epcs_controller_atom| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|epcs_controller:the_epcs_controller|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom ; work ; ; |epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port| ; 26 (26) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port ; work ; ; |jtag_uart_0:the_jtag_uart_0| ; 133 (33) ; 108 (13) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0 ; work ; ; |alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic| ; 50 (50) ; 55 (55) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic ; work ; ; |jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r ; work ; ; |scfifo:rfifo| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo ; work ; ; |scfifo_1n21:auto_generated| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated ; work ; ; |a_dpfifo_8t21:dpfifo| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo ; work ; ; |a_fefifo_7cf:fifo_state| ; 13 (7) ; 8 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state ; work ; ; |cntr_rj7:count_usedw| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw ; work ; ; |cntr_fjb:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:rd_ptr_count ; work ; ; |cntr_fjb:wr_ptr| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:wr_ptr ; work ; ; |dpram_5h21:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram ; work ; ; |altsyncram_9tl1:altsyncram2| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 ; work ; ; |jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w ; work ; ; |scfifo:wfifo| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo ; work ; ; |scfifo_1n21:auto_generated| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated ; work ; ; |a_dpfifo_8t21:dpfifo| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo ; work ; ; |a_fefifo_7cf:fifo_state| ; 13 (7) ; 8 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state ; work ; ; |cntr_rj7:count_usedw| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw ; work ; ; |cntr_fjb:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:rd_ptr_count ; work ; ; |cntr_fjb:wr_ptr| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:wr_ptr ; work ; ; |dpram_5h21:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram ; work ; ; |altsyncram_9tl1:altsyncram2| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 ; work ; ; |jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave ; work ; ; |sdram_0:the_sdram_0| ; 268 (217) ; 240 (154) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0 ; work ; ; |sdram_0_input_efifo_module:the_sdram_0_input_efifo_module| ; 51 (51) ; 86 (86) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module ; work ; ; |sdram_0_s1_arbitrator:the_sdram_0_s1| ; 114 (64) ; 42 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1 ; work ; ; |rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1| ; 32 (32) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1 ; work ; ; |rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1| ; 18 (18) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1 ; work ; ; |sram_0_avalonS_arbitrator:the_sram_0_avalonS| ; 74 (74) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS ; work ; ; |system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch ; work ; ; |tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave| ; 79 (79) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave ; work ; ; |uart_0:the_uart_0| ; 122 (0) ; 94 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|uart_0:the_uart_0 ; work ; ; |uart_0_regs:the_uart_0_regs| ; 38 (38) ; 29 (29) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs ; work ; ; |uart_0_rx:the_uart_0_rx| ; 46 (46) ; 38 (38) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx ; work ; ; |uart_0_tx:the_uart_0_tx| ; 38 (38) ; 27 (27) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx ; work ; ; |uart_0_s1_arbitrator:the_uart_0_s1| ; 8 (8) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE1_NIOS|system_0:u0|uart_0_s1_arbitrator:the_uart_0_s1 ; work ; +---------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis RAM Summary ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-----------------------------------+ ; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-----------------------------------+ ; system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_4nd1:auto_generated|altsyncram_3um1:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 2 ; 256 ; 2 ; 512 ; bht_ram.mif ; ; system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 512 ; 32 ; 512 ; 32 ; 16384 ; None ; ; system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_9u12:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 512 ; 15 ; 512 ; 15 ; 7680 ; dc_tag_ram.mif ; ; system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 1024 ; 32 ; 1024 ; 32 ; 32768 ; None ; ; system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_73e1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128 ; 20 ; 128 ; 20 ; 2560 ; ic_tag_ram.mif ; ; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 32 ; 256 ; 32 ; 8192 ; cpu_0_ociram_default_contents.mif ; ; system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_epd1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; rf_ram_a.mif ; ; system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_fpd1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; rf_ram_b.mif ; ; system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_lo31:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 128 ; 32 ; -- ; -- ; 4096 ; epcs_controller_boot_rom.hex ; ; system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 8 ; 64 ; 8 ; 512 ; None ; ; system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 8 ; 64 ; 8 ; 512 ; None ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-----------------------------------+ +-----------------------------------------------------+ ; Analysis & Synthesis DSP Block Usage Summary ; +---------------------------------------+-------------+ ; Statistic ; Number Used ; +---------------------------------------+-------------+ ; Simple Multipliers (9-bit) ; 0 ; ; Simple Multipliers (18-bit) ; 2 ; ; Embedded Multiplier Blocks ; -- ; ; Embedded Multiplier 9-bit elements ; 4 ; ; Signed Embedded Multipliers ; 0 ; ; Unsigned Embedded Multipliers ; 2 ; ; Mixed Sign Embedded Multipliers ; 0 ; ; Variable Sign Embedded Multipliers ; 0 ; ; Dedicated Input Shift Register Chains ; 0 ; +---------------------------------------+-------------+ Note: number of Embedded Multiplier Blocks used is only available after a successful fit. Encoding Type: One-Hot +----------------------------------------------------------------------------------------------+ ; State Machine - |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_next ; +------------------+------------------+------------------+------------------+------------------+ ; Name ; m_next.010000000 ; m_next.000010000 ; m_next.000001000 ; m_next.000000001 ; +------------------+------------------+------------------+------------------+------------------+ ; m_next.000000001 ; 0 ; 0 ; 0 ; 0 ; ; m_next.000001000 ; 0 ; 0 ; 1 ; 1 ; ; m_next.010000000 ; 1 ; 0 ; 0 ; 1 ; ; m_next.000010000 ; 0 ; 1 ; 0 ; 1 ; +------------------+------------------+------------------+------------------+------------------+ Encoding Type: One-Hot +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_state ; +-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+ ; Name ; m_state.100000000 ; m_state.010000000 ; m_state.001000000 ; m_state.000100000 ; m_state.000010000 ; m_state.000001000 ; m_state.000000100 ; m_state.000000010 ; m_state.000000001 ; +-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+ ; m_state.000000001 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; m_state.000100000 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; ; m_state.000010000 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; ; m_state.000001000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; ; m_state.100000000 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ; m_state.000000100 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; ; m_state.000000010 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; ; m_state.001000000 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ; m_state.010000000 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+ Encoding Type: One-Hot +------------------------------------------------------------------+ ; State Machine - |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_next ; +------------+------------+------------+------------+--------------+ ; Name ; i_next.101 ; i_next.010 ; i_next.111 ; i_next.000 ; +------------+------------+------------+------------+--------------+ ; i_next.000 ; 0 ; 0 ; 0 ; 0 ; ; i_next.111 ; 0 ; 0 ; 1 ; 1 ; ; i_next.010 ; 0 ; 1 ; 0 ; 1 ; ; i_next.101 ; 1 ; 0 ; 0 ; 1 ; +------------+------------+------------+------------+--------------+ Encoding Type: One-Hot +-------------------------------------------------------------------------------------------------+ ; State Machine - |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_state ; +-------------+-------------+-------------+-------------+-------------+-------------+-------------+ ; Name ; i_state.101 ; i_state.111 ; i_state.001 ; i_state.011 ; i_state.010 ; i_state.000 ; +-------------+-------------+-------------+-------------+-------------+-------------+-------------+ ; i_state.000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; i_state.010 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; ; i_state.011 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; ; i_state.001 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; ; i_state.111 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; ; i_state.101 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +-------------+-------------+-------------+-------------+-------------+-------------+-------------+ Encoding Type: One-Hot +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize ; +------------+------------+------------+------------+------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------+ ; Name ; DRsize.011 ; DRsize.100 ; DRsize.101 ; DRsize.010 ; DRsize.001 ; DRsize.000 ; +------------+------------+------------+------------+------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------+ ; DRsize.000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; DRsize.001 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; ; DRsize.010 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; ; DRsize.101 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; ; DRsize.100 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; ; DRsize.011 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +------------+------------+------------+------------+------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Registers Protected by Synthesis ; +-----------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ ; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ; +-----------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ ; system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_out ; yes ; yes ; ; system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_in_d1 ; yes ; yes ; +-----------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ +-------------------------------------------------------------+ ; Logic Cells Representing Combinational Loops ; +--------------------------------------------------------+----+ ; Logic Cell Name ; ; +--------------------------------------------------------+----+ ; rtl~0 ; ; ; rtl~1 ; ; ; rtl~2 ; ; ; rtl~3 ; ; ; rtl~4 ; ; ; rtl~5 ; ; ; rtl~6 ; ; ; rtl~7 ; ; ; rtl~8 ; ; ; rtl~9 ; ; ; Number of logic cells representing combinational loops ; 10 ; +--------------------------------------------------------+----+ Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Registers Removed During Synthesis ; +------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+ ; Register name ; Reason for Removal ; +------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+ ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[0..35] ; Lost fanout ; ; u0/the_uart_0/the_uart_0_regs/readdata[10..15] ; Stuck at GND due to stuck port data_in ; ; u0/the_sdram_0/i_addr[4..5] ; Stuck at VCC due to stuck port data_in ; ; u0/the_cpu_0/A_ipending_reg[4..31] ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_im_addr[0..6] ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/tracemem_tw ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_dbrk/dbrk_break_pulse ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_dbrk/dbrk_goto0 ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_dbrk/dbrk_goto1 ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/xbrk_hit0 ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/xbrk_hit1 ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/xbrk_hit2 ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/xbrk_hit3 ; Lost fanout ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/xbrk_break ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/E_xbrk_goto0 ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/E_xbrk_goto1 ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/M_xbrk_goto0 ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_break/dbrk_hit3_latch ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_break/dbrk_hit2_latch ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_break/dbrk_hit1_latch ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_break/dbrk_hit0_latch ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_avalon_reg/oci_ienable[4..31] ; Stuck at VCC due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/M_xbrk_goto1 ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[0..16] ; Lost fanout ; ; u0/the_uart_0/the_uart_0_rx/delayed_unxsync_rxdxx2 ; Merged with u0/the_uart_0/the_uart_0_rx/delayed_unxsync_rxdxx1 ; ; u0/the_tri_state_bridge_0_avalon_slave/d1_tri_state_bridge_0_avalon_slave_end_xfer ; Merged with u0/the_tri_state_bridge_0_avalon_slave/d1_reasons_to_wait ; ; u0/the_sram_0_avalonS/d1_sram_0_avalonS_end_xfer ; Merged with u0/the_sram_0_avalonS/d1_reasons_to_wait ; ; u0/the_sdram_0/i_addr[0..3,6..10] ; Merged with u0/the_sdram_0/i_addr[11] ; ; u0/the_epcs_controller_epcs_control_port/d1_epcs_controller_epcs_control_port_end_xfer ; Merged with u0/the_epcs_controller_epcs_control_port/d1_reasons_to_wait ; ; u0/the_cpu_0_jtag_debug_module/d1_cpu_0_jtag_debug_module_end_xfer ; Merged with u0/the_cpu_0_jtag_debug_module/d1_reasons_to_wait ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_break/trigger_state ; Stuck at GND due to stuck port data_in ; ; u0/the_sdram_0_s1/rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1/full_6 ; Merged with u0/the_sdram_0_s1/rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1/full_6 ; ; u0/the_sdram_0_s1/rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1/full_5 ; Merged with u0/the_sdram_0_s1/rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1/full_5 ; ; u0/the_sdram_0_s1/rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1/full_4 ; Merged with u0/the_sdram_0_s1/rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1/full_4 ; ; u0/the_sdram_0_s1/rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1/full_3 ; Merged with u0/the_sdram_0_s1/rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1/full_3 ; ; u0/the_sdram_0_s1/rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1/full_2 ; Merged with u0/the_sdram_0_s1/rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1/full_2 ; ; u0/the_sdram_0_s1/rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1/full_1 ; Merged with u0/the_sdram_0_s1/rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1/full_1 ; ; u0/the_sdram_0_s1/rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1/full_0 ; Merged with u0/the_sdram_0_s1/rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1/full_0 ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_dbrk/dbrk_break ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_break/trigbrktype ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0/D_ctrl_jmp_direct ; Merged with u0/the_cpu_0/D_ctrl_a_not_src ; ; u0/the_cpu_0/D_ctrl_b_is_dst ; Merged with u0/the_cpu_0/D_ctrl_b_not_src ; ; u0/the_cpu_0_jtag_debug_module/cpu_0_jtag_debug_module_arb_share_counter[2] ; Stuck at GND due to stuck port data_in ; ; u0/the_epcs_controller_epcs_control_port/epcs_controller_epcs_control_port_arb_share_counter[2] ; Stuck at GND due to stuck port data_in ; ; u0/the_sdram_0/m_next~64 ; Lost fanout ; ; u0/the_sdram_0/m_next~65 ; Lost fanout ; ; u0/the_sdram_0/m_next~68 ; Lost fanout ; ; u0/the_sdram_0/m_next~69 ; Lost fanout ; ; u0/the_sdram_0/m_next~71 ; Lost fanout ; ; u0/the_sdram_0/i_next~17 ; Lost fanout ; ; u0/the_sdram_0/i_next~18 ; Lost fanout ; ; u0/the_sdram_0/i_next~19 ; Lost fanout ; ; u0/the_sdram_0/i_state~56 ; Lost fanout ; ; u0/the_sdram_0/i_state~57 ; Lost fanout ; ; u0/the_sdram_0/i_state~58 ; Lost fanout ; ; u0/the_epcs_controller_epcs_control_port/epcs_controller_epcs_control_port_slavearbiterlockenable ; Stuck at GND due to stuck port data_in ; ; u0/the_cpu_0_jtag_debug_module/cpu_0_jtag_debug_module_slavearbiterlockenable ; Stuck at GND due to stuck port data_in ; ; u0/the_epcs_controller_epcs_control_port/epcs_controller_epcs_control_port_arb_share_counter[0..1] ; Lost fanout ; ; u0/the_cpu_0_jtag_debug_module/cpu_0_jtag_debug_module_arb_share_counter[0..1] ; Lost fanout ; ; u0/the_epcs_controller_epcs_control_port/last_cycle_cpu_0_data_master_granted_slave_epcs_controller_epcs_control_port ; Lost fanout ; ; u0/the_epcs_controller_epcs_control_port/last_cycle_cpu_0_instruction_master_granted_slave_epcs_controller_epcs_control_port ; Lost fanout ; ; u0/the_cpu_0_jtag_debug_module/last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module ; Lost fanout ; ; u0/the_cpu_0_jtag_debug_module/last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module ; Lost fanout ; ; u0/the_epcs_controller_epcs_control_port/epcs_controller_epcs_control_port_saved_chosen_master_vector[1] ; Lost fanout ; ; u0/the_cpu_0_jtag_debug_module/cpu_0_jtag_debug_module_saved_chosen_master_vector[0..1] ; Lost fanout ; ; Total Number of Removed Registers = 193 ; ; +------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Removed Registers Triggering Further Register Optimizations ; +---------------------------------------------------------------------------------------------------+---------------------------+------------------------------------------------------------------------------------------------------------------------------+ ; Register name ; Reason for Removal ; Registers Removed due to This Register ; +---------------------------------------------------------------------------------------------------+---------------------------+------------------------------------------------------------------------------------------------------------------------------+ ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/xbrk_hit0 ; Stuck at GND ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/xbrk_hit3, ; ; ; due to stuck port data_in ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/xbrk_break, ; ; ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/E_xbrk_goto0, ; ; ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/E_xbrk_goto1, ; ; ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/M_xbrk_goto0, ; ; ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/M_xbrk_goto1 ; ; u0/the_cpu_0_jtag_debug_module/cpu_0_jtag_debug_module_arb_share_counter[2] ; Stuck at GND ; u0/the_cpu_0_jtag_debug_module/cpu_0_jtag_debug_module_arb_share_counter[1], ; ; ; due to stuck port data_in ; u0/the_cpu_0_jtag_debug_module/last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module, ; ; ; ; u0/the_cpu_0_jtag_debug_module/last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module ; ; u0/the_epcs_controller_epcs_control_port/epcs_controller_epcs_control_port_arb_share_counter[2] ; Stuck at GND ; u0/the_epcs_controller_epcs_control_port/epcs_controller_epcs_control_port_arb_share_counter[0], ; ; ; due to stuck port data_in ; u0/the_epcs_controller_epcs_control_port/last_cycle_cpu_0_data_master_granted_slave_epcs_controller_epcs_control_port, ; ; ; ; u0/the_epcs_controller_epcs_control_port/last_cycle_cpu_0_instruction_master_granted_slave_epcs_controller_epcs_control_port ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_dbrk/dbrk_break_pulse ; Stuck at GND ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_dbrk/dbrk_break, ; ; ; due to stuck port data_in ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_break/trigbrktype ; ; u0/the_cpu_0_jtag_debug_module/cpu_0_jtag_debug_module_slavearbiterlockenable ; Stuck at GND ; u0/the_cpu_0_jtag_debug_module/cpu_0_jtag_debug_module_saved_chosen_master_vector[1], ; ; ; due to stuck port data_in ; u0/the_cpu_0_jtag_debug_module/cpu_0_jtag_debug_module_saved_chosen_master_vector[0] ; ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_dbrk/dbrk_goto0 ; Stuck at GND ; u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_break/trigger_state ; ; ; due to stuck port data_in ; ; ; u0/the_epcs_controller_epcs_control_port/epcs_controller_epcs_control_port_slavearbiterlockenable ; Stuck at GND ; u0/the_epcs_controller_epcs_control_port/epcs_controller_epcs_control_port_saved_chosen_master_vector[1] ; ; ; due to stuck port data_in ; ; +---------------------------------------------------------------------------------------------------+---------------------------+------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 2479 ; ; Number of registers using Synchronous Clear ; 55 ; ; Number of registers using Synchronous Load ; 233 ; ; Number of registers using Asynchronous Clear ; 2234 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 1758 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Inverted Register Statistics ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ ; Inverted Register ; Fan out ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ ; system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|txd ; 1 ; ; system_0:u0|sdram_0:the_sdram_0|m_cmd[0] ; 2 ; ; system_0:u0|sdram_0:the_sdram_0|m_cmd[1] ; 2 ; ; system_0:u0|sdram_0:the_sdram_0|m_cmd[2] ; 2 ; ; system_0:u0|sdram_0:the_sdram_0|m_cmd[3] ; 1 ; ; system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|write_n_to_the_cfi_flash_0 ; 1 ; ; system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn ; 1 ; ; system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|select_n_to_the_cfi_flash_0 ; 1 ; ; system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n ; 5 ; ; system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_addend[0] ; 6 ; ; system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest ; 15 ; ; system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|pre_txd ; 2 ; ; system_0:u0|sdram_0:the_sdram_0|i_addr[11] ; 10 ; ; system_0:u0|sdram_0:the_sdram_0|i_cmd[0] ; 2 ; ; system_0:u0|sdram_0:the_sdram_0|i_cmd[1] ; 2 ; ; system_0:u0|sdram_0:the_sdram_0|i_cmd[2] ; 2 ; ; system_0:u0|sdram_0:the_sdram_0|i_cmd[3] ; 2 ; ; system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0] ; 6 ; ; system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|fifo_contains_ones_n ; 2 ; ; system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_addend[0] ; 6 ; ; system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[0] ; 5 ; ; system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[0] ; 7 ; ; system_0:u0|cpu_0:the_cpu_0|M_pipe_flush ; 40 ; ; sld_hub:sld_hub_inst|hub_tdo_reg ; 2 ; ; system_0:u0|jtag_uart_0:the_jtag_uart_0|av_waitrequest ; 3 ; ; system_0:u0|sdram_0:the_sdram_0|refresh_counter[13] ; 2 ; ; system_0:u0|sdram_0:the_sdram_0|refresh_counter[10] ; 2 ; ; system_0:u0|sdram_0:the_sdram_0|refresh_counter[9] ; 2 ; ; system_0:u0|sdram_0:the_sdram_0|refresh_counter[8] ; 2 ; ; system_0:u0|sdram_0:the_sdram_0|refresh_counter[4] ; 2 ; ; system_0:u0|cpu_0:the_cpu_0|hbreak_enabled ; 12 ; ; system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[9] ; 11 ; ; system_0:u0|jtag_uart_0:the_jtag_uart_0|t_dav ; 3 ; ; system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|tx_ready ; 6 ; ; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[3] ; 2 ; ; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[2] ; 2 ; ; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[1] ; 2 ; ; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[0] ; 2 ; ; system_0:u0|cpu_0:the_cpu_0|A_wr_dst_reg_from_M ; 66 ; ; system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|tx_shift_empty ; 2 ; ; system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rst2 ; 2 ; ; system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[0] ; 2 ; ; system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rst1 ; 1 ; ; system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_holding_reg[0] ; 1 ; ; system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|stateZero ; 1 ; ; Total number of inverted registers = 45 ; ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Restructuring Statistics (Restructuring Performed) ; +--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|M_mem_byte_en[0] ; ; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[6] ; ; 3:1 ; 26 bits ; 52 LEs ; 52 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|D_iw[31] ; ; 3:1 ; 28 bits ; 56 LEs ; 56 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|A_inst_result[24] ; ; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|A_inst_result[0] ; ; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |DE1_NIOS|system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] ; ; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_cnt[1] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_offset[2] ; ; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entries[1] ; ; 4:1 ; 20 bits ; 40 LEs ; 40 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[13] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[5] ; ; 4:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[9] ; ; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |DE1_NIOS|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |DE1_NIOS|system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] ; ; 8:1 ; 3 bits ; 15 LEs ; 6 LEs ; 9 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|E_control_rd_data_without_mmu_regs[3] ; ; 4:1 ; 15 bits ; 30 LEs ; 30 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|E_src2[24] ; ; 8:1 ; 5 bits ; 25 LEs ; 10 LEs ; 15 LEs ; Yes ; |DE1_NIOS|system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[12] ; ; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; Yes ; |DE1_NIOS|system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[8] ; ; 8:1 ; 3 bits ; 15 LEs ; 6 LEs ; 9 LEs ; Yes ; |DE1_NIOS|system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[2] ; ; 8:1 ; 4 bits ; 20 LEs ; 12 LEs ; 8 LEs ; Yes ; |DE1_NIOS|system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[6] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |DE1_NIOS|system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[2] ; ; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[0] ; ; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_wait_counter[0] ; ; 4:1 ; 9 bits ; 18 LEs ; 18 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[29] ; ; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|M_st_data[25] ; ; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[17] ; ; 5:1 ; 22 bits ; 66 LEs ; 66 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[5] ; ; 5:1 ; 32 bits ; 96 LEs ; 96 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|E_src1[6] ; ; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |DE1_NIOS|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[1] ; ; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_dqm[1] ; ; 5:1 ; 2 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|M_mem_byte_en[3] ; ; 6:1 ; 12 bits ; 48 LEs ; 48 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|F_pc[13] ; ; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_addr[9] ; ; 7:1 ; 2 bits ; 8 LEs ; 6 LEs ; 2 LEs ; Yes ; |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_addr[4] ; ; 7:1 ; 6 bits ; 24 LEs ; 18 LEs ; 6 LEs ; Yes ; |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_addr[0] ; ; 28:1 ; 4 bits ; 72 LEs ; 48 LEs ; 24 LEs ; Yes ; |DE1_NIOS|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[2] ; ; 12:1 ; 41 bits ; 328 LEs ; 0 LEs ; 328 LEs ; Yes ; |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|active_addr[6] ; ; 4:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_data[4] ; ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|comb~2 ; ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |DE1_NIOS|system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|sram_0_avalonS_arb_share_counter_next_value[2] ; ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cfgdout[2] ; ; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter_next_value[2] ; ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |DE1_NIOS|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_share_counter_next_value[2] ; ; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|E_logic_result[2] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; No ; |DE1_NIOS|system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_share_counter_next_value[2] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_share_counter_next_value[1] ; ; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|F_iw[0] ; ; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|dc_data_portb_byte_en[3] ; ; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |DE1_NIOS|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_set_values[2] ; ; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |DE1_NIOS|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|updated_one_count~15 ; ; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |DE1_NIOS|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|updated_one_count~15 ; ; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|D_dst_regnum[0] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|E_alu_result[31] ; ; 4:1 ; 9 bits ; 18 LEs ; 18 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|E_alu_result[7] ; ; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[0] ; ; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|readdata[3] ; ; 5:1 ; 7 bits ; 21 LEs ; 21 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|E_alu_result[25] ; ; 5:1 ; 13 bits ; 39 LEs ; 39 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|E_alu_result[22] ; ; 5:1 ; 32 bits ; 96 LEs ; 96 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|D_src2_reg[22] ; ; 5:1 ; 16 bits ; 48 LEs ; 48 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[29] ; ; 5:1 ; 8 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[12] ; ; 6:1 ; 8 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[3] ; ; 6:1 ; 10 bits ; 40 LEs ; 40 LEs ; 0 LEs ; No ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|F_ic_data_rd_addr_nxt[2] ; ; 11:1 ; 2 bits ; 14 LEs ; 4 LEs ; 10 LEs ; No ; |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|Selector34 ; ; 16:1 ; 2 bits ; 20 LEs ; 8 LEs ; 12 LEs ; No ; |DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|Selector26 ; ; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[36] ; ; 6:1 ; 6 bits ; 24 LEs ; 18 LEs ; 6 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12] ; ; 6:1 ; 18 bits ; 72 LEs ; 36 LEs ; 36 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[21] ; ; 6:1 ; 7 bits ; 28 LEs ; 21 LEs ; 7 LEs ; Yes ; |DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[4] ; ; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[1] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[9] ; ; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[7] ; ; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |DE1_NIOS|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[1] ; +--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated ; +---------------------------------+--------------------+------+----------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+----------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+----------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1 ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_73e1:auto_generated ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_4nd1:auto_generated ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_4nd1:auto_generated|altsyncram_3um1:altsyncram1 ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_epd1:auto_generated ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_fpd1:auto_generated ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_9u12:auto_generated ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+--------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated ; +---------------------------------+--------------------+------+----------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+----------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+----------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result ; +---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+ ; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; +---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result ; +---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+ ; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; +---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated ; +---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_lo31:auto_generated ; +---------------------------------+--------------------+------+------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------+ ; Source assignments for system_0:u0|sdram_0:the_sdram_0 ; +-----------------------------+-------+------+------------------+ ; Assignment ; Value ; From ; To ; +-----------------------------+-------+------+------------------+ ; FAST_INPUT_REGISTER ; ON ; - ; za_data[15] ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[14] ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[13] ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[12] ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[11] ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[10] ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[9] ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[8] ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[7] ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[6] ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[5] ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[4] ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[3] ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[2] ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[1] ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[0] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_cmd[3] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_cmd[2] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_cmd[1] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_cmd[0] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_bank[1] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_bank[0] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[11] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[10] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[9] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[8] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[7] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[6] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[5] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[4] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[3] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[2] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[1] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[0] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[15] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[15] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[14] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[14] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[13] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[13] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[12] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[12] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[11] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[11] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[10] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[10] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[9] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[9] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[8] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[8] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[7] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[7] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[6] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[6] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[5] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[5] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[4] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[4] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[3] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[3] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[2] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[2] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[1] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[1] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[0] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[0] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_dqm[1] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; m_dqm[0] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; oe ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[15]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[14]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[13]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[12]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[11]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[10]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[9]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[8]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[7]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[6]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[5]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[4]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[3]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[2]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[1]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; za_data[0]~reg0 ; +-----------------------------+-------+------+------------------+ +-------------------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave ; +-----------------------------+-------+------+----------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +-----------------------------+-------+------+----------------------------------------------------------------------+ ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[7] ; ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[6] ; ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[5] ; ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[4] ; ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[3] ; ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[2] ; ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[1] ; ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[0] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; select_n_to_the_cfi_flash_0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[21] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[20] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[19] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[18] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[17] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[16] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[15] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[14] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[13] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[12] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[11] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[10] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[9] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[8] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[7] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[6] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[5] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[4] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[3] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[2] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[1] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[0] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_readn ; ; FAST_OUTPUT_REGISTER ; ON ; - ; write_n_to_the_cfi_flash_0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; select_n_to_the_cfi_flash_0~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[7]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[6]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[5]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[4]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[3]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[2]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[1]~reg0 ; ; FAST_INPUT_REGISTER ; ON ; - ; incoming_tri_state_bridge_0_data[0]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; d1_outgoing_tri_state_bridge_0_data[7] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; d1_outgoing_tri_state_bridge_0_data[6] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; d1_outgoing_tri_state_bridge_0_data[5] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; d1_outgoing_tri_state_bridge_0_data[4] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; d1_outgoing_tri_state_bridge_0_data[3] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; d1_outgoing_tri_state_bridge_0_data[2] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; d1_outgoing_tri_state_bridge_0_data[1] ; ; FAST_OUTPUT_REGISTER ; ON ; - ; d1_outgoing_tri_state_bridge_0_data[0] ; ; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; d1_in_a_write_cycle ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_readn~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; write_n_to_the_cfi_flash_0~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[21]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[20]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[19]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[18]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[17]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[16]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[15]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[14]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[13]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[12]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[11]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[10]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[9]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[8]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[7]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[6]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[5]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[4]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[3]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[2]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[1]~reg0 ; ; FAST_OUTPUT_REGISTER ; ON ; - ; tri_state_bridge_0_address[0]~reg0 ; +-----------------------------+-------+------+----------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------+ ; Source assignments for system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch ; +-------------------+-------+------+------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +-------------------+-------+------+------------------------------------------------------------------------+ ; PRESERVE_REGISTER ; ON ; - ; data_out ; ; PRESERVE_REGISTER ; ON ; - ; data_out~reg0 ; ; MAX_DELAY ; 100ns ; - ; data_in_d1 ; ; PRESERVE_REGISTER ; ON ; - ; data_in_d1 ; +-------------------+-------+------+------------------------------------------------------------------------+ +----------------------------------------------------------+ ; Source assignments for sld_hub:sld_hub_inst ; +------------------------------+-------+------+------------+ ; Assignment ; Value ; From ; To ; +------------------------------+-------+------+------------+ ; IGNORE_LCELL_BUFFERS ; OFF ; - ; - ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF ; - ; - ; ; NOT_GATE_PUSH_BACK ; OFF ; - ; CLR_SIGNAL ; ; POWER_UP_LEVEL ; LOW ; - ; CLR_SIGNAL ; +------------------------------+-------+------+------------+ +---------------------------------------------------------------------+ ; Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ; +----------------------+-------+------+-------------------------------+ ; Assignment ; Value ; From ; To ; +----------------------+-------+------+-------------------------------+ ; AUTO_ROM_RECOGNITION ; OFF ; - ; - ; +----------------------+-------+------+-------------------------------+ +-------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: SDRAM_PLL:PLL1|altpll:altpll_component ; +-------------------------------+-------------------+---------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------------+-------------------+---------------------------------+ ; OPERATION_MODE ; NORMAL ; Untyped ; ; PLL_TYPE ; FAST ; Untyped ; ; QUALIFY_CONF_DONE ; OFF ; Untyped ; ; COMPENSATE_CLOCK ; CLK0 ; Untyped ; ; SCAN_CHAIN ; LONG ; Untyped ; ; PRIMARY_CLOCK ; INCLK0 ; Untyped ; ; INCLK0_INPUT_FREQUENCY ; 20000 ; Signed Integer ; ; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; ; GATE_LOCK_SIGNAL ; NO ; Untyped ; ; GATE_LOCK_COUNTER ; 0 ; Untyped ; ; LOCK_HIGH ; 1 ; Untyped ; ; LOCK_LOW ; 1 ; Untyped ; ; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; ; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; ; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; ; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; ; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; ; SKIP_VCO ; OFF ; Untyped ; ; SWITCH_OVER_COUNTER ; 0 ; Untyped ; ; SWITCH_OVER_TYPE ; AUTO ; Untyped ; ; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; ; BANDWIDTH ; 0 ; Untyped ; ; BANDWIDTH_TYPE ; AUTO ; Untyped ; ; SPREAD_FREQUENCY ; 0 ; Untyped ; ; DOWN_SPREAD ; 0 ; Untyped ; ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; ; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; ; CLK9_MULTIPLY_BY ; 0 ; Untyped ; ; CLK8_MULTIPLY_BY ; 0 ; Untyped ; ; CLK7_MULTIPLY_BY ; 0 ; Untyped ; ; CLK6_MULTIPLY_BY ; 0 ; Untyped ; ; CLK5_MULTIPLY_BY ; 1 ; Untyped ; ; CLK4_MULTIPLY_BY ; 1 ; Untyped ; ; CLK3_MULTIPLY_BY ; 1 ; Untyped ; ; CLK2_MULTIPLY_BY ; 1 ; Untyped ; ; CLK1_MULTIPLY_BY ; 2 ; Signed Integer ; ; CLK0_MULTIPLY_BY ; 2 ; Signed Integer ; ; CLK9_DIVIDE_BY ; 0 ; Untyped ; ; CLK8_DIVIDE_BY ; 0 ; Untyped ; ; CLK7_DIVIDE_BY ; 0 ; Untyped ; ; CLK6_DIVIDE_BY ; 0 ; Untyped ; ; CLK5_DIVIDE_BY ; 1 ; Untyped ; ; CLK4_DIVIDE_BY ; 1 ; Untyped ; ; CLK3_DIVIDE_BY ; 1 ; Untyped ; ; CLK2_DIVIDE_BY ; 1 ; Untyped ; ; CLK1_DIVIDE_BY ; 1 ; Signed Integer ; ; CLK0_DIVIDE_BY ; 1 ; Signed Integer ; ; CLK9_PHASE_SHIFT ; 0 ; Untyped ; ; CLK8_PHASE_SHIFT ; 0 ; Untyped ; ; CLK7_PHASE_SHIFT ; 0 ; Untyped ; ; CLK6_PHASE_SHIFT ; 0 ; Untyped ; ; CLK5_PHASE_SHIFT ; 0 ; Untyped ; ; CLK4_PHASE_SHIFT ; 0 ; Untyped ; ; CLK3_PHASE_SHIFT ; 0 ; Untyped ; ; CLK2_PHASE_SHIFT ; 0 ; Untyped ; ; CLK1_PHASE_SHIFT ; 0 ; Untyped ; ; CLK0_PHASE_SHIFT ; -3000 ; Untyped ; ; CLK5_TIME_DELAY ; 0 ; Untyped ; ; CLK4_TIME_DELAY ; 0 ; Untyped ; ; CLK3_TIME_DELAY ; 0 ; Untyped ; ; CLK2_TIME_DELAY ; 0 ; Untyped ; ; CLK1_TIME_DELAY ; 0 ; Untyped ; ; CLK0_TIME_DELAY ; 0 ; Untyped ; ; CLK9_DUTY_CYCLE ; 50 ; Untyped ; ; CLK8_DUTY_CYCLE ; 50 ; Untyped ; ; CLK7_DUTY_CYCLE ; 50 ; Untyped ; ; CLK6_DUTY_CYCLE ; 50 ; Untyped ; ; CLK5_DUTY_CYCLE ; 50 ; Untyped ; ; CLK4_DUTY_CYCLE ; 50 ; Untyped ; ; CLK3_DUTY_CYCLE ; 50 ; Untyped ; ; CLK2_DUTY_CYCLE ; 50 ; Untyped ; ; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; ; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; ; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; LOCK_WINDOW_UI ; 0.05 ; Untyped ; ; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; ; VCO_MULTIPLY_BY ; 0 ; Untyped ; ; VCO_DIVIDE_BY ; 0 ; Untyped ; ; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; ; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; ; VCO_MIN ; 0 ; Untyped ; ; VCO_MAX ; 0 ; Untyped ; ; VCO_CENTER ; 0 ; Untyped ; ; PFD_MIN ; 0 ; Untyped ; ; PFD_MAX ; 0 ; Untyped ; ; M_INITIAL ; 0 ; Untyped ; ; M ; 0 ; Untyped ; ; N ; 1 ; Untyped ; ; M2 ; 1 ; Untyped ; ; N2 ; 1 ; Untyped ; ; SS ; 1 ; Untyped ; ; C0_HIGH ; 0 ; Untyped ; ; C1_HIGH ; 0 ; Untyped ; ; C2_HIGH ; 0 ; Untyped ; ; C3_HIGH ; 0 ; Untyped ; ; C4_HIGH ; 0 ; Untyped ; ; C5_HIGH ; 0 ; Untyped ; ; C6_HIGH ; 0 ; Untyped ; ; C7_HIGH ; 0 ; Untyped ; ; C8_HIGH ; 0 ; Untyped ; ; C9_HIGH ; 0 ; Untyped ; ; C0_LOW ; 0 ; Untyped ; ; C1_LOW ; 0 ; Untyped ; ; C2_LOW ; 0 ; Untyped ; ; C3_LOW ; 0 ; Untyped ; ; C4_LOW ; 0 ; Untyped ; ; C5_LOW ; 0 ; Untyped ; ; C6_LOW ; 0 ; Untyped ; ; C7_LOW ; 0 ; Untyped ; ; C8_LOW ; 0 ; Untyped ; ; C9_LOW ; 0 ; Untyped ; ; C0_INITIAL ; 0 ; Untyped ; ; C1_INITIAL ; 0 ; Untyped ; ; C2_INITIAL ; 0 ; Untyped ; ; C3_INITIAL ; 0 ; Untyped ; ; C4_INITIAL ; 0 ; Untyped ; ; C5_INITIAL ; 0 ; Untyped ; ; C6_INITIAL ; 0 ; Untyped ; ; C7_INITIAL ; 0 ; Untyped ; ; C8_INITIAL ; 0 ; Untyped ; ; C9_INITIAL ; 0 ; Untyped ; ; C0_MODE ; BYPASS ; Untyped ; ; C1_MODE ; BYPASS ; Untyped ; ; C2_MODE ; BYPASS ; Untyped ; ; C3_MODE ; BYPASS ; Untyped ; ; C4_MODE ; BYPASS ; Untyped ; ; C5_MODE ; BYPASS ; Untyped ; ; C6_MODE ; BYPASS ; Untyped ; ; C7_MODE ; BYPASS ; Untyped ; ; C8_MODE ; BYPASS ; Untyped ; ; C9_MODE ; BYPASS ; Untyped ; ; C0_PH ; 0 ; Untyped ; ; C1_PH ; 0 ; Untyped ; ; C2_PH ; 0 ; Untyped ; ; C3_PH ; 0 ; Untyped ; ; C4_PH ; 0 ; Untyped ; ; C5_PH ; 0 ; Untyped ; ; C6_PH ; 0 ; Untyped ; ; C7_PH ; 0 ; Untyped ; ; C8_PH ; 0 ; Untyped ; ; C9_PH ; 0 ; Untyped ; ; L0_HIGH ; 1 ; Untyped ; ; L1_HIGH ; 1 ; Untyped ; ; G0_HIGH ; 1 ; Untyped ; ; G1_HIGH ; 1 ; Untyped ; ; G2_HIGH ; 1 ; Untyped ; ; G3_HIGH ; 1 ; Untyped ; ; E0_HIGH ; 1 ; Untyped ; ; E1_HIGH ; 1 ; Untyped ; ; E2_HIGH ; 1 ; Untyped ; ; E3_HIGH ; 1 ; Untyped ; ; L0_LOW ; 1 ; Untyped ; ; L1_LOW ; 1 ; Untyped ; ; G0_LOW ; 1 ; Untyped ; ; G1_LOW ; 1 ; Untyped ; ; G2_LOW ; 1 ; Untyped ; ; G3_LOW ; 1 ; Untyped ; ; E0_LOW ; 1 ; Untyped ; ; E1_LOW ; 1 ; Untyped ; ; E2_LOW ; 1 ; Untyped ; ; E3_LOW ; 1 ; Untyped ; ; L0_INITIAL ; 1 ; Untyped ; ; L1_INITIAL ; 1 ; Untyped ; ; G0_INITIAL ; 1 ; Untyped ; ; G1_INITIAL ; 1 ; Untyped ; ; G2_INITIAL ; 1 ; Untyped ; ; G3_INITIAL ; 1 ; Untyped ; ; E0_INITIAL ; 1 ; Untyped ; ; E1_INITIAL ; 1 ; Untyped ; ; E2_INITIAL ; 1 ; Untyped ; ; E3_INITIAL ; 1 ; Untyped ; ; L0_MODE ; BYPASS ; Untyped ; ; L1_MODE ; BYPASS ; Untyped ; ; G0_MODE ; BYPASS ; Untyped ; ; G1_MODE ; BYPASS ; Untyped ; ; G2_MODE ; BYPASS ; Untyped ; ; G3_MODE ; BYPASS ; Untyped ; ; E0_MODE ; BYPASS ; Untyped ; ; E1_MODE ; BYPASS ; Untyped ; ; E2_MODE ; BYPASS ; Untyped ; ; E3_MODE ; BYPASS ; Untyped ; ; L0_PH ; 0 ; Untyped ; ; L1_PH ; 0 ; Untyped ; ; G0_PH ; 0 ; Untyped ; ; G1_PH ; 0 ; Untyped ; ; G2_PH ; 0 ; Untyped ; ; G3_PH ; 0 ; Untyped ; ; E0_PH ; 0 ; Untyped ; ; E1_PH ; 0 ; Untyped ; ; E2_PH ; 0 ; Untyped ; ; E3_PH ; 0 ; Untyped ; ; M_PH ; 0 ; Untyped ; ; C1_USE_CASC_IN ; OFF ; Untyped ; ; C2_USE_CASC_IN ; OFF ; Untyped ; ; C3_USE_CASC_IN ; OFF ; Untyped ; ; C4_USE_CASC_IN ; OFF ; Untyped ; ; C5_USE_CASC_IN ; OFF ; Untyped ; ; C6_USE_CASC_IN ; OFF ; Untyped ; ; C7_USE_CASC_IN ; OFF ; Untyped ; ; C8_USE_CASC_IN ; OFF ; Untyped ; ; C9_USE_CASC_IN ; OFF ; Untyped ; ; CLK0_COUNTER ; G0 ; Untyped ; ; CLK1_COUNTER ; G0 ; Untyped ; ; CLK2_COUNTER ; G0 ; Untyped ; ; CLK3_COUNTER ; G0 ; Untyped ; ; CLK4_COUNTER ; G0 ; Untyped ; ; CLK5_COUNTER ; G0 ; Untyped ; ; L0_TIME_DELAY ; 0 ; Untyped ; ; L1_TIME_DELAY ; 0 ; Untyped ; ; G0_TIME_DELAY ; 0 ; Untyped ; ; G1_TIME_DELAY ; 0 ; Untyped ; ; G2_TIME_DELAY ; 0 ; Untyped ; ; G3_TIME_DELAY ; 0 ; Untyped ; ; E0_TIME_DELAY ; 0 ; Untyped ; ; E1_TIME_DELAY ; 0 ; Untyped ; ; E2_TIME_DELAY ; 0 ; Untyped ; ; E3_TIME_DELAY ; 0 ; Untyped ; ; M_TIME_DELAY ; 0 ; Untyped ; ; N_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_COUNTER ; E3 ; Untyped ; ; EXTCLK2_COUNTER ; E2 ; Untyped ; ; EXTCLK1_COUNTER ; E1 ; Untyped ; ; EXTCLK0_COUNTER ; E0 ; Untyped ; ; ENABLE0_COUNTER ; L0 ; Untyped ; ; ENABLE1_COUNTER ; L0 ; Untyped ; ; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; ; LOOP_FILTER_R ; 1.000000 ; Untyped ; ; LOOP_FILTER_C ; 5 ; Untyped ; ; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; ; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; ; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; ; VCO_POST_SCALE ; 0 ; Untyped ; ; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; INTENDED_DEVICE_FAMILY ; Cyclone II ; Untyped ; ; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK4 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK6 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK7 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK8 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK9 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ; ; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_INCLK0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ARESET ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_LOCKED ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CONFIGUPDATE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PHASEDONE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PHASESTEP ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PHASEUPDOWN ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANCLKENA ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PHASECOUNTERSELECT ; PORT_CONNECTIVITY ; Untyped ; ; M_TEST_SOURCE ; 5 ; Untyped ; ; C0_TEST_SOURCE ; 5 ; Untyped ; ; C1_TEST_SOURCE ; 5 ; Untyped ; ; C2_TEST_SOURCE ; 5 ; Untyped ; ; C3_TEST_SOURCE ; 5 ; Untyped ; ; C4_TEST_SOURCE ; 5 ; Untyped ; ; C5_TEST_SOURCE ; 5 ; Untyped ; ; C6_TEST_SOURCE ; 5 ; Untyped ; ; C7_TEST_SOURCE ; 5 ; Untyped ; ; C8_TEST_SOURCE ; 5 ; Untyped ; ; C9_TEST_SOURCE ; 5 ; Untyped ; ; CBXI_PARAMETER ; NOTHING ; Untyped ; ; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; ; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; ; WIDTH_CLOCK ; 6 ; Untyped ; ; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; ; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +-------------------------------+-------------------+---------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data ; +----------------+--------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+--------+-----------------------------------------------------------------------------------+ ; lpm_file ; UNUSED ; String ; +----------------+--------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram ; +------------------------------------+----------------------+---------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+----------------------+---------------------------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; DUAL_PORT ; Untyped ; ; WIDTH_A ; 32 ; Signed Integer ; ; WIDTHAD_A ; 10 ; Signed Integer ; ; NUMWORDS_A ; 1024 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 32 ; Signed Integer ; ; WIDTHAD_B ; 10 ; Signed Integer ; ; NUMWORDS_B ; 1024 ; Signed Integer ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Untyped ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; UNUSED ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Signed Integer ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; CBXI_PARAMETER ; altsyncram_cub1 ; Untyped ; +------------------------------------+----------------------+---------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1 ; +-------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+ ; PORT_A_ADDRESS_WIDTH ; 1 ; Untyped ; ; PORT_A_BYTE_ENABLE_MASK_WIDTH ; 1 ; Untyped ; ; PORT_A_DATA_WIDTH ; 1 ; Untyped ; ; PORT_B_ADDRESS_WIDTH ; 1 ; Untyped ; ; PORT_B_BYTE_ENABLE_MASK_WIDTH ; 1 ; Untyped ; ; PORT_B_DATA_WIDTH ; 1 ; Untyped ; +-------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag ; +----------------+----------------+-------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+----------------+-------------------------------------------------------------------------+ ; lpm_file ; ic_tag_ram.mif ; String ; +----------------+----------------+-------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram ; +------------------------------------+----------------------+-------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+----------------------+-------------------------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; DUAL_PORT ; Untyped ; ; WIDTH_A ; 20 ; Signed Integer ; ; WIDTHAD_A ; 7 ; Signed Integer ; ; NUMWORDS_A ; 128 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 20 ; Signed Integer ; ; WIDTHAD_B ; 7 ; Signed Integer ; ; NUMWORDS_B ; 128 ; Signed Integer ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Untyped ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; ic_tag_ram.mif ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Signed Integer ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; CBXI_PARAMETER ; altsyncram_73e1 ; Untyped ; +------------------------------------+----------------------+-------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht ; +----------------+-------------+----------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------------+----------------------------------------------------------------------+ ; lpm_file ; bht_ram.mif ; String ; +----------------+-------------+----------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram ; +------------------------------------+----------------------+-------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+----------------------+-------------------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; DUAL_PORT ; Untyped ; ; WIDTH_A ; 2 ; Signed Integer ; ; WIDTHAD_A ; 8 ; Signed Integer ; ; NUMWORDS_A ; 256 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 2 ; Signed Integer ; ; WIDTHAD_B ; 8 ; Signed Integer ; ; NUMWORDS_B ; 256 ; Signed Integer ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Untyped ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; bht_ram.mif ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Signed Integer ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; CBXI_PARAMETER ; altsyncram_4nd1 ; Untyped ; +------------------------------------+----------------------+-------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_4nd1:auto_generated|altsyncram_3um1:altsyncram1 ; +-------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ ; PORT_A_ADDRESS_WIDTH ; 1 ; Untyped ; ; PORT_A_BYTE_ENABLE_MASK_WIDTH ; 1 ; Untyped ; ; PORT_A_DATA_WIDTH ; 1 ; Untyped ; ; PORT_B_ADDRESS_WIDTH ; 1 ; Untyped ; ; PORT_B_BYTE_ENABLE_MASK_WIDTH ; 1 ; Untyped ; ; PORT_B_DATA_WIDTH ; 1 ; Untyped ; +-------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a ; +----------------+--------------+---------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+--------------+---------------------------------------------------------------------------------------------+ ; lpm_file ; rf_ram_a.mif ; String ; +----------------+--------------+---------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram ; +------------------------------------+----------------------+-------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+----------------------+-------------------------------------------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; DUAL_PORT ; Untyped ; ; WIDTH_A ; 32 ; Signed Integer ; ; WIDTHAD_A ; 5 ; Signed Integer ; ; NUMWORDS_A ; 32 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 32 ; Signed Integer ; ; WIDTHAD_B ; 5 ; Signed Integer ; ; NUMWORDS_B ; 32 ; Signed Integer ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Untyped ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; rf_ram_a.mif ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Signed Integer ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; CBXI_PARAMETER ; altsyncram_epd1 ; Untyped ; +------------------------------------+----------------------+-------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b ; +----------------+--------------+---------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+--------------+---------------------------------------------------------------------------------------------+ ; lpm_file ; rf_ram_b.mif ; String ; +----------------+--------------+---------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram ; +------------------------------------+----------------------+-------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+----------------------+-------------------------------------------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; DUAL_PORT ; Untyped ; ; WIDTH_A ; 32 ; Signed Integer ; ; WIDTHAD_A ; 5 ; Signed Integer ; ; NUMWORDS_A ; 32 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 32 ; Signed Integer ; ; WIDTHAD_B ; 5 ; Signed Integer ; ; NUMWORDS_B ; 32 ; Signed Integer ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Untyped ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; rf_ram_b.mif ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Signed Integer ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; CBXI_PARAMETER ; altsyncram_fpd1 ; Untyped ; +------------------------------------+----------------------+-------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag ; +----------------+----------------+-------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+----------------+-------------------------------------------------------------------------+ ; lpm_file ; dc_tag_ram.mif ; String ; +----------------+----------------+-------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram ; +------------------------------------+----------------------+-------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+----------------------+-------------------------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; ; WIDTH_A ; 15 ; Signed Integer ; ; WIDTHAD_A ; 9 ; Signed Integer ; ; NUMWORDS_A ; 512 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 15 ; Signed Integer ; ; WIDTHAD_B ; 9 ; Signed Integer ; ; NUMWORDS_B ; 512 ; Signed Integer ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Untyped ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; dc_tag_ram.mif ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; CBXI_PARAMETER ; altsyncram_9u12 ; Untyped ; +------------------------------------+----------------------+-------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data ; +----------------+--------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+--------+-----------------------------------------------------------------------------------+ ; lpm_file ; UNUSED ; String ; +----------------+--------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram ; +------------------------------------+----------------------+---------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+----------------------+---------------------------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; ; WIDTH_A ; 32 ; Signed Integer ; ; WIDTHAD_A ; 9 ; Signed Integer ; ; NUMWORDS_A ; 512 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 32 ; Signed Integer ; ; WIDTHAD_B ; 9 ; Signed Integer ; ; NUMWORDS_B ; 512 ; Signed Integer ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Untyped ; ; WIDTH_BYTEENA_B ; 4 ; Signed Integer ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; UNUSED ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; CBXI_PARAMETER ; altsyncram_a422 ; Untyped ; +------------------------------------+----------------------+---------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1 ; +---------------------------------------+-------------------+-------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +---------------------------------------+-------------------+-------------------------------------------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; ACCUM_DIRECTION ; ADD ; Untyped ; ; ACCUM_SLOAD_ACLR ; ACLR3 ; Untyped ; ; ACCUM_SLOAD_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; ACCUM_SLOAD_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; ACCUM_SLOAD_REGISTER ; CLOCK0 ; Untyped ; ; ACCUMULATOR ; NO ; Untyped ; ; ADDER1_ROUNDING ; NO ; Untyped ; ; ADDER3_ROUNDING ; NO ; Untyped ; ; ADDNSUB1_ROUND_ACLR ; ACLR3 ; Untyped ; ; ADDNSUB1_ROUND_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; ADDNSUB1_ROUND_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; ADDNSUB1_ROUND_REGISTER ; CLOCK0 ; Untyped ; ; ADDNSUB3_ROUND_ACLR ; ACLR3 ; Untyped ; ; ADDNSUB3_ROUND_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; ADDNSUB3_ROUND_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; ADDNSUB3_ROUND_REGISTER ; CLOCK0 ; Untyped ; ; ADDNSUB_MULTIPLIER_ACLR1 ; ACLR3 ; Untyped ; ; ADDNSUB_MULTIPLIER_ACLR3 ; ACLR3 ; Untyped ; ; ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 ; ACLR0 ; Untyped ; ; ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 ; ACLR3 ; Untyped ; ; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 ; CLOCK0 ; Untyped ; ; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 ; CLOCK0 ; Untyped ; ; ADDNSUB_MULTIPLIER_REGISTER1 ; UNREGISTERED ; Untyped ; ; ADDNSUB_MULTIPLIER_REGISTER3 ; CLOCK0 ; Untyped ; ; CHAINOUT_ACLR ; ACLR3 ; Untyped ; ; CHAINOUT_ADDER ; NO ; Untyped ; ; CHAINOUT_REGISTER ; CLOCK0 ; Untyped ; ; CHAINOUT_ROUND_ACLR ; ACLR3 ; Untyped ; ; CHAINOUT_ROUND_OUTPUT_ACLR ; ACLR3 ; Untyped ; ; CHAINOUT_ROUND_OUTPUT_REGISTER ; CLOCK0 ; Untyped ; ; CHAINOUT_ROUND_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; CHAINOUT_ROUND_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; CHAINOUT_ROUND_REGISTER ; CLOCK0 ; Untyped ; ; CHAINOUT_ROUNDING ; NO ; Untyped ; ; CHAINOUT_SATURATE_ACLR ; ACLR3 ; Untyped ; ; CHAINOUT_SATURATE_OUTPUT_ACLR ; ACLR3 ; Untyped ; ; CHAINOUT_SATURATE_OUTPUT_REGISTER ; CLOCK0 ; Untyped ; ; CHAINOUT_SATURATE_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; CHAINOUT_SATURATE_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; CHAINOUT_SATURATE_REGISTER ; CLOCK0 ; Untyped ; ; CHAINOUT_SATURATION ; NO ; Untyped ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; YES ; Untyped ; ; DSP_BLOCK_BALANCING ; AUTO ; Untyped ; ; EXTRA_LATENCY ; 0 ; Untyped ; ; INPUT_ACLR_A0 ; ACLR3 ; Untyped ; ; INPUT_ACLR_A1 ; ACLR3 ; Untyped ; ; INPUT_ACLR_A2 ; ACLR3 ; Untyped ; ; INPUT_ACLR_A3 ; ACLR3 ; Untyped ; ; INPUT_ACLR_B0 ; ACLR3 ; Untyped ; ; INPUT_ACLR_B1 ; ACLR3 ; Untyped ; ; INPUT_ACLR_B2 ; ACLR3 ; Untyped ; ; INPUT_ACLR_B3 ; ACLR3 ; Untyped ; ; INPUT_REGISTER_A0 ; UNREGISTERED ; Untyped ; ; INPUT_REGISTER_A1 ; CLOCK0 ; Untyped ; ; INPUT_REGISTER_A2 ; CLOCK0 ; Untyped ; ; INPUT_REGISTER_A3 ; CLOCK0 ; Untyped ; ; INPUT_REGISTER_B0 ; UNREGISTERED ; Untyped ; ; INPUT_REGISTER_B1 ; CLOCK0 ; Untyped ; ; INPUT_REGISTER_B2 ; CLOCK0 ; Untyped ; ; INPUT_REGISTER_B3 ; CLOCK0 ; Untyped ; ; INPUT_SOURCE_A0 ; DATAA ; Untyped ; ; INPUT_SOURCE_A1 ; DATAA ; Untyped ; ; INPUT_SOURCE_A2 ; DATAA ; Untyped ; ; INPUT_SOURCE_A3 ; DATAA ; Untyped ; ; INPUT_SOURCE_B0 ; DATAB ; Untyped ; ; INPUT_SOURCE_B1 ; DATAB ; Untyped ; ; INPUT_SOURCE_B2 ; DATAB ; Untyped ; ; INPUT_SOURCE_B3 ; DATAB ; Untyped ; ; MULT01_ROUND_ACLR ; ACLR3 ; Untyped ; ; MULT01_ROUND_REGISTER ; CLOCK0 ; Untyped ; ; MULT01_SATURATION_ACLR ; ACLR2 ; Untyped ; ; MULT01_SATURATION_REGISTER ; CLOCK0 ; Untyped ; ; MULT23_ROUND_ACLR ; ACLR3 ; Untyped ; ; MULT23_ROUND_REGISTER ; CLOCK0 ; Untyped ; ; MULT23_SATURATION_ACLR ; ACLR3 ; Untyped ; ; MULT23_SATURATION_REGISTER ; CLOCK0 ; Untyped ; ; MULTIPLIER01_ROUNDING ; NO ; Untyped ; ; MULTIPLIER01_SATURATION ; NO ; Untyped ; ; MULTIPLIER1_DIRECTION ; ADD ; Untyped ; ; MULTIPLIER23_ROUNDING ; NO ; Untyped ; ; MULTIPLIER23_SATURATION ; NO ; Untyped ; ; MULTIPLIER3_DIRECTION ; ADD ; Untyped ; ; MULTIPLIER_ACLR0 ; ACLR0 ; Untyped ; ; MULTIPLIER_ACLR1 ; ACLR3 ; Untyped ; ; MULTIPLIER_ACLR2 ; ACLR3 ; Untyped ; ; MULTIPLIER_ACLR3 ; ACLR3 ; Untyped ; ; MULTIPLIER_REGISTER0 ; CLOCK0 ; Untyped ; ; MULTIPLIER_REGISTER1 ; CLOCK0 ; Untyped ; ; MULTIPLIER_REGISTER2 ; CLOCK0 ; Untyped ; ; MULTIPLIER_REGISTER3 ; CLOCK0 ; Untyped ; ; NUMBER_OF_MULTIPLIERS ; 1 ; Signed Integer ; ; OUTPUT_ACLR ; ACLR3 ; Untyped ; ; OUTPUT_REGISTER ; UNREGISTERED ; Untyped ; ; OUTPUT_ROUND_ACLR ; ACLR3 ; Untyped ; ; OUTPUT_ROUND_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; OUTPUT_ROUND_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; OUTPUT_ROUND_REGISTER ; CLOCK0 ; Untyped ; ; OUTPUT_ROUND_TYPE ; NEAREST_INTEGER ; Untyped ; ; OUTPUT_ROUNDING ; NO ; Untyped ; ; OUTPUT_SATURATE_ACLR ; ACLR3 ; Untyped ; ; OUTPUT_SATURATE_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; OUTPUT_SATURATE_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; OUTPUT_SATURATE_REGISTER ; CLOCK0 ; Untyped ; ; OUTPUT_SATURATE_TYPE ; ASYMMETRIC ; Untyped ; ; OUTPUT_SATURATION ; NO ; Untyped ; ; port_addnsub1 ; PORT_UNUSED ; Untyped ; ; port_addnsub3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CHAINOUT_SAT_IS_OVERFLOW ; PORT_UNUSED ; Untyped ; ; PORT_MULT0_IS_SATURATED ; UNUSED ; Untyped ; ; PORT_MULT1_IS_SATURATED ; UNUSED ; Untyped ; ; PORT_MULT2_IS_SATURATED ; UNUSED ; Untyped ; ; PORT_MULT3_IS_SATURATED ; UNUSED ; Untyped ; ; PORT_OUTPUT_IS_OVERFLOW ; PORT_UNUSED ; Untyped ; ; port_signa ; PORT_UNUSED ; Untyped ; ; port_signb ; PORT_UNUSED ; Untyped ; ; REPRESENTATION_A ; UNSIGNED ; Untyped ; ; REPRESENTATION_B ; UNSIGNED ; Untyped ; ; ROTATE_ACLR ; ACLR3 ; Untyped ; ; ROTATE_OUTPUT_ACLR ; ACLR3 ; Untyped ; ; ROTATE_OUTPUT_REGISTER ; CLOCK0 ; Untyped ; ; ROTATE_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; ROTATE_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; ROTATE_REGISTER ; CLOCK0 ; Untyped ; ; WIDTH_MSB ; 17 ; Untyped ; ; WIDTH_SATURATE_SIGN ; 1 ; Untyped ; ; SCANOUTA_ACLR ; ACLR3 ; Untyped ; ; SCANOUTA_REGISTER ; UNREGISTERED ; Untyped ; ; SHIFT_MODE ; NO ; Untyped ; ; SHIFT_RIGHT_ACLR ; ACLR3 ; Untyped ; ; SHIFT_RIGHT_OUTPUT_ACLR ; ACLR3 ; Untyped ; ; SHIFT_RIGHT_OUTPUT_REGISTER ; CLOCK0 ; Untyped ; ; SHIFT_RIGHT_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; SHIFT_RIGHT_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; SHIFT_RIGHT_REGISTER ; CLOCK0 ; Untyped ; ; SIGNED_ACLR_A ; ACLR3 ; Untyped ; ; SIGNED_ACLR_B ; ACLR3 ; Untyped ; ; SIGNED_PIPELINE_ACLR_A ; ACLR0 ; Untyped ; ; SIGNED_PIPELINE_ACLR_B ; ACLR0 ; Untyped ; ; SIGNED_PIPELINE_REGISTER_A ; CLOCK0 ; Untyped ; ; SIGNED_PIPELINE_REGISTER_B ; CLOCK0 ; Untyped ; ; SIGNED_REGISTER_A ; UNREGISTERED ; Untyped ; ; SIGNED_REGISTER_B ; UNREGISTERED ; Untyped ; ; WIDTH_A ; 16 ; Signed Integer ; ; WIDTH_B ; 16 ; Signed Integer ; ; WIDTH_CHAININ ; 1 ; Untyped ; ; WIDTH_RESULT ; 32 ; Signed Integer ; ; ZERO_CHAINOUT_OUTPUT_ACLR ; ACLR3 ; Untyped ; ; ZERO_CHAINOUT_OUTPUT_REGISTER ; CLOCK0 ; Untyped ; ; ZERO_LOOPBACK_ACLR ; ACLR3 ; Untyped ; ; ZERO_LOOPBACK_OUTPUT_ACLR ; ACLR3 ; Untyped ; ; ZERO_LOOPBACK_OUTPUT_REGISTER ; CLOCK0 ; Untyped ; ; ZERO_LOOPBACK_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; ZERO_LOOPBACK_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; ZERO_LOOPBACK_REGISTER ; CLOCK0 ; Untyped ; ; CBXI_PARAMETER ; mult_add_4cr2 ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; +---------------------------------------+-------------------+-------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1 ; +----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; dataa_width ; 0 ; Untyped ; +----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2 ; +---------------------------------------+-------------------+-------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +---------------------------------------+-------------------+-------------------------------------------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; ACCUM_DIRECTION ; ADD ; Untyped ; ; ACCUM_SLOAD_ACLR ; ACLR3 ; Untyped ; ; ACCUM_SLOAD_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; ACCUM_SLOAD_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; ACCUM_SLOAD_REGISTER ; CLOCK0 ; Untyped ; ; ACCUMULATOR ; NO ; Untyped ; ; ADDER1_ROUNDING ; NO ; Untyped ; ; ADDER3_ROUNDING ; NO ; Untyped ; ; ADDNSUB1_ROUND_ACLR ; ACLR3 ; Untyped ; ; ADDNSUB1_ROUND_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; ADDNSUB1_ROUND_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; ADDNSUB1_ROUND_REGISTER ; CLOCK0 ; Untyped ; ; ADDNSUB3_ROUND_ACLR ; ACLR3 ; Untyped ; ; ADDNSUB3_ROUND_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; ADDNSUB3_ROUND_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; ADDNSUB3_ROUND_REGISTER ; CLOCK0 ; Untyped ; ; ADDNSUB_MULTIPLIER_ACLR1 ; ACLR3 ; Untyped ; ; ADDNSUB_MULTIPLIER_ACLR3 ; ACLR3 ; Untyped ; ; ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 ; ACLR0 ; Untyped ; ; ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 ; ACLR3 ; Untyped ; ; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 ; CLOCK0 ; Untyped ; ; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 ; CLOCK0 ; Untyped ; ; ADDNSUB_MULTIPLIER_REGISTER1 ; UNREGISTERED ; Untyped ; ; ADDNSUB_MULTIPLIER_REGISTER3 ; CLOCK0 ; Untyped ; ; CHAINOUT_ACLR ; ACLR3 ; Untyped ; ; CHAINOUT_ADDER ; NO ; Untyped ; ; CHAINOUT_REGISTER ; CLOCK0 ; Untyped ; ; CHAINOUT_ROUND_ACLR ; ACLR3 ; Untyped ; ; CHAINOUT_ROUND_OUTPUT_ACLR ; ACLR3 ; Untyped ; ; CHAINOUT_ROUND_OUTPUT_REGISTER ; CLOCK0 ; Untyped ; ; CHAINOUT_ROUND_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; CHAINOUT_ROUND_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; CHAINOUT_ROUND_REGISTER ; CLOCK0 ; Untyped ; ; CHAINOUT_ROUNDING ; NO ; Untyped ; ; CHAINOUT_SATURATE_ACLR ; ACLR3 ; Untyped ; ; CHAINOUT_SATURATE_OUTPUT_ACLR ; ACLR3 ; Untyped ; ; CHAINOUT_SATURATE_OUTPUT_REGISTER ; CLOCK0 ; Untyped ; ; CHAINOUT_SATURATE_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; CHAINOUT_SATURATE_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; CHAINOUT_SATURATE_REGISTER ; CLOCK0 ; Untyped ; ; CHAINOUT_SATURATION ; NO ; Untyped ; ; DEDICATED_MULTIPLIER_CIRCUITRY ; YES ; Untyped ; ; DSP_BLOCK_BALANCING ; AUTO ; Untyped ; ; EXTRA_LATENCY ; 0 ; Untyped ; ; INPUT_ACLR_A0 ; ACLR3 ; Untyped ; ; INPUT_ACLR_A1 ; ACLR3 ; Untyped ; ; INPUT_ACLR_A2 ; ACLR3 ; Untyped ; ; INPUT_ACLR_A3 ; ACLR3 ; Untyped ; ; INPUT_ACLR_B0 ; ACLR3 ; Untyped ; ; INPUT_ACLR_B1 ; ACLR3 ; Untyped ; ; INPUT_ACLR_B2 ; ACLR3 ; Untyped ; ; INPUT_ACLR_B3 ; ACLR3 ; Untyped ; ; INPUT_REGISTER_A0 ; UNREGISTERED ; Untyped ; ; INPUT_REGISTER_A1 ; CLOCK0 ; Untyped ; ; INPUT_REGISTER_A2 ; CLOCK0 ; Untyped ; ; INPUT_REGISTER_A3 ; CLOCK0 ; Untyped ; ; INPUT_REGISTER_B0 ; UNREGISTERED ; Untyped ; ; INPUT_REGISTER_B1 ; CLOCK0 ; Untyped ; ; INPUT_REGISTER_B2 ; CLOCK0 ; Untyped ; ; INPUT_REGISTER_B3 ; CLOCK0 ; Untyped ; ; INPUT_SOURCE_A0 ; DATAA ; Untyped ; ; INPUT_SOURCE_A1 ; DATAA ; Untyped ; ; INPUT_SOURCE_A2 ; DATAA ; Untyped ; ; INPUT_SOURCE_A3 ; DATAA ; Untyped ; ; INPUT_SOURCE_B0 ; DATAB ; Untyped ; ; INPUT_SOURCE_B1 ; DATAB ; Untyped ; ; INPUT_SOURCE_B2 ; DATAB ; Untyped ; ; INPUT_SOURCE_B3 ; DATAB ; Untyped ; ; MULT01_ROUND_ACLR ; ACLR3 ; Untyped ; ; MULT01_ROUND_REGISTER ; CLOCK0 ; Untyped ; ; MULT01_SATURATION_ACLR ; ACLR2 ; Untyped ; ; MULT01_SATURATION_REGISTER ; CLOCK0 ; Untyped ; ; MULT23_ROUND_ACLR ; ACLR3 ; Untyped ; ; MULT23_ROUND_REGISTER ; CLOCK0 ; Untyped ; ; MULT23_SATURATION_ACLR ; ACLR3 ; Untyped ; ; MULT23_SATURATION_REGISTER ; CLOCK0 ; Untyped ; ; MULTIPLIER01_ROUNDING ; NO ; Untyped ; ; MULTIPLIER01_SATURATION ; NO ; Untyped ; ; MULTIPLIER1_DIRECTION ; ADD ; Untyped ; ; MULTIPLIER23_ROUNDING ; NO ; Untyped ; ; MULTIPLIER23_SATURATION ; NO ; Untyped ; ; MULTIPLIER3_DIRECTION ; ADD ; Untyped ; ; MULTIPLIER_ACLR0 ; ACLR0 ; Untyped ; ; MULTIPLIER_ACLR1 ; ACLR3 ; Untyped ; ; MULTIPLIER_ACLR2 ; ACLR3 ; Untyped ; ; MULTIPLIER_ACLR3 ; ACLR3 ; Untyped ; ; MULTIPLIER_REGISTER0 ; CLOCK0 ; Untyped ; ; MULTIPLIER_REGISTER1 ; CLOCK0 ; Untyped ; ; MULTIPLIER_REGISTER2 ; CLOCK0 ; Untyped ; ; MULTIPLIER_REGISTER3 ; CLOCK0 ; Untyped ; ; NUMBER_OF_MULTIPLIERS ; 1 ; Signed Integer ; ; OUTPUT_ACLR ; ACLR3 ; Untyped ; ; OUTPUT_REGISTER ; UNREGISTERED ; Untyped ; ; OUTPUT_ROUND_ACLR ; ACLR3 ; Untyped ; ; OUTPUT_ROUND_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; OUTPUT_ROUND_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; OUTPUT_ROUND_REGISTER ; CLOCK0 ; Untyped ; ; OUTPUT_ROUND_TYPE ; NEAREST_INTEGER ; Untyped ; ; OUTPUT_ROUNDING ; NO ; Untyped ; ; OUTPUT_SATURATE_ACLR ; ACLR3 ; Untyped ; ; OUTPUT_SATURATE_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; OUTPUT_SATURATE_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; OUTPUT_SATURATE_REGISTER ; CLOCK0 ; Untyped ; ; OUTPUT_SATURATE_TYPE ; ASYMMETRIC ; Untyped ; ; OUTPUT_SATURATION ; NO ; Untyped ; ; port_addnsub1 ; PORT_UNUSED ; Untyped ; ; port_addnsub3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CHAINOUT_SAT_IS_OVERFLOW ; PORT_UNUSED ; Untyped ; ; PORT_MULT0_IS_SATURATED ; UNUSED ; Untyped ; ; PORT_MULT1_IS_SATURATED ; UNUSED ; Untyped ; ; PORT_MULT2_IS_SATURATED ; UNUSED ; Untyped ; ; PORT_MULT3_IS_SATURATED ; UNUSED ; Untyped ; ; PORT_OUTPUT_IS_OVERFLOW ; PORT_UNUSED ; Untyped ; ; port_signa ; PORT_UNUSED ; Untyped ; ; port_signb ; PORT_UNUSED ; Untyped ; ; REPRESENTATION_A ; UNSIGNED ; Untyped ; ; REPRESENTATION_B ; UNSIGNED ; Untyped ; ; ROTATE_ACLR ; ACLR3 ; Untyped ; ; ROTATE_OUTPUT_ACLR ; ACLR3 ; Untyped ; ; ROTATE_OUTPUT_REGISTER ; CLOCK0 ; Untyped ; ; ROTATE_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; ROTATE_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; ROTATE_REGISTER ; CLOCK0 ; Untyped ; ; WIDTH_MSB ; 17 ; Untyped ; ; WIDTH_SATURATE_SIGN ; 1 ; Untyped ; ; SCANOUTA_ACLR ; ACLR3 ; Untyped ; ; SCANOUTA_REGISTER ; UNREGISTERED ; Untyped ; ; SHIFT_MODE ; NO ; Untyped ; ; SHIFT_RIGHT_ACLR ; ACLR3 ; Untyped ; ; SHIFT_RIGHT_OUTPUT_ACLR ; ACLR3 ; Untyped ; ; SHIFT_RIGHT_OUTPUT_REGISTER ; CLOCK0 ; Untyped ; ; SHIFT_RIGHT_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; SHIFT_RIGHT_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; SHIFT_RIGHT_REGISTER ; CLOCK0 ; Untyped ; ; SIGNED_ACLR_A ; ACLR3 ; Untyped ; ; SIGNED_ACLR_B ; ACLR3 ; Untyped ; ; SIGNED_PIPELINE_ACLR_A ; ACLR0 ; Untyped ; ; SIGNED_PIPELINE_ACLR_B ; ACLR0 ; Untyped ; ; SIGNED_PIPELINE_REGISTER_A ; CLOCK0 ; Untyped ; ; SIGNED_PIPELINE_REGISTER_B ; CLOCK0 ; Untyped ; ; SIGNED_REGISTER_A ; UNREGISTERED ; Untyped ; ; SIGNED_REGISTER_B ; UNREGISTERED ; Untyped ; ; WIDTH_A ; 16 ; Signed Integer ; ; WIDTH_B ; 16 ; Signed Integer ; ; WIDTH_CHAININ ; 1 ; Untyped ; ; WIDTH_RESULT ; 16 ; Signed Integer ; ; ZERO_CHAINOUT_OUTPUT_ACLR ; ACLR3 ; Untyped ; ; ZERO_CHAINOUT_OUTPUT_REGISTER ; CLOCK0 ; Untyped ; ; ZERO_LOOPBACK_ACLR ; ACLR3 ; Untyped ; ; ZERO_LOOPBACK_OUTPUT_ACLR ; ACLR3 ; Untyped ; ; ZERO_LOOPBACK_OUTPUT_REGISTER ; CLOCK0 ; Untyped ; ; ZERO_LOOPBACK_PIPELINE_ACLR ; ACLR3 ; Untyped ; ; ZERO_LOOPBACK_PIPELINE_REGISTER ; CLOCK0 ; Untyped ; ; ZERO_LOOPBACK_REGISTER ; CLOCK0 ; Untyped ; ; CBXI_PARAMETER ; mult_add_6cr2 ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; +---------------------------------------+-------------------+-------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1 ; +----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; dataa_width ; 0 ; Untyped ; +----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component ; +----------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; lpm_file ; cpu_0_ociram_default_contents.mif ; String ; +----------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram ; +------------------------------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; ; WIDTH_A ; 32 ; Signed Integer ; ; WIDTHAD_A ; 8 ; Signed Integer ; ; NUMWORDS_A ; 256 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 32 ; Signed Integer ; ; WIDTHAD_B ; 8 ; Signed Integer ; ; NUMWORDS_B ; 256 ; Signed Integer ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 4 ; Signed Integer ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; cpu_0_ociram_default_contents.mif ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; CBXI_PARAMETER ; altsyncram_c572 ; Untyped ; +------------------------------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component ; +----------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; lpm_file ; UNUSED ; String ; +----------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram ; +------------------------------------+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; ; WIDTH_A ; 36 ; Signed Integer ; ; WIDTHAD_A ; 7 ; Signed Integer ; ; NUMWORDS_A ; 128 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 36 ; Signed Integer ; ; WIDTHAD_B ; 7 ; Signed Integer ; ; NUMWORDS_B ; 128 ; Signed Integer ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Untyped ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; UNUSED ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; CBXI_PARAMETER ; altsyncram_e502 ; Untyped ; +------------------------------------+----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1 ; +----------------+-----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; SLD_NODE_INFO ; 286279168 ; Signed Integer ; +----------------+-----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom ; +------------------------------------+------------------------------+---------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+------------------------------+---------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; ROM ; Untyped ; ; WIDTH_A ; 32 ; Signed Integer ; ; WIDTHAD_A ; 7 ; Signed Integer ; ; NUMWORDS_A ; 128 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 1 ; Untyped ; ; WIDTHAD_B ; 1 ; Untyped ; ; NUMWORDS_B ; 1 ; Untyped ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Untyped ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Signed Integer ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; epcs_controller_boot_rom.hex ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; CBXI_PARAMETER ; altsyncram_lo31 ; Untyped ; +------------------------------------+------------------------------+---------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo ; +-------------------------+-------------+---------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------+-------------+---------------------------------------------------------------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; lpm_width ; 8 ; Signed Integer ; ; LPM_NUMWORDS ; 64 ; Signed Integer ; ; LPM_WIDTHU ; 6 ; Signed Integer ; ; LPM_SHOWAHEAD ; OFF ; Untyped ; ; UNDERFLOW_CHECKING ; OFF ; Untyped ; ; OVERFLOW_CHECKING ; OFF ; Untyped ; ; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; ; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; ; ALMOST_FULL_VALUE ; 0 ; Untyped ; ; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; ; USE_EAB ; ON ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; ; CBXI_PARAMETER ; scfifo_1n21 ; Untyped ; +-------------------------+-------------+---------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 ; +-------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; PORT_A_ADDRESS_WIDTH ; 1 ; Untyped ; ; PORT_A_BYTE_ENABLE_MASK_WIDTH ; 1 ; Untyped ; ; PORT_A_DATA_WIDTH ; 1 ; Untyped ; ; PORT_B_ADDRESS_WIDTH ; 1 ; Untyped ; ; PORT_B_BYTE_ENABLE_MASK_WIDTH ; 1 ; Untyped ; ; PORT_B_DATA_WIDTH ; 1 ; Untyped ; +-------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo ; +-------------------------+-------------+---------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------+-------------+---------------------------------------------------------------------------------------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; lpm_width ; 8 ; Signed Integer ; ; LPM_NUMWORDS ; 64 ; Signed Integer ; ; LPM_WIDTHU ; 6 ; Signed Integer ; ; LPM_SHOWAHEAD ; OFF ; Untyped ; ; UNDERFLOW_CHECKING ; OFF ; Untyped ; ; OVERFLOW_CHECKING ; OFF ; Untyped ; ; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; ; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; ; ALMOST_FULL_VALUE ; 0 ; Untyped ; ; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; ; USE_EAB ; ON ; Untyped ; ; MAXIMIZE_SPEED ; 5 ; Untyped ; ; DEVICE_FAMILY ; Cyclone II ; Untyped ; ; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; ; CBXI_PARAMETER ; scfifo_1n21 ; Untyped ; +-------------------------+-------------+---------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 ; +-------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; PORT_A_ADDRESS_WIDTH ; 1 ; Untyped ; ; PORT_A_BYTE_ENABLE_MASK_WIDTH ; 1 ; Untyped ; ; PORT_A_DATA_WIDTH ; 1 ; Untyped ; ; PORT_B_ADDRESS_WIDTH ; 1 ; Untyped ; ; PORT_B_BYTE_ENABLE_MASK_WIDTH ; 1 ; Untyped ; ; PORT_B_DATA_WIDTH ; 1 ; Untyped ; +-------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic ; +-------------------+----------------------------------+-------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------+----------------------------------+-------------------------------------------------------------------------------+ ; INSTANCE_ID ; 0 ; Signed Integer ; ; SLD_NODE_INFO ; 00001100000000000110111000000000 ; Unsigned Binary ; ; LOG2_TXFIFO_DEPTH ; 6 ; Signed Integer ; ; LOG2_RXFIFO_DEPTH ; 6 ; Signed Integer ; ; RESERVED ; 0 ; Signed Integer ; ; DATA_WIDTH ; 8 ; Signed Integer ; ; NODE_IR_WIDTH ; 1 ; Signed Integer ; ; SCAN_LENGTH ; 11 ; Signed Integer ; +-------------------+----------------------------------+-------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst ; +--------------------------+------------------------------------------------------------------+-----------------+ ; Parameter Name ; Value ; Type ; +--------------------------+------------------------------------------------------------------+-----------------+ ; sld_hub_ip_version ; 1 ; Untyped ; ; sld_hub_ip_minor_version ; 3 ; Untyped ; ; sld_common_ip_version ; 0 ; Untyped ; ; device_family ; Cyclone II ; Untyped ; ; n_nodes ; 2 ; Untyped ; ; n_sel_bits ; 2 ; Untyped ; ; n_node_ir_bits ; 5 ; Untyped ; ; node_info ; 0000110000000000011011100000000000010001000100000100011000000000 ; Unsigned Binary ; ; compilation_mode ; 0 ; Untyped ; +--------------------------+------------------------------------------------------------------+-----------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------------------+ ; altmult_add Parameter Settings by Entity Instance ; +---------------------------------------+----------------------------------------------------------------------------------------------------+ ; Name ; Value ; +---------------------------------------+----------------------------------------------------------------------------------------------------+ ; Number of entity instances ; 2 ; ; Entity Instance ; system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1 ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES ; ; -- NUMBER_OF_MULTIPLIERS ; 1 ; ; -- port_signa ; PORT_UNUSED ; ; -- port_signb ; PORT_UNUSED ; ; -- REPRESENTATION_A ; UNSIGNED ; ; -- REPRESENTATION_B ; UNSIGNED ; ; -- WIDTH_A ; 16 ; ; -- WIDTH_B ; 16 ; ; -- WIDTH_RESULT ; 32 ; ; Entity Instance ; system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2 ; ; -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES ; ; -- NUMBER_OF_MULTIPLIERS ; 1 ; ; -- port_signa ; PORT_UNUSED ; ; -- port_signb ; PORT_UNUSED ; ; -- REPRESENTATION_A ; UNSIGNED ; ; -- REPRESENTATION_B ; UNSIGNED ; ; -- WIDTH_A ; 16 ; ; -- WIDTH_B ; 16 ; ; -- WIDTH_RESULT ; 16 ; +---------------------------------------+----------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------+ ; scfifo Parameter Settings by Entity Instance ; +----------------------------+----------------------------------------------------------------------------------------------------+ ; Name ; Value ; +----------------------------+----------------------------------------------------------------------------------------------------+ ; Number of entity instances ; 2 ; ; Entity Instance ; system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo ; ; -- FIFO Type ; Single Clock ; ; -- lpm_width ; 8 ; ; -- LPM_NUMWORDS ; 64 ; ; -- LPM_SHOWAHEAD ; OFF ; ; -- USE_EAB ; ON ; ; Entity Instance ; system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo ; ; -- FIFO Type ; Single Clock ; ; -- lpm_width ; 8 ; ; -- LPM_NUMWORDS ; 64 ; ; -- LPM_SHOWAHEAD ; OFF ; ; -- USE_EAB ; ON ; +----------------------------+----------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis INI Usage ; +----------------------+--------------------------------------------------------------------------------------------------------------------+ ; Option ; Usage ; +----------------------+--------------------------------------------------------------------------------------------------------------------+ ; Initialization file: ; c:/altera/71/quartus/bin/quartus.ini ; ; dev_password ; e81f0e65b8afc1da24522b894c886f598ff5e3fafae3453dd1029e508011004342234235215526025211557545361520042000410042555455 ; +----------------------+--------------------------------------------------------------------------------------------------------------------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version Info: Processing started: Thu Aug 30 15:44:30 2007 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE1_NIOS -c DE1_NIOS Info: Found 29 design units, including 29 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0.v Info: Found entity 1: cpu_0_ic_data_module Info: Found entity 2: cpu_0_ic_tag_module Info: Found entity 3: cpu_0_bht_module Info: Found entity 4: cpu_0_register_bank_a_module Info: Found entity 5: cpu_0_register_bank_b_module Info: Found entity 6: cpu_0_dc_tag_module Info: Found entity 7: cpu_0_dc_data_module Info: Found entity 8: cpu_0_nios2_oci_debug Info: Found entity 9: cpu_0_ociram_lpm_dram_bdp_component_module Info: Found entity 10: cpu_0_nios2_ocimem Info: Found entity 11: cpu_0_nios2_avalon_reg Info: Found entity 12: cpu_0_nios2_oci_break Info: Found entity 13: cpu_0_nios2_oci_xbrk Info: Found entity 14: cpu_0_nios2_oci_match_paired Info: Found entity 15: cpu_0_nios2_oci_match_single Info: Found entity 16: cpu_0_nios2_oci_dbrk Info: Found entity 17: cpu_0_nios2_oci_itrace Info: Found entity 18: cpu_0_nios2_oci_td_mode Info: Found entity 19: cpu_0_nios2_oci_dtrace Info: Found entity 20: cpu_0_nios2_oci_compute_tm_count Info: Found entity 21: cpu_0_nios2_oci_fifowp_inc Info: Found entity 22: cpu_0_nios2_oci_fifocount_inc Info: Found entity 23: cpu_0_nios2_oci_fifo Info: Found entity 24: cpu_0_nios2_oci_pib Info: Found entity 25: cpu_0_traceram_lpm_dram_bdp_component_module Info: Found entity 26: cpu_0_nios2_oci_im Info: Found entity 27: cpu_0_nios2_performance_monitors Info: Found entity 28: cpu_0_nios2_oci Info: Found entity 29: cpu_0 Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module.v Info: Found entity 1: cpu_0_jtag_debug_module Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_jtag_debug_module_wrapper.v Info: Found entity 1: cpu_0_jtag_debug_module_wrapper Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_mult_cell.v Info: Found entity 1: cpu_0_mult_cell Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/cpu_0_test_bench.v Info: Found entity 1: cpu_0_test_bench Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.v Info: Found entity 1: DE1_NIOS Info: Found 3 design units, including 3 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/epcs_controller.v Info: Found entity 1: epcs_controller_sub Info: Found entity 2: tornado_epcs_controller_atom Info: Found entity 3: epcs_controller Info: Found 7 design units, including 7 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/jtag_uart_0.v Info: Found entity 1: jtag_uart_0_log_module Info: Found entity 2: jtag_uart_0_sim_scfifo_w Info: Found entity 3: jtag_uart_0_scfifo_w Info: Found entity 4: jtag_uart_0_drom_module Info: Found entity 5: jtag_uart_0_sim_scfifo_r Info: Found entity 6: jtag_uart_0_scfifo_r Info: Found entity 7: jtag_uart_0 Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/KEY.v Info: Found entity 1: KEY Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/LEDG.v Info: Found entity 1: LEDG Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/LEDR.v Info: Found entity 1: LEDR Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Reset_Delay.v Info: Found entity 1: Reset_Delay Info: Found 2 design units, including 2 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0.v Info: Found entity 1: sdram_0_input_efifo_module Info: Found entity 2: sdram_0 Info: Found 2 design units, including 2 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sdram_0_test_component.v Info: Found entity 1: sdram_0_test_component_ram_module Info: Found entity 2: sdram_0_test_component Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SDRAM_PLL.v Info: Found entity 1: SDRAM_PLL Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SEG7.v Info: Found entity 1: SEG7 Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SEG7_LUT.v Info: Found entity 1: SEG7_LUT Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SEG7_LUT_4.v Info: Found entity 1: SEG7_LUT_4 Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/sram_0.v Info: Found entity 1: sram_0 Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/SRAM_16Bit_512K.v Info: Found entity 1: SRAM_16Bit_512K Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/Switch.v Info: Found entity 1: Switch Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v(52) Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v(282) Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v(505) Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v(720) Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v(930) Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v(1155) Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v(1623) Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v(2019) Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v(2413) Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v(2812) Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v(3753) Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v(4220) Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v(4650) Warning (10335): Unrecognized synthesis attribute "auto_dissolve" at //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v(5285) Info: Found 21 design units, including 21 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/system_0.v Info: Found entity 1: KEY_s1_arbitrator Info: Found entity 2: LEDG_s1_arbitrator Info: Found entity 3: LEDR_s1_arbitrator Info: Found entity 4: SEG7_avalonS_arbitrator Info: Found entity 5: Switch_s1_arbitrator Info: Found entity 6: cpu_0_jtag_debug_module_arbitrator Info: Found entity 7: cpu_0_data_master_arbitrator Info: Found entity 8: cpu_0_instruction_master_arbitrator Info: Found entity 9: epcs_controller_epcs_control_port_arbitrator Info: Found entity 10: jtag_uart_0_avalon_jtag_slave_arbitrator Info: Found entity 11: rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module Info: Found entity 12: rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module Info: Found entity 13: sdram_0_s1_arbitrator Info: Found entity 14: sram_0_avalonS_arbitrator Info: Found entity 15: tri_state_bridge_0_avalon_slave_arbitrator Info: Found entity 16: tri_state_bridge_0_bridge_arbitrator Info: Found entity 17: uart_0_s1_arbitrator Info: Found entity 18: system_0_reset_clk_domain_synch_module Info: Found entity 19: system_0 Info: Found entity 20: cfi_flash_0_lane0_module Info: Found entity 21: cfi_flash_0 Info: Found 7 design units, including 7 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/uart_0.v Info: Found entity 1: uart_0_log_module Info: Found entity 2: uart_0_tx Info: Found entity 3: uart_0_rx_stimulus_source_character_source_rom_module Info: Found entity 4: uart_0_rx_stimulus_source Info: Found entity 5: uart_0_rx Info: Found entity 6: uart_0_regs Info: Found entity 7: uart_0 Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/user_logic_SRAM_16Bits_512K_0.v Info: Found entity 1: user_logic_SRAM_16Bits_512K_0 Info: Elaborating entity "DE1_NIOS" for the top level hierarchy Warning (10034): Output port "SD_CLK" at DE1_NIOS.v(179) has no driver Warning (10034): Output port "I2C_SCLK" at DE1_NIOS.v(182) has no driver Warning (10034): Output port "TDO" at DE1_NIOS.v(190) has no driver Warning (10034): Output port "VGA_HS" at DE1_NIOS.v(192) has no driver Warning (10034): Output port "VGA_VS" at DE1_NIOS.v(193) has no driver Warning (10034): Output port "VGA_R[3]" at DE1_NIOS.v(194) has no driver Warning (10034): Output port "VGA_R[2]" at DE1_NIOS.v(194) has no driver Warning (10034): Output port "VGA_R[1]" at DE1_NIOS.v(194) has no driver Warning (10034): Output port "VGA_R[0]" at DE1_NIOS.v(194) has no driver Warning (10034): Output port "VGA_G[3]" at DE1_NIOS.v(195) has no driver Warning (10034): Output port "VGA_G[2]" at DE1_NIOS.v(195) has no driver Warning (10034): Output port "VGA_G[1]" at DE1_NIOS.v(195) has no driver Warning (10034): Output port "VGA_G[0]" at DE1_NIOS.v(195) has no driver Warning (10034): Output port "VGA_B[3]" at DE1_NIOS.v(196) has no driver Warning (10034): Output port "VGA_B[2]" at DE1_NIOS.v(196) has no driver Warning (10034): Output port "VGA_B[1]" at DE1_NIOS.v(196) has no driver Warning (10034): Output port "VGA_B[0]" at DE1_NIOS.v(196) has no driver Warning (10034): Output port "AUD_DACDAT" at DE1_NIOS.v(201) has no driver Warning (10034): Output port "AUD_XCK" at DE1_NIOS.v(203) has no driver Info: Elaborating entity "Reset_Delay" for hierarchy "Reset_Delay:delay1" Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(18): truncated value with size 32 to match size of target (24) Info: Elaborating entity "SDRAM_PLL" for hierarchy "SDRAM_PLL:PLL1" Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/altpll.tdf Info: Found entity 1: altpll Info: Elaborating entity "altpll" for hierarchy "SDRAM_PLL:PLL1|altpll:altpll_component" Info: Elaborated megafunction instantiation "SDRAM_PLL:PLL1|altpll:altpll_component" Info: Elaborating entity "system_0" for hierarchy "system_0:u0" Info: Elaborating entity "KEY_s1_arbitrator" for hierarchy "system_0:u0|KEY_s1_arbitrator:the_KEY_s1" Info: Elaborating entity "KEY" for hierarchy "system_0:u0|KEY:the_KEY" Info: Elaborating entity "LEDG_s1_arbitrator" for hierarchy "system_0:u0|LEDG_s1_arbitrator:the_LEDG_s1" Info: Elaborating entity "LEDG" for hierarchy "system_0:u0|LEDG:the_LEDG" Info: Elaborating entity "LEDR_s1_arbitrator" for hierarchy "system_0:u0|LEDR_s1_arbitrator:the_LEDR_s1" Info: Elaborating entity "LEDR" for hierarchy "system_0:u0|LEDR:the_LEDR" Info: Elaborating entity "SEG7_avalonS_arbitrator" for hierarchy "system_0:u0|SEG7_avalonS_arbitrator:the_SEG7_avalonS" Info: Elaborating entity "SEG7" for hierarchy "system_0:u0|SEG7:the_SEG7" Info: Elaborating entity "SEG7_LUT_4" for hierarchy "system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4" Info: Elaborating entity "SEG7_LUT" for hierarchy "system_0:u0|SEG7:the_SEG7|SEG7_LUT_4:the_SEG7_LUT_4|SEG7_LUT:u0" Info: Elaborating entity "Switch_s1_arbitrator" for hierarchy "system_0:u0|Switch_s1_arbitrator:the_Switch_s1" Info: Elaborating entity "Switch" for hierarchy "system_0:u0|Switch:the_Switch" Info: Elaborating entity "cpu_0_jtag_debug_module_arbitrator" for hierarchy "system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module" Info: Elaborating entity "cpu_0_data_master_arbitrator" for hierarchy "system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master" Info: Elaborating entity "cpu_0_instruction_master_arbitrator" for hierarchy "system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master" Info: Elaborating entity "cpu_0" for hierarchy "system_0:u0|cpu_0:the_cpu_0" Info: Elaborating entity "cpu_0_test_bench" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench" Info: Elaborating entity "cpu_0_ic_data_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data" Warning: Entity "altsyncram" obtained from "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" instead of from Quartus II megafunction library Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf Info: Found entity 1: altsyncram Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_cub1.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: altsyncram_cub1 Info: Elaborating entity "altsyncram_cub1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_k1l1.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: altsyncram_k1l1 Info: Elaborating entity "altsyncram_k1l1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1" Info: Elaborating entity "cpu_0_ic_tag_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag" Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_73e1.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: altsyncram_73e1 Info: Elaborating entity "altsyncram_73e1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_73e1:auto_generated" Info: Elaborating entity "cpu_0_bht_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht" Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_4nd1.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: altsyncram_4nd1 Info: Elaborating entity "altsyncram_4nd1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_4nd1:auto_generated" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_3um1.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: altsyncram_3um1 Info: Elaborating entity "altsyncram_3um1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_4nd1:auto_generated|altsyncram_3um1:altsyncram1" Info: Elaborating entity "cpu_0_register_bank_a_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a" Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_epd1.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: altsyncram_epd1 Info: Elaborating entity "altsyncram_epd1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_epd1:auto_generated" Info: Elaborating entity "cpu_0_register_bank_b_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b" Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_fpd1.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: altsyncram_fpd1 Info: Elaborating entity "altsyncram_fpd1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_fpd1:auto_generated" Info: Elaborating entity "cpu_0_dc_tag_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag" Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_9u12.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: altsyncram_9u12 Info: Elaborating entity "altsyncram_9u12" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_9u12:auto_generated" Info: Elaborating entity "cpu_0_dc_data_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data" Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_a422.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: altsyncram_a422 Info: Elaborating entity "altsyncram_a422" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated" Info: Elaborating entity "cpu_0_mult_cell" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell" Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/altmult_add.tdf Info: Found entity 1: altmult_add Info: Elaborating entity "altmult_add" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1" Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/mult_add_4cr2.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: mult_add_4cr2 Info: Elaborating entity "mult_add_4cr2" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/ded_mult_2o81.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: ded_mult_2o81 Info: Elaborating entity "ded_mult_2o81" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/dffpipe_93c.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: dffpipe_93c Info: Elaborating entity "dffpipe_93c" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result" Info: Elaborating entity "altmult_add" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2" Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/mult_add_6cr2.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: mult_add_6cr2 Info: Elaborating entity "mult_add_6cr2" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated" Info: Elaborating entity "cpu_0_nios2_oci" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci" Info: Elaborating entity "cpu_0_nios2_oci_debug" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug" Info: Elaborating entity "cpu_0_nios2_ocimem" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem" Info: Elaborating entity "cpu_0_ociram_lpm_dram_bdp_component_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component" Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_c572.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: altsyncram_c572 Info: Elaborating entity "altsyncram_c572" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated" Info: Elaborating entity "cpu_0_nios2_avalon_reg" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg" Info: Elaborating entity "cpu_0_nios2_oci_break" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break" Info: Elaborating entity "cpu_0_nios2_oci_xbrk" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk" Info: Elaborating entity "cpu_0_nios2_oci_dbrk" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk" Info: Elaborating entity "cpu_0_nios2_oci_match_paired" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_paired:cpu_0_nios2_oci_dbrk_hit0_match_paired" Info: Elaborating entity "cpu_0_nios2_oci_match_single" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit0_match_single" Info: Elaborating entity "cpu_0_nios2_oci_itrace" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace" Info: Elaborating entity "cpu_0_nios2_oci_dtrace" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace" Info: Elaborating entity "cpu_0_nios2_oci_td_mode" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace|cpu_0_nios2_oci_td_mode:cpu_0_nios2_oci_trc_ctrl_td_mode" Info: Elaborating entity "cpu_0_nios2_oci_fifo" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo" Info: Elaborating entity "cpu_0_nios2_oci_compute_tm_count" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_compute_tm_count:cpu_0_nios2_oci_compute_tm_count_tm_count" Info: Elaborating entity "cpu_0_nios2_oci_fifowp_inc" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifowp_inc:cpu_0_nios2_oci_fifowp_inc_fifowp" Info: Elaborating entity "cpu_0_nios2_oci_fifocount_inc" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifocount_inc:cpu_0_nios2_oci_fifocount_inc_fifocount" Info: Elaborating entity "cpu_0_nios2_oci_pib" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_pib:the_cpu_0_nios2_oci_pib" Info: Elaborating entity "cpu_0_nios2_oci_im" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im" Info: Elaborating entity "cpu_0_traceram_lpm_dram_bdp_component_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component" Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_e502.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: altsyncram_e502 Info: Elaborating entity "altsyncram_e502" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated" Info: Elaborating entity "cpu_0_jtag_debug_module_wrapper" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper" Info: Elaborating entity "cpu_0_jtag_debug_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1" Info: Elaborating entity "epcs_controller_epcs_control_port_arbitrator" for hierarchy "system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port" Info: Elaborating entity "epcs_controller" for hierarchy "system_0:u0|epcs_controller:the_epcs_controller" Info: Elaborating entity "epcs_controller_sub" for hierarchy "system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub" Info: Elaborating entity "tornado_epcs_controller_atom" for hierarchy "system_0:u0|epcs_controller:the_epcs_controller|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom" Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom" Info: Elaborated megafunction instantiation "system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_lo31.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: altsyncram_lo31 Info: Elaborating entity "altsyncram_lo31" for hierarchy "system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_lo31:auto_generated" Info: Elaborating entity "jtag_uart_0_avalon_jtag_slave_arbitrator" for hierarchy "system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave" Info: Elaborating entity "jtag_uart_0" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0" Info: Elaborating entity "jtag_uart_0_scfifo_w" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w" Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/scfifo.tdf Info: Found entity 1: scfifo Info: Elaborating entity "scfifo" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo" Info: Elaborated megafunction instantiation "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/scfifo_1n21.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: scfifo_1n21 Info: Elaborating entity "scfifo_1n21" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/a_dpfifo_8t21.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: a_dpfifo_8t21 Info: Elaborating entity "a_dpfifo_8t21" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/a_fefifo_7cf.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: a_fefifo_7cf Info: Elaborating entity "a_fefifo_7cf" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/cntr_rj7.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cntr_rj7 Info: Elaborating entity "cntr_rj7" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/dpram_5h21.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: dpram_5h21 Info: Elaborating entity "dpram_5h21" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/altsyncram_9tl1.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: altsyncram_9tl1 Info: Elaborating entity "altsyncram_9tl1" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2" Warning: Using design file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/cntr_fjb.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cntr_fjb Info: Elaborating entity "cntr_fjb" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_fjb:rd_ptr_count" Info: Elaborating entity "jtag_uart_0_scfifo_r" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r" Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/alt_jtag_atlantic.v Info: Found entity 1: alt_jtag_atlantic Info: Elaborating entity "alt_jtag_atlantic" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic" Info: Elaborated megafunction instantiation "system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic" Info: Elaborating entity "sdram_0_s1_arbitrator" for hierarchy "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1" Info: Elaborating entity "rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module" for hierarchy "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1" Info: Elaborating entity "rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module" for hierarchy "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1" Info: Elaborating entity "sdram_0" for hierarchy "system_0:u0|sdram_0:the_sdram_0" Warning (10766): Verilog HDL warning at sdram_0.v(352): ignoring full_case attribute on case statement with explicit default Info: Elaborating entity "sdram_0_input_efifo_module" for hierarchy "system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module" Warning (10766): Verilog HDL warning at sdram_0.v(67): ignoring full_case attribute on case statement with explicit default Warning (10766): Verilog HDL warning at sdram_0.v(93): ignoring full_case attribute on case statement with explicit default Warning (10766): Verilog HDL warning at sdram_0.v(129): ignoring full_case attribute on case statement with explicit default Info: Elaborating entity "sram_0_avalonS_arbitrator" for hierarchy "system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS" Info: Elaborating entity "sram_0" for hierarchy "system_0:u0|sram_0:the_sram_0" Info: Elaborating entity "SRAM_16Bit_512K" for hierarchy "system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K" Warning (10036): Verilog HDL or VHDL warning at SRAM_16Bit_512K.v(37): object "SRAM_RST_N" assigned a value but never read Info: Elaborating entity "tri_state_bridge_0_avalon_slave_arbitrator" for hierarchy "system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave" Info: Elaborating entity "uart_0_s1_arbitrator" for hierarchy "system_0:u0|uart_0_s1_arbitrator:the_uart_0_s1" Info: Elaborating entity "uart_0" for hierarchy "system_0:u0|uart_0:the_uart_0" Info: Elaborating entity "uart_0_tx" for hierarchy "system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx" Info: Elaborating entity "uart_0_rx" for hierarchy "system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx" Info: Elaborating entity "uart_0_rx_stimulus_source" for hierarchy "system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|uart_0_rx_stimulus_source:the_uart_0_rx_stimulus_source" Info: Elaborating entity "uart_0_regs" for hierarchy "system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs" Info: Elaborating entity "system_0_reset_clk_domain_synch_module" for hierarchy "system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch" Warning: Port "iLB_N" on the entity instantiation of "the_sram_0" is connected to a signal of width 2. The formal width of the signal in the module is 1. Extra bits will be ignored. Warning: Port "iUB_N" on the entity instantiation of "the_sram_0" is connected to a signal of width 2. The formal width of the signal in the module is 1. Extra bits will be ignored. Warning: Port "address_b" on the entity instantiation of "cpu_0_traceram_lpm_dram_bdp_component" is connected to a signal of width 17. The formal width of the signal in the module is 7. Extra bits will be ignored. Warning: Port "jdo" on the entity instantiation of "the_cpu_0_nios2_oci_itrace" is connected to a signal of width 38. The formal width of the signal in the module is 16. Extra bits will be ignored. Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit3_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71. Extra bits will be ignored. Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit2_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71. Extra bits will be ignored. Warning: Port "dbrka" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit2_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71. Extra bits will be ignored. Warning: Port "dbrkb" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit2_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71. Extra bits will be ignored. Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit1_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71. Extra bits will be ignored. Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit0_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71. Extra bits will be ignored. Warning: Port "dbrka" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit0_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71. Extra bits will be ignored. Warning: Port "dbrkb" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit0_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71. Extra bits will be ignored. Info: Found 6 design units, including 2 entities, in source file c:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd Info: Found design unit 1: HUB_PACK Info: Found design unit 2: JTAG_PACK Info: Found design unit 3: sld_hub-rtl Info: Found design unit 4: sld_jtag_state_machine-rtl Info: Found entity 1: sld_hub Info: Found entity 2: sld_jtag_state_machine Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst" Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Cyclone II" Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf Info: Found entity 1: lpm_shiftreg Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Cyclone II" Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/lpm_decode.tdf Info: Found entity 1: lpm_decode Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|lpm_decode:instruction_decoder", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Cyclone II" Info: Found 1 design units, including 1 entities, in source file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/db/decode_aoi.tdf Info: Found entity 1: decode_aoi Info: Found 2 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd Info: Found design unit 1: sld_dffex-DFFEX Info: Found entity 1: sld_dffex Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:RESET", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Cyclone II" Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:IRSR", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Cyclone II" Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Cyclone II" Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:IRF_ENA", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Cyclone II" Info: Found 2 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd Info: Found design unit 1: sld_rom_sr-INFO_REG Info: Found entity 1: sld_rom_sr Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Cyclone II" Warning: Reduced register "system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[15]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[14]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[13]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[12]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[11]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[10]" with stuck data_in port to stuck value GND Info: Power-up level of register "system_0:u0|sdram_0:the_sdram_0|i_addr[5]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|sdram_0:the_sdram_0|i_addr[5]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|sdram_0:the_sdram_0|i_addr[4]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|sdram_0:the_sdram_0|i_addr[4]" with stuck data_in port to stuck value VCC Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[31]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[30]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[29]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[28]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[27]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[26]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[25]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[24]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[23]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[22]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[21]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[20]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[19]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[18]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[17]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[16]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[15]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[14]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[13]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[12]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[11]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[10]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[9]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[8]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[7]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[6]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[5]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[4]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[6]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[5]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[4]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[3]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[2]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[1]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[0]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|tracemem_tw" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_break_pulse" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_goto0" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_goto1" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|xbrk_hit0" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|xbrk_hit1" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|xbrk_hit2" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|xbrk_break" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|E_xbrk_goto0" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|E_xbrk_goto1" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|M_xbrk_goto0" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|dbrk_hit3_latch" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|dbrk_hit2_latch" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|dbrk_hit1_latch" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|dbrk_hit0_latch" with stuck data_in port to stuck value GND Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[31]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[31]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[30]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[30]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[29]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[29]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[28]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[28]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[27]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[27]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[26]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[26]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[25]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[25]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[24]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[24]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[23]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[23]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[22]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[22]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[21]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[21]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[20]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[20]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[19]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[19]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[18]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[18]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[17]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[17]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[16]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[16]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[15]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[15]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[14]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[14]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[13]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[13]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[12]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[12]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[11]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[11]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[10]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[10]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[9]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[9]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[8]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[8]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[7]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[7]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[6]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[6]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[5]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[5]" with stuck data_in port to stuck value VCC Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[4]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[4]" with stuck data_in port to stuck value VCC Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|M_xbrk_goto1" with stuck data_in port to stuck value GND Warning: Synthesized away the following node(s): Warning: Synthesized away the following RAM node(s): Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[0]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[1]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[2]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[3]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[4]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[5]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[6]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[7]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[8]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[9]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[10]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[11]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[12]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[13]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[14]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[15]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[16]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[17]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[18]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[19]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[20]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[21]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[22]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[23]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[24]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[25]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[26]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[27]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[28]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[29]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[30]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[31]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[32]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[33]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[34]" Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[35]" Info: Duplicate registers merged to single register Info: Duplicate register "system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|delayed_unxsync_rxdxx2" merged to single register "system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|delayed_unxsync_rxdxx1" Info: Duplicate register "system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_tri_state_bridge_0_avalon_slave_end_xfer" merged to single register "system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_reasons_to_wait", power-up level changed Info: Duplicate register "system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|d1_sram_0_avalonS_end_xfer" merged to single register "system_0:u0|sram_0_avalonS_arbitrator:the_sram_0_avalonS|d1_reasons_to_wait", power-up level changed Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[0]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]" Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[1]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]" Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[2]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]" Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[3]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]" Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[6]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]" Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[7]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]" Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[8]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]" Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[9]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]" Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[10]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]" Info: Duplicate register "system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|d1_epcs_controller_epcs_control_port_end_xfer" merged to single register "system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|d1_reasons_to_wait", power-up level changed Info: Duplicate register "system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|d1_cpu_0_jtag_debug_module_end_xfer" merged to single register "system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|d1_reasons_to_wait", power-up level changed Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|trigger_state" with stuck data_in port to stuck value GND Info: Duplicate registers merged to single register Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|full_6" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_6" Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|full_5" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_5" Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|full_4" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_4" Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|full_3" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_3" Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|full_2" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_2" Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|full_1" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_1" Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1|full_0" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|full_0" Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_break" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|trigbrktype" with stuck data_in port to stuck value GND Info: Duplicate registers merged to single register Info: Duplicate register "system_0:u0|cpu_0:the_cpu_0|D_ctrl_jmp_direct" merged to single register "system_0:u0|cpu_0:the_cpu_0|D_ctrl_a_not_src" Info: Duplicate register "system_0:u0|cpu_0:the_cpu_0|D_ctrl_b_is_dst" merged to single register "system_0:u0|cpu_0:the_cpu_0|D_ctrl_b_not_src" Warning: Reduced register "system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_share_counter[2]" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_share_counter[2]" with stuck data_in port to stuck value GND Info: State machine "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_next" contains 4 states Info: State machine "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_state" contains 9 states Info: State machine "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_next" contains 4 states Info: State machine "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_state" contains 6 states Info: Selected Auto state machine encoding method for state machine "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_next" Info: Encoding result for state machine "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_next" Info: Completed encoding using 4 state bits Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_next.010000000" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_next.000010000" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_next.000001000" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_next.000000001" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_next.000000001" uses code string "0000" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_next.000001000" uses code string "0011" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_next.010000000" uses code string "1001" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_next.000010000" uses code string "0101" Info: Selected Auto state machine encoding method for state machine "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_state" Info: Encoding result for state machine "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_state" Info: Completed encoding using 9 state bits Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.100000000" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.010000000" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.001000000" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000100000" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000010000" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000001000" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000000100" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000000010" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000000001" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_state.000000001" uses code string "000000000" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_state.000100000" uses code string "000100001" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_state.000010000" uses code string "000010001" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_state.000001000" uses code string "000001001" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_state.100000000" uses code string "100000001" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_state.000000100" uses code string "000000101" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_state.000000010" uses code string "000000011" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_state.001000000" uses code string "001000001" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|m_state.010000000" uses code string "010000001" Info: Selected Auto state machine encoding method for state machine "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_next" Info: Encoding result for state machine "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_next" Info: Completed encoding using 4 state bits Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_next.101" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_next.010" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_next.111" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_next.000" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_next.000" uses code string "0000" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_next.111" uses code string "0011" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_next.010" uses code string "0101" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_next.101" uses code string "1001" Info: Selected Auto state machine encoding method for state machine "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_state" Info: Encoding result for state machine "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_state" Info: Completed encoding using 6 state bits Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.101" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.111" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.001" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.011" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.010" Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.000" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_state.000" uses code string "000000" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_state.010" uses code string "000011" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_state.011" uses code string "000101" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_state.001" uses code string "001001" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_state.111" uses code string "010001" Info: State "|DE1_NIOS|system_0:u0|sdram_0:the_sdram_0|i_state.101" uses code string "100001" Warning: Reduced register "system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_slavearbiterlockenable" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_slavearbiterlockenable" with stuck data_in port to stuck value GND Info: State machine "|DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize" contains 6 states Info: Selected Auto state machine encoding method for state machine "|DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize" Info: Encoding result for state machine "|DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize" Info: Completed encoding using 6 state bits Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.011" Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.100" Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.101" Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.010" Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.001" Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.000" Info: State "|DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.000" uses code string "000000" Info: State "|DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.001" uses code string "000011" Info: State "|DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.010" uses code string "000101" Info: State "|DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.101" uses code string "001001" Info: State "|DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.100" uses code string "010001" Info: State "|DE1_NIOS|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.011" uses code string "100001" Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.001" with stuck data_in port to stuck value GND Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.011" with stuck data_in port to stuck value GND Warning: The bidir "SD_DAT3" has no source; inserted an always disabled tri-state buffer. Warning: The bidir "SD_CMD" has no source; inserted an always disabled tri-state buffer. Info: Registers with preset signals will power-up high Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back Warning: Converted presettable and clearable register to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state. Warning: Register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir" converted into equivalent circuit using register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir~_emulated" and latch "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir~7" Warning: Register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr" converted into equivalent circuit using register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr~_emulated" and latch "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr~8" Warning: Output pins are stuck at VCC or GND Warning: Pin "DRAM_CKE" stuck at VCC Warning: Pin "FL_RST_N" stuck at VCC Warning: Pin "SD_CLK" stuck at GND Warning: Pin "TDO" stuck at GND Warning: Pin "I2C_SCLK" stuck at GND Warning: Pin "VGA_HS" stuck at GND Warning: Pin "VGA_VS" stuck at GND Warning: Pin "VGA_R[0]" stuck at GND Warning: Pin "VGA_R[1]" stuck at GND Warning: Pin "VGA_R[2]" stuck at GND Warning: Pin "VGA_R[3]" stuck at GND Warning: Pin "VGA_G[0]" stuck at GND Warning: Pin "VGA_G[1]" stuck at GND Warning: Pin "VGA_G[2]" stuck at GND Warning: Pin "VGA_G[3]" stuck at GND Warning: Pin "VGA_B[0]" stuck at GND Warning: Pin "VGA_B[1]" stuck at GND Warning: Pin "VGA_B[2]" stuck at GND Warning: Pin "VGA_B[3]" stuck at GND Warning: Pin "AUD_DACDAT" stuck at GND Warning: Pin "AUD_XCK" stuck at GND Info: 76 registers lost all their fanouts during netlist optimizations. The first 76 are displayed below. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[0]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[1]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[2]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[3]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[4]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[5]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[6]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[7]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[8]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[9]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[10]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[11]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[12]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[13]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[14]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[15]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[16]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[17]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[18]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[19]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[20]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[21]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[22]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[23]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[24]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[25]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[26]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[27]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[28]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[29]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[30]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[31]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[32]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[33]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[34]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_itrace/itm[35]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_xbrk/xbrk_hit3" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[0]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[16]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[15]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[14]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[13]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[12]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[11]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[10]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[9]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[8]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[7]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[6]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[5]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[4]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[3]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[2]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0/the_cpu_0_nios2_oci/the_cpu_0_nios2_oci_im/trc_jtag_addr[1]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_sdram_0/m_next~64" lost all its fanouts during netlist optimizations. Info: Register "u0/the_sdram_0/m_next~65" lost all its fanouts during netlist optimizations. Info: Register "u0/the_sdram_0/m_next~68" lost all its fanouts during netlist optimizations. Info: Register "u0/the_sdram_0/m_next~69" lost all its fanouts during netlist optimizations. Info: Register "u0/the_sdram_0/m_next~71" lost all its fanouts during netlist optimizations. Info: Register "u0/the_sdram_0/i_next~17" lost all its fanouts during netlist optimizations. Info: Register "u0/the_sdram_0/i_next~18" lost all its fanouts during netlist optimizations. Info: Register "u0/the_sdram_0/i_next~19" lost all its fanouts during netlist optimizations. Info: Register "u0/the_sdram_0/i_state~56" lost all its fanouts during netlist optimizations. Info: Register "u0/the_sdram_0/i_state~57" lost all its fanouts during netlist optimizations. Info: Register "u0/the_sdram_0/i_state~58" lost all its fanouts during netlist optimizations. Info: Register "u0/the_epcs_controller_epcs_control_port/epcs_controller_epcs_control_port_arb_share_counter[1]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_epcs_controller_epcs_control_port/epcs_controller_epcs_control_port_arb_share_counter[0]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0_jtag_debug_module/cpu_0_jtag_debug_module_arb_share_counter[1]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0_jtag_debug_module/cpu_0_jtag_debug_module_arb_share_counter[0]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_epcs_controller_epcs_control_port/last_cycle_cpu_0_data_master_granted_slave_epcs_controller_epcs_control_port" lost all its fanouts during netlist optimizations. Info: Register "u0/the_epcs_controller_epcs_control_port/last_cycle_cpu_0_instruction_master_granted_slave_epcs_controller_epcs_control_port" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0_jtag_debug_module/last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0_jtag_debug_module/last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module" lost all its fanouts during netlist optimizations. Info: Register "u0/the_epcs_controller_epcs_control_port/epcs_controller_epcs_control_port_saved_chosen_master_vector[1]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0_jtag_debug_module/cpu_0_jtag_debug_module_saved_chosen_master_vector[1]" lost all its fanouts during netlist optimizations. Info: Register "u0/the_cpu_0_jtag_debug_module/cpu_0_jtag_debug_module_saved_chosen_master_vector[0]" lost all its fanouts during netlist optimizations. Warning: Design contains 11 input pin(s) that do not drive logic Warning: No output dependent on input pin "CLOCK_24[0]" Warning: No output dependent on input pin "CLOCK_24[1]" Warning: No output dependent on input pin "CLOCK_27[0]" Warning: No output dependent on input pin "CLOCK_27[1]" Warning: No output dependent on input pin "EXT_CLOCK" Warning: No output dependent on input pin "TDI" Warning: No output dependent on input pin "TCK" Warning: No output dependent on input pin "TCS" Warning: No output dependent on input pin "PS2_DAT" Warning: No output dependent on input pin "PS2_CLK" Warning: No output dependent on input pin "AUD_ADCDAT" Info: Implemented 5236 device resources after synthesis - the final resource count might be different Info: Implemented 30 input pins Info: Implemented 138 output pins Info: Implemented 119 bidirectional pins Info: Implemented 4697 logic cells Info: Implemented 245 RAM segments Info: Implemented 1 ClockLock PLLs Info: Implemented 4 DSP elements Info: Generated suppressed messages file //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.map.smsg Info: Quartus II Analysis & Synthesis was successful. 0 errors, 248 warnings Info: Allocated 229 megabytes of memory during processing Info: Processing ended: Thu Aug 30 15:46:19 2007 Info: Elapsed time: 00:01:49 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ The suppressed messages can be found in //file2/R1/DE1/cd/source/DE1_CD_v0.7/DE1_demonstrations/DE1_NIOS/DE1_NIOS.map.smsg.