library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Quad is
    Port (  ENC_1A_IN : in std_logic;
	 			ENC_1B_IN : in std_logic;
				ENC_2A_IN : in std_logic;
	 			ENC_2B_IN : in std_logic;
				NCS : in std_logic;
            NRD : in std_logic;
				NWR : in std_logic;
	         ADDRESS : in std_logic;
            DATA_BUS : inout std_logic_vector(15 downto 0)
			);
end Quad;

architecture Quad_Arch of Quad is

	signal COUNT_1 : Std_logic_vector(15 downto 0);
	signal COUNT_2 : Std_logic_vector(15 downto 0);
begin

-- Counter 1
process(ENC_1A_IN,NCS,NWR,ADDRESS)
begin

-- Async reset
	if(NCS = '0' and NWR = '0' and ADDRESS = '0')then
		COUNT_1 <= "0000000000000000";
		
-- On rising edge of frequency 1 
		else if(ENC_1A_IN'event and ENC_1A_IN = '1') then
			
			if(ENC_1B_IN = '0') then
				COUNT_1 <= COUNT_1 + 1;
			else
				COUNT_1 <= COUNT_1 - 1;
			end if;
		end if;
	end if;
end process;


-- Counter 2
process(ENC_2A_IN,NCS,NWR,ADDRESS)
begin
	
-- Async reset
	if (NCS = '0' and NWR = '0' and ADDRESS = '1')then
 		COUNT_2 <= "0000000000000000";
		
-- On rising edge of frequency 2 
		else if(ENC_2A_IN'event and ENC_2A_IN = '1') then

			if(ENC_2B_IN = '0') then
				COUNT_2 <= COUNT_2 + 1;
			else
				COUNT_2 <= COUNT_2 - 1;
			end if;
		end if;
	end if;
end process;

-- Read counters
DATA_BUS <= COUNT_1 when (NCS = '0' and NRD = '0' and ADDRESS = '0') else
	COUNT_2 when (NCS = '0' and NRD = '0' and ADDRESS = '1') else
	"ZZZZZZZZZZZZZZZZ";

end Quad_Arch;