module dfilter(clk, D, Q);
input clk;
input D;
output reg Q;
reg [7:0] dfilter4;
parameter valid0 = 8'b00000000, valid1 = 8'b11111111;
always @ (posedge clk)
begin
dfilter4 <= {dfilter4[6:0], D};
case(dfilter4)
valid0: Q <= 0;
valid1: Q <= 1;
default: Q <= Q; // hold value
endcase
end
endmodule