ENTITY ddd IS
	PORT
	(
		clk		: IN STD_LOGIC ;
		rotary_a_in		: IN STD_LOGIC ;
		rotary_b_in		: IN STD_LOGIC ;
		rotary_q1		: OUT STD_LOGIC_VECTOR 
		rotary_q2 : OUT STD_LOGIC_VECTOR
	);
END ddd;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

rotary_filter: process(clk)
begin
if clk'event and clk='1' then
rotary_in <= rotary_b_in & rotary_a_in;
case rotary_in is
when "00" => rotary_q1 <= '0';
rotary_q2 <= rotary_q2;
when "01" => rotary_q1 <= rotary_q1;
rotary_q2 <= '0';
when "10" => rotary_q1 <= rotary_q1;
rotary_q2 <= '1';
when "11" => rotary_q1 <= '1';
rotary_q2 <= rotary_q2;
when others => rotary_q1 <= rotary_q1;
rotary_q2 <= rotary_q2;
end case;
end if;
end process rotary_filter;


direction: process(clk)
begin
if clk'event and clk='1' then
delay_rotary_q1 <= rotary_q1;
if rotary_q1='1' and delay_rotary_q1='0' then
rotary_event <= '1';
rotary_left <= rotary_q2;
else
rotary_event <= '0';
rotary_left <= rotary_left;
end if;
end if;
end process direction;