--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=4 LPM_WIDTH=10 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 9.0 cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2009:01:29:16:12:07:SJ  VERSION_END


-- Copyright (C) 1991-2009 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 20 
SUBDESIGN mux_tjb
( 
	data[39..0]	:	input;
	result[9..0]	:	output;
	sel[1..0]	:	input;
) 
VARIABLE 
	result_node[9..0]	: WIRE;
	sel_node[1..0]	: WIRE;
	w_data544w[3..0]	: WIRE;
	w_data574w[3..0]	: WIRE;
	w_data599w[3..0]	: WIRE;
	w_data624w[3..0]	: WIRE;
	w_data649w[3..0]	: WIRE;
	w_data674w[3..0]	: WIRE;
	w_data699w[3..0]	: WIRE;
	w_data724w[3..0]	: WIRE;
	w_data749w[3..0]	: WIRE;
	w_data774w[3..0]	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( (((w_data774w[1..1] & sel_node[0..0]) & (! (((w_data774w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data774w[2..2]))))) # ((((w_data774w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data774w[2..2]))) & (w_data774w[3..3] # (! sel_node[0..0])))), (((w_data749w[1..1] & sel_node[0..0]) & (! (((w_data749w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data749w[2..2]))))) # ((((w_data749w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data749w[2..2]))) & (w_data749w[3..3] # (! sel_node[0..0])))), (((w_data724w[1..1] & sel_node[0..0]) & (! (((w_data724w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data724w[2..2]))))) # ((((w_data724w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data724w[2..2]))) & (w_data724w[3..3] # (! sel_node[0..0])))), (((w_data699w[1..1] & sel_node[0..0]) & (! (((w_data699w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data699w[2..2]))))) # ((((w_data699w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data699w[2..2]))) & (w_data699w[3..3] # (! sel_node[0..0])))), (((w_data674w[1..1] & sel_node[0..0]) & (! (((w_data674w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data674w[2..2]))))) # ((((w_data674w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data674w[2..2]))) & (w_data674w[3..3] # (! sel_node[0..0])))), (((w_data649w[1..1] & sel_node[0..0]) & (! (((w_data649w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data649w[2..2]))))) # ((((w_data649w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data649w[2..2]))) & (w_data649w[3..3] # (! sel_node[0..0])))), (((w_data624w[1..1] & sel_node[0..0]) & (! (((w_data624w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data624w[2..2]))))) # ((((w_data624w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data624w[2..2]))) & (w_data624w[3..3] # (! sel_node[0..0])))), (((w_data599w[1..1] & sel_node[0..0]) & (! (((w_data599w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data599w[2..2]))))) # ((((w_data599w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data599w[2..2]))) & (w_data599w[3..3] # (! sel_node[0..0])))), (((w_data574w[1..1] & sel_node[0..0]) & (! (((w_data574w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data574w[2..2]))))) # ((((w_data574w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data574w[2..2]))) & (w_data574w[3..3] # (! sel_node[0..0])))), (((w_data544w[1..1] & sel_node[0..0]) & (! (((w_data544w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data544w[2..2]))))) # ((((w_data544w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data544w[2..2]))) & (w_data544w[3..3] # (! sel_node[0..0])))));
	sel_node[] = ( sel[1..0]);
	w_data544w[] = ( data[30..30], data[20..20], data[10..10], data[0..0]);
	w_data574w[] = ( data[31..31], data[21..21], data[11..11], data[1..1]);
	w_data599w[] = ( data[32..32], data[22..22], data[12..12], data[2..2]);
	w_data624w[] = ( data[33..33], data[23..23], data[13..13], data[3..3]);
	w_data649w[] = ( data[34..34], data[24..24], data[14..14], data[4..4]);
	w_data674w[] = ( data[35..35], data[25..25], data[15..15], data[5..5]);
	w_data699w[] = ( data[36..36], data[26..26], data[16..16], data[6..6]);
	w_data724w[] = ( data[37..37], data[27..27], data[17..17], data[7..7]);
	w_data749w[] = ( data[38..38], data[28..28], data[18..18], data[8..8]);
	w_data774w[] = ( data[39..39], data[29..29], data[19..19], data[9..9]);
END;
--VALID FILE