--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=8 LPM_WIDTH=6 LPM_WIDTHS=3 data result sel --VERSION_BEGIN 9.0 cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2009:01:29:16:12:07:SJ VERSION_END -- Copyright (C) 1991-2009 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. --synthesis_resources = lut 30 SUBDESIGN mux_nib ( data[47..0] : input; result[5..0] : output; sel[2..0] : input; ) VARIABLE result_node[5..0] : WIRE; sel_ffs_wire[2..0] : WIRE; sel_node[2..0] : WIRE; w_data1016w[7..0] : WIRE; w_data1038w[3..0] : WIRE; w_data1039w[3..0] : WIRE; w_data669w[7..0] : WIRE; w_data691w[3..0] : WIRE; w_data692w[3..0] : WIRE; w_data740w[7..0] : WIRE; w_data762w[3..0] : WIRE; w_data763w[3..0] : WIRE; w_data809w[7..0] : WIRE; w_data831w[3..0] : WIRE; w_data832w[3..0] : WIRE; w_data878w[7..0] : WIRE; w_data900w[3..0] : WIRE; w_data901w[3..0] : WIRE; w_data947w[7..0] : WIRE; w_data969w[3..0] : WIRE; w_data970w[3..0] : WIRE; w_sel1040w[1..0] : WIRE; w_sel693w[1..0] : WIRE; w_sel764w[1..0] : WIRE; w_sel833w[1..0] : WIRE; w_sel902w[1..0] : WIRE; w_sel971w[1..0] : WIRE; BEGIN result[] = result_node[]; result_node[] = ( ((sel_node[2..2] & (((w_data1039w[1..1] & w_sel1040w[0..0]) & (! (((w_data1039w[0..0] & (! w_sel1040w[1..1])) & (! w_sel1040w[0..0])) # (w_sel1040w[1..1] & (w_sel1040w[0..0] # w_data1039w[2..2]))))) # ((((w_data1039w[0..0] & (! w_sel1040w[1..1])) & (! w_sel1040w[0..0])) # (w_sel1040w[1..1] & (w_sel1040w[0..0] # w_data1039w[2..2]))) & (w_data1039w[3..3] # (! w_sel1040w[0..0]))))) # ((! sel_node[2..2]) & (((w_data1038w[1..1] & w_sel1040w[0..0]) & (! (((w_data1038w[0..0] & (! w_sel1040w[1..1])) & (! w_sel1040w[0..0])) # (w_sel1040w[1..1] & (w_sel1040w[0..0] # w_data1038w[2..2]))))) # ((((w_data1038w[0..0] & (! w_sel1040w[1..1])) & (! w_sel1040w[0..0])) # (w_sel1040w[1..1] & (w_sel1040w[0..0] # w_data1038w[2..2]))) & (w_data1038w[3..3] # (! w_sel1040w[0..0])))))), ((sel_node[2..2] & (((w_data970w[1..1] & w_sel971w[0..0]) & (! (((w_data970w[0..0] & (! w_sel971w[1..1])) & (! w_sel971w[0..0])) # (w_sel971w[1..1] & (w_sel971w[0..0] # w_data970w[2..2]))))) # ((((w_data970w[0..0] & (! w_sel971w[1..1])) & (! w_sel971w[0..0])) # (w_sel971w[1..1] & (w_sel971w[0..0] # w_data970w[2..2]))) & (w_data970w[3..3] # (! w_sel971w[0..0]))))) # ((! sel_node[2..2]) & (((w_data969w[1..1] & w_sel971w[0..0]) & (! (((w_data969w[0..0] & (! w_sel971w[1..1])) & (! w_sel971w[0..0])) # (w_sel971w[1..1] & (w_sel971w[0..0] # w_data969w[2..2]))))) # ((((w_data969w[0..0] & (! w_sel971w[1..1])) & (! w_sel971w[0..0])) # (w_sel971w[1..1] & (w_sel971w[0..0] # w_data969w[2..2]))) & (w_data969w[3..3] # (! w_sel971w[0..0])))))), ((sel_node[2..2] & (((w_data901w[1..1] & w_sel902w[0..0]) & (! (((w_data901w[0..0] & (! w_sel902w[1..1])) & (! w_sel902w[0..0])) # (w_sel902w[1..1] & (w_sel902w[0..0] # w_data901w[2..2]))))) # ((((w_data901w[0..0] & (! w_sel902w[1..1])) & (! w_sel902w[0..0])) # (w_sel902w[1..1] & (w_sel902w[0..0] # w_data901w[2..2]))) & (w_data901w[3..3] # (! w_sel902w[0..0]))))) # ((! sel_node[2..2]) & (((w_data900w[1..1] & w_sel902w[0..0]) & (! (((w_data900w[0..0] & (! w_sel902w[1..1])) & (! w_sel902w[0..0])) # (w_sel902w[1..1] & (w_sel902w[0..0] # w_data900w[2..2]))))) # ((((w_data900w[0..0] & (! w_sel902w[1..1])) & (! w_sel902w[0..0])) # (w_sel902w[1..1] & (w_sel902w[0..0] # w_data900w[2..2]))) & (w_data900w[3..3] # (! w_sel902w[0..0])))))), ((sel_node[2..2] & (((w_data832w[1..1] & w_sel833w[0..0]) & (! (((w_data832w[0..0] & (! w_sel833w[1..1])) & (! w_sel833w[0..0])) # (w_sel833w[1..1] & (w_sel833w[0..0] # w_data832w[2..2]))))) # ((((w_data832w[0..0] & (! w_sel833w[1..1])) & (! w_sel833w[0..0])) # (w_sel833w[1..1] & (w_sel833w[0..0] # w_data832w[2..2]))) & (w_data832w[3..3] # (! w_sel833w[0..0]))))) # ((! sel_node[2..2]) & (((w_data831w[1..1] & w_sel833w[0..0]) & (! (((w_data831w[0..0] & (! w_sel833w[1..1])) & (! w_sel833w[0..0])) # (w_sel833w[1..1] & (w_sel833w[0..0] # w_data831w[2..2]))))) # ((((w_data831w[0..0] & (! w_sel833w[1..1])) & (! w_sel833w[0..0])) # (w_sel833w[1..1] & (w_sel833w[0..0] # w_data831w[2..2]))) & (w_data831w[3..3] # (! w_sel833w[0..0])))))), ((sel_node[2..2] & (((w_data763w[1..1] & w_sel764w[0..0]) & (! (((w_data763w[0..0] & (! w_sel764w[1..1])) & (! w_sel764w[0..0])) # (w_sel764w[1..1] & (w_sel764w[0..0] # w_data763w[2..2]))))) # ((((w_data763w[0..0] & (! w_sel764w[1..1])) & (! w_sel764w[0..0])) # (w_sel764w[1..1] & (w_sel764w[0..0] # w_data763w[2..2]))) & (w_data763w[3..3] # (! w_sel764w[0..0]))))) # ((! sel_node[2..2]) & (((w_data762w[1..1] & w_sel764w[0..0]) & (! (((w_data762w[0..0] & (! w_sel764w[1..1])) & (! w_sel764w[0..0])) # (w_sel764w[1..1] & (w_sel764w[0..0] # w_data762w[2..2]))))) # ((((w_data762w[0..0] & (! w_sel764w[1..1])) & (! w_sel764w[0..0])) # (w_sel764w[1..1] & (w_sel764w[0..0] # w_data762w[2..2]))) & (w_data762w[3..3] # (! w_sel764w[0..0])))))), ((sel_node[2..2] & (((w_data692w[1..1] & w_sel693w[0..0]) & (! (((w_data692w[0..0] & (! w_sel693w[1..1])) & (! w_sel693w[0..0])) # (w_sel693w[1..1] & (w_sel693w[0..0] # w_data692w[2..2]))))) # ((((w_data692w[0..0] & (! w_sel693w[1..1])) & (! w_sel693w[0..0])) # (w_sel693w[1..1] & (w_sel693w[0..0] # w_data692w[2..2]))) & (w_data692w[3..3] # (! w_sel693w[0..0]))))) # ((! sel_node[2..2]) & (((w_data691w[1..1] & w_sel693w[0..0]) & (! (((w_data691w[0..0] & (! w_sel693w[1..1])) & (! w_sel693w[0..0])) # (w_sel693w[1..1] & (w_sel693w[0..0] # w_data691w[2..2]))))) # ((((w_data691w[0..0] & (! w_sel693w[1..1])) & (! w_sel693w[0..0])) # (w_sel693w[1..1] & (w_sel693w[0..0] # w_data691w[2..2]))) & (w_data691w[3..3] # (! w_sel693w[0..0]))))))); sel_ffs_wire[] = ( sel[2..0]); sel_node[] = ( sel_ffs_wire[2..2], sel[1..0]); w_data1016w[] = ( data[47..47], data[41..41], data[35..35], data[29..29], data[23..23], data[17..17], data[11..11], data[5..5]); w_data1038w[3..0] = w_data1016w[3..0]; w_data1039w[3..0] = w_data1016w[7..4]; w_data669w[] = ( data[42..42], data[36..36], data[30..30], data[24..24], data[18..18], data[12..12], data[6..6], data[0..0]); w_data691w[3..0] = w_data669w[3..0]; w_data692w[3..0] = w_data669w[7..4]; w_data740w[] = ( data[43..43], data[37..37], data[31..31], data[25..25], data[19..19], data[13..13], data[7..7], data[1..1]); w_data762w[3..0] = w_data740w[3..0]; w_data763w[3..0] = w_data740w[7..4]; w_data809w[] = ( data[44..44], data[38..38], data[32..32], data[26..26], data[20..20], data[14..14], data[8..8], data[2..2]); w_data831w[3..0] = w_data809w[3..0]; w_data832w[3..0] = w_data809w[7..4]; w_data878w[] = ( data[45..45], data[39..39], data[33..33], data[27..27], data[21..21], data[15..15], data[9..9], data[3..3]); w_data900w[3..0] = w_data878w[3..0]; w_data901w[3..0] = w_data878w[7..4]; w_data947w[] = ( data[46..46], data[40..40], data[34..34], data[28..28], data[22..22], data[16..16], data[10..10], data[4..4]); w_data969w[3..0] = w_data947w[3..0]; w_data970w[3..0] = w_data947w[7..4]; w_sel1040w[1..0] = sel_node[1..0]; w_sel693w[1..0] = sel_node[1..0]; w_sel764w[1..0] = sel_node[1..0]; w_sel833w[1..0] = sel_node[1..0]; w_sel902w[1..0] = sel_node[1..0]; w_sel971w[1..0] = sel_node[1..0]; END; --VALID FILE