--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=8 LPM_WIDTH=4 LPM_WIDTHS=3 data result sel --VERSION_BEGIN 9.0 cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2009:01:29:16:12:07:SJ VERSION_END -- Copyright (C) 1991-2009 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. --synthesis_resources = lut 20 SUBDESIGN mux_lib ( data[31..0] : input; result[3..0] : output; sel[2..0] : input; ) VARIABLE result_node[3..0] : WIRE; sel_ffs_wire[2..0] : WIRE; sel_node[2..0] : WIRE; w_data561w[7..0] : WIRE; w_data583w[3..0] : WIRE; w_data584w[3..0] : WIRE; w_data632w[7..0] : WIRE; w_data654w[3..0] : WIRE; w_data655w[3..0] : WIRE; w_data701w[7..0] : WIRE; w_data723w[3..0] : WIRE; w_data724w[3..0] : WIRE; w_data770w[7..0] : WIRE; w_data792w[3..0] : WIRE; w_data793w[3..0] : WIRE; w_sel585w[1..0] : WIRE; w_sel656w[1..0] : WIRE; w_sel725w[1..0] : WIRE; w_sel794w[1..0] : WIRE; BEGIN result[] = result_node[]; result_node[] = ( ((sel_node[2..2] & (((w_data793w[1..1] & w_sel794w[0..0]) & (! (((w_data793w[0..0] & (! w_sel794w[1..1])) & (! w_sel794w[0..0])) # (w_sel794w[1..1] & (w_sel794w[0..0] # w_data793w[2..2]))))) # ((((w_data793w[0..0] & (! w_sel794w[1..1])) & (! w_sel794w[0..0])) # (w_sel794w[1..1] & (w_sel794w[0..0] # w_data793w[2..2]))) & (w_data793w[3..3] # (! w_sel794w[0..0]))))) # ((! sel_node[2..2]) & (((w_data792w[1..1] & w_sel794w[0..0]) & (! (((w_data792w[0..0] & (! w_sel794w[1..1])) & (! w_sel794w[0..0])) # (w_sel794w[1..1] & (w_sel794w[0..0] # w_data792w[2..2]))))) # ((((w_data792w[0..0] & (! w_sel794w[1..1])) & (! w_sel794w[0..0])) # (w_sel794w[1..1] & (w_sel794w[0..0] # w_data792w[2..2]))) & (w_data792w[3..3] # (! w_sel794w[0..0])))))), ((sel_node[2..2] & (((w_data724w[1..1] & w_sel725w[0..0]) & (! (((w_data724w[0..0] & (! w_sel725w[1..1])) & (! w_sel725w[0..0])) # (w_sel725w[1..1] & (w_sel725w[0..0] # w_data724w[2..2]))))) # ((((w_data724w[0..0] & (! w_sel725w[1..1])) & (! w_sel725w[0..0])) # (w_sel725w[1..1] & (w_sel725w[0..0] # w_data724w[2..2]))) & (w_data724w[3..3] # (! w_sel725w[0..0]))))) # ((! sel_node[2..2]) & (((w_data723w[1..1] & w_sel725w[0..0]) & (! (((w_data723w[0..0] & (! w_sel725w[1..1])) & (! w_sel725w[0..0])) # (w_sel725w[1..1] & (w_sel725w[0..0] # w_data723w[2..2]))))) # ((((w_data723w[0..0] & (! w_sel725w[1..1])) & (! w_sel725w[0..0])) # (w_sel725w[1..1] & (w_sel725w[0..0] # w_data723w[2..2]))) & (w_data723w[3..3] # (! w_sel725w[0..0])))))), ((sel_node[2..2] & (((w_data655w[1..1] & w_sel656w[0..0]) & (! (((w_data655w[0..0] & (! w_sel656w[1..1])) & (! w_sel656w[0..0])) # (w_sel656w[1..1] & (w_sel656w[0..0] # w_data655w[2..2]))))) # ((((w_data655w[0..0] & (! w_sel656w[1..1])) & (! w_sel656w[0..0])) # (w_sel656w[1..1] & (w_sel656w[0..0] # w_data655w[2..2]))) & (w_data655w[3..3] # (! w_sel656w[0..0]))))) # ((! sel_node[2..2]) & (((w_data654w[1..1] & w_sel656w[0..0]) & (! (((w_data654w[0..0] & (! w_sel656w[1..1])) & (! w_sel656w[0..0])) # (w_sel656w[1..1] & (w_sel656w[0..0] # w_data654w[2..2]))))) # ((((w_data654w[0..0] & (! w_sel656w[1..1])) & (! w_sel656w[0..0])) # (w_sel656w[1..1] & (w_sel656w[0..0] # w_data654w[2..2]))) & (w_data654w[3..3] # (! w_sel656w[0..0])))))), ((sel_node[2..2] & (((w_data584w[1..1] & w_sel585w[0..0]) & (! (((w_data584w[0..0] & (! w_sel585w[1..1])) & (! w_sel585w[0..0])) # (w_sel585w[1..1] & (w_sel585w[0..0] # w_data584w[2..2]))))) # ((((w_data584w[0..0] & (! w_sel585w[1..1])) & (! w_sel585w[0..0])) # (w_sel585w[1..1] & (w_sel585w[0..0] # w_data584w[2..2]))) & (w_data584w[3..3] # (! w_sel585w[0..0]))))) # ((! sel_node[2..2]) & (((w_data583w[1..1] & w_sel585w[0..0]) & (! (((w_data583w[0..0] & (! w_sel585w[1..1])) & (! w_sel585w[0..0])) # (w_sel585w[1..1] & (w_sel585w[0..0] # w_data583w[2..2]))))) # ((((w_data583w[0..0] & (! w_sel585w[1..1])) & (! w_sel585w[0..0])) # (w_sel585w[1..1] & (w_sel585w[0..0] # w_data583w[2..2]))) & (w_data583w[3..3] # (! w_sel585w[0..0]))))))); sel_ffs_wire[] = ( sel[2..0]); sel_node[] = ( sel_ffs_wire[2..2], sel[1..0]); w_data561w[] = ( data[28..28], data[24..24], data[20..20], data[16..16], data[12..12], data[8..8], data[4..4], data[0..0]); w_data583w[3..0] = w_data561w[3..0]; w_data584w[3..0] = w_data561w[7..4]; w_data632w[] = ( data[29..29], data[25..25], data[21..21], data[17..17], data[13..13], data[9..9], data[5..5], data[1..1]); w_data654w[3..0] = w_data632w[3..0]; w_data655w[3..0] = w_data632w[7..4]; w_data701w[] = ( data[30..30], data[26..26], data[22..22], data[18..18], data[14..14], data[10..10], data[6..6], data[2..2]); w_data723w[3..0] = w_data701w[3..0]; w_data724w[3..0] = w_data701w[7..4]; w_data770w[] = ( data[31..31], data[27..27], data[23..23], data[19..19], data[15..15], data[11..11], data[7..7], data[3..3]); w_data792w[3..0] = w_data770w[3..0]; w_data793w[3..0] = w_data770w[7..4]; w_sel585w[1..0] = sel_node[1..0]; w_sel656w[1..0] = sel_node[1..0]; w_sel725w[1..0] = sel_node[1..0]; w_sel794w[1..0] = sel_node[1..0]; END; --VALID FILE