--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=4 LPM_WIDTH=6 LPM_WIDTHS=2 data result sel --VERSION_BEGIN 9.0 cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2009:01:29:16:12:07:SJ VERSION_END -- Copyright (C) 1991-2009 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. --synthesis_resources = lut 12 SUBDESIGN mux_jib ( data[23..0] : input; result[5..0] : output; sel[1..0] : input; ) VARIABLE result_node[5..0] : WIRE; sel_node[1..0] : WIRE; w_data344w[3..0] : WIRE; w_data374w[3..0] : WIRE; w_data399w[3..0] : WIRE; w_data424w[3..0] : WIRE; w_data449w[3..0] : WIRE; w_data474w[3..0] : WIRE; BEGIN result[] = result_node[]; result_node[] = ( (((w_data474w[1..1] & sel_node[0..0]) & (! (((w_data474w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data474w[2..2]))))) # ((((w_data474w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data474w[2..2]))) & (w_data474w[3..3] # (! sel_node[0..0])))), (((w_data449w[1..1] & sel_node[0..0]) & (! (((w_data449w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data449w[2..2]))))) # ((((w_data449w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data449w[2..2]))) & (w_data449w[3..3] # (! sel_node[0..0])))), (((w_data424w[1..1] & sel_node[0..0]) & (! (((w_data424w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data424w[2..2]))))) # ((((w_data424w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data424w[2..2]))) & (w_data424w[3..3] # (! sel_node[0..0])))), (((w_data399w[1..1] & sel_node[0..0]) & (! (((w_data399w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data399w[2..2]))))) # ((((w_data399w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data399w[2..2]))) & (w_data399w[3..3] # (! sel_node[0..0])))), (((w_data374w[1..1] & sel_node[0..0]) & (! (((w_data374w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data374w[2..2]))))) # ((((w_data374w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data374w[2..2]))) & (w_data374w[3..3] # (! sel_node[0..0])))), (((w_data344w[1..1] & sel_node[0..0]) & (! (((w_data344w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data344w[2..2]))))) # ((((w_data344w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data344w[2..2]))) & (w_data344w[3..3] # (! sel_node[0..0]))))); sel_node[] = ( sel[1..0]); w_data344w[] = ( data[18..18], data[12..12], data[6..6], data[0..0]); w_data374w[] = ( data[19..19], data[13..13], data[7..7], data[1..1]); w_data399w[] = ( data[20..20], data[14..14], data[8..8], data[2..2]); w_data424w[] = ( data[21..21], data[15..15], data[9..9], data[3..3]); w_data449w[] = ( data[22..22], data[16..16], data[10..10], data[4..4]); w_data474w[] = ( data[23..23], data[17..17], data[11..11], data[5..5]); END; --VALID FILE