--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_DECODES=8 LPM_WIDTH=3 data enable eq --VERSION_BEGIN 9.0 cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:12:09:22:11:50:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_mgl 2009:01:29:16:12:07:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ VERSION_END -- Copyright (C) 1991-2009 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. --synthesis_resources = lut 8 SUBDESIGN decode_9oa ( data[2..0] : input; enable : input; eq[7..0] : output; ) VARIABLE data_wire[2..0] : WIRE; enable_wire : WIRE; eq_node[7..0] : WIRE; eq_wire[7..0] : WIRE; w_anode465w[3..0] : WIRE; w_anode482w[3..0] : WIRE; w_anode492w[3..0] : WIRE; w_anode502w[3..0] : WIRE; w_anode512w[3..0] : WIRE; w_anode522w[3..0] : WIRE; w_anode532w[3..0] : WIRE; w_anode542w[3..0] : WIRE; BEGIN data_wire[] = data[]; enable_wire = enable; eq[] = eq_node[]; eq_node[7..0] = eq_wire[7..0]; eq_wire[] = ( w_anode542w[3..3], w_anode532w[3..3], w_anode522w[3..3], w_anode512w[3..3], w_anode502w[3..3], w_anode492w[3..3], w_anode482w[3..3], w_anode465w[3..3]); w_anode465w[] = ( (w_anode465w[2..2] & (! data_wire[2..2])), (w_anode465w[1..1] & (! data_wire[1..1])), (w_anode465w[0..0] & (! data_wire[0..0])), enable_wire); w_anode482w[] = ( (w_anode482w[2..2] & (! data_wire[2..2])), (w_anode482w[1..1] & (! data_wire[1..1])), (w_anode482w[0..0] & data_wire[0..0]), enable_wire); w_anode492w[] = ( (w_anode492w[2..2] & (! data_wire[2..2])), (w_anode492w[1..1] & data_wire[1..1]), (w_anode492w[0..0] & (! data_wire[0..0])), enable_wire); w_anode502w[] = ( (w_anode502w[2..2] & (! data_wire[2..2])), (w_anode502w[1..1] & data_wire[1..1]), (w_anode502w[0..0] & data_wire[0..0]), enable_wire); w_anode512w[] = ( (w_anode512w[2..2] & data_wire[2..2]), (w_anode512w[1..1] & (! data_wire[1..1])), (w_anode512w[0..0] & (! data_wire[0..0])), enable_wire); w_anode522w[] = ( (w_anode522w[2..2] & data_wire[2..2]), (w_anode522w[1..1] & (! data_wire[1..1])), (w_anode522w[0..0] & data_wire[0..0]), enable_wire); w_anode532w[] = ( (w_anode532w[2..2] & data_wire[2..2]), (w_anode532w[1..1] & data_wire[1..1]), (w_anode532w[0..0] & (! data_wire[0..0])), enable_wire); w_anode542w[] = ( (w_anode542w[2..2] & data_wire[2..2]), (w_anode542w[1..1] & data_wire[1..1]), (w_anode542w[0..0] & data_wire[0..0]), enable_wire); END; --VALID FILE