--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_DECODES=4 LPM_WIDTH=2 data enable eq
--VERSION_BEGIN 9.0 cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:12:09:22:11:50:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_mgl 2009:01:29:16:12:07:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ  VERSION_END


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--  (including device programming or simulation files), and any 
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--  without limitation, that your use is for the sole purpose of 
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--synthesis_resources = lut 4 
SUBDESIGN decode_4oa
( 
	data[1..0]	:	input;
	enable	:	input;
	eq[3..0]	:	output;
) 
VARIABLE 
	data_wire[1..0]	: WIRE;
	enable_wire	: WIRE;
	eq_node[3..0]	: WIRE;
	eq_wire[3..0]	: WIRE;
	w_anode441w[2..0]	: WIRE;
	w_anode454w[2..0]	: WIRE;
	w_anode462w[2..0]	: WIRE;
	w_anode470w[2..0]	: WIRE;

BEGIN 
	data_wire[] = data[];
	enable_wire = enable;
	eq[] = eq_node[];
	eq_node[3..0] = eq_wire[3..0];
	eq_wire[] = ( w_anode470w[2..2], w_anode462w[2..2], w_anode454w[2..2], w_anode441w[2..2]);
	w_anode441w[] = ( (w_anode441w[1..1] & (! data_wire[1..1])), (w_anode441w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode454w[] = ( (w_anode454w[1..1] & (! data_wire[1..1])), (w_anode454w[0..0] & data_wire[0..0]), enable_wire);
	w_anode462w[] = ( (w_anode462w[1..1] & data_wire[1..1]), (w_anode462w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode470w[] = ( (w_anode470w[1..1] & data_wire[1..1]), (w_anode470w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE