--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_WIDTH=3 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab
--VERSION_BEGIN 9.0 cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:12:09:22:11:50:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_mgl 2009:01:29:16:12:07:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ  VERSION_END


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--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  without limitation, that your use is for the sole purpose of 
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--  applicable agreement for further details.



--synthesis_resources = 
SUBDESIGN cmpr_7cc
( 
	aeb	:	output;
	dataa[2..0]	:	input;
	datab[2..0]	:	input;
) 
VARIABLE 
	data_wire[7..0]	: WIRE;
	eq_wire	: WIRE;
	result_wire[0..0]	: WIRE;

BEGIN 
	aeb = eq_wire;
	data_wire[] = ( datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[6..6] $ data_wire[7..7]), ((data_wire[2..2] $ data_wire[3..3]) # (data_wire[4..4] $ data_wire[5..5])));
	eq_wire = (! result_wire[]);
	result_wire[] = (data_wire[0..0] # data_wire[1..1]);
END;
--VALID FILE