--altsyncram ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" CYCLONEII_SAFE_WRITE="NO_CHANGE" DEVICE_FAMILY="Cyclone II" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=0 NUMWORDS_B=0 OPERATION_MODE="BIDIR_DUAL_PORT" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" WIDTH_A=5 WIDTH_B=5 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=14 WIDTHAD_B=14 WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 clocken0 clocken1 data_a data_b q_a wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 --VERSION_BEGIN 9.0 cbx_altsyncram 2008:11:06:10:05:41:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:12:09:22:11:50:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2009:01:29:16:12:07:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ cbx_stratixiii 2008:12:24:11:49:14:SJ cbx_util_mgl 2008:11:21:14:58:47:SJ VERSION_END -- Copyright (C) 1991-2009 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. FUNCTION decode_4oa (data[1..0], enable) RETURNS ( eq[3..0]); FUNCTION mux_iib (data[19..0], sel[1..0]) RETURNS ( result[4..0]); FUNCTION cycloneii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe) WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE) RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); --synthesis_resources = lut 20 M4K 20 reg 4 OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; SUBDESIGN altsyncram_udq1 ( address_a[13..0] : input; address_b[13..0] : input; clock0 : input; clock1 : input; clocken0 : input; clocken1 : input; data_a[4..0] : input; data_b[4..0] : input; q_a[4..0] : output; q_b[4..0] : output; wren_a : input; wren_b : input; ) VARIABLE address_reg_a[1..0] : dffe; address_reg_b[1..0] : dffe; decode3 : decode_4oa; decode4 : decode_4oa; decode_a : decode_4oa; decode_b : decode_4oa; mux5 : mux_iib; mux6 : mux_iib; ram_block2a0 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 4095, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 4095, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a1 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 4095, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 1, PORT_B_LAST_ADDRESS = 4095, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a2 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 2, PORT_A_LAST_ADDRESS = 4095, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 2, PORT_B_LAST_ADDRESS = 4095, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a3 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 3, PORT_A_LAST_ADDRESS = 4095, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 3, PORT_B_LAST_ADDRESS = 4095, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a4 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 4, PORT_A_LAST_ADDRESS = 4095, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 4, PORT_B_LAST_ADDRESS = 4095, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a5 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 4096, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 8191, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 4096, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 8191, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a6 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 4096, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 8191, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 4096, PORT_B_FIRST_BIT_NUMBER = 1, PORT_B_LAST_ADDRESS = 8191, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a7 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 4096, PORT_A_FIRST_BIT_NUMBER = 2, PORT_A_LAST_ADDRESS = 8191, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 4096, PORT_B_FIRST_BIT_NUMBER = 2, PORT_B_LAST_ADDRESS = 8191, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a8 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 4096, PORT_A_FIRST_BIT_NUMBER = 3, PORT_A_LAST_ADDRESS = 8191, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 4096, PORT_B_FIRST_BIT_NUMBER = 3, PORT_B_LAST_ADDRESS = 8191, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a9 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 4096, PORT_A_FIRST_BIT_NUMBER = 4, PORT_A_LAST_ADDRESS = 8191, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 4096, PORT_B_FIRST_BIT_NUMBER = 4, PORT_B_LAST_ADDRESS = 8191, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a10 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 8192, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 12287, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 8192, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 12287, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a11 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 8192, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 12287, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 8192, PORT_B_FIRST_BIT_NUMBER = 1, PORT_B_LAST_ADDRESS = 12287, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a12 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 8192, PORT_A_FIRST_BIT_NUMBER = 2, PORT_A_LAST_ADDRESS = 12287, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 8192, PORT_B_FIRST_BIT_NUMBER = 2, PORT_B_LAST_ADDRESS = 12287, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a13 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 8192, PORT_A_FIRST_BIT_NUMBER = 3, PORT_A_LAST_ADDRESS = 12287, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 8192, PORT_B_FIRST_BIT_NUMBER = 3, PORT_B_LAST_ADDRESS = 12287, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a14 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 8192, PORT_A_FIRST_BIT_NUMBER = 4, PORT_A_LAST_ADDRESS = 12287, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 8192, PORT_B_FIRST_BIT_NUMBER = 4, PORT_B_LAST_ADDRESS = 12287, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a15 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 12288, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 16383, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 12288, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 16383, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a16 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 12288, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 16383, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 12288, PORT_B_FIRST_BIT_NUMBER = 1, PORT_B_LAST_ADDRESS = 16383, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a17 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 12288, PORT_A_FIRST_BIT_NUMBER = 2, PORT_A_LAST_ADDRESS = 16383, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 12288, PORT_B_FIRST_BIT_NUMBER = 2, PORT_B_LAST_ADDRESS = 16383, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a18 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 12288, PORT_A_FIRST_BIT_NUMBER = 3, PORT_A_LAST_ADDRESS = 16383, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 12288, PORT_B_FIRST_BIT_NUMBER = 3, PORT_B_LAST_ADDRESS = 16383, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block2a19 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 12, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 12288, PORT_A_FIRST_BIT_NUMBER = 4, PORT_A_LAST_ADDRESS = 16383, PORT_A_LOGICAL_RAM_DEPTH = 16384, PORT_A_LOGICAL_RAM_WIDTH = 5, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 12288, PORT_B_FIRST_BIT_NUMBER = 4, PORT_B_LAST_ADDRESS = 16383, PORT_B_LOGICAL_RAM_DEPTH = 16384, PORT_B_LOGICAL_RAM_WIDTH = 5, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); address_a_sel[1..0] : WIRE; address_a_wire[13..0] : WIRE; address_b_sel[1..0] : WIRE; address_b_wire[13..0] : WIRE; BEGIN address_reg_a[].clk = clock0; address_reg_a[].d = address_a_sel[]; address_reg_a[].ena = clocken0; address_reg_b[].clk = clock1; address_reg_b[].d = address_b_sel[]; address_reg_b[].ena = clocken1; decode3.data[1..0] = address_a_wire[13..12]; decode3.enable = wren_a; decode4.data[1..0] = address_b_wire[13..12]; decode4.enable = wren_b; decode_a.data[1..0] = address_a_wire[13..12]; decode_a.enable = clocken0; decode_b.data[1..0] = address_b_wire[13..12]; decode_b.enable = clocken1; mux5.data[] = ( ram_block2a[19..0].portadataout[0..0]); mux5.sel[] = address_reg_a[].q; mux6.data[] = ( ram_block2a[19..0].portbdataout[0..0]); mux6.sel[] = address_reg_b[].q; ram_block2a[19..0].clk0 = clock0; ram_block2a[19..0].clk1 = clock1; ram_block2a[19..0].ena0 = ( decode_a.eq[3..3], decode_a.eq[3..3], decode_a.eq[3..3], decode_a.eq[3..3], decode_a.eq[3..2], decode_a.eq[2..2], decode_a.eq[2..2], decode_a.eq[2..2], decode_a.eq[2..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0]); ram_block2a[19..0].ena1 = ( decode_b.eq[3..3], decode_b.eq[3..3], decode_b.eq[3..3], decode_b.eq[3..3], decode_b.eq[3..2], decode_b.eq[2..2], decode_b.eq[2..2], decode_b.eq[2..2], decode_b.eq[2..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0]); ram_block2a[19..0].portaaddr[] = ( address_a_wire[11..0]); ram_block2a[0].portadatain[] = ( data_a[0..0]); ram_block2a[1].portadatain[] = ( data_a[1..1]); ram_block2a[2].portadatain[] = ( data_a[2..2]); ram_block2a[3].portadatain[] = ( data_a[3..3]); ram_block2a[4].portadatain[] = ( data_a[4..4]); ram_block2a[5].portadatain[] = ( data_a[0..0]); ram_block2a[6].portadatain[] = ( data_a[1..1]); ram_block2a[7].portadatain[] = ( data_a[2..2]); ram_block2a[8].portadatain[] = ( data_a[3..3]); ram_block2a[9].portadatain[] = ( data_a[4..4]); ram_block2a[10].portadatain[] = ( data_a[0..0]); ram_block2a[11].portadatain[] = ( data_a[1..1]); ram_block2a[12].portadatain[] = ( data_a[2..2]); ram_block2a[13].portadatain[] = ( data_a[3..3]); ram_block2a[14].portadatain[] = ( data_a[4..4]); ram_block2a[15].portadatain[] = ( data_a[0..0]); ram_block2a[16].portadatain[] = ( data_a[1..1]); ram_block2a[17].portadatain[] = ( data_a[2..2]); ram_block2a[18].portadatain[] = ( data_a[3..3]); ram_block2a[19].portadatain[] = ( data_a[4..4]); ram_block2a[19..0].portawe = ( decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]); ram_block2a[19..0].portbaddr[] = ( address_b_wire[11..0]); ram_block2a[0].portbdatain[] = ( data_b[0..0]); ram_block2a[1].portbdatain[] = ( data_b[1..1]); ram_block2a[2].portbdatain[] = ( data_b[2..2]); ram_block2a[3].portbdatain[] = ( data_b[3..3]); ram_block2a[4].portbdatain[] = ( data_b[4..4]); ram_block2a[5].portbdatain[] = ( data_b[0..0]); ram_block2a[6].portbdatain[] = ( data_b[1..1]); ram_block2a[7].portbdatain[] = ( data_b[2..2]); ram_block2a[8].portbdatain[] = ( data_b[3..3]); ram_block2a[9].portbdatain[] = ( data_b[4..4]); ram_block2a[10].portbdatain[] = ( data_b[0..0]); ram_block2a[11].portbdatain[] = ( data_b[1..1]); ram_block2a[12].portbdatain[] = ( data_b[2..2]); ram_block2a[13].portbdatain[] = ( data_b[3..3]); ram_block2a[14].portbdatain[] = ( data_b[4..4]); ram_block2a[15].portbdatain[] = ( data_b[0..0]); ram_block2a[16].portbdatain[] = ( data_b[1..1]); ram_block2a[17].portbdatain[] = ( data_b[2..2]); ram_block2a[18].portbdatain[] = ( data_b[3..3]); ram_block2a[19].portbdatain[] = ( data_b[4..4]); ram_block2a[19..0].portbrewe = ( decode4.eq[3..3], decode4.eq[3..3], decode4.eq[3..3], decode4.eq[3..3], decode4.eq[3..2], decode4.eq[2..2], decode4.eq[2..2], decode4.eq[2..2], decode4.eq[2..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0]); address_a_sel[1..0] = address_a[13..12]; address_a_wire[] = address_a[]; address_b_sel[1..0] = address_b[13..12]; address_b_wire[] = address_b[]; q_a[] = mux5.result[]; q_b[] = mux6.result[]; END; --VALID FILE