--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone II" INIT_FILE="Img_DATA.hex" INIT_FILE_LAYOUT="PORT_B" LOW_POWER_MODE="AUTO" NUMWORDS_A=208000 NUMWORDS_B=26000 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK1" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="M4K" WIDTH_A=1 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=18 WIDTHAD_B=15 address_a address_b clock0 clock1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 9.0 cbx_altsyncram 2008:11:06:10:05:41:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:12:09:22:11:50:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2009:01:29:16:12:07:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ cbx_stratixiii 2008:12:24:11:49:14:SJ cbx_util_mgl 2008:11:21:14:58:47:SJ  VERSION_END


-- Copyright (C) 1991-2009 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION altsyncram_e132 (address_a[14..0], address_b[17..0], clock0, clock1, clocken1, data_a[7..0], data_b[0..0], wren_a, wren_b)
RETURNS ( q_a[7..0], q_b[0..0]);

--synthesis_resources = lut 666 M4K 51 reg 18 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_f7o1
( 
	address_a[17..0]	:	input;
	address_b[14..0]	:	input;
	clock0	:	input;
	clock1	:	input;
	data_a[0..0]	:	input;
	q_b[7..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	altsyncram1 : altsyncram_e132;

BEGIN 
	altsyncram1.address_a[] = address_b[];
	altsyncram1.address_b[] = address_a[];
	altsyncram1.clock0 = clock1;
	altsyncram1.clock1 = clock0;
	altsyncram1.clocken1 = wren_a;
	altsyncram1.data_a[] = B"11111111";
	altsyncram1.data_b[] = data_a[];
	altsyncram1.wren_a = B"0";
	altsyncram1.wren_b = wren_a;
	q_b[] = altsyncram1.q_a[];
END;
--VALID FILE