--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" CYCLONEII_SAFE_WRITE="NO_CHANGE" DEVICE_FAMILY="Cyclone II" INIT_FILE="Img_DATA.hex" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" NUMWORDS_A=26000 NUMWORDS_B=208000 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="M4K" WIDTH_A=8 WIDTH_B=1 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=15 WIDTHAD_B=18 WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 clocken1 data_a data_b q_a wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 --VERSION_BEGIN 9.0 cbx_altsyncram 2008:11:06:10:05:41:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:12:09:22:11:50:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2009:01:29:16:12:07:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ cbx_stratixiii 2008:12:24:11:49:14:SJ cbx_util_mgl 2008:11:21:14:58:47:SJ VERSION_END -- Copyright (C) 1991-2009 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. FUNCTION decode_qpa (data[5..0], enable) RETURNS ( eq[50..0]); FUNCTION mux_akb (data[407..0], sel[5..0]) RETURNS ( result[7..0]); FUNCTION mux_3kb (data[50..0], sel[5..0]) RETURNS ( result[0..0]); FUNCTION cycloneii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe) WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE) RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); --synthesis_resources = lut 666 M4K 51 reg 18 OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; SUBDESIGN altsyncram_e132 ( address_a[14..0] : input; address_b[17..0] : input; clock0 : input; clock1 : input; clocken1 : input; data_a[7..0] : input; data_b[0..0] : input; q_a[7..0] : output; q_b[0..0] : output; wren_a : input; wren_b : input; ) VARIABLE address_reg_a[5..0] : dffe; address_reg_b[5..0] : dffe; out_address_reg_a[5..0] : dffe; decode3 : decode_qpa; decode4 : decode_qpa; decode_a : decode_qpa; decode_b : decode_qpa; mux5 : mux_akb; mux6 : mux_3kb; ram_block2a0 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 511, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 4095, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a1 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 512, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 4096, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 8191, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a2 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 1024, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 1535, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 8192, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 12287, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a3 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 1536, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 2047, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 12288, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 16383, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a4 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 2048, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 2559, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 16384, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 20479, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a5 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 2560, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 3071, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 20480, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 24575, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a6 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 3072, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 3583, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 24576, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 28671, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a7 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 3584, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 4095, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 28672, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 32767, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a8 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 4096, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 4607, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 32768, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 36863, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a9 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 4608, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 5119, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 36864, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 40959, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a10 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 5120, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 5631, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 40960, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 45055, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a11 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 5632, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 6143, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 45056, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 49151, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a12 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 6144, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 6655, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 49152, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 53247, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a13 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 6656, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 7167, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 53248, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 57343, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a14 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 7168, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 7679, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 57344, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 61439, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a15 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 7680, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 8191, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 61440, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 65535, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a16 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 8192, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 8703, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 65536, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 69631, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a17 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 8704, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 9215, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 69632, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 73727, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a18 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 9216, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 9727, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 73728, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 77823, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a19 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 9728, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 10239, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 77824, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 81919, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a20 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 10240, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 10751, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 81920, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 86015, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a21 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 10752, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 11263, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 86016, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 90111, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a22 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 11264, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 11775, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 90112, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 94207, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a23 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 11776, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 12287, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 94208, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 98303, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a24 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 12288, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 12799, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 98304, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 102399, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a25 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 12800, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 13311, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 102400, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 106495, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a26 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 13312, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 13823, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 106496, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 110591, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a27 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 13824, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 14335, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 110592, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 114687, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a28 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 14336, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 14847, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 114688, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 118783, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a29 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 14848, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 15359, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 118784, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 122879, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a30 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 15360, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 15871, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 122880, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 126975, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a31 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 15872, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 16383, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 126976, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 131071, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a32 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 16384, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 16895, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 131072, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 135167, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a33 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 16896, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 17407, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 135168, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 139263, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a34 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 17408, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 17919, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 139264, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 143359, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a35 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 17920, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 18431, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 143360, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 147455, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a36 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 18432, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 18943, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 147456, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 151551, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a37 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 18944, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 19455, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 151552, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 155647, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a38 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 19456, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 19967, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 155648, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 159743, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a39 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 19968, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 20479, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 159744, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 163839, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a40 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 20480, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 20991, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 163840, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 167935, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a41 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 20992, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 21503, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 167936, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 172031, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a42 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 21504, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 22015, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 172032, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 176127, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a43 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 22016, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 22527, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 176128, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 180223, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a44 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 22528, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 23039, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 180224, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 184319, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a45 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 23040, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 23551, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 184320, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 188415, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a46 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 23552, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 24063, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 188416, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 192511, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a47 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 24064, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 24575, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 192512, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 196607, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a48 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 24576, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 25087, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 196608, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 200703, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a49 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 25088, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 25599, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 200704, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 204799, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); ram_block2a50 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", DATA_INTERLEAVE_OFFSET_IN_BITS = 1, DATA_INTERLEAVE_WIDTH_IN_BITS = 1, INIT_FILE = "Img_DATA.hex", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 9, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "clock0", PORT_A_DATA_WIDTH = 8, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_A_FIRST_ADDRESS = 25600, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 25999, PORT_A_LOGICAL_RAM_DEPTH = 26000, PORT_A_LOGICAL_RAM_WIDTH = 8, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 12, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", PORT_B_FIRST_ADDRESS = 204800, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 207999, PORT_B_LOGICAL_RAM_DEPTH = 208000, PORT_B_LOGICAL_RAM_WIDTH = 1, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "M4K" ); address_a_sel[5..0] : WIRE; address_a_wire[14..0] : WIRE; address_b_sel[5..0] : WIRE; address_b_wire[17..0] : WIRE; BEGIN address_reg_a[].clk = clock0; address_reg_a[].d = address_a_sel[]; address_reg_b[].clk = clock1; address_reg_b[].d = address_b_sel[]; out_address_reg_a[].clk = clock0; out_address_reg_a[].d = address_reg_a[].q; decode3.data[5..0] = address_a_wire[14..9]; decode3.enable = wren_a; decode4.data[5..0] = address_b_wire[17..12]; decode4.enable = wren_b; decode_a.data[5..0] = address_a_wire[14..9]; decode_a.enable = B"1"; decode_b.data[5..0] = address_b_wire[17..12]; decode_b.enable = B"1"; mux5.data[] = ( ram_block2a[50..0].portadataout[7..0]); mux5.sel[] = out_address_reg_a[].q; mux6.data[] = ( ram_block2a[50..0].portbdataout[0..0]); mux6.sel[] = address_reg_b[].q; ram_block2a[50..0].clk0 = clock0; ram_block2a[50..0].clk1 = clock1; ram_block2a[50..0].ena0 = ( decode_a.eq[50..0]); ram_block2a[50..0].ena1 = ( decode_b.eq[50..0]); ram_block2a[50..0].portaaddr[] = ( address_a_wire[8..0]); ram_block2a[0].portadatain[] = ( data_a[7..0]); ram_block2a[1].portadatain[] = ( data_a[7..0]); ram_block2a[2].portadatain[] = ( data_a[7..0]); ram_block2a[3].portadatain[] = ( data_a[7..0]); ram_block2a[4].portadatain[] = ( data_a[7..0]); ram_block2a[5].portadatain[] = ( data_a[7..0]); ram_block2a[6].portadatain[] = ( data_a[7..0]); ram_block2a[7].portadatain[] = ( data_a[7..0]); ram_block2a[8].portadatain[] = ( data_a[7..0]); ram_block2a[9].portadatain[] = ( data_a[7..0]); ram_block2a[10].portadatain[] = ( data_a[7..0]); ram_block2a[11].portadatain[] = ( data_a[7..0]); ram_block2a[12].portadatain[] = ( data_a[7..0]); ram_block2a[13].portadatain[] = ( data_a[7..0]); ram_block2a[14].portadatain[] = ( data_a[7..0]); ram_block2a[15].portadatain[] = ( data_a[7..0]); ram_block2a[16].portadatain[] = ( data_a[7..0]); ram_block2a[17].portadatain[] = ( data_a[7..0]); ram_block2a[18].portadatain[] = ( data_a[7..0]); ram_block2a[19].portadatain[] = ( data_a[7..0]); ram_block2a[20].portadatain[] = ( data_a[7..0]); ram_block2a[21].portadatain[] = ( data_a[7..0]); ram_block2a[22].portadatain[] = ( data_a[7..0]); ram_block2a[23].portadatain[] = ( data_a[7..0]); ram_block2a[24].portadatain[] = ( data_a[7..0]); ram_block2a[25].portadatain[] = ( data_a[7..0]); ram_block2a[26].portadatain[] = ( data_a[7..0]); ram_block2a[27].portadatain[] = ( data_a[7..0]); ram_block2a[28].portadatain[] = ( data_a[7..0]); ram_block2a[29].portadatain[] = ( data_a[7..0]); ram_block2a[30].portadatain[] = ( data_a[7..0]); ram_block2a[31].portadatain[] = ( data_a[7..0]); ram_block2a[32].portadatain[] = ( data_a[7..0]); ram_block2a[33].portadatain[] = ( data_a[7..0]); ram_block2a[34].portadatain[] = ( data_a[7..0]); ram_block2a[35].portadatain[] = ( data_a[7..0]); ram_block2a[36].portadatain[] = ( data_a[7..0]); ram_block2a[37].portadatain[] = ( data_a[7..0]); ram_block2a[38].portadatain[] = ( data_a[7..0]); ram_block2a[39].portadatain[] = ( data_a[7..0]); ram_block2a[40].portadatain[] = ( data_a[7..0]); ram_block2a[41].portadatain[] = ( data_a[7..0]); ram_block2a[42].portadatain[] = ( data_a[7..0]); ram_block2a[43].portadatain[] = ( data_a[7..0]); ram_block2a[44].portadatain[] = ( data_a[7..0]); ram_block2a[45].portadatain[] = ( data_a[7..0]); ram_block2a[46].portadatain[] = ( data_a[7..0]); ram_block2a[47].portadatain[] = ( data_a[7..0]); ram_block2a[48].portadatain[] = ( data_a[7..0]); ram_block2a[49].portadatain[] = ( data_a[7..0]); ram_block2a[50].portadatain[] = ( data_a[7..0]); ram_block2a[50..0].portawe = ( decode3.eq[50..0]); ram_block2a[50..0].portbaddr[] = ( address_b_wire[11..0]); ram_block2a[50..0].portbdatain[] = ( data_b[0..0]); ram_block2a[50..0].portbrewe = ( decode4.eq[50..0]); address_a_sel[5..0] = address_a[14..9]; address_a_wire[] = address_a[]; address_b_sel[5..0] = address_b[17..12]; address_b_wire[] = address_b[]; q_a[] = mux5.result[]; q_b[] = mux6.result[]; END; --VALID FILE