Fitter report for DE1_Default Thu Mar 11 05:23:15 2010 Quartus II 64-Bit Version 9.0 Build 132 02/25/2009 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Fitter Summary 3. Fitter Settings 4. Parallel Compilation 5. Pin-Out File 6. Fitter Resource Usage Summary 7. Input Pins 8. Output Pins 9. I/O Bank Usage 10. All Package Pins 11. PLL Summary 12. PLL Usage 13. Output Pin Default Load For Reported TCO 14. Fitter Resource Utilization by Entity 15. Delay Chain Summary 16. Pad To Core Delay Chain Fanout 17. Control Signals 18. Global & Other Fast Signals 19. Non-Global High Fan-Out Signals 20. Fitter RAM Summary 21. Interconnect Usage Summary 22. LAB Logic Elements 23. LAB-wide Signals 24. LAB Signals Sourced 25. LAB Signals Sourced Out 26. LAB Distinct Inputs 27. Fitter Device Options 28. Operating Settings and Conditions 29. Estimated Delay Added for Hold Timing 30. Fitter Messages 31. Fitter Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2009 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Fitter Summary ; +------------------------------------+------------------------------------------+ ; Fitter Status ; Successful - Thu Mar 11 05:23:15 2010 ; ; Quartus II 64-Bit Version ; 9.0 Build 132 02/25/2009 SJ Full Version ; ; Revision Name ; DE1_Default ; ; Top-level Entity Name ; Block1 ; ; Family ; Cyclone II ; ; Device ; EP2C20F484C7 ; ; Timing Models ; Final ; ; Total logic elements ; 682 / 18,752 ( 4 % ) ; ; Total combinational functions ; 494 / 18,752 ( 3 % ) ; ; Dedicated logic registers ; 519 / 18,752 ( 3 % ) ; ; Total registers ; 519 ; ; Total pins ; 36 / 315 ( 11 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 98,304 / 239,616 ( 41 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; ; Total PLLs ; 1 / 4 ( 25 % ) ; +------------------------------------+------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------+ ; Fitter Settings ; +--------------------------------------------------------------------+--------------------------------+--------------------------------+ ; Option ; Setting ; Default Value ; +--------------------------------------------------------------------+--------------------------------+--------------------------------+ ; Device ; EP2C20F484C7 ; ; ; Fit Attempts to Skip ; 0 ; 0.0 ; ; Device I/O Standard ; 3.3-V LVTTL ; ; ; Use smart compilation ; Off ; Off ; ; Use TimeQuest Timing Analyzer ; Off ; Off ; ; Router Timing Optimization Level ; Normal ; Normal ; ; Placement Effort Multiplier ; 1.0 ; 1.0 ; ; Router Effort Multiplier ; 1.0 ; 1.0 ; ; Always Enable Input Buffers ; Off ; Off ; ; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; ; Optimize Multi-Corner Timing ; Off ; Off ; ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; ; Optimize Timing ; Normal compilation ; Normal compilation ; ; Optimize Timing for ECOs ; Off ; Off ; ; Regenerate full fit report during ECO compiles ; Off ; Off ; ; Optimize IOC Register Placement for Timing ; On ; On ; ; Limit to One Fitting Attempt ; Off ; Off ; ; Final Placement Optimizations ; Automatically ; Automatically ; ; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; ; Fitter Initial Placement Seed ; 1 ; 1 ; ; PCI I/O ; Off ; Off ; ; Weak Pull-Up Resistor ; Off ; Off ; ; Enable Bus-Hold Circuitry ; Off ; Off ; ; Auto Global Memory Control Signals ; Off ; Off ; ; Auto Packed Registers ; Auto ; Auto ; ; Auto Delay Chains ; On ; On ; ; Auto Merge PLLs ; On ; On ; ; Ignore PLL Mode When Merging PLLs ; Off ; Off ; ; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; ; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; ; Perform Register Duplication for Performance ; Off ; Off ; ; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; ; Perform Register Retiming for Performance ; Off ; Off ; ; Perform Asynchronous Signal Pipelining ; Off ; Off ; ; Fitter Effort ; Auto Fit ; Auto Fit ; ; Physical Synthesis Effort Level ; Normal ; Normal ; ; Auto Global Clock ; On ; On ; ; Auto Global Register Control Signals ; On ; On ; ; Stop After Congestion Map Generation ; Off ; Off ; ; Save Intermediate Fitting Results ; Off ; Off ; ; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +--------------------------------------------------------------------+--------------------------------+--------------------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; 1 processor ; 100.0% ; ; 2-4 processors ; < 0.1% ; +----------------------------+-------------+ +--------------+ ; Pin-Out File ; +--------------+ The pin-out file can be found in E:/.DATABANK/!!!Текущие разработки/DB ALTERA 2C20-START/DE1_demonstrations/DE1_Default/DE1_Default.pin. +--------------------------------------------------------------------------------------------------------------------------------------+ ; Fitter Resource Usage Summary ; +---------------------------------------------+----------------------------------------------------------------------------------------+ ; Resource ; Usage ; +---------------------------------------------+----------------------------------------------------------------------------------------+ ; Total logic elements ; 682 / 18,752 ( 4 % ) ; ; -- Combinational with no register ; 163 ; ; -- Register only ; 188 ; ; -- Combinational with a register ; 331 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 180 ; ; -- 3 input functions ; 183 ; ; -- <=2 input functions ; 131 ; ; -- Register only ; 188 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 413 ; ; -- arithmetic mode ; 81 ; ; ; ; ; Total registers* ; 519 / 19,649 ( 3 % ) ; ; -- Dedicated logic registers ; 519 / 18,752 ( 3 % ) ; ; -- I/O registers ; 0 / 897 ( 0 % ) ; ; ; ; ; Total LABs: partially or completely used ; 77 / 1,172 ( 7 % ) ; ; User inserted logic elements ; 0 ; ; Virtual pins ; 0 ; ; I/O pins ; 36 / 315 ( 11 % ) ; ; -- Clock pins ; 1 / 8 ( 13 % ) ; ; Global signals ; 8 ; ; M4Ks ; 24 / 52 ( 46 % ) ; ; Total block memory bits ; 98,304 / 239,616 ( 41 % ) ; ; Total block memory implementation bits ; 110,592 / 239,616 ( 46 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; ; PLLs ; 1 / 4 ( 25 % ) ; ; Global clocks ; 8 / 16 ( 50 % ) ; ; JTAGs ; 1 / 1 ( 100 % ) ; ; ASMI blocks ; 0 / 1 ( 0 % ) ; ; CRC blocks ; 0 / 1 ( 0 % ) ; ; Average interconnect usage (total/H/V) ; 1% / 1% / 1% ; ; Peak interconnect usage (total/H/V) ; 3% / 3% / 3% ; ; Maximum fan-out node ; altera_internal_jtag~TCKUTAPclkctrl ; ; Maximum fan-out ; 307 ; ; Highest non-global fan-out signal ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|trigger_setup_ena ; ; Highest non-global fan-out ; 64 ; ; Total fan-out ; 4040 ; ; Average fan-out ; 3.30 ; +---------------------------------------------+----------------------------------------------------------------------------------------+ * Register count does not include registers inside RAM blocks or DSP blocks. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Input Pins ; +-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; +-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ ; CLOCK_24[0] ; B12 ; 4 ; 24 ; 27 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; ; GPIO_0[0] ; A13 ; 4 ; 26 ; 27 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; ; GPIO_0[1] ; B13 ; 4 ; 26 ; 27 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; ; GPIO_0[2] ; A14 ; 4 ; 29 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; ; KEY[2] ; T22 ; 6 ; 50 ; 9 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Output Pins ; +---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; +---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+ ; HEX0[0] ; J2 ; 2 ; 0 ; 18 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX0[1] ; J1 ; 2 ; 0 ; 18 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX0[2] ; H2 ; 2 ; 0 ; 19 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX0[3] ; H1 ; 2 ; 0 ; 19 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX0[4] ; F2 ; 2 ; 0 ; 20 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX0[5] ; F1 ; 2 ; 0 ; 20 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX0[6] ; E2 ; 2 ; 0 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX1[0] ; E1 ; 2 ; 0 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX1[1] ; H6 ; 2 ; 0 ; 21 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX1[2] ; H5 ; 2 ; 0 ; 21 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX1[3] ; H4 ; 2 ; 0 ; 21 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX1[4] ; G3 ; 2 ; 0 ; 21 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX1[5] ; D2 ; 2 ; 0 ; 22 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX1[6] ; D1 ; 2 ; 0 ; 22 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX2[0] ; G5 ; 2 ; 0 ; 22 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX2[1] ; G6 ; 2 ; 0 ; 23 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX2[2] ; C2 ; 2 ; 0 ; 23 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX2[3] ; C1 ; 2 ; 0 ; 23 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX2[4] ; E3 ; 2 ; 0 ; 24 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX2[5] ; E4 ; 2 ; 0 ; 24 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX2[6] ; D3 ; 2 ; 0 ; 25 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX3[0] ; F4 ; 2 ; 0 ; 23 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX3[1] ; D5 ; 2 ; 0 ; 24 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX3[2] ; D6 ; 2 ; 0 ; 24 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX3[3] ; J4 ; 2 ; 0 ; 18 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX3[4] ; L8 ; 2 ; 0 ; 19 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX3[5] ; F3 ; 2 ; 0 ; 22 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; HEX3[6] ; D4 ; 2 ; 0 ; 25 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; LEDG[0] ; U22 ; 6 ; 50 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; LEDG[1] ; U21 ; 6 ; 50 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; ; LEDG[4] ; W22 ; 6 ; 50 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 20 pF ; +---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+ +------------------------------------------------------------+ ; I/O Bank Usage ; +----------+------------------+---------------+--------------+ ; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; +----------+------------------+---------------+--------------+ ; 1 ; 0 / 41 ( 0 % ) ; 3.3V ; -- ; ; 2 ; 30 / 33 ( 91 % ) ; 3.3V ; -- ; ; 3 ; 0 / 43 ( 0 % ) ; 3.3V ; -- ; ; 4 ; 4 / 40 ( 10 % ) ; 3.3V ; -- ; ; 5 ; 0 / 39 ( 0 % ) ; 3.3V ; -- ; ; 6 ; 5 / 36 ( 14 % ) ; 3.3V ; -- ; ; 7 ; 0 / 40 ( 0 % ) ; 3.3V ; -- ; ; 8 ; 0 / 43 ( 0 % ) ; 3.3V ; -- ; +----------+------------------+---------------+--------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; All Package Pins ; +----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ ; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; +----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ ; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; A2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; A3 ; 325 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; A4 ; 324 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; A5 ; 322 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; A6 ; 320 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; A7 ; 306 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; A8 ; 304 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; A9 ; 298 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; A10 ; 293 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; A11 ; 287 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; A12 ; 283 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; ; A13 ; 281 ; 4 ; GPIO_0[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ; A14 ; 279 ; 4 ; GPIO_0[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ; A15 ; 273 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; A16 ; 271 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; A17 ; 265 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; A18 ; 251 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; A19 ; 249 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; A20 ; 247 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; A21 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AA1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AA3 ; 82 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA4 ; 85 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA5 ; 89 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA6 ; 97 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA7 ; 103 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA8 ; 111 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA9 ; 114 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA10 ; 120 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA11 ; 122 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA12 ; 128 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA13 ; 130 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA14 ; 136 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA15 ; 138 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA16 ; 140 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA17 ; 144 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA18 ; 153 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA19 ; 162 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA20 ; 164 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AA22 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AB2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; AB3 ; 83 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB4 ; 84 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB5 ; 88 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB6 ; 96 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB7 ; 102 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB8 ; 110 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB9 ; 113 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB10 ; 119 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB11 ; 121 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB12 ; 127 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB13 ; 129 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB14 ; 135 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB15 ; 137 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB16 ; 139 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB17 ; 143 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB18 ; 152 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB19 ; 161 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB20 ; 163 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; AB21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; B1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; B3 ; 326 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B4 ; 323 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B5 ; 321 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B6 ; 319 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B7 ; 305 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B8 ; 303 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B9 ; 297 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B10 ; 292 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B11 ; 286 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B12 ; 282 ; 4 ; CLOCK_24[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ; B13 ; 280 ; 4 ; GPIO_0[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ; B14 ; 278 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B15 ; 272 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B16 ; 270 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B17 ; 264 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B18 ; 250 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B19 ; 248 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B20 ; 246 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; B22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; C1 ; 8 ; 2 ; HEX2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; C2 ; 9 ; 2 ; HEX2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; C3 ; 1 ; 2 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; ; C4 ; 0 ; 2 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; ; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; C6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; C7 ; 315 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; C8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; C9 ; 310 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; C10 ; 296 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; C11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; C12 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; C13 ; 275 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; C14 ; 260 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; C15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; C16 ; 254 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; C17 ; 245 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; C18 ; 244 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; C19 ; 238 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; C20 ; 239 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; C21 ; 236 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; C22 ; 237 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; D1 ; 14 ; 2 ; HEX1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; D2 ; 15 ; 2 ; HEX1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; D3 ; 2 ; 2 ; HEX2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; D4 ; 3 ; 2 ; HEX3[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; D5 ; 4 ; 2 ; HEX3[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; D6 ; 5 ; 2 ; HEX3[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; D7 ; 311 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; D8 ; 309 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; D9 ; 302 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; D11 ; 289 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; D12 ; 284 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; ; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; D14 ; 267 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; D15 ; 259 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; D16 ; 255 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; D17 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; D18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; D19 ; 240 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; D20 ; 241 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; D21 ; 229 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; D22 ; 230 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; E1 ; 20 ; 2 ; HEX1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; E2 ; 21 ; 2 ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; E3 ; 6 ; 2 ; HEX2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; E4 ; 7 ; 2 ; HEX2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; E5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; E6 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; E7 ; 316 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; E8 ; 308 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; E9 ; 301 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; E10 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; E11 ; 288 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; E12 ; 285 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; ; E13 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; E14 ; 266 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; E15 ; 256 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; E16 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; ; E17 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; ; E18 ; 243 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; E19 ; 242 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; E20 ; 234 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; E21 ; 227 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; E22 ; 228 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; F1 ; 22 ; 2 ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; F2 ; 23 ; 2 ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; F3 ; 13 ; 2 ; HEX3[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; F4 ; 10 ; 2 ; HEX3[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; F5 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; ; F6 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; ; F7 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; ; F8 ; 312 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; F9 ; 307 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; F10 ; 295 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; F11 ; 294 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; F12 ; 276 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; F13 ; 269 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; F14 ; 268 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; F15 ; 262 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; F16 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; F17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; F18 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; ; F19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; F20 ; 235 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; F21 ; 223 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; F22 ; 224 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; G1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; G2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; G3 ; 16 ; 2 ; HEX1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; G5 ; 12 ; 2 ; HEX2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; G6 ; 11 ; 2 ; HEX2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; G7 ; 317 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; G8 ; 313 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; G9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; G10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; G11 ; 291 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; G12 ; 277 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; G14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; G15 ; 261 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; G16 ; 252 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; G17 ; 231 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; G18 ; 232 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; G19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; G20 ; 233 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; G21 ; 221 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; G22 ; 222 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; H1 ; 24 ; 2 ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; H2 ; 25 ; 2 ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; H3 ; 27 ; 2 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; H4 ; 17 ; 2 ; HEX1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; H5 ; 18 ; 2 ; HEX1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; H6 ; 19 ; 2 ; HEX1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; H7 ; 318 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; H8 ; 314 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; H9 ; 300 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; H10 ; 299 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; H11 ; 290 ; 3 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; H12 ; 274 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; H13 ; 263 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; H14 ; 257 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; H15 ; 253 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; H16 ; 219 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; H17 ; 226 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; H18 ; 225 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; H19 ; 214 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; H21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; H22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; J1 ; 29 ; 2 ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; J2 ; 30 ; 2 ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; J3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; J4 ; 28 ; 2 ; HEX3[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; J5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; J6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; J7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; J8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; J9 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; J14 ; 258 ; 4 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; J15 ; 220 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; J16 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; J17 ; 218 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; J18 ; 217 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; J19 ; 216 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; J20 ; 213 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; J21 ; 211 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; J22 ; 212 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; K1 ; 37 ; 2 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; ; K2 ; 32 ; 2 ; altera_reserved_tck ; input ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; ; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K4 ; 36 ; 2 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; ; K5 ; 31 ; 2 ; altera_reserved_tdi ; input ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; ; K6 ; 33 ; 2 ; altera_reserved_tms ; input ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; ; K7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; K15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; K18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K20 ; 215 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; K21 ; 209 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; K22 ; 210 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; L1 ; 38 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; L2 ; 39 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; L3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; L4 ; 40 ; 2 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; ; L5 ; 34 ; 2 ; altera_reserved_tdo ; output ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; ; L6 ; 35 ; 2 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; ; L7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; L8 ; 26 ; 2 ; HEX3[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; L15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; L16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; L17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; L18 ; 208 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; L19 ; 207 ; 5 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; L20 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; L21 ; 205 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; L22 ; 206 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; M1 ; 41 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; M2 ; 42 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; M3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; M5 ; 43 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; M6 ; 44 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; M7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; M8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; M15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; M16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; M17 ; 198 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; ; M18 ; 202 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; M19 ; 201 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; M20 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; M21 ; 203 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; M22 ; 204 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; N1 ; 45 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; N2 ; 46 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; N3 ; 51 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; N4 ; 52 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; N5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; N6 ; 49 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; N15 ; 194 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N17 ; 197 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; ; N18 ; 196 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; ; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N20 ; 195 ; 6 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; ; N21 ; 199 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; N22 ; 200 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; P1 ; 47 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; P2 ; 48 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; P3 ; 50 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; P4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; P5 ; 55 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; P6 ; 56 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; P7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; P8 ; 95 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; P9 ; 94 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; P14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; P15 ; 193 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; P16 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; P17 ; 186 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; P18 ; 187 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; P19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; P20 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; P21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; P22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; R1 ; 57 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; R2 ; 58 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; R4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; R5 ; 63 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; R6 ; 64 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; R7 ; 54 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; R8 ; 53 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; R9 ; 109 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; R10 ; 108 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; R11 ; 116 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; R12 ; 134 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; R13 ; 145 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; R14 ; 150 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; R15 ; 151 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; R16 ; 155 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; R17 ; 177 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; R18 ; 184 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; R19 ; 185 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; R20 ; 192 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; R21 ; 190 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; R22 ; 191 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; T1 ; 59 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; T2 ; 60 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; T3 ; 69 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; T4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; T5 ; 67 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; T6 ; 68 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; T7 ; 91 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; T8 ; 90 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; T9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; T11 ; 115 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; T12 ; 131 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; T13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; T14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; T15 ; 147 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; T16 ; 156 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; T17 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; ; T18 ; 171 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; T19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; T21 ; 188 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; T22 ; 189 ; 6 ; KEY[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; U1 ; 61 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; U2 ; 62 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; U3 ; 70 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; U4 ; 80 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; U5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; ; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; U7 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; U8 ; 92 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; U9 ; 106 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; U10 ; 107 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; U11 ; 123 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; ; U12 ; 124 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; ; U13 ; 132 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; U14 ; 146 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; U15 ; 157 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; U16 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; U17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; U18 ; 170 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; U19 ; 172 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; U20 ; 176 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; U21 ; 182 ; 6 ; LEDG[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; U22 ; 183 ; 6 ; LEDG[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; V1 ; 65 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; V2 ; 66 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; V4 ; 81 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; V5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; ; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; V7 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; ; V8 ; 98 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; V9 ; 101 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; V10 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; V11 ; 118 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; V12 ; 126 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; ; V13 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; V14 ; 142 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; V15 ; 158 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; V16 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; ; V17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; V18 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; ; V19 ; 166 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; V20 ; 173 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; V21 ; 180 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; V22 ; 181 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; W1 ; 71 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; W2 ; 72 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; W3 ; 75 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; W4 ; 76 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; W5 ; 79 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; W6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; W7 ; 99 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; W8 ; 100 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; W9 ; 105 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; W10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; W11 ; 117 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; W12 ; 125 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; ; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; W14 ; 141 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; W15 ; 149 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; W16 ; 160 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; W17 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; W18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; W20 ; 167 ; 6 ; ~LVDS91p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; W21 ; 174 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; W22 ; 175 ; 6 ; LEDG[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; Y1 ; 73 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; Y2 ; 74 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; Y3 ; 77 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; Y4 ; 78 ; 1 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; Y5 ; 86 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; Y6 ; 87 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; Y7 ; 93 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; Y9 ; 104 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; Y10 ; 112 ; 8 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; Y11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; Y12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; Y13 ; 133 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; Y14 ; 148 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; Y16 ; 154 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; Y17 ; 159 ; 7 ; RESERVED ; ; ; ; Column I/O ; ; no ; Off ; ; Y18 ; 165 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; Y19 ; 168 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; Y20 ; 169 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; Y21 ; 178 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; ; Y22 ; 179 ; 6 ; RESERVED ; ; ; ; Row I/O ; ; no ; Off ; +----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ Note: Pin directions (input, output or bidir) are based on device operating in user mode. +----------------------------------------------------------------------------+ ; PLL Summary ; +----------------------------------+-----------------------------------------+ ; Name ; plld:inst17|altpll:altpll_component|pll ; +----------------------------------+-----------------------------------------+ ; SDC pin name ; inst17|altpll_component|pll ; ; PLL mode ; Normal ; ; Compensate clock ; clock0 ; ; Compensated input/output pins ; -- ; ; Self reset on gated loss of lock ; Off ; ; Gate lock counter ; -- ; ; Input frequency 0 ; 24.0 MHz ; ; Input frequency 1 ; -- ; ; Nominal PFD frequency ; 12.0 MHz ; ; Nominal VCO frequency ; 300.0 MHz ; ; VCO post scale ; 2 ; ; VCO multiply ; -- ; ; VCO divide ; -- ; ; Freq min lock ; 24.0 MHz ; ; Freq max lock ; 40.0 MHz ; ; M VCO Tap ; 0 ; ; M Initial ; 1 ; ; M value ; 25 ; ; N value ; 2 ; ; Preserve PLL counter order ; Off ; ; PLL location ; PLL_3 ; ; Inclk0 signal ; CLOCK_24[0] ; ; Inclk1 signal ; -- ; ; Inclk0 signal type ; Dedicated Pin ; ; Inclk1 signal type ; -- ; +----------------------------------+-----------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; PLL Usage ; +-------------------------------------------+--------------+------+-----+------------------+-------------+------------+---------+---------------+------------+---------+---------+------------------------------------+ ; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Initial ; VCO Tap ; SDC Pin Name ; +-------------------------------------------+--------------+------+-----+------------------+-------------+------------+---------+---------------+------------+---------+---------+------------------------------------+ ; plld:inst17|altpll:altpll_component|_clk0 ; clock0 ; 5 ; 12 ; 10.0 MHz ; 0 (0 ps) ; 50/50 ; C0 ; 30 ; 15/15 Even ; 1 ; 0 ; inst17|altpll_component|pll|clk[0] ; +-------------------------------------------+--------------+------+-----+------------------+-------------+------------+---------+---------------+------------+---------+---------+------------------------------------+ +-------------------------------------------------------------------------------+ ; Output Pin Default Load For Reported TCO ; +----------------------------------+-------+------------------------------------+ ; I/O Standard ; Load ; Termination Resistance ; +----------------------------------+-------+------------------------------------+ ; 3.3-V LVTTL ; 0 pF ; Not Available ; ; 3.3-V LVCMOS ; 0 pF ; Not Available ; ; 2.5 V ; 0 pF ; Not Available ; ; 1.8 V ; 0 pF ; Not Available ; ; 1.5 V ; 0 pF ; Not Available ; ; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; ; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; ; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; ; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; ; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; ; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; ; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; ; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; ; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; ; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; ; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; ; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; ; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; ; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; ; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; ; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; ; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; ; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; ; LVDS ; 0 pF ; 100 Ohm (Differential) ; ; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; ; RSDS ; 0 pF ; 100 Ohm (Differential) ; ; Simple RSDS ; 0 pF ; Not Available ; ; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; +----------------------------------+-------+------------------------------------+ Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fitter Resource Utilization by Entity ; +------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; +------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ ; |Block1 ; 682 (1) ; 519 (0) ; 0 (0) ; 98304 ; 24 ; 0 ; 0 ; 0 ; 36 ; 0 ; 163 (1) ; 188 (0) ; 331 (0) ; |Block1 ; work ; ; |QuadratureDecoderPorts:inst27| ; 19 (19) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (9) ; 1 (1) ; 9 (9) ; |Block1|QuadratureDecoderPorts:inst27 ; work ; ; |SEG7_LUT_4:inst8| ; 14 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (0) ; 0 (0) ; 0 (0) ; |Block1|SEG7_LUT_4:inst8 ; work ; ; |SEG7_LUT:u0| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; |Block1|SEG7_LUT_4:inst8|SEG7_LUT:u0 ; work ; ; |SEG7_LUT:u1| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; |Block1|SEG7_LUT_4:inst8|SEG7_LUT:u1 ; work ; ; |lpm_counter0:inst| ; 8 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (0) ; |Block1|lpm_counter0:inst ; work ; ; |lpm_counter:lpm_counter_component| ; 8 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (0) ; |Block1|lpm_counter0:inst|lpm_counter:lpm_counter_component ; work ; ; |cntr_7cg:auto_generated| ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; |Block1|lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_7cg:auto_generated ; work ; ; |lpm_counter1:inst18| ; 11 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 2 (0) ; 7 (0) ; |Block1|lpm_counter1:inst18 ; work ; ; |lpm_counter:lpm_counter_component| ; 11 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 2 (0) ; 7 (0) ; |Block1|lpm_counter1:inst18|lpm_counter:lpm_counter_component ; work ; ; |cntr_6mh:auto_generated| ; 11 (11) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 2 (2) ; 7 (7) ; |Block1|lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated ; work ; ; |plld:inst17| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |Block1|plld:inst17 ; work ; ; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |Block1|plld:inst17|altpll:altpll_component ; work ; ; |sld_hub:sld_hub_inst| ; 117 (78) ; 73 (45) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 43 (30) ; 8 (8) ; 66 (41) ; |Block1|sld_hub:sld_hub_inst ; work ; ; |sld_rom_sr:hub_info_reg| ; 22 (22) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 9 (9) ; |Block1|sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg ; work ; ; |sld_shadow_jsm:shadow_jsm| ; 19 (19) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 19 (19) ; |Block1|sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm ; work ; ; |sld_signaltap:auto_signaltap_0| ; 513 (0) ; 419 (0) ; 0 (0) ; 98304 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 94 (0) ; 177 (0) ; 242 (0) ; |Block1|sld_signaltap:auto_signaltap_0 ; work ; ; |sld_signaltap_impl:sld_signaltap_body| ; 513 (60) ; 419 (55) ; 0 (0) ; 98304 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 94 (5) ; 177 (42) ; 242 (5) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body ; work ; ; |altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem| ; 90 (88) ; 88 (88) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 59 (59) ; 30 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem ; work ; ; |lpm_decode:wdecoder| ; 2 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 1 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder ; work ; ; |decode_rqf:auto_generated| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 1 (1) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_rqf:auto_generated ; work ; ; |lpm_mux:mux| ; 29 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 29 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux ; work ; ; |mux_foc:auto_generated| ; 29 (29) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 29 (29) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux|mux_foc:auto_generated ; work ; ; |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram| ; 18 (0) ; 2 (0) ; 0 (0) ; 98304 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (0) ; 0 (0) ; 4 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram ; work ; ; |altsyncram_j4p3:auto_generated| ; 18 (0) ; 2 (0) ; 0 (0) ; 98304 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (0) ; 0 (0) ; 4 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_j4p3:auto_generated ; work ; ; |altsyncram_vdq1:altsyncram1| ; 18 (2) ; 2 (2) ; 0 (0) ; 98304 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (0) ; 0 (0) ; 4 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_j4p3:auto_generated|altsyncram_vdq1:altsyncram1 ; work ; ; |decode_4oa:decode4| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_j4p3:auto_generated|altsyncram_vdq1:altsyncram1|decode_4oa:decode4 ; work ; ; |decode_4oa:decode_a| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_j4p3:auto_generated|altsyncram_vdq1:altsyncram1|decode_4oa:decode_a ; work ; ; |mux_jib:mux5| ; 10 (10) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 2 (2) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_j4p3:auto_generated|altsyncram_vdq1:altsyncram1|mux_jib:mux5 ; work ; ; |lpm_shiftreg:segment_offset_config_deserialize| ; 14 (14) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 6 (6) ; 8 (8) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize ; work ; ; |lpm_shiftreg:status_register| ; 19 (19) ; 17 (17) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 17 (17) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|lpm_shiftreg:status_register ; work ; ; |sld_buffer_manager:sld_buffer_manager_inst| ; 129 (129) ; 79 (79) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 41 (41) ; 23 (23) ; 65 (65) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst ; work ; ; |sld_ela_control:ela_control| ; 78 (1) ; 69 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 47 (0) ; 26 (1) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control ; work ; ; |lpm_shiftreg:trigger_config_deserialize| ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize ; work ; ; |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 55 (0) ; 51 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 35 (0) ; 20 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm ; work ; ; |lpm_shiftreg:trigger_condition_deserialize| ; 36 (36) ; 36 (36) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 32 (32) ; 4 (4) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize ; work ; ; |sld_mbpmg:\trigger_modules_gen:0:trigger_match| ; 10 (0) ; 6 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 10 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1| ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1| ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1| ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1| ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1 ; work ; ; |sld_mbpmg:\trigger_modules_gen:1:trigger_match| ; 13 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 3 (0) ; 10 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:1:trigger_match ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1| ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:1:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1| ; 3 (3) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 2 (2) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:1:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:1:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:1:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1| ; 3 (3) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 2 (2) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:1:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1 ; work ; ; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1| ; 3 (3) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 2 (2) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:1:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1 ; work ; ; |sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity| ; 18 (8) ; 13 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 8 (0) ; 5 (4) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity ; work ; ; |lpm_shiftreg:trigger_config_deserialize| ; 10 (10) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 8 (8) ; 2 (2) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|lpm_shiftreg:trigger_config_deserialize ; work ; ; |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst| ; 104 (9) ; 87 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 17 (9) ; 0 (0) ; 87 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst ; work ; ; |lpm_counter:\adv_point_3_and_more:advance_pointer_counter| ; 5 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 3 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter ; work ; ; |cntr_bai:auto_generated| ; 5 (5) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 3 (3) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_bai:auto_generated ; work ; ; |lpm_counter:read_pointer_counter| ; 14 (0) ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 14 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter ; work ; ; |cntr_p6j:auto_generated| ; 14 (14) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 14 (14) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_p6j:auto_generated ; work ; ; |lpm_counter:status_advance_pointer_counter| ; 7 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 5 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter ; work ; ; |cntr_2ci:auto_generated| ; 7 (7) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 5 (5) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_2ci:auto_generated ; work ; ; |lpm_counter:status_read_pointer_counter| ; 3 (0) ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 1 (0) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter ; work ; ; |cntr_gui:auto_generated| ; 3 (3) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 1 (1) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_gui:auto_generated ; work ; ; |lpm_shiftreg:info_data_shift_out| ; 29 (29) ; 29 (29) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 29 (29) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out ; work ; ; |lpm_shiftreg:ram_data_shift_out| ; 8 (8) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 6 (6) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out ; work ; ; |lpm_shiftreg:status_data_shift_out| ; 29 (29) ; 29 (29) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 29 (29) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out ; work ; ; |sld_rom_sr:crc_rom_sr| ; 17 (17) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (9) ; 0 (0) ; 8 (8) ; |Block1|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr ; work ; +------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +--------------------------------------------------------------------------------------+ ; Delay Chain Summary ; +-------------+----------+---------------+---------------+-----------------------+-----+ ; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; +-------------+----------+---------------+---------------+-----------------------+-----+ ; GPIO_0[2] ; Input ; 0 ; 0 ; -- ; -- ; ; GPIO_0[0] ; Input ; 6 ; 6 ; -- ; -- ; ; GPIO_0[1] ; Input ; 6 ; 6 ; -- ; -- ; ; KEY[2] ; Input ; 6 ; 6 ; -- ; -- ; ; CLOCK_24[0] ; Input ; -- ; -- ; -- ; -- ; ; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; ; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; ; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; ; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; ; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; ; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; ; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; ; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; ; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; ; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; ; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; ; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; ; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; ; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; ; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; ; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; ; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; ; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; ; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; ; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; ; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; ; HEX3[6] ; Output ; -- ; -- ; -- ; -- ; ; HEX3[5] ; Output ; -- ; -- ; -- ; -- ; ; HEX3[4] ; Output ; -- ; -- ; -- ; -- ; ; HEX3[3] ; Output ; -- ; -- ; -- ; -- ; ; HEX3[2] ; Output ; -- ; -- ; -- ; -- ; ; HEX3[1] ; Output ; -- ; -- ; -- ; -- ; ; HEX3[0] ; Output ; -- ; -- ; -- ; -- ; ; LEDG[1] ; Output ; -- ; -- ; -- ; -- ; ; LEDG[0] ; Output ; -- ; -- ; -- ; -- ; ; LEDG[4] ; Output ; -- ; -- ; -- ; -- ; +-------------+----------+---------------+---------------+-----------------------+-----+ +---------------------------------------------------------------------------------------------------------------------------------+ ; Pad To Core Delay Chain Fanout ; +---------------------------------------------------------------------------------------------------+-------------------+---------+ ; Source Pin / Fanout ; Pad To Core Index ; Setting ; +---------------------------------------------------------------------------------------------------+-------------------+---------+ ; GPIO_0[2] ; ; ; ; GPIO_0[0] ; ; ; ; - LEDG[1] ; 0 ; 6 ; ; - QuadratureDecoderPorts:inst27|Quad[1] ; 0 ; 6 ; ; - sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1] ; 0 ; 6 ; ; GPIO_0[1] ; ; ; ; - LEDG[0] ; 0 ; 6 ; ; - QuadratureDecoderPorts:inst27|Quad[0] ; 0 ; 6 ; ; - sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[0] ; 0 ; 6 ; ; KEY[2] ; ; ; ; - LEDG[4] ; 1 ; 6 ; ; CLOCK_24[0] ; ; ; +---------------------------------------------------------------------------------------------------+-------------------+---------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Control Signals ; +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ ; CLOCK_24[0] ; PIN_B12 ; 1 ; Clock ; no ; -- ; -- ; -- ; ; QuadratureDecoderPorts:inst27|CountEnable ; LCFF_X26_Y3_N21 ; 8 ; Clock ; yes ; Global Clock ; GCLK13 ; -- ; ; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y14_N0 ; 307 ; Clock ; yes ; Global Clock ; GCLK1 ; -- ; ; altera_internal_jtag~TMSUTAP ; JTAG_X1_Y14_N0 ; 23 ; Sync. clear ; no ; -- ; -- ; -- ; ; lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|safe_q[4] ; LCFF_X25_Y3_N31 ; 233 ; Clock ; yes ; Global Clock ; GCLK15 ; -- ; ; lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|safe_q[8] ; LCFF_X25_Y3_N1 ; 3 ; Clock ; no ; -- ; -- ; -- ; ; lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|safe_q[8] ; LCFF_X25_Y3_N1 ; 9 ; Clock ; yes ; Global Clock ; GCLK14 ; -- ; ; plld:inst17|altpll:altpll_component|_clk0 ; PLL_3 ; 9 ; Clock ; yes ; Global Clock ; GCLK11 ; -- ; ; sld_hub:sld_hub_inst|clr_reg ; LCFF_X31_Y18_N17 ; 28 ; Async. clear ; yes ; Global Clock ; GCLK10 ; -- ; ; sld_hub:sld_hub_inst|irf_reg[1][4] ; LCFF_X30_Y15_N15 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_hub:sld_hub_inst|irf_reg[1][6]~59 ; LCCOMB_X31_Y15_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_hub:sld_hub_inst|irf_reg[1][7] ; LCFF_X30_Y15_N29 ; 36 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_hub:sld_hub_inst|irsr_reg[0]~44 ; LCCOMB_X31_Y15_N6 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_hub:sld_hub_inst|irsr_reg[8] ; LCFF_X29_Y15_N23 ; 22 ; Sync. clear ; no ; -- ; -- ; -- ; ; sld_hub:sld_hub_inst|reset_ena_reg ; LCFF_X31_Y15_N27 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_hub:sld_hub_inst|shadow_irf_reg[1][6]~50 ; LCCOMB_X31_Y15_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3]~28 ; LCCOMB_X31_Y17_N14 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3]~30 ; LCCOMB_X31_Y17_N30 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; ; sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3]~31 ; LCCOMB_X30_Y15_N26 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; LCFF_X31_Y16_N1 ; 12 ; Async. clear ; yes ; Global Clock ; GCLK8 ; -- ; ; sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; LCFF_X29_Y16_N19 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; LCFF_X31_Y16_N17 ; 30 ; Sync. clear ; no ; -- ; -- ; -- ; ; sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; LCFF_X31_Y16_N7 ; 9 ; Async. clear ; no ; -- ; -- ; -- ; ; sld_hub:sld_hub_inst|virtual_ir_dr_scan_proc~2 ; LCCOMB_X31_Y16_N2 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_hub:sld_hub_inst|virtual_ir_scan_reg ; LCFF_X32_Y16_N17 ; 18 ; Async. clear, Clock enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_rqf:auto_generated|eq_node[0]~2 ; LCCOMB_X32_Y12_N28 ; 29 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_rqf:auto_generated|eq_node[1]~1 ; LCCOMB_X32_Y12_N26 ; 29 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_j4p3:auto_generated|altsyncram_vdq1:altsyncram1|decode_4oa:decode4|w_anode441w[2] ; LCCOMB_X32_Y12_N16 ; 6 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_j4p3:auto_generated|altsyncram_vdq1:altsyncram1|decode_4oa:decode4|w_anode454w[2] ; LCCOMB_X32_Y12_N4 ; 6 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_j4p3:auto_generated|altsyncram_vdq1:altsyncram1|decode_4oa:decode4|w_anode462w[2] ; LCCOMB_X32_Y12_N22 ; 6 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_j4p3:auto_generated|altsyncram_vdq1:altsyncram1|decode_4oa:decode4|w_anode470w[2] ; LCCOMB_X32_Y12_N2 ; 6 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_j4p3:auto_generated|altsyncram_vdq1:altsyncram1|decode_4oa:decode_a|w_anode441w[2] ; LCCOMB_X40_Y15_N16 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_j4p3:auto_generated|altsyncram_vdq1:altsyncram1|decode_4oa:decode_a|w_anode454w[2] ; LCCOMB_X39_Y15_N28 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_j4p3:auto_generated|altsyncram_vdq1:altsyncram1|decode_4oa:decode_a|w_anode462w[2] ; LCCOMB_X39_Y15_N30 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_j4p3:auto_generated|altsyncram_vdq1:altsyncram1|decode_4oa:decode_a|w_anode470w[2] ; LCCOMB_X40_Y15_N10 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|collect_data ; LCCOMB_X32_Y12_N18 ; 36 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|reset_all ; LCFF_X33_Y16_N17 ; 212 ; Async. clear ; yes ; Global Clock ; GCLK7 ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|final_trigger_set~3 ; LCCOMB_X33_Y13_N14 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0]~14 ; LCCOMB_X32_Y12_N6 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|Equal2~1 ; LCCOMB_X35_Y15_N4 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset ; LCCOMB_X35_Y15_N0 ; 14 ; Sync. load ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_bai:auto_generated|counter_reg_bit1a[2]~4 ; LCCOMB_X36_Y15_N2 ; 3 ; Sync. load ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_2ci:auto_generated|counter_reg_bit1a[4]~6 ; LCCOMB_X35_Y15_N12 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_gui:auto_generated|counter_reg_bit1a[0]~2 ; LCCOMB_X35_Y15_N8 ; 1 ; Sync. load ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter_clk_ena ; LCCOMB_X35_Y15_N6 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[1]~24 ; LCCOMB_X32_Y15_N14 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[0]~19 ; LCCOMB_X33_Y15_N16 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~1 ; LCCOMB_X31_Y12_N26 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|trigger_setup_ena ; LCCOMB_X30_Y13_N14 ; 64 ; Clock enable ; no ; -- ; -- ; -- ; +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Global & Other Fast Signals ; +-----------------------------------------------------------------------------------------+------------------+---------+----------------------+------------------+---------------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; +-----------------------------------------------------------------------------------------+------------------+---------+----------------------+------------------+---------------------------+ ; QuadratureDecoderPorts:inst27|CountEnable ; LCFF_X26_Y3_N21 ; 8 ; Global Clock ; GCLK13 ; -- ; ; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y14_N0 ; 307 ; Global Clock ; GCLK1 ; -- ; ; lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|safe_q[4] ; LCFF_X25_Y3_N31 ; 233 ; Global Clock ; GCLK15 ; -- ; ; lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|safe_q[8] ; LCFF_X25_Y3_N1 ; 9 ; Global Clock ; GCLK14 ; -- ; ; plld:inst17|altpll:altpll_component|_clk0 ; PLL_3 ; 9 ; Global Clock ; GCLK11 ; -- ; ; sld_hub:sld_hub_inst|clr_reg ; LCFF_X31_Y18_N17 ; 28 ; Global Clock ; GCLK10 ; -- ; ; sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; LCFF_X31_Y16_N1 ; 12 ; Global Clock ; GCLK8 ; -- ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|reset_all ; LCFF_X33_Y16_N17 ; 212 ; Global Clock ; GCLK7 ; -- ; +-----------------------------------------------------------------------------------------+------------------+---------+----------------------+------------------+---------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Non-Global High Fan-Out Signals ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ ; Name ; Fan-Out ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|trigger_setup_ena ; 64 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|collect_data ; 36 ; ; sld_hub:sld_hub_inst|irf_reg[1][7] ; 36 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~9 ; 35 ; ; ~GND ; 31 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sdr~0 ; 31 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|final_trigger_set~3 ; 30 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|status_ram_shift_load~0 ; 30 ; ; sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; 30 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_rqf:auto_generated|eq_node[0]~2 ; 29 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_rqf:auto_generated|eq_node[1]~1 ; 29 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xraddr[0] ; 29 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[11] ; 26 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[10] ; 26 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[9] ; 26 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[8] ; 26 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[7] ; 26 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[6] ; 26 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[5] ; 26 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[4] ; 26 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[3] ; 26 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[2] ; 26 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[1] ; 26 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_address_delayed[0] ; 26 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_p6j:auto_generated|safe_q[11] ; 25 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_p6j:auto_generated|safe_q[10] ; 25 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_p6j:auto_generated|safe_q[9] ; 25 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_p6j:auto_generated|safe_q[8] ; 25 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_p6j:auto_generated|safe_q[7] ; 25 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_p6j:auto_generated|safe_q[6] ; 25 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_p6j:auto_generated|safe_q[5] ; 25 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_p6j:auto_generated|safe_q[4] ; 25 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_p6j:auto_generated|safe_q[3] ; 25 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_p6j:auto_generated|safe_q[2] ; 25 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_p6j:auto_generated|safe_q[1] ; 25 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_p6j:auto_generated|safe_q[0] ; 25 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|final_trigger_set ; 24 ; ; sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; 23 ; ; altera_internal_jtag~TMSUTAP ; 23 ; ; sld_hub:sld_hub_inst|irsr_reg[8] ; 22 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal0~4 ; 19 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~1 ; 18 ; ; sld_hub:sld_hub_inst|virtual_ir_scan_reg ; 18 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|process_0~18 ; 17 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_load_on~1 ; 17 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~2 ; 15 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter_clk_ena ; 14 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset ; 14 ; ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0]~14 ; 14 ; ; sld_hub:sld_hub_inst|irf_reg[1][4] ; 13 ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fitter RAM Summary ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+-------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+-------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_j4p3:auto_generated|altsyncram_vdq1:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 16384 ; 6 ; 16384 ; 6 ; yes ; no ; yes ; no ; 98304 ; 16384 ; 6 ; 16384 ; 6 ; 98304 ; 24 ; None ; M4K_X41_Y7, M4K_X41_Y8, M4K_X41_Y11, M4K_X41_Y16, M4K_X17_Y9, M4K_X17_Y10, M4K_X17_Y11, M4K_X17_Y18, M4K_X41_Y12, M4K_X41_Y14, M4K_X41_Y15, M4K_X41_Y18, M4K_X41_Y10, M4K_X41_Y9, M4K_X41_Y13, M4K_X41_Y17, M4K_X17_Y12, M4K_X17_Y14, M4K_X17_Y15, M4K_X17_Y17, M4K_X17_Y16, M4K_X17_Y7, M4K_X17_Y8, M4K_X17_Y13 ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+-------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. +-----------------------------------------------------+ ; Interconnect Usage Summary ; +----------------------------+------------------------+ ; Interconnect Resource Type ; Usage ; +----------------------------+------------------------+ ; Block interconnects ; 1,353 / 54,004 ( 3 % ) ; ; C16 interconnects ; 13 / 2,100 ( < 1 % ) ; ; C4 interconnects ; 586 / 36,000 ( 2 % ) ; ; Direct links ; 229 / 54,004 ( < 1 % ) ; ; Global clocks ; 8 / 16 ( 50 % ) ; ; Local interconnects ; 392 / 18,752 ( 2 % ) ; ; R24 interconnects ; 17 / 1,900 ( < 1 % ) ; ; R4 interconnects ; 738 / 46,920 ( 2 % ) ; +----------------------------+------------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ ; Number of Logic Elements (Average = 8.86) ; Number of LABs (Total = 77) ; +--------------------------------------------+------------------------------+ ; 1 ; 22 ; ; 2 ; 6 ; ; 3 ; 1 ; ; 4 ; 2 ; ; 5 ; 0 ; ; 6 ; 2 ; ; 7 ; 2 ; ; 8 ; 3 ; ; 9 ; 1 ; ; 10 ; 1 ; ; 11 ; 2 ; ; 12 ; 3 ; ; 13 ; 0 ; ; 14 ; 1 ; ; 15 ; 0 ; ; 16 ; 31 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ ; LAB-wide Signals (Average = 1.95) ; Number of LABs (Total = 77) ; +------------------------------------+------------------------------+ ; 1 Async. clear ; 34 ; ; 1 Clock ; 62 ; ; 1 Clock enable ; 24 ; ; 1 Sync. clear ; 4 ; ; 1 Sync. load ; 2 ; ; 2 Clock enables ; 12 ; ; 2 Clocks ; 12 ; +------------------------------------+------------------------------+ +-----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +----------------------------------------------+------------------------------+ ; Number of Signals Sourced (Average = 14.91) ; Number of LABs (Total = 77) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 6 ; ; 2 ; 17 ; ; 3 ; 3 ; ; 4 ; 2 ; ; 5 ; 0 ; ; 6 ; 2 ; ; 7 ; 1 ; ; 8 ; 1 ; ; 9 ; 0 ; ; 10 ; 1 ; ; 11 ; 1 ; ; 12 ; 0 ; ; 13 ; 0 ; ; 14 ; 2 ; ; 15 ; 1 ; ; 16 ; 3 ; ; 17 ; 1 ; ; 18 ; 2 ; ; 19 ; 0 ; ; 20 ; 1 ; ; 21 ; 2 ; ; 22 ; 5 ; ; 23 ; 0 ; ; 24 ; 5 ; ; 25 ; 0 ; ; 26 ; 5 ; ; 27 ; 2 ; ; 28 ; 3 ; ; 29 ; 1 ; ; 30 ; 3 ; ; 31 ; 4 ; ; 32 ; 3 ; +----------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ ; Number of Signals Sourced Out (Average = 5.62) ; Number of LABs (Total = 77) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 32 ; ; 2 ; 6 ; ; 3 ; 5 ; ; 4 ; 1 ; ; 5 ; 2 ; ; 6 ; 6 ; ; 7 ; 0 ; ; 8 ; 3 ; ; 9 ; 3 ; ; 10 ; 3 ; ; 11 ; 3 ; ; 12 ; 2 ; ; 13 ; 1 ; ; 14 ; 0 ; ; 15 ; 2 ; ; 16 ; 5 ; ; 17 ; 1 ; ; 18 ; 0 ; ; 19 ; 0 ; ; 20 ; 0 ; ; 21 ; 0 ; ; 22 ; 1 ; ; 23 ; 0 ; ; 24 ; 1 ; +-------------------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +---------------------------------------------+------------------------------+ ; Number of Distinct Inputs (Average = 9.52) ; Number of LABs (Total = 77) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 3 ; ; 2 ; 21 ; ; 3 ; 4 ; ; 4 ; 4 ; ; 5 ; 4 ; ; 6 ; 2 ; ; 7 ; 2 ; ; 8 ; 5 ; ; 9 ; 1 ; ; 10 ; 2 ; ; 11 ; 3 ; ; 12 ; 1 ; ; 13 ; 2 ; ; 14 ; 1 ; ; 15 ; 2 ; ; 16 ; 0 ; ; 17 ; 2 ; ; 18 ; 2 ; ; 19 ; 4 ; ; 20 ; 3 ; ; 21 ; 2 ; ; 22 ; 2 ; ; 23 ; 1 ; ; 24 ; 0 ; ; 25 ; 0 ; ; 26 ; 1 ; ; 27 ; 1 ; ; 28 ; 0 ; ; 29 ; 0 ; ; 30 ; 1 ; ; 31 ; 0 ; ; 32 ; 1 ; +---------------------------------------------+------------------------------+ +----------------------------------------------------------------------------------------+ ; Fitter Device Options ; +----------------------------------------------+-----------------------------------------+ ; Option ; Setting ; +----------------------------------------------+-----------------------------------------+ ; Enable user-supplied start-up clock (CLKUSR) ; Off ; ; Enable device-wide reset (DEV_CLRn) ; Off ; ; Enable device-wide output enable (DEV_OE) ; Off ; ; Enable INIT_DONE output ; Off ; ; Configuration scheme ; Active Serial ; ; Error detection CRC ; Off ; ; nCEO ; As output driving ground ; ; ASDO,nCSO ; As input tri-stated ; ; Reserve all unused pins ; As output driving an unspecified signal ; ; Base pin-out file on sameframe device ; Off ; +----------------------------------------------+-----------------------------------------+ +------------------------------------+ ; Operating Settings and Conditions ; +---------------------------+--------+ ; Setting ; Value ; +---------------------------+--------+ ; Nominal Core Voltage ; 1.20 V ; ; Low Junction Temperature ; 0 °C ; ; High Junction Temperature ; 85 °C ; +---------------------------+--------+ +-----------------------------------------------------------------------------------------------------------+ ; Estimated Delay Added for Hold Timing ; +-------------------------------------------+-------------------------------------------+-------------------+ ; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; +-------------------------------------------+-------------------------------------------+-------------------+ ; plld:inst17|altpll:altpll_component|_clk0 ; plld:inst17|altpll:altpll_component|_clk0 ; 0.825 ; +-------------------------------------------+-------------------------------------------+-------------------+ Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer. +-----------------+ ; Fitter Messages ; +-----------------+ Info: ******************************************************************* Info: Running Quartus II 64-Bit Fitter Info: Version 9.0 Build 132 02/25/2009 SJ Full Version Info: Processing started: Thu Mar 11 05:23:08 2010 Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DE1_Default -c DE1_Default Info: Parallel compilation is enabled and will use 4 of the 4 processors detected Info: Selected device EP2C20F484C7 for design "DE1_Default" Info: Implemented PLL "plld:inst17|altpll:altpll_component|pll" as Cyclone II PLL type Info: Implementing clock multiplication of 5, clock division of 12, and phase shift of 0 degrees (0 ps) for plld:inst17|altpll:altpll_component|_clk0 port Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices Info: Device EP2C15AF484C7 is compatible Info: Device EP2C35F484C7 is compatible Info: Device EP2C50F484C7 is compatible Info: Fitter converted 3 user pins into dedicated programming pins Info: Pin ~ASDO~ is reserved at location C4 Info: Pin ~nCSO~ is reserved at location C3 Info: Pin ~LVDS91p/nCEO~ is reserved at location W20 Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Info: Fitter is using the Classic Timing Analyzer Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements Info: Automatically promoted node plld:inst17|altpll:altpll_component|_clk0 (placed in counter C0 of PLL_3) Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G11 Info: Automatically promoted node altera_internal_jtag~TCKUTAP Info: Automatically promoted destinations to use location or clock signal Global Clock Info: Automatically promoted node lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|safe_q[4] Info: Automatically promoted destinations to use location or clock signal Global Clock Info: Following destination nodes may be non-global or may not use global or regional clocks Info: Destination node lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|counter_comb_bita4 Info: Automatically promoted node lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|safe_q[8] Info: Automatically promoted destinations to use location or clock signal Global Clock Info: Following destination nodes may be non-global or may not use global or regional clocks Info: Destination node QuadratureDecoderPorts:inst27|CountEnable Info: Destination node lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|counter_comb_bita8 Info: Automatically promoted node QuadratureDecoderPorts:inst27|CountEnable Info: Automatically promoted destinations to use location or clock signal Global Clock Info: Following destination nodes may be non-global or may not use global or regional clocks Info: Destination node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[4] Info: Automatically promoted node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|reset_all Info: Automatically promoted destinations to use location or clock signal Global Clock Info: Following destination nodes may be non-global or may not use global or regional clocks Info: Destination node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset~1 Info: Automatically promoted node sld_hub:sld_hub_inst|clr_reg Info: Automatically promoted destinations to use location or clock signal Global Clock Info: Following destination nodes may be non-global or may not use global or regional clocks Info: Destination node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|reset_all~0 Info: Automatically promoted node sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] Info: Automatically promoted destinations to use location or clock signal Global Clock Info: Following destination nodes may be non-global or may not use global or regional clocks Info: Destination node sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state~29 Info: Destination node sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state~3 Info: Starting register packing Info: Finished register packing Extra Info: No registers were packed into other blocks Warning: Ignored I/O standard assignments to the following nodes Warning: Ignored I/O standard assignment to node "AUD_ADCDAT" Warning: Ignored I/O standard assignment to node "AUD_ADCLRCK" Warning: Ignored I/O standard assignment to node "AUD_BCLK" Warning: Ignored I/O standard assignment to node "AUD_DACDAT" Warning: Ignored I/O standard assignment to node "AUD_DACLRCK" Warning: Ignored I/O standard assignment to node "AUD_XCK" Warning: Ignored I/O standard assignment to node "CLOCK_24[1]" Warning: Ignored I/O standard assignment to node "CLOCK_27[1]" Warning: Ignored I/O standard assignment to node "CLOCK_50" Warning: Ignored I/O standard assignment to node "EXT_CLOCK" Warning: Ignored I/O standard assignment to node "GPIO_0[10]" Warning: Ignored I/O standard assignment to node "GPIO_0[11]" Warning: Ignored I/O standard assignment to node "GPIO_0[12]" Warning: Ignored I/O standard assignment to node "GPIO_0[13]" Warning: Ignored I/O standard assignment to node "GPIO_0[14]" Warning: Ignored I/O standard assignment to node "GPIO_0[15]" Warning: Ignored I/O standard assignment to node "GPIO_0[16]" Warning: Ignored I/O standard assignment to node "GPIO_0[17]" Warning: Ignored I/O standard assignment to node "GPIO_0[18]" Warning: Ignored I/O standard assignment to node "GPIO_0[19]" Warning: Ignored I/O standard assignment to node "GPIO_0[20]" Warning: Ignored I/O standard assignment to node "GPIO_0[21]" Warning: Ignored I/O standard assignment to node "GPIO_0[22]" Warning: Ignored I/O standard assignment to node "GPIO_0[23]" Warning: Ignored I/O standard assignment to node "GPIO_0[24]" Warning: Ignored I/O standard assignment to node "GPIO_0[25]" Warning: Ignored I/O standard assignment to node "GPIO_0[26]" Warning: Ignored I/O standard assignment to node "GPIO_0[27]" Warning: Ignored I/O standard assignment to node "GPIO_0[28]" Warning: Ignored I/O standard assignment to node "GPIO_0[29]" Warning: Ignored I/O standard assignment to node "GPIO_0[30]" Warning: Ignored I/O standard assignment to node "GPIO_0[31]" Warning: Ignored I/O standard assignment to node "GPIO_0[32]" Warning: Ignored I/O standard assignment to node "GPIO_0[33]" Warning: Ignored I/O standard assignment to node "GPIO_0[34]" Warning: Ignored I/O standard assignment to node "GPIO_0[35]" Warning: Ignored I/O standard assignment to node "GPIO_0[3]" Warning: Ignored I/O standard assignment to node "GPIO_0[4]" Warning: Ignored I/O standard assignment to node "GPIO_0[5]" Warning: Ignored I/O standard assignment to node "GPIO_0[6]" Warning: Ignored I/O standard assignment to node "GPIO_0[7]" Warning: Ignored I/O standard assignment to node "GPIO_0[8]" Warning: Ignored I/O standard assignment to node "GPIO_0[9]" Warning: Ignored I/O standard assignment to node "GPIO_1[0]" Warning: Ignored I/O standard assignment to node "GPIO_1[10]" Warning: Ignored I/O standard assignment to node "GPIO_1[11]" Warning: Ignored I/O standard assignment to node "GPIO_1[12]" Warning: Ignored I/O standard assignment to node "GPIO_1[13]" Warning: Ignored I/O standard assignment to node "GPIO_1[14]" Warning: Ignored I/O standard assignment to node "GPIO_1[15]" Warning: Ignored I/O standard assignment to node "GPIO_1[16]" Warning: Ignored I/O standard assignment to node "GPIO_1[17]" Warning: Ignored I/O standard assignment to node "GPIO_1[18]" Warning: Ignored I/O standard assignment to node "GPIO_1[19]" Warning: Ignored I/O standard assignment to node "GPIO_1[1]" Warning: Ignored I/O standard assignment to node "GPIO_1[20]" Warning: Ignored I/O standard assignment to node "GPIO_1[21]" Warning: Ignored I/O standard assignment to node "GPIO_1[22]" Warning: Ignored I/O standard assignment to node "GPIO_1[23]" Warning: Ignored I/O standard assignment to node "GPIO_1[24]" Warning: Ignored I/O standard assignment to node "GPIO_1[25]" Warning: Ignored I/O standard assignment to node "GPIO_1[26]" Warning: Ignored I/O standard assignment to node "GPIO_1[27]" Warning: Ignored I/O standard assignment to node "GPIO_1[28]" Warning: Ignored I/O standard assignment to node "GPIO_1[29]" Warning: Ignored I/O standard assignment to node "GPIO_1[2]" Warning: Ignored I/O standard assignment to node "GPIO_1[30]" Warning: Ignored I/O standard assignment to node "GPIO_1[31]" Warning: Ignored I/O standard assignment to node "GPIO_1[32]" Warning: Ignored I/O standard assignment to node "GPIO_1[33]" Warning: Ignored I/O standard assignment to node "GPIO_1[34]" Warning: Ignored I/O standard assignment to node "GPIO_1[35]" Warning: Ignored I/O standard assignment to node "GPIO_1[3]" Warning: Ignored I/O standard assignment to node "GPIO_1[4]" Warning: Ignored I/O standard assignment to node "GPIO_1[5]" Warning: Ignored I/O standard assignment to node "GPIO_1[6]" Warning: Ignored I/O standard assignment to node "GPIO_1[7]" Warning: Ignored I/O standard assignment to node "GPIO_1[8]" Warning: Ignored I/O standard assignment to node "GPIO_1[9]" Warning: Ignored I/O standard assignment to node "I2C_SCLK" Warning: Ignored I/O standard assignment to node "I2C_SDAT" Warning: Ignored I/O standard assignment to node "KEY[0]" Warning: Ignored I/O standard assignment to node "KEY[1]" Warning: Ignored I/O standard assignment to node "KEY[3]" Warning: Ignored I/O standard assignment to node "LEDG[2]" Warning: Ignored I/O standard assignment to node "LEDG[3]" Warning: Ignored I/O standard assignment to node "LEDG[5]" Warning: Ignored I/O standard assignment to node "LEDG[6]" Warning: Ignored I/O standard assignment to node "LEDG[7]" Warning: Ignored I/O standard assignment to node "LEDR[0]" Warning: Ignored I/O standard assignment to node "LEDR[1]" Warning: Ignored I/O standard assignment to node "LEDR[2]" Warning: Ignored I/O standard assignment to node "LEDR[3]" Warning: Ignored I/O standard assignment to node "LEDR[4]" Warning: Ignored I/O standard assignment to node "LEDR[5]" Warning: Ignored I/O standard assignment to node "LEDR[6]" Warning: Ignored I/O standard assignment to node "LEDR[7]" Warning: Ignored I/O standard assignment to node "LEDR[8]" Warning: Ignored I/O standard assignment to node "LEDR[9]" Warning: Ignored I/O standard assignment to node "PS2_CLK" Warning: Ignored I/O standard assignment to node "PS2_DAT" Warning: Ignored I/O standard assignment to node "SW[0]" Warning: Ignored I/O standard assignment to node "SW[1]" Warning: Ignored I/O standard assignment to node "SW[2]" Warning: Ignored I/O standard assignment to node "SW[3]" Warning: Ignored I/O standard assignment to node "SW[4]" Warning: Ignored I/O standard assignment to node "SW[5]" Warning: Ignored I/O standard assignment to node "SW[6]" Warning: Ignored I/O standard assignment to node "SW[7]" Warning: Ignored I/O standard assignment to node "SW[8]" Warning: Ignored I/O standard assignment to node "SW[9]" Warning: Ignored I/O standard assignment to node "TCK" Warning: Ignored I/O standard assignment to node "TCS" Warning: Ignored I/O standard assignment to node "TDI" Warning: Ignored I/O standard assignment to node "TDO" Warning: Ignored I/O standard assignment to node "UART_RXD" Warning: Ignored I/O standard assignment to node "UART_TXD" Warning: Ignored I/O standard assignment to node "VGA_B[0]" Warning: Ignored I/O standard assignment to node "VGA_B[1]" Warning: Ignored I/O standard assignment to node "VGA_B[2]" Warning: Ignored I/O standard assignment to node "VGA_B[3]" Warning: Ignored I/O standard assignment to node "VGA_G[0]" Warning: Ignored I/O standard assignment to node "VGA_G[1]" Warning: Ignored I/O standard assignment to node "VGA_G[2]" Warning: Ignored I/O standard assignment to node "VGA_G[3]" Warning: Ignored I/O standard assignment to node "VGA_HS" Warning: Ignored I/O standard assignment to node "VGA_R[0]" Warning: Ignored I/O standard assignment to node "VGA_R[1]" Warning: Ignored I/O standard assignment to node "VGA_R[2]" Warning: Ignored I/O standard assignment to node "VGA_R[3]" Warning: Ignored I/O standard assignment to node "VGA_VS" Warning: Ignored locations or region assignments to the following nodes Warning: Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design Warning: Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design Warning: Node "AUD_BCLK" is assigned to location or region, but does not exist in design Warning: Node "AUD_DACDAT" is assigned to location or region, but does not exist in design Warning: Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design Warning: Node "AUD_XCK" is assigned to location or region, but does not exist in design Warning: Node "CLOCK_24[1]" is assigned to location or region, but does not exist in design Warning: Node "CLOCK_27[0]" is assigned to location or region, but does not exist in design Warning: Node "CLOCK_27[1]" is assigned to location or region, but does not exist in design Warning: Node "CLOCK_50" is assigned to location or region, but does not exist in design Warning: Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_BA_0" is assigned to location or region, but does not exist in design Warning: Node "DRAM_BA_1" is assigned to location or region, but does not exist in design Warning: Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design Warning: Node "DRAM_CKE" is assigned to location or region, but does not exist in design Warning: Node "DRAM_CLK" is assigned to location or region, but does not exist in design Warning: Node "DRAM_CS_N" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design Warning: Node "DRAM_LDQM" is assigned to location or region, but does not exist in design Warning: Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design Warning: Node "DRAM_UDQM" is assigned to location or region, but does not exist in design Warning: Node "DRAM_WE_N" is assigned to location or region, but does not exist in design Warning: Node "EXT_CLOCK" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design Warning: Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design Warning: Node "FL_CE_N" is assigned to location or region, but does not exist in design Warning: Node "FL_DQ[0]" is assigned to location or region, but does not exist in design Warning: Node "FL_DQ[1]" is assigned to location or region, but does not exist in design Warning: Node "FL_DQ[2]" is assigned to location or region, but does not exist in design Warning: Node "FL_DQ[3]" is assigned to location or region, but does not exist in design Warning: Node "FL_DQ[4]" is assigned to location or region, but does not exist in design Warning: Node "FL_DQ[5]" is assigned to location or region, but does not exist in design Warning: Node "FL_DQ[6]" is assigned to location or region, but does not exist in design Warning: Node "FL_DQ[7]" is assigned to location or region, but does not exist in design Warning: Node "FL_OE_N" is assigned to location or region, but does not exist in design Warning: Node "FL_RST_N" is assigned to location or region, but does not exist in design Warning: Node "FL_WE_N" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[10]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[11]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[12]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[13]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[14]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[15]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[16]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[17]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[18]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[19]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[20]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[21]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[22]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[23]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[24]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[25]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[26]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[27]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[28]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[29]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[30]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[31]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[32]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[33]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[34]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[35]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[3]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[4]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[5]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[6]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[7]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[8]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_0[9]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[0]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[10]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[11]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[12]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[13]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[14]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[15]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[16]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[17]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[18]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[19]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[1]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[20]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[21]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[22]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[23]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[24]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[25]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[26]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[27]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[28]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[29]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[2]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[30]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[31]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[32]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[33]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[34]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[35]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[3]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[4]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[5]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[6]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[7]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[8]" is assigned to location or region, but does not exist in design Warning: Node "GPIO_1[9]" is assigned to location or region, but does not exist in design Warning: Node "I2C_SCLK" is assigned to location or region, but does not exist in design Warning: Node "I2C_SDAT" is assigned to location or region, but does not exist in design Warning: Node "KEY[0]" is assigned to location or region, but does not exist in design Warning: Node "KEY[1]" is assigned to location or region, but does not exist in design Warning: Node "KEY[3]" is assigned to location or region, but does not exist in design Warning: Node "LEDG[2]" is assigned to location or region, but does not exist in design Warning: Node "LEDG[3]" is assigned to location or region, but does not exist in design Warning: Node "LEDG[5]" is assigned to location or region, but does not exist in design Warning: Node "LEDG[6]" is assigned to location or region, but does not exist in design Warning: Node "LEDG[7]" is assigned to location or region, but does not exist in design Warning: Node "LEDR[0]" is assigned to location or region, but does not exist in design Warning: Node "LEDR[1]" is assigned to location or region, but does not exist in design Warning: Node "LEDR[2]" is assigned to location or region, but does not exist in design Warning: Node "LEDR[3]" is assigned to location or region, but does not exist in design Warning: Node "LEDR[4]" is assigned to location or region, but does not exist in design Warning: Node "LEDR[5]" is assigned to location or region, but does not exist in design Warning: Node "LEDR[6]" is assigned to location or region, but does not exist in design Warning: Node "LEDR[7]" is assigned to location or region, but does not exist in design Warning: Node "LEDR[8]" is assigned to location or region, but does not exist in design Warning: Node "LEDR[9]" is assigned to location or region, but does not exist in design Warning: Node "PS2_CLK" is assigned to location or region, but does not exist in design Warning: Node "PS2_DAT" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_CE_N" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design Warning: Node "SRAM_LB_N" is assigned to location or region, but does not exist in design Warning: Node "SRAM_OE_N" is assigned to location or region, but does not exist in design Warning: Node "SRAM_UB_N" is assigned to location or region, but does not exist in design Warning: Node "SRAM_WE_N" is assigned to location or region, but does not exist in design Warning: Node "SW[0]" is assigned to location or region, but does not exist in design Warning: Node "SW[1]" is assigned to location or region, but does not exist in design Warning: Node "SW[2]" is assigned to location or region, but does not exist in design Warning: Node "SW[3]" is assigned to location or region, but does not exist in design Warning: Node "SW[4]" is assigned to location or region, but does not exist in design Warning: Node "SW[5]" is assigned to location or region, but does not exist in design Warning: Node "SW[6]" is assigned to location or region, but does not exist in design Warning: Node "SW[7]" is assigned to location or region, but does not exist in design Warning: Node "SW[8]" is assigned to location or region, but does not exist in design Warning: Node "SW[9]" is assigned to location or region, but does not exist in design Warning: Node "TCK" is assigned to location or region, but does not exist in design Warning: Node "TCS" is assigned to location or region, but does not exist in design Warning: Node "TDI" is assigned to location or region, but does not exist in design Warning: Node "TDO" is assigned to location or region, but does not exist in design Warning: Node "UART_RXD" is assigned to location or region, but does not exist in design Warning: Node "UART_TXD" is assigned to location or region, but does not exist in design Warning: Node "VGA_B[0]" is assigned to location or region, but does not exist in design Warning: Node "VGA_B[1]" is assigned to location or region, but does not exist in design Warning: Node "VGA_B[2]" is assigned to location or region, but does not exist in design Warning: Node "VGA_B[3]" is assigned to location or region, but does not exist in design Warning: Node "VGA_G[0]" is assigned to location or region, but does not exist in design Warning: Node "VGA_G[1]" is assigned to location or region, but does not exist in design Warning: Node "VGA_G[2]" is assigned to location or region, but does not exist in design Warning: Node "VGA_G[3]" is assigned to location or region, but does not exist in design Warning: Node "VGA_HS" is assigned to location or region, but does not exist in design Warning: Node "VGA_R[0]" is assigned to location or region, but does not exist in design Warning: Node "VGA_R[1]" is assigned to location or region, but does not exist in design Warning: Node "VGA_R[2]" is assigned to location or region, but does not exist in design Warning: Node "VGA_R[3]" is assigned to location or region, but does not exist in design Warning: Node "VGA_VS" is assigned to location or region, but does not exist in design Info: Fitter preparation operations ending: elapsed time is 00:00:01 Info: Fitter placement preparation operations beginning Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 Info: Fitter placement operations beginning Info: Fitter placement was successful Info: Fitter placement operations ending: elapsed time is 00:00:01 Info: Slack time is 93.949 ns between source register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[11]" and destination register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0]" Info: + Largest register to register requirement is 99.759 ns Info: Shortest clock path from clock "plld:inst17|altpll:altpll_component|_clk0" to destination register is 5.581 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'plld:inst17|altpll:altpll_component|_clk0' Info: 2: + IC(0.922 ns) + CELL(0.000 ns) = 0.922 ns; Loc. = Unassigned; Fanout = 9; COMB Node = 'plld:inst17|altpll:altpll_component|_clk0~clkctrl' Info: 3: + IC(0.988 ns) + CELL(0.879 ns) = 2.789 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|safe_q[4]' Info: 4: + IC(1.202 ns) + CELL(0.000 ns) = 3.991 ns; Loc. = Unassigned; Fanout = 569; COMB Node = 'lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|safe_q[4]~clkctrl' Info: 5: + IC(0.988 ns) + CELL(0.602 ns) = 5.581 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0]' Info: Total cell delay = 1.481 ns ( 26.54 % ) Info: Total interconnect delay = 4.100 ns ( 73.46 % ) Info: Longest clock path from clock "plld:inst17|altpll:altpll_component|_clk0" to destination register is 5.581 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'plld:inst17|altpll:altpll_component|_clk0' Info: 2: + IC(0.922 ns) + CELL(0.000 ns) = 0.922 ns; Loc. = Unassigned; Fanout = 9; COMB Node = 'plld:inst17|altpll:altpll_component|_clk0~clkctrl' Info: 3: + IC(0.988 ns) + CELL(0.879 ns) = 2.789 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|safe_q[4]' Info: 4: + IC(1.202 ns) + CELL(0.000 ns) = 3.991 ns; Loc. = Unassigned; Fanout = 569; COMB Node = 'lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|safe_q[4]~clkctrl' Info: 5: + IC(0.988 ns) + CELL(0.602 ns) = 5.581 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0]' Info: Total cell delay = 1.481 ns ( 26.54 % ) Info: Total interconnect delay = 4.100 ns ( 73.46 % ) Info: Shortest clock path from clock "plld:inst17|altpll:altpll_component|_clk0" to source register is 5.581 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'plld:inst17|altpll:altpll_component|_clk0' Info: 2: + IC(0.922 ns) + CELL(0.000 ns) = 0.922 ns; Loc. = Unassigned; Fanout = 9; COMB Node = 'plld:inst17|altpll:altpll_component|_clk0~clkctrl' Info: 3: + IC(0.988 ns) + CELL(0.879 ns) = 2.789 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|safe_q[4]' Info: 4: + IC(1.202 ns) + CELL(0.000 ns) = 3.991 ns; Loc. = Unassigned; Fanout = 569; COMB Node = 'lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|safe_q[4]~clkctrl' Info: 5: + IC(0.988 ns) + CELL(0.602 ns) = 5.581 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[11]' Info: Total cell delay = 1.481 ns ( 26.54 % ) Info: Total interconnect delay = 4.100 ns ( 73.46 % ) Info: Longest clock path from clock "plld:inst17|altpll:altpll_component|_clk0" to source register is 5.581 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'plld:inst17|altpll:altpll_component|_clk0' Info: 2: + IC(0.922 ns) + CELL(0.000 ns) = 0.922 ns; Loc. = Unassigned; Fanout = 9; COMB Node = 'plld:inst17|altpll:altpll_component|_clk0~clkctrl' Info: 3: + IC(0.988 ns) + CELL(0.879 ns) = 2.789 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|safe_q[4]' Info: 4: + IC(1.202 ns) + CELL(0.000 ns) = 3.991 ns; Loc. = Unassigned; Fanout = 569; COMB Node = 'lpm_counter1:inst18|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated|safe_q[4]~clkctrl' Info: 5: + IC(0.988 ns) + CELL(0.602 ns) = 5.581 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[11]' Info: Total cell delay = 1.481 ns ( 26.54 % ) Info: Total interconnect delay = 4.100 ns ( 73.46 % ) Info: Micro clock to output delay of source is 0.277 ns Info: Micro setup delay of destination is -0.038 ns Info: - Longest register to register delay is 5.810 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[11]' Info: 2: + IC(1.100 ns) + CELL(0.516 ns) = 1.616 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~5' Info: 3: + IC(1.037 ns) + CELL(0.491 ns) = 3.144 ns; Loc. = Unassigned; Fanout = 35; COMB Node = 'sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~9' Info: 4: + IC(1.381 ns) + CELL(0.177 ns) = 4.702 ns; Loc. = Unassigned; Fanout = 3; COMB Node = 'sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~28' Info: 5: + IC(1.012 ns) + CELL(0.096 ns) = 5.810 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0]' Info: Total cell delay = 1.280 ns ( 22.03 % ) Info: Total interconnect delay = 4.530 ns ( 77.97 % ) Info: Estimated most critical path is register to register delay of 5.810 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X31_Y13; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[11]' Info: 2: + IC(1.100 ns) + CELL(0.516 ns) = 1.616 ns; Loc. = LAB_X34_Y14; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~5' Info: 3: + IC(1.037 ns) + CELL(0.491 ns) = 3.144 ns; Loc. = LAB_X32_Y13; Fanout = 35; COMB Node = 'sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~9' Info: 4: + IC(1.381 ns) + CELL(0.177 ns) = 4.702 ns; Loc. = LAB_X34_Y14; Fanout = 3; COMB Node = 'sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~28' Info: 5: + IC(1.012 ns) + CELL(0.096 ns) = 5.810 ns; Loc. = LAB_X32_Y14; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0]' Info: Total cell delay = 1.280 ns ( 22.03 % ) Info: Total interconnect delay = 4.530 ns ( 77.97 % ) Info: Fitter routing operations beginning Info: Average interconnect usage is 1% of the available device resources Info: Peak interconnect usage is 3% of the available device resources in the region that extends from location X25_Y0 to location X37_Y13 Info: Fitter routing operations ending: elapsed time is 00:00:01 Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info: Optimizations that may affect the design's routability were skipped Info: Optimizations that may affect the design's timing were skipped Info: Started post-fitting delay annotation Info: Delay annotation completed successfully Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Warning: Following 14 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results Info: Pin HEX2[6] has VCC driving its datain port Info: Pin HEX2[5] has GND driving its datain port Info: Pin HEX2[4] has GND driving its datain port Info: Pin HEX2[3] has GND driving its datain port Info: Pin HEX2[2] has GND driving its datain port Info: Pin HEX2[1] has GND driving its datain port Info: Pin HEX2[0] has GND driving its datain port Info: Pin HEX3[6] has VCC driving its datain port Info: Pin HEX3[5] has GND driving its datain port Info: Pin HEX3[4] has GND driving its datain port Info: Pin HEX3[3] has GND driving its datain port Info: Pin HEX3[2] has GND driving its datain port Info: Pin HEX3[1] has GND driving its datain port Info: Pin HEX3[0] has GND driving its datain port Info: Generated suppressed messages file E:/.DATABANK/!!!Текущие разработки/DB ALTERA 2C20-START/DE1_demonstrations/DE1_Default/DE1_Default.fit.smsg Info: Quartus II 64-Bit Fitter was successful. 0 errors, 377 warnings Info: Peak virtual memory: 319 megabytes Info: Processing ended: Thu Mar 11 05:23:15 2010 Info: Elapsed time: 00:00:07 Info: Total CPU time (on all processors): 00:00:07 +----------------------------+ ; Fitter Suppressed Messages ; +----------------------------+ The suppressed messages can be found in E:/.DATABANK/!!!Текущие разработки/DB ALTERA 2C20-START/DE1_demonstrations/DE1_Default/DE1_Default.fit.smsg.