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--Cont[24] is Cont[24] at LCFF_X1_Y20_N21
Cont[24] = DFFEAS(A1L91, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[25] is Cont[25] at LCFF_X1_Y20_N23
Cont[25] = DFFEAS(A1L94, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[26] is Cont[26] at LCFF_X1_Y20_N25
Cont[26] = DFFEAS(A1L97, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[27] is Cont[27] at LCFF_X1_Y20_N27
Cont[27] = DFFEAS(A1L100, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--L1L1 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[0]~70 at LCCOMB_X1_Y20_N30
L1L1 = Cont[26] & !Cont[25] & (Cont[27] $ !Cont[24]) # !Cont[26] & Cont[24] & (Cont[27] $ !Cont[25]);


--L1L2 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[1]~71 at LCCOMB_X1_Y20_N28
L1L2 = Cont[27] & (Cont[24] & (Cont[25]) # !Cont[24] & Cont[26]) # !Cont[27] & Cont[26] & (Cont[24] $ Cont[25]);


--L1L3 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[2]~72 at LCCOMB_X1_Y19_N24
L1L3 = Cont[27] & Cont[26] & (Cont[25] # !Cont[24]) # !Cont[27] & Cont[25] & !Cont[24] & !Cont[26];


--L1L4 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[3]~73 at LCCOMB_X1_Y19_N22
L1L4 = Cont[24] & (Cont[25] $ (!Cont[26])) # !Cont[24] & (Cont[25] & Cont[27] & !Cont[26] # !Cont[25] & !Cont[27] & Cont[26]);


--L1L5 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[4]~74 at LCCOMB_X1_Y19_N0
L1L5 = Cont[25] & !Cont[27] & Cont[24] # !Cont[25] & (Cont[26] & !Cont[27] # !Cont[26] & (Cont[24]));


--L1L6 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[5]~75 at LCCOMB_X1_Y19_N10
L1L6 = Cont[25] & !Cont[27] & (Cont[24] # !Cont[26]) # !Cont[25] & Cont[24] & (Cont[27] $ !Cont[26]);


--L1L7 is SEG7_LUT_4:u0|SEG7_LUT:u0|oSEG[6]~76 at LCCOMB_X1_Y19_N12
L1L7 = Cont[24] & (Cont[27] # Cont[25] $ Cont[26]) # !Cont[24] & (Cont[25] # Cont[27] $ Cont[26]);


--D1_mLED[0] is LEDG_Driver:u2|mLED[0] at LCFF_X30_Y9_N31
D1_mLED[0] = DFFEAS(D1L80, GLOBAL(D1L65), KEY[0],  ,  ,  ,  ,  ,  );


--D1_mLED[1] is LEDG_Driver:u2|mLED[1] at LCFF_X30_Y7_N23
D1_mLED[1] = DFFEAS(D1L81, GLOBAL(D1L65), KEY[0],  ,  ,  ,  ,  ,  );


--D1_mLED[2] is LEDG_Driver:u2|mLED[2] at LCFF_X30_Y7_N29
D1_mLED[2] = DFFEAS(D1L82, GLOBAL(D1L65), KEY[0],  ,  ,  ,  ,  ,  );


--D1_mLED[3] is LEDG_Driver:u2|mLED[3] at LCFF_X30_Y7_N19
D1_mLED[3] = DFFEAS(D1L83, GLOBAL(D1L65), KEY[0],  ,  ,  ,  ,  ,  );


--D1_mLED[4] is LEDG_Driver:u2|mLED[4] at LCFF_X49_Y7_N5
D1_mLED[4] = DFFEAS(D1L84, GLOBAL(D1L65), KEY[0],  ,  ,  ,  ,  ,  );


--D1_mLED[5] is LEDG_Driver:u2|mLED[5] at LCFF_X49_Y7_N17
D1_mLED[5] = DFFEAS(D1L85, GLOBAL(D1L65), KEY[0],  ,  ,  ,  ,  ,  );


--D1_mLED[6] is LEDG_Driver:u2|mLED[6] at LCFF_X31_Y12_N27
D1_mLED[6] = DFFEAS(D1L86, GLOBAL(D1L65), KEY[0],  ,  ,  ,  ,  ,  );


--D1_mLED[7] is LEDG_Driver:u2|mLED[7] at LCFF_X31_Y12_N25
D1_mLED[7] = DFFEAS(D1L87, GLOBAL(D1L65), KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[0] is LEDR_Driver:u1|mLED[0] at LCFF_X49_Y7_N1
C1_mLED[0] = DFFEAS(C1L82, GLOBAL(C1L65), KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[1] is LEDR_Driver:u1|mLED[1] at LCFF_X49_Y7_N19
C1_mLED[1] = DFFEAS(C1L83, GLOBAL(C1L65), KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[2] is LEDR_Driver:u1|mLED[2] at LCFF_X49_Y7_N27
C1_mLED[2] = DFFEAS(C1L84, GLOBAL(C1L65), KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[3] is LEDR_Driver:u1|mLED[3] at LCFF_X49_Y7_N11
C1_mLED[3] = DFFEAS(C1L85, GLOBAL(C1L65), KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[4] is LEDR_Driver:u1|mLED[4] at LCFF_X49_Y7_N23
C1_mLED[4] = DFFEAS(C1L86, GLOBAL(C1L65), KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[5] is LEDR_Driver:u1|mLED[5] at LCFF_X49_Y7_N31
C1_mLED[5] = DFFEAS(C1L87, GLOBAL(C1L65), KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[6] is LEDR_Driver:u1|mLED[6] at LCFF_X49_Y7_N29
C1_mLED[6] = DFFEAS(C1L88, GLOBAL(C1L65), KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[7] is LEDR_Driver:u1|mLED[7] at LCFF_X49_Y7_N7
C1_mLED[7] = DFFEAS(C1L89, GLOBAL(C1L65), KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[8] is LEDR_Driver:u1|mLED[8] at LCFF_X49_Y7_N3
C1_mLED[8] = DFFEAS(C1L90, GLOBAL(C1L65), KEY[0],  ,  ,  ,  ,  ,  );


--C1_mLED[9] is LEDR_Driver:u1|mLED[9] at LCFF_X49_Y7_N21
C1_mLED[9] = DFFEAS(C1L91, GLOBAL(C1L65), KEY[0],  ,  ,  ,  ,  ,  );


--V1L43Q is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[0]~reg0 at LCFF_X34_Y13_N21
V1L43Q = DFFEAS(V1L41, GLOBAL(J1L73), KEY[0],  ,  , VCC,  ,  , !J1_mI2C_GO);


--V1L49Q is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[2]~reg0 at LCFF_X34_Y13_N25
V1L49Q = DFFEAS(V1L47, GLOBAL(J1L73), KEY[0],  ,  , VCC,  ,  , !J1_mI2C_GO);


--V1L52Q is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[3]~reg0 at LCFF_X34_Y13_N27
V1L52Q = DFFEAS(V1L50, GLOBAL(J1L73), KEY[0],  ,  , VCC,  ,  , !J1_mI2C_GO);


--V1L46Q is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[1]~reg0 at LCFF_X34_Y13_N23
V1L46Q = DFFEAS(V1L44, GLOBAL(J1L73), KEY[0],  ,  , VCC,  ,  , !J1_mI2C_GO);


--V1L15 is I2C_AV_Config:u7|I2C_Controller:u0|I2C_SCLK~253 at LCCOMB_X33_Y14_N18
V1L15 = V1L46Q # V1L49Q # V1L43Q # V1L52Q;


--V1L55Q is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[4]~reg0 at LCFF_X34_Y13_N29
V1L55Q = DFFEAS(V1L53, GLOBAL(J1L73), KEY[0],  ,  , VCC,  ,  , !J1_mI2C_GO);


--V1L16 is I2C_AV_Config:u7|I2C_Controller:u0|I2C_SCLK~254 at LCCOMB_X35_Y14_N28
V1L16 = V1L55Q & (!V1L52Q # !V1L49Q) # !V1L55Q & V1L15;


--V1L58Q is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[5]~reg0 at LCFF_X34_Y13_N31
V1L58Q = DFFEAS(V1L56, GLOBAL(J1L73), KEY[0],  ,  , VCC,  ,  , !J1_mI2C_GO);


--J1_mI2C_CTRL_CLK is I2C_AV_Config:u7|mI2C_CTRL_CLK at LCFF_X35_Y14_N3
J1_mI2C_CTRL_CLK = DFFEAS(J1L72, GLOBAL(A1L16), KEY[0],  ,  ,  ,  ,  ,  );


--V1_SCLK is I2C_AV_Config:u7|I2C_Controller:u0|SCLK at LCFF_X35_Y14_N25
V1_SCLK = DFFEAS(V1L23, GLOBAL(J1L73), KEY[0],  ,  ,  ,  ,  ,  );


--V1L17 is I2C_AV_Config:u7|I2C_Controller:u0|I2C_SCLK~255 at LCCOMB_X35_Y14_N8
V1L17 = V1L58Q & !J1_mI2C_CTRL_CLK & V1L16 # !V1_SCLK;


--F1_oVGA_H_SYNC is VGA_Controller:u4|oVGA_H_SYNC at LCFF_X30_Y11_N25
F1_oVGA_H_SYNC = DFFEAS(F1L56, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--F1_oVGA_V_SYNC is VGA_Controller:u4|oVGA_V_SYNC at LCFF_X24_Y11_N25
F1_oVGA_V_SYNC = DFFEAS(F1L267, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--F1_Cur_Color_R[7] is VGA_Controller:u4|Cur_Color_R[7] at LCFF_X25_Y11_N31
F1_Cur_Color_R[7] = DFFEAS(A1L402, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--F1_H_Cont[5] is VGA_Controller:u4|H_Cont[5] at LCFF_X30_Y9_N13
F1_H_Cont[5] = DFFEAS(F1L37, GLOBAL(M1L2), KEY[0],  ,  ,  ,  , F1L57,  );


--F1_H_Cont[6] is VGA_Controller:u4|H_Cont[6] at LCFF_X30_Y9_N15
F1_H_Cont[6] = DFFEAS(F1L40, GLOBAL(M1L2), KEY[0],  ,  ,  ,  , F1L57,  );


--F1L15 is VGA_Controller:u4|Equal~110 at LCCOMB_X30_Y11_N20
F1L15 = !F1_H_Cont[6] & !F1_H_Cont[5];


--F1_H_Cont[0] is VGA_Controller:u4|H_Cont[0] at LCFF_X30_Y9_N3
F1_H_Cont[0] = DFFEAS(F1L22, GLOBAL(M1L2), KEY[0],  ,  ,  ,  , F1L57,  );


--F1_H_Cont[1] is VGA_Controller:u4|H_Cont[1] at LCFF_X30_Y9_N5
F1_H_Cont[1] = DFFEAS(F1L25, GLOBAL(M1L2), KEY[0],  ,  ,  ,  , F1L57,  );


--F1_H_Cont[2] is VGA_Controller:u4|H_Cont[2] at LCFF_X30_Y9_N7
F1_H_Cont[2] = DFFEAS(F1L28, GLOBAL(M1L2), KEY[0],  ,  ,  ,  , F1L57,  );


--F1_H_Cont[3] is VGA_Controller:u4|H_Cont[3] at LCFF_X30_Y9_N9
F1_H_Cont[3] = DFFEAS(F1L31, GLOBAL(M1L2), KEY[0],  ,  ,  ,  , F1L57,  );


--F1L51 is VGA_Controller:u4|LessThan~1165 at LCCOMB_X29_Y10_N18
F1L51 = !F1_H_Cont[1] & !F1_H_Cont[0] # !F1_H_Cont[3] # !F1_H_Cont[2];


--F1_H_Cont[4] is VGA_Controller:u4|H_Cont[4] at LCFF_X30_Y9_N11
F1_H_Cont[4] = DFFEAS(F1L34, GLOBAL(M1L2), KEY[0],  ,  ,  ,  , F1L57,  );


--F1_H_Cont[7] is VGA_Controller:u4|H_Cont[7] at LCFF_X30_Y9_N17
F1_H_Cont[7] = DFFEAS(F1L43, GLOBAL(M1L2), KEY[0],  ,  ,  ,  , F1L57,  );


--F1_H_Cont[8] is VGA_Controller:u4|H_Cont[8] at LCFF_X30_Y9_N19
F1_H_Cont[8] = DFFEAS(F1L46, GLOBAL(M1L2), KEY[0],  ,  ,  ,  , F1L57,  );


--F1_H_Cont[9] is VGA_Controller:u4|H_Cont[9] at LCFF_X30_Y9_N21
F1_H_Cont[9] = DFFEAS(F1L49, GLOBAL(M1L2), KEY[0],  ,  ,  ,  , F1L57,  );


--F1L264 is VGA_Controller:u4|oVGA_R~305 at LCCOMB_X30_Y11_N28
F1L264 = !F1_H_Cont[7] & F1L61 # !F1_H_Cont[8] # !F1_H_Cont[9];


--F1_V_Cont[6] is VGA_Controller:u4|V_Cont[6] at LCFF_X24_Y11_N15
F1_V_Cont[6] = DFFEAS(F1L84, GLOBAL(M1L2), KEY[0],  , F1L19,  ,  , F1L60,  );


--F1_V_Cont[7] is VGA_Controller:u4|V_Cont[7] at LCFF_X24_Y11_N17
F1_V_Cont[7] = DFFEAS(F1L87, GLOBAL(M1L2), KEY[0],  , F1L19,  ,  , F1L60,  );


--F1_V_Cont[8] is VGA_Controller:u4|V_Cont[8] at LCFF_X24_Y11_N19
F1_V_Cont[8] = DFFEAS(F1L90, GLOBAL(M1L2), KEY[0],  , F1L19,  ,  , F1L60,  );


--F1L52 is VGA_Controller:u4|LessThan~1166 at LCCOMB_X24_Y10_N30
F1L52 = !F1_V_Cont[8] & !F1_V_Cont[7] & !F1_V_Cont[6];


--F1_V_Cont[1] is VGA_Controller:u4|V_Cont[1] at LCFF_X24_Y11_N5
F1_V_Cont[1] = DFFEAS(F1L69, GLOBAL(M1L2), KEY[0],  , F1L19,  ,  , F1L60,  );


--F1_V_Cont[2] is VGA_Controller:u4|V_Cont[2] at LCFF_X24_Y11_N7
F1_V_Cont[2] = DFFEAS(F1L72, GLOBAL(M1L2), KEY[0],  , F1L19,  ,  , F1L60,  );


--F1_V_Cont[3] is VGA_Controller:u4|V_Cont[3] at LCFF_X24_Y11_N9
F1_V_Cont[3] = DFFEAS(F1L75, GLOBAL(M1L2), KEY[0],  , F1L19,  ,  , F1L60,  );


--F1L53 is VGA_Controller:u4|LessThan~1167 at LCCOMB_X24_Y10_N28
F1L53 = !F1_V_Cont[3] & !F1_V_Cont[2] & !F1_V_Cont[1];


--F1_V_Cont[4] is VGA_Controller:u4|V_Cont[4] at LCFF_X24_Y11_N11
F1_V_Cont[4] = DFFEAS(F1L78, GLOBAL(M1L2), KEY[0],  , F1L19,  ,  , F1L60,  );


--F1_V_Cont[5] is VGA_Controller:u4|V_Cont[5] at LCFF_X24_Y11_N13
F1_V_Cont[5] = DFFEAS(F1L81, GLOBAL(M1L2), KEY[0],  , F1L19,  ,  , F1L60,  );


--F1L54 is VGA_Controller:u4|LessThan~1168 at LCCOMB_X24_Y10_N6
F1L54 = F1L53 & !F1_V_Cont[4] # !F1_V_Cont[5];


--F1_V_Cont[9] is VGA_Controller:u4|V_Cont[9] at LCFF_X24_Y11_N21
F1_V_Cont[9] = DFFEAS(F1L93, GLOBAL(M1L2), KEY[0],  , F1L19,  ,  , F1L60,  );


--F1L55 is VGA_Controller:u4|LessThan~1169 at LCCOMB_X24_Y10_N2
F1L55 = F1_V_Cont[4] # F1_V_Cont[5] # !F1L53 # !F1L52;


--F1L265 is VGA_Controller:u4|oVGA_R~306 at LCCOMB_X24_Y10_N4
F1L265 = F1_V_Cont[9] & (!F1L55) # !F1_V_Cont[9] & (!F1L52 # !F1L54);


--F1L16 is VGA_Controller:u4|Equal~111 at LCCOMB_X30_Y11_N22
F1L16 = !F1_H_Cont[8] & !F1_H_Cont[9];


--F1L261 is VGA_Controller:u4|oVGA_R[6]~307 at LCCOMB_X25_Y11_N2
F1L261 = F1L264 & F1_Cur_Color_R[7] & !F1L62 & F1L265;


--F1_Cur_Color_R[8] is VGA_Controller:u4|Cur_Color_R[8] at LCFF_X25_Y11_N15
F1_Cur_Color_R[8] = DFFEAS(A1L403, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--F1L262 is VGA_Controller:u4|oVGA_R[8]~308 at LCCOMB_X25_Y11_N26
F1L262 = F1L264 & F1_Cur_Color_R[8] & !F1L62 & F1L265;


--F1_Cur_Color_R[9] is VGA_Controller:u4|Cur_Color_R[9] at LCFF_X25_Y11_N25
F1_Cur_Color_R[9] = DFFEAS(A1L404, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--F1L263 is VGA_Controller:u4|oVGA_R[9]~309 at LCCOMB_X25_Y11_N8
F1L263 = F1L264 & F1L265 & !F1L62 & F1_Cur_Color_R[9];


--F1_Cur_Color_G[6] is VGA_Controller:u4|Cur_Color_G[6] at LCFF_X25_Y11_N11
F1_Cur_Color_G[6] = DFFEAS(A1L398, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--F1L256 is VGA_Controller:u4|oVGA_G[6]~60 at LCCOMB_X25_Y11_N0
F1L256 = F1L264 & F1L265 & !F1L62 & F1_Cur_Color_G[6];


--F1_Cur_Color_G[7] is VGA_Controller:u4|Cur_Color_G[7] at LCFF_X25_Y11_N21
F1_Cur_Color_G[7] = DFFEAS(A1L399, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--F1L257 is VGA_Controller:u4|oVGA_G[7]~61 at LCCOMB_X25_Y11_N18
F1L257 = F1L264 & F1L265 & !F1L62 & F1_Cur_Color_G[7];


--F1_Cur_Color_G[8] is VGA_Controller:u4|Cur_Color_G[8] at LCFF_X24_Y11_N23
F1_Cur_Color_G[8] = DFFEAS(A1L400, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--F1L258 is VGA_Controller:u4|oVGA_G[8]~62 at LCCOMB_X24_Y11_N30
F1L258 = F1L264 & F1_Cur_Color_G[8] & F1L265 & !F1L62;


--F1_Cur_Color_G[9] is VGA_Controller:u4|Cur_Color_G[9] at LCFF_X31_Y12_N17
F1_Cur_Color_G[9] = DFFEAS(A1L401, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--F1L259 is VGA_Controller:u4|oVGA_G[9]~63 at LCCOMB_X31_Y12_N28
F1L259 = F1L265 & F1L264 & F1_Cur_Color_G[9] & !F1L62;


--F1_Cur_Color_B[6] is VGA_Controller:u4|Cur_Color_B[6] at LCFF_X31_Y12_N23
F1_Cur_Color_B[6] = DFFEAS(A1L394, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--F1L252 is VGA_Controller:u4|oVGA_B[6]~60 at LCCOMB_X31_Y12_N6
F1L252 = F1L265 & F1L264 & F1_Cur_Color_B[6] & !F1L62;


--F1_Cur_Color_B[7] is VGA_Controller:u4|Cur_Color_B[7] at LCFF_X26_Y12_N25
F1_Cur_Color_B[7] = DFFEAS(A1L395, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--F1L253 is VGA_Controller:u4|oVGA_B[7]~61 at LCCOMB_X31_Y12_N10
F1L253 = F1L265 & F1L264 & F1_Cur_Color_B[7] & !F1L62;


--F1_Cur_Color_B[8] is VGA_Controller:u4|Cur_Color_B[8] at LCFF_X26_Y12_N15
F1_Cur_Color_B[8] = DFFEAS(A1L396, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--F1L254 is VGA_Controller:u4|oVGA_B[8]~62 at LCCOMB_X26_Y12_N4
F1L254 = F1L264 & F1_Cur_Color_B[8] & !F1L62 & F1L265;


--F1_Cur_Color_B[9] is VGA_Controller:u4|Cur_Color_B[9] at LCFF_X26_Y12_N1
F1_Cur_Color_B[9] = DFFEAS(A1L397, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--F1L255 is VGA_Controller:u4|oVGA_B[9]~63 at LCCOMB_X31_Y12_N4
F1L255 = F1L265 & F1L264 & F1_Cur_Color_B[9] & !F1L62;


--K1_LRCK_1X is AUDIO_DAC:u8|LRCK_1X at LCFF_X30_Y7_N21
K1_LRCK_1X = DFFEAS(K1L37, GLOBAL(M1L4), KEY[0],  ,  ,  ,  ,  ,  );


--K1L133Q is AUDIO_DAC:u8|rom~47 at LCFF_X29_Y20_N11
K1L133Q = DFFEAS(K1L143, !GLOBAL(K1L38), KEY[0],  ,  ,  ,  , K1L43,  );


--K1_SEL_Cont[1] is AUDIO_DAC:u8|SEL_Cont[1] at LCFF_X30_Y19_N11
K1_SEL_Cont[1] = DFFEAS(K1L119, !GLOBAL(K1L126), KEY[0],  ,  ,  ,  ,  ,  );


--K1_SEL_Cont[3] is AUDIO_DAC:u8|SEL_Cont[3] at LCFF_X30_Y19_N1
K1_SEL_Cont[3] = DFFEAS(K1L123, !GLOBAL(K1L126), KEY[0],  ,  ,  ,  ,  ,  );


--K1L131Q is AUDIO_DAC:u8|rom~45 at LCFF_X29_Y20_N7
K1L131Q = DFFEAS(K1L139, !GLOBAL(K1L38), KEY[0],  ,  ,  ,  , K1L43,  );


--K1_SEL_Cont[0] is AUDIO_DAC:u8|SEL_Cont[0] at LCFF_X30_Y19_N29
K1_SEL_Cont[0] = DFFEAS(K1L117, !GLOBAL(K1L126), KEY[0],  ,  ,  ,  ,  ,  );


--K1L44 is AUDIO_DAC:u8|Mux~1930 at LCCOMB_X30_Y20_N26
K1L44 = K1L131Q & (K1_SEL_Cont[0] & (!K1_SEL_Cont[3]) # !K1_SEL_Cont[0] & !K1_SEL_Cont[1] & K1_SEL_Cont[3]) # !K1L131Q & K1_SEL_Cont[1] & (K1_SEL_Cont[0] $ !K1_SEL_Cont[3]);


--K1L130Q is AUDIO_DAC:u8|rom~44 at LCFF_X29_Y20_N5
K1L130Q = DFFEAS(K1L137, !GLOBAL(K1L38), KEY[0],  ,  ,  ,  , K1L43,  );


--K1_SEL_Cont[2] is AUDIO_DAC:u8|SEL_Cont[2] at LCFF_X30_Y19_N19
K1_SEL_Cont[2] = DFFEAS(K1L121, !GLOBAL(K1L126), KEY[0],  ,  ,  ,  ,  ,  );


--K1L45 is AUDIO_DAC:u8|Mux~1931 at LCCOMB_X30_Y20_N12
K1L45 = K1L131Q & (K1_SEL_Cont[1] & K1_SEL_Cont[2] & K1_SEL_Cont[3] # !K1_SEL_Cont[1] & !K1_SEL_Cont[2] & !K1_SEL_Cont[3]);


--K1L46 is AUDIO_DAC:u8|Mux~1932 at LCCOMB_X30_Y20_N8
K1L46 = K1L130Q & (K1_SEL_Cont[2]) # !K1L130Q & K1L45 & (K1_SEL_Cont[0] # !K1_SEL_Cont[2]);


--K1L47 is AUDIO_DAC:u8|Mux~1933 at LCCOMB_X30_Y20_N20
K1L47 = K1L131Q & (K1_SEL_Cont[0] & K1_SEL_Cont[1] & K1_SEL_Cont[3] # !K1_SEL_Cont[0] & (!K1_SEL_Cont[3])) # !K1L131Q & (K1_SEL_Cont[3] # K1_SEL_Cont[1] & K1_SEL_Cont[0]);


--K1L48 is AUDIO_DAC:u8|Mux~1934 at LCCOMB_X30_Y20_N30
K1L48 = K1L46 & (!K1L130Q # !K1L47) # !K1L46 & (K1L130Q & !K1L44);


--K1L132Q is AUDIO_DAC:u8|rom~46 at LCFF_X29_Y20_N9
K1L132Q = DFFEAS(K1L141, !GLOBAL(K1L38), KEY[0],  ,  ,  ,  , K1L43,  );


--K1L49 is AUDIO_DAC:u8|Mux~1935 at LCCOMB_X29_Y21_N22
K1L49 = !K1_SEL_Cont[2] & K1_SEL_Cont[1] & (K1_SEL_Cont[0] # !K1L130Q);


--K1L50 is AUDIO_DAC:u8|Mux~1936 at LCCOMB_X29_Y21_N14
K1L50 = K1_SEL_Cont[1] & !K1_SEL_Cont[2] & (K1_SEL_Cont[0] # !K1L130Q) # !K1_SEL_Cont[1] & K1_SEL_Cont[0] & (K1_SEL_Cont[2] # !K1L130Q);


--K1L51 is AUDIO_DAC:u8|Mux~1937 at LCCOMB_X29_Y21_N30
K1L51 = K1_SEL_Cont[2] & (K1_SEL_Cont[0] # !K1_SEL_Cont[1] & K1L130Q) # !K1_SEL_Cont[2] & (K1_SEL_Cont[1] & !K1L130Q & !K1_SEL_Cont[0] # !K1_SEL_Cont[1] & (K1_SEL_Cont[0]));


--K1L52 is AUDIO_DAC:u8|Mux~1938 at LCCOMB_X29_Y20_N14
K1L52 = K1_SEL_Cont[3] & (K1L131Q # !K1L50) # !K1_SEL_Cont[3] & (K1L51 & !K1L131Q);


--K1L53 is AUDIO_DAC:u8|Mux~1939 at LCCOMB_X29_Y21_N12
K1L53 = K1_SEL_Cont[2] & (K1L130Q $ (!K1_SEL_Cont[1] & K1_SEL_Cont[0])) # !K1_SEL_Cont[2] & !K1_SEL_Cont[1] & K1L130Q & K1_SEL_Cont[0];


--K1L54 is AUDIO_DAC:u8|Mux~1940 at LCCOMB_X29_Y20_N28
K1L54 = K1L52 & (!K1L131Q # !K1L53) # !K1L52 & K1L49 & (K1L131Q);


--K1L129Q is AUDIO_DAC:u8|rom~43 at LCFF_X29_Y20_N3
K1L129Q = DFFEAS(K1L135, !GLOBAL(K1L38), KEY[0],  ,  ,  ,  , K1L43,  );


--K1L55 is AUDIO_DAC:u8|Mux~1941 at LCCOMB_X30_Y20_N18
K1L55 = !K1L131Q & (K1_SEL_Cont[0] & !K1_SEL_Cont[2] & !K1_SEL_Cont[3] # !K1_SEL_Cont[0] & (K1_SEL_Cont[2] $ K1_SEL_Cont[3]));


--K1L56 is AUDIO_DAC:u8|Mux~1942 at LCCOMB_X30_Y20_N16
K1L56 = K1L131Q # K1_SEL_Cont[0] $ !K1_SEL_Cont[3];


--K1L57 is AUDIO_DAC:u8|Mux~1943 at LCCOMB_X30_Y20_N28
K1L57 = K1_SEL_Cont[2] & (K1L131Q # !K1_SEL_Cont[3] # !K1_SEL_Cont[0]) # !K1_SEL_Cont[2] & (K1_SEL_Cont[3] # K1_SEL_Cont[0] & !K1L131Q);


--K1L58 is AUDIO_DAC:u8|Mux~1944 at LCCOMB_X30_Y20_N2
K1L58 = K1L130Q & (K1_SEL_Cont[1]) # !K1L130Q & (K1_SEL_Cont[1] & K1L56 # !K1_SEL_Cont[1] & (K1L57));


--K1L59 is AUDIO_DAC:u8|Mux~1945 at LCCOMB_X30_Y20_N10
K1L59 = K1_SEL_Cont[3] & (K1_SEL_Cont[0] & K1_SEL_Cont[2] & !K1L131Q # !K1_SEL_Cont[0] & !K1_SEL_Cont[2] & K1L131Q) # !K1_SEL_Cont[3] & (K1_SEL_Cont[0] $ K1_SEL_Cont[2] $ K1L131Q);


--K1L60 is AUDIO_DAC:u8|Mux~1946 at LCCOMB_X30_Y20_N0
K1L60 = K1L58 & (K1L59 # !K1L130Q) # !K1L58 & (K1L130Q & K1L55);


--K1L61 is AUDIO_DAC:u8|Mux~1947 at LCCOMB_X29_Y20_N0
K1L61 = K1L132Q & (K1L129Q) # !K1L132Q & (K1L129Q & (K1L54) # !K1L129Q & K1L60);


--K1L62 is AUDIO_DAC:u8|Mux~1948 at LCCOMB_X29_Y21_N0
K1L62 = K1_SEL_Cont[0] & (K1_SEL_Cont[1] $ (K1_SEL_Cont[2] & K1L130Q)) # !K1_SEL_Cont[0] & K1_SEL_Cont[1] & (K1_SEL_Cont[2] $ K1L130Q);


--K1L63 is AUDIO_DAC:u8|Mux~1949 at LCCOMB_X30_Y20_N6
K1L63 = K1L130Q & K1_SEL_Cont[0] & (!K1_SEL_Cont[1]) # !K1L130Q & (K1_SEL_Cont[2]);


--K1L64 is AUDIO_DAC:u8|Mux~1950 at LCCOMB_X30_Y20_N14
K1L64 = K1L131Q & (K1L63 & K1_SEL_Cont[0] # !K1L63 & (K1L62)) # !K1L131Q & (K1L63 $ (K1_SEL_Cont[0] & !K1L62));


--K1L65 is AUDIO_DAC:u8|Mux~1951 at LCCOMB_X30_Y20_N22
K1L65 = K1L62 & (K1L63 $ (!K1L131Q # !K1_SEL_Cont[0])) # !K1L62 & K1L131Q & (K1_SEL_Cont[0] # K1L63);


--K1L66 is AUDIO_DAC:u8|Mux~1952 at LCCOMB_X30_Y20_N24
K1L66 = K1_SEL_Cont[3] & (K1L64) # !K1_SEL_Cont[3] & !K1L65;


--K1L67 is AUDIO_DAC:u8|Mux~1953 at LCCOMB_X29_Y20_N20
K1L67 = K1L61 & (K1L66 # !K1L132Q) # !K1L61 & (K1L132Q & K1L48);


--K1L134Q is AUDIO_DAC:u8|rom~48 at LCFF_X29_Y20_N13
K1L134Q = DFFEAS(K1L145, !GLOBAL(K1L38), KEY[0],  ,  ,  ,  , K1L43,  );


--K1L68 is AUDIO_DAC:u8|Mux~1954 at LCCOMB_X30_Y19_N26
K1L68 = K1_SEL_Cont[1] & (K1L132Q # !K1_SEL_Cont[3] # !K1_SEL_Cont[0]) # !K1_SEL_Cont[1] & (K1_SEL_Cont[3] # K1_SEL_Cont[0] & !K1L132Q);


--K1L69 is AUDIO_DAC:u8|Mux~1955 at LCCOMB_X30_Y19_N8
K1L69 = K1_SEL_Cont[3] & K1L132Q & (K1_SEL_Cont[1] # !K1_SEL_Cont[0]) # !K1_SEL_Cont[3] & (K1_SEL_Cont[0] $ (K1_SEL_Cont[1] & !K1L132Q));


--K1L70 is AUDIO_DAC:u8|Mux~1956 at LCCOMB_X30_Y19_N20
K1L70 = K1_SEL_Cont[1] & !K1_SEL_Cont[3] & (!K1L132Q # !K1_SEL_Cont[0]) # !K1_SEL_Cont[1] & (K1_SEL_Cont[0] $ (K1_SEL_Cont[3] & K1L132Q));


--K1L71 is AUDIO_DAC:u8|Mux~1957 at LCCOMB_X30_Y19_N22
K1L71 = K1L131Q & (K1_SEL_Cont[2]) # !K1L131Q & (K1_SEL_Cont[2] & !K1L69 # !K1_SEL_Cont[2] & (!K1L70));


--K1L72 is AUDIO_DAC:u8|Mux~1958 at LCCOMB_X30_Y19_N24
K1L72 = K1_SEL_Cont[1] & (K1_SEL_Cont[0] # !K1_SEL_Cont[3] & K1L132Q) # !K1_SEL_Cont[1] & (K1L132Q $ (!K1_SEL_Cont[0] & K1_SEL_Cont[3]));


--K1L73 is AUDIO_DAC:u8|Mux~1959 at LCCOMB_X30_Y19_N14
K1L73 = K1L131Q & (K1L71 & K1L72 # !K1L71 & (!K1L68)) # !K1L131Q & K1L71;


--K1L74 is AUDIO_DAC:u8|Mux~1960 at LCCOMB_X29_Y19_N30
K1L74 = K1_SEL_Cont[2] & (K1_SEL_Cont[3] & (K1L131Q) # !K1_SEL_Cont[3] & !K1_SEL_Cont[0] & !K1L131Q) # !K1_SEL_Cont[2] & !K1L131Q & (K1_SEL_Cont[0] $ K1_SEL_Cont[3]);


--K1L75 is AUDIO_DAC:u8|Mux~1961 at LCCOMB_X30_Y19_N12
K1L75 = K1_SEL_Cont[1] & K1_SEL_Cont[0] & (K1_SEL_Cont[3]) # !K1_SEL_Cont[1] & (K1_SEL_Cont[0] & !K1_SEL_Cont[2] & !K1_SEL_Cont[3] # !K1_SEL_Cont[0] & (K1_SEL_Cont[2] $ K1_SEL_Cont[3]));


--K1L76 is AUDIO_DAC:u8|Mux~1962 at LCCOMB_X30_Y19_N16
K1L76 = K1_SEL_Cont[1] $ (!K1L75 & !K1L132Q);


--K1L77 is AUDIO_DAC:u8|Mux~1963 at LCCOMB_X29_Y19_N14
K1L77 = K1_SEL_Cont[3] & (K1_SEL_Cont[0] & (K1_SEL_Cont[2] # K1L131Q) # !K1_SEL_Cont[0] & K1_SEL_Cont[2] & K1L131Q) # !K1_SEL_Cont[3] & (K1_SEL_Cont[0] $ K1_SEL_Cont[2] $ K1L131Q);


--K1L78 is AUDIO_DAC:u8|Mux~1964 at LCCOMB_X29_Y19_N6
K1L78 = K1L76 & (!K1L132Q # !K1L77) # !K1L76 & !K1L74 & (K1L132Q);


--K1L79 is AUDIO_DAC:u8|Mux~1965 at LCCOMB_X30_Y19_N6
K1L79 = K1_SEL_Cont[0] & (K1_SEL_Cont[3] & (K1_SEL_Cont[2]) # !K1_SEL_Cont[3] & K1_SEL_Cont[1]) # !K1_SEL_Cont[0] & (K1_SEL_Cont[1] & (K1_SEL_Cont[3]) # !K1_SEL_Cont[1] & !K1_SEL_Cont[2] & !K1_SEL_Cont[3]);


--K1L80 is AUDIO_DAC:u8|Mux~1966 at LCCOMB_X30_Y19_N4
K1L80 = K1_SEL_Cont[3] # K1_SEL_Cont[2] # K1_SEL_Cont[0] & !K1L132Q;


--K1L81 is AUDIO_DAC:u8|Mux~1967 at LCCOMB_X30_Y19_N30
K1L81 = K1L131Q & !K1_SEL_Cont[1] & !K1L80 # !K1L131Q & (K1L79);


--K1L82 is AUDIO_DAC:u8|Mux~1968 at LCCOMB_X29_Y19_N2
K1L82 = K1L130Q & (K1L78 # K1L129Q) # !K1L130Q & (K1L81 & !K1L129Q);


--K1L83 is AUDIO_DAC:u8|Mux~1969 at LCCOMB_X30_Y19_N2
K1L83 = K1L132Q & (K1_SEL_Cont[0] & K1_SEL_Cont[1] # !K1_SEL_Cont[0] & (K1_SEL_Cont[3])) # !K1L132Q & (K1_SEL_Cont[1] & (!K1_SEL_Cont[3]) # !K1_SEL_Cont[1] & K1_SEL_Cont[0]);


--K1L84 is AUDIO_DAC:u8|Mux~1970 at LCCOMB_X29_Y19_N20
K1L84 = K1_SEL_Cont[1] & (K1_SEL_Cont[0] $ (!K1_SEL_Cont[3] & K1L132Q)) # !K1_SEL_Cont[1] & K1_SEL_Cont[3] & (K1_SEL_Cont[0] $ !K1L132Q);


--K1L85 is AUDIO_DAC:u8|Mux~1971 at LCCOMB_X29_Y19_N16
K1L85 = K1_SEL_Cont[1] & (K1_SEL_Cont[3] & !K1_SEL_Cont[0] # !K1_SEL_Cont[3] & (!K1L132Q)) # !K1_SEL_Cont[1] & (K1_SEL_Cont[0] # K1_SEL_Cont[3]);


--K1L86 is AUDIO_DAC:u8|Mux~1972 at LCCOMB_X29_Y19_N24
K1L86 = K1_SEL_Cont[2] & (K1L84 # K1L131Q) # !K1_SEL_Cont[2] & !K1L85 & (!K1L131Q);


--K1L87 is AUDIO_DAC:u8|Mux~1973 at LCCOMB_X29_Y19_N22
K1L87 = K1_SEL_Cont[1] & !K1_SEL_Cont[0] & !K1_SEL_Cont[3] & !K1L132Q # !K1_SEL_Cont[1] & K1_SEL_Cont[0] & (K1_SEL_Cont[3] $ !K1L132Q);


--K1L88 is AUDIO_DAC:u8|Mux~1974 at LCCOMB_X29_Y19_N10
K1L88 = K1L86 & (!K1L131Q # !K1L87) # !K1L86 & !K1L83 & (K1L131Q);


--K1L89 is AUDIO_DAC:u8|Mux~1975 at LCCOMB_X29_Y19_N28
K1L89 = K1L82 & (K1L88 # !K1L129Q) # !K1L82 & (K1L73 & K1L129Q);


--K1L90 is AUDIO_DAC:u8|Mux~1976 at LCCOMB_X29_Y19_N26
K1L90 = K1_SEL_Cont[0] & (K1_SEL_Cont[1] $ (K1L130Q & !K1L129Q)) # !K1_SEL_Cont[0] & !K1L130Q & !K1_SEL_Cont[1] & K1L129Q;


--K1L91 is AUDIO_DAC:u8|Mux~1977 at LCCOMB_X29_Y19_N18
K1L91 = K1_SEL_Cont[0] & (K1L129Q & (K1_SEL_Cont[1]) # !K1L129Q & K1L130Q) # !K1_SEL_Cont[0] & !K1L130Q & (K1_SEL_Cont[1] # K1L129Q);


--K1L92 is AUDIO_DAC:u8|Mux~1978 at LCCOMB_X29_Y19_N8
K1L92 = K1_SEL_Cont[0] & (K1L130Q # K1L129Q # !K1_SEL_Cont[1]) # !K1_SEL_Cont[0] & (K1_SEL_Cont[1]);


--K1L93 is AUDIO_DAC:u8|Mux~1979 at LCCOMB_X29_Y19_N12
K1L93 = K1_SEL_Cont[3] & (K1_SEL_Cont[2] # !K1L91) # !K1_SEL_Cont[3] & (K1L92 & !K1_SEL_Cont[2]);


--K1L94 is AUDIO_DAC:u8|Mux~1980 at LCCOMB_X29_Y19_N4
K1L94 = K1L130Q & (K1_SEL_Cont[0] & (K1_SEL_Cont[1] # !K1L129Q) # !K1_SEL_Cont[0] & !K1_SEL_Cont[1]) # !K1L130Q & (K1L129Q # K1_SEL_Cont[0] $ K1_SEL_Cont[1]);


--K1L95 is AUDIO_DAC:u8|Mux~1981 at LCCOMB_X29_Y19_N0
K1L95 = K1L93 & (!K1_SEL_Cont[2] # !K1L94) # !K1L93 & !K1L90 & (K1_SEL_Cont[2]);


--K1L96 is AUDIO_DAC:u8|Mux~1982 at LCCOMB_X30_Y20_N4
K1L96 = K1_SEL_Cont[1] & !K1_SEL_Cont[3] & (K1_SEL_Cont[0] $ K1L129Q) # !K1_SEL_Cont[1] & (K1_SEL_Cont[3] $ K1_SEL_Cont[0]);


--K1L97 is AUDIO_DAC:u8|Mux~1983 at LCCOMB_X30_Y21_N28
K1L97 = K1L129Q & (K1_SEL_Cont[3] & K1_SEL_Cont[0] & !K1_SEL_Cont[1] # !K1_SEL_Cont[3] & !K1_SEL_Cont[0] & K1_SEL_Cont[1]);


--K1L98 is AUDIO_DAC:u8|Mux~1984 at LCCOMB_X30_Y21_N6
K1L98 = K1L129Q & (K1_SEL_Cont[0] & (!K1_SEL_Cont[1]) # !K1_SEL_Cont[0] & K1_SEL_Cont[3]) # !K1L129Q & (K1_SEL_Cont[3] # K1_SEL_Cont[1]);


--K1L99 is AUDIO_DAC:u8|Mux~1985 at LCCOMB_X30_Y21_N10
K1L99 = K1_SEL_Cont[2] & (K1L130Q # !K1L97) # !K1_SEL_Cont[2] & K1L98 & (!K1L130Q);


--K1L100 is AUDIO_DAC:u8|Mux~1986 at LCCOMB_X30_Y21_N0
K1L100 = K1_SEL_Cont[3] & (K1_SEL_Cont[0] & !K1_SEL_Cont[1] # !K1_SEL_Cont[0] & (!K1L129Q)) # !K1_SEL_Cont[3] & (K1_SEL_Cont[0] $ (K1L129Q));


--K1L101 is AUDIO_DAC:u8|Mux~1987 at LCCOMB_X30_Y21_N4
K1L101 = K1L99 & (!K1L130Q # !K1L100) # !K1L99 & (K1L96 & K1L130Q);


--K1L102 is AUDIO_DAC:u8|Mux~1988 at LCCOMB_X29_Y21_N24
K1L102 = K1L130Q & (K1_SEL_Cont[1] # K1_SEL_Cont[3]) # !K1L130Q & (K1_SEL_Cont[0] & K1_SEL_Cont[1] # !K1_SEL_Cont[0] & (K1_SEL_Cont[3]));


--K1L103 is AUDIO_DAC:u8|Mux~1989 at LCCOMB_X29_Y21_N4
K1L103 = K1L130Q & (K1_SEL_Cont[2] & K1_SEL_Cont[0] & !K1_SEL_Cont[3] # !K1_SEL_Cont[2] & !K1_SEL_Cont[0]);


--K1L104 is AUDIO_DAC:u8|Mux~1990 at LCCOMB_X29_Y21_N26
K1L104 = K1L129Q & K1_SEL_Cont[2] # !K1L129Q & (K1_SEL_Cont[1] & K1L103);


--K1L105 is AUDIO_DAC:u8|Mux~1991 at LCCOMB_X29_Y21_N10
K1L105 = K1_SEL_Cont[3] & (K1L130Q $ (!K1_SEL_Cont[1] & K1_SEL_Cont[0]));


--K1L106 is AUDIO_DAC:u8|Mux~1992 at LCCOMB_X29_Y21_N20
K1L106 = K1L104 & (K1L105 # !K1L129Q) # !K1L104 & (K1L102 & K1L129Q);


--K1L107 is AUDIO_DAC:u8|Mux~1993 at LCCOMB_X29_Y20_N22
K1L107 = K1L132Q & (K1L131Q) # !K1L132Q & (K1L131Q & K1L101 # !K1L131Q & (K1L106));


--K1L108 is AUDIO_DAC:u8|Mux~1994 at LCCOMB_X29_Y21_N2
K1L108 = K1_SEL_Cont[0] & (K1_SEL_Cont[1] $ K1L129Q # !K1_SEL_Cont[2]) # !K1_SEL_Cont[0] & (K1_SEL_Cont[1] # K1_SEL_Cont[2] & !K1L129Q);


--K1L109 is AUDIO_DAC:u8|Mux~1995 at LCCOMB_X29_Y21_N28
K1L109 = K1L129Q & (K1_SEL_Cont[0] & (K1_SEL_Cont[1]) # !K1_SEL_Cont[0] & K1_SEL_Cont[2] & !K1_SEL_Cont[1]);


--K1L110 is AUDIO_DAC:u8|Mux~1996 at LCCOMB_X29_Y21_N6
K1L110 = K1_SEL_Cont[2] & (!K1L129Q # !K1_SEL_Cont[1] # !K1_SEL_Cont[0]) # !K1_SEL_Cont[2] & (K1_SEL_Cont[0] # K1_SEL_Cont[1]);


--K1L111 is AUDIO_DAC:u8|Mux~1997 at LCCOMB_X29_Y21_N16
K1L111 = K1L130Q & (K1_SEL_Cont[3]) # !K1L130Q & (K1_SEL_Cont[3] & (!K1L109) # !K1_SEL_Cont[3] & K1L110);


--K1L112 is AUDIO_DAC:u8|Mux~1998 at LCCOMB_X29_Y21_N18
K1L112 = K1_SEL_Cont[1] & (K1_SEL_Cont[0] # K1L129Q) # !K1_SEL_Cont[1] & (K1_SEL_Cont[2] # K1_SEL_Cont[0] $ K1L129Q);


--K1L113 is AUDIO_DAC:u8|Mux~1999 at LCCOMB_X29_Y21_N8
K1L113 = K1L111 & (!K1L130Q # !K1L112) # !K1L111 & (K1L130Q & K1L108);


--K1L114 is AUDIO_DAC:u8|Mux~2000 at LCCOMB_X29_Y20_N18
K1L114 = K1L107 & (K1L113 # !K1L132Q) # !K1L107 & (K1L132Q & K1L95);


--M1__clk0 is VGA_Audio_PLL:u3|altpll:altpll_component|_clk0 at PLL_3
M1__clk0 = PLL.CLK0(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_27[0]), .INCLK());

--M1__clk1 is VGA_Audio_PLL:u3|altpll:altpll_component|_clk1 at PLL_3
M1__clk1 = PLL.CLK1(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_27[0]), .INCLK());


--Cont[23] is Cont[23] at LCFF_X1_Y20_N19
Cont[23] = DFFEAS(A1L88, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[22] is Cont[22] at LCFF_X1_Y20_N17
Cont[22] = DFFEAS(A1L85, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[21] is Cont[21] at LCFF_X1_Y20_N15
Cont[21] = DFFEAS(A1L82, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[20] is Cont[20] at LCFF_X1_Y20_N13
Cont[20] = DFFEAS(A1L79, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[19] is Cont[19] at LCFF_X1_Y20_N11
Cont[19] = DFFEAS(A1L76, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[18] is Cont[18] at LCFF_X1_Y20_N9
Cont[18] = DFFEAS(A1L73, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[17] is Cont[17] at LCFF_X1_Y20_N7
Cont[17] = DFFEAS(A1L70, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[16] is Cont[16] at LCFF_X1_Y20_N5
Cont[16] = DFFEAS(A1L67, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[15] is Cont[15] at LCFF_X1_Y20_N3
Cont[15] = DFFEAS(A1L64, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[14] is Cont[14] at LCFF_X1_Y20_N1
Cont[14] = DFFEAS(A1L61, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[13] is Cont[13] at LCFF_X1_Y21_N31
Cont[13] = DFFEAS(A1L58, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[12] is Cont[12] at LCFF_X1_Y21_N29
Cont[12] = DFFEAS(A1L55, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[11] is Cont[11] at LCFF_X1_Y21_N27
Cont[11] = DFFEAS(A1L52, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[10] is Cont[10] at LCFF_X1_Y21_N25
Cont[10] = DFFEAS(A1L49, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[9] is Cont[9] at LCFF_X1_Y21_N23
Cont[9] = DFFEAS(A1L46, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[8] is Cont[8] at LCFF_X1_Y21_N21
Cont[8] = DFFEAS(A1L43, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[7] is Cont[7] at LCFF_X1_Y21_N19
Cont[7] = DFFEAS(A1L40, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[6] is Cont[6] at LCFF_X1_Y21_N17
Cont[6] = DFFEAS(A1L37, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[5] is Cont[5] at LCFF_X1_Y21_N15
Cont[5] = DFFEAS(A1L34, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[4] is Cont[4] at LCFF_X1_Y21_N13
Cont[4] = DFFEAS(A1L31, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[3] is Cont[3] at LCFF_X1_Y21_N11
Cont[3] = DFFEAS(A1L28, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[2] is Cont[2] at LCFF_X1_Y21_N9
Cont[2] = DFFEAS(A1L25, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[1] is Cont[1] at LCFF_X1_Y21_N7
Cont[1] = DFFEAS(A1L22, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--Cont[0] is Cont[0] at LCFF_X1_Y21_N5
Cont[0] = DFFEAS(A1L19, GLOBAL(A1L16),  ,  ,  ,  ,  ,  ,  );


--A1L19 is Cont[0]~224 at LCCOMB_X1_Y21_N4
A1L19 = Cont[0] $ VCC;

--A1L20 is Cont[0]~225 at LCCOMB_X1_Y21_N4
A1L20 = CARRY(Cont[0]);


--A1L22 is Cont[1]~226 at LCCOMB_X1_Y21_N6
A1L22 = Cont[1] & !A1L20 # !Cont[1] & (A1L20 # GND);

--A1L23 is Cont[1]~227 at LCCOMB_X1_Y21_N6
A1L23 = CARRY(!A1L20 # !Cont[1]);


--A1L25 is Cont[2]~228 at LCCOMB_X1_Y21_N8
A1L25 = Cont[2] & (A1L23 $ GND) # !Cont[2] & !A1L23 & VCC;

--A1L26 is Cont[2]~229 at LCCOMB_X1_Y21_N8
A1L26 = CARRY(Cont[2] & !A1L23);


--A1L28 is Cont[3]~230 at LCCOMB_X1_Y21_N10
A1L28 = Cont[3] & !A1L26 # !Cont[3] & (A1L26 # GND);

--A1L29 is Cont[3]~231 at LCCOMB_X1_Y21_N10
A1L29 = CARRY(!A1L26 # !Cont[3]);


--A1L31 is Cont[4]~232 at LCCOMB_X1_Y21_N12
A1L31 = Cont[4] & (A1L29 $ GND) # !Cont[4] & !A1L29 & VCC;

--A1L32 is Cont[4]~233 at LCCOMB_X1_Y21_N12
A1L32 = CARRY(Cont[4] & !A1L29);


--A1L34 is Cont[5]~234 at LCCOMB_X1_Y21_N14
A1L34 = Cont[5] & !A1L32 # !Cont[5] & (A1L32 # GND);

--A1L35 is Cont[5]~235 at LCCOMB_X1_Y21_N14
A1L35 = CARRY(!A1L32 # !Cont[5]);


--A1L37 is Cont[6]~236 at LCCOMB_X1_Y21_N16
A1L37 = Cont[6] & (A1L35 $ GND) # !Cont[6] & !A1L35 & VCC;

--A1L38 is Cont[6]~237 at LCCOMB_X1_Y21_N16
A1L38 = CARRY(Cont[6] & !A1L35);


--A1L40 is Cont[7]~238 at LCCOMB_X1_Y21_N18
A1L40 = Cont[7] & !A1L38 # !Cont[7] & (A1L38 # GND);

--A1L41 is Cont[7]~239 at LCCOMB_X1_Y21_N18
A1L41 = CARRY(!A1L38 # !Cont[7]);


--A1L43 is Cont[8]~240 at LCCOMB_X1_Y21_N20
A1L43 = Cont[8] & (A1L41 $ GND) # !Cont[8] & !A1L41 & VCC;

--A1L44 is Cont[8]~241 at LCCOMB_X1_Y21_N20
A1L44 = CARRY(Cont[8] & !A1L41);


--A1L46 is Cont[9]~242 at LCCOMB_X1_Y21_N22
A1L46 = Cont[9] & !A1L44 # !Cont[9] & (A1L44 # GND);

--A1L47 is Cont[9]~243 at LCCOMB_X1_Y21_N22
A1L47 = CARRY(!A1L44 # !Cont[9]);


--A1L49 is Cont[10]~244 at LCCOMB_X1_Y21_N24
A1L49 = Cont[10] & (A1L47 $ GND) # !Cont[10] & !A1L47 & VCC;

--A1L50 is Cont[10]~245 at LCCOMB_X1_Y21_N24
A1L50 = CARRY(Cont[10] & !A1L47);


--A1L52 is Cont[11]~246 at LCCOMB_X1_Y21_N26
A1L52 = Cont[11] & !A1L50 # !Cont[11] & (A1L50 # GND);

--A1L53 is Cont[11]~247 at LCCOMB_X1_Y21_N26
A1L53 = CARRY(!A1L50 # !Cont[11]);


--A1L55 is Cont[12]~248 at LCCOMB_X1_Y21_N28
A1L55 = Cont[12] & (A1L53 $ GND) # !Cont[12] & !A1L53 & VCC;

--A1L56 is Cont[12]~249 at LCCOMB_X1_Y21_N28
A1L56 = CARRY(Cont[12] & !A1L53);


--A1L58 is Cont[13]~250 at LCCOMB_X1_Y21_N30
A1L58 = Cont[13] & !A1L56 # !Cont[13] & (A1L56 # GND);

--A1L59 is Cont[13]~251 at LCCOMB_X1_Y21_N30
A1L59 = CARRY(!A1L56 # !Cont[13]);


--A1L61 is Cont[14]~252 at LCCOMB_X1_Y20_N0
A1L61 = Cont[14] & (A1L59 $ GND) # !Cont[14] & !A1L59 & VCC;

--A1L62 is Cont[14]~253 at LCCOMB_X1_Y20_N0
A1L62 = CARRY(Cont[14] & !A1L59);


--A1L64 is Cont[15]~254 at LCCOMB_X1_Y20_N2
A1L64 = Cont[15] & !A1L62 # !Cont[15] & (A1L62 # GND);

--A1L65 is Cont[15]~255 at LCCOMB_X1_Y20_N2
A1L65 = CARRY(!A1L62 # !Cont[15]);


--A1L67 is Cont[16]~256 at LCCOMB_X1_Y20_N4
A1L67 = Cont[16] & (A1L65 $ GND) # !Cont[16] & !A1L65 & VCC;

--A1L68 is Cont[16]~257 at LCCOMB_X1_Y20_N4
A1L68 = CARRY(Cont[16] & !A1L65);


--A1L70 is Cont[17]~258 at LCCOMB_X1_Y20_N6
A1L70 = Cont[17] & !A1L68 # !Cont[17] & (A1L68 # GND);

--A1L71 is Cont[17]~259 at LCCOMB_X1_Y20_N6
A1L71 = CARRY(!A1L68 # !Cont[17]);


--A1L73 is Cont[18]~260 at LCCOMB_X1_Y20_N8
A1L73 = Cont[18] & (A1L71 $ GND) # !Cont[18] & !A1L71 & VCC;

--A1L74 is Cont[18]~261 at LCCOMB_X1_Y20_N8
A1L74 = CARRY(Cont[18] & !A1L71);


--A1L76 is Cont[19]~262 at LCCOMB_X1_Y20_N10
A1L76 = Cont[19] & !A1L74 # !Cont[19] & (A1L74 # GND);

--A1L77 is Cont[19]~263 at LCCOMB_X1_Y20_N10
A1L77 = CARRY(!A1L74 # !Cont[19]);


--A1L79 is Cont[20]~264 at LCCOMB_X1_Y20_N12
A1L79 = Cont[20] & (A1L77 $ GND) # !Cont[20] & !A1L77 & VCC;

--A1L80 is Cont[20]~265 at LCCOMB_X1_Y20_N12
A1L80 = CARRY(Cont[20] & !A1L77);


--A1L82 is Cont[21]~266 at LCCOMB_X1_Y20_N14
A1L82 = Cont[21] & !A1L80 # !Cont[21] & (A1L80 # GND);

--A1L83 is Cont[21]~267 at LCCOMB_X1_Y20_N14
A1L83 = CARRY(!A1L80 # !Cont[21]);


--A1L85 is Cont[22]~268 at LCCOMB_X1_Y20_N16
A1L85 = Cont[22] & (A1L83 $ GND) # !Cont[22] & !A1L83 & VCC;

--A1L86 is Cont[22]~269 at LCCOMB_X1_Y20_N16
A1L86 = CARRY(Cont[22] & !A1L83);


--A1L88 is Cont[23]~270 at LCCOMB_X1_Y20_N18
A1L88 = Cont[23] & !A1L86 # !Cont[23] & (A1L86 # GND);

--A1L89 is Cont[23]~271 at LCCOMB_X1_Y20_N18
A1L89 = CARRY(!A1L86 # !Cont[23]);


--A1L91 is Cont[24]~272 at LCCOMB_X1_Y20_N20
A1L91 = Cont[24] & (A1L89 $ GND) # !Cont[24] & !A1L89 & VCC;

--A1L92 is Cont[24]~273 at LCCOMB_X1_Y20_N20
A1L92 = CARRY(Cont[24] & !A1L89);


--A1L94 is Cont[25]~274 at LCCOMB_X1_Y20_N22
A1L94 = Cont[25] & !A1L92 # !Cont[25] & (A1L92 # GND);

--A1L95 is Cont[25]~275 at LCCOMB_X1_Y20_N22
A1L95 = CARRY(!A1L92 # !Cont[25]);


--A1L97 is Cont[26]~276 at LCCOMB_X1_Y20_N24
A1L97 = Cont[26] & (A1L95 $ GND) # !Cont[26] & !A1L95 & VCC;

--A1L98 is Cont[26]~277 at LCCOMB_X1_Y20_N24
A1L98 = CARRY(Cont[26] & !A1L95);


--A1L100 is Cont[27]~278 at LCCOMB_X1_Y20_N26
A1L100 = A1L98 $ Cont[27];


--D1_DIR is LEDG_Driver:u2|DIR at LCFF_X30_Y9_N23
D1_DIR = DFFEAS(D1L70, GLOBAL(D1L65), KEY[0],  ,  ,  ,  ,  ,  );


--D1L80 is LEDG_Driver:u2|mLED~96 at LCCOMB_X30_Y9_N30
D1L80 = D1_DIR & (D1_mLED[1]) # !D1_DIR & !D1_mLED[7];


--D1_Cont[20] is LEDG_Driver:u2|Cont[20] at LCFF_X1_Y12_N21
D1_Cont[20] = DFFEAS(D1L63, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1L81 is LEDG_Driver:u2|mLED~97 at LCCOMB_X30_Y7_N22
D1L81 = D1_DIR & (D1_mLED[2]) # !D1_DIR & D1_mLED[0];


--D1L82 is LEDG_Driver:u2|mLED~98 at LCCOMB_X30_Y7_N28
D1L82 = D1_DIR & !D1_mLED[3] # !D1_DIR & (D1_mLED[1]);


--D1L83 is LEDG_Driver:u2|mLED~99 at LCCOMB_X30_Y7_N18
D1L83 = D1_DIR & D1_mLED[4] # !D1_DIR & (!D1_mLED[2]);


--D1L84 is LEDG_Driver:u2|mLED~100 at LCCOMB_X49_Y7_N4
D1L84 = D1_DIR & D1_mLED[5] # !D1_DIR & (D1_mLED[3]);


--D1L85 is LEDG_Driver:u2|mLED~101 at LCCOMB_X49_Y7_N16
D1L85 = D1_DIR & D1_mLED[6] # !D1_DIR & (D1_mLED[4]);


--D1L86 is LEDG_Driver:u2|mLED~102 at LCCOMB_X31_Y12_N26
D1L86 = D1_DIR & D1_mLED[7] # !D1_DIR & (D1_mLED[5]);


--D1L87 is LEDG_Driver:u2|mLED~103 at LCCOMB_X31_Y12_N24
D1L87 = D1_DIR & (!D1_mLED[0]) # !D1_DIR & D1_mLED[6];


--C1_DIR is LEDR_Driver:u1|DIR at LCFF_X49_Y7_N15
C1_DIR = DFFEAS(C1L69, GLOBAL(C1L65), KEY[0],  ,  ,  ,  ,  ,  );


--C1L82 is LEDR_Driver:u1|mLED~120 at LCCOMB_X49_Y7_N0
C1L82 = C1_DIR & (C1_mLED[1]) # !C1_DIR & !C1_mLED[9];


--C1_Cont[20] is LEDR_Driver:u1|Cont[20] at LCFF_X2_Y12_N21
C1_Cont[20] = DFFEAS(C1L63, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1L83 is LEDR_Driver:u1|mLED~121 at LCCOMB_X49_Y7_N18
C1L83 = C1_DIR & C1_mLED[2] # !C1_DIR & (C1_mLED[0]);


--C1L84 is LEDR_Driver:u1|mLED~122 at LCCOMB_X49_Y7_N26
C1L84 = C1_DIR & !C1_mLED[3] # !C1_DIR & (C1_mLED[1]);


--C1L85 is LEDR_Driver:u1|mLED~123 at LCCOMB_X49_Y7_N10
C1L85 = C1_DIR & C1_mLED[4] # !C1_DIR & (!C1_mLED[2]);


--C1L86 is LEDR_Driver:u1|mLED~124 at LCCOMB_X49_Y7_N22
C1L86 = C1_DIR & C1_mLED[5] # !C1_DIR & (C1_mLED[3]);


--C1L87 is LEDR_Driver:u1|mLED~125 at LCCOMB_X49_Y7_N30
C1L87 = C1_DIR & C1_mLED[6] # !C1_DIR & (C1_mLED[4]);


--C1L88 is LEDR_Driver:u1|mLED~126 at LCCOMB_X49_Y7_N28
C1L88 = C1_DIR & C1_mLED[7] # !C1_DIR & (C1_mLED[5]);


--C1L89 is LEDR_Driver:u1|mLED~127 at LCCOMB_X49_Y7_N6
C1L89 = C1_DIR & C1_mLED[8] # !C1_DIR & (C1_mLED[6]);


--C1L90 is LEDR_Driver:u1|mLED~128 at LCCOMB_X49_Y7_N2
C1L90 = C1_DIR & C1_mLED[9] # !C1_DIR & (C1_mLED[7]);


--C1L91 is LEDR_Driver:u1|mLED~129 at LCCOMB_X49_Y7_N20
C1L91 = C1_DIR & (!C1_mLED[0]) # !C1_DIR & C1_mLED[8];


--V1L59 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1103 at LCCOMB_X34_Y13_N2
V1L59 = !V1L46Q & !V1L55Q & !V1L49Q & !V1L52Q;


--V1L18 is I2C_AV_Config:u7|I2C_Controller:u0|LessThan~163 at LCCOMB_X34_Y13_N18
V1L18 = V1L58Q # V1L43Q # !V1L59;


--V1L41 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[0]~280 at LCCOMB_X34_Y13_N20
V1L41 = V1L43Q & !V1L18 & VCC # !V1L43Q & V1L18;

--V1L42 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[0]~281 at LCCOMB_X34_Y13_N20
V1L42 = CARRY(!V1L43Q & V1L18);


--J1_mI2C_GO is I2C_AV_Config:u7|mI2C_GO at LCFF_X34_Y14_N7
J1_mI2C_GO = DFFEAS(J1L19, GLOBAL(J1L73), KEY[0],  ,  ,  ,  ,  ,  );


--V1L44 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[1]~282 at LCCOMB_X34_Y13_N22
V1L44 = V1L46Q & (GND # !V1L42) # !V1L46Q & (V1L42 $ GND);

--V1L45 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[1]~283 at LCCOMB_X34_Y13_N22
V1L45 = CARRY(V1L46Q # !V1L42);


--V1L47 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[2]~284 at LCCOMB_X34_Y13_N24
V1L47 = V1L49Q & V1L45 & VCC # !V1L49Q & !V1L45;

--V1L48 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[2]~285 at LCCOMB_X34_Y13_N24
V1L48 = CARRY(!V1L49Q & !V1L45);


--V1L50 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[3]~286 at LCCOMB_X34_Y13_N26
V1L50 = V1L52Q & (GND # !V1L48) # !V1L52Q & (V1L48 $ GND);

--V1L51 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[3]~287 at LCCOMB_X34_Y13_N26
V1L51 = CARRY(V1L52Q # !V1L48);


--V1L53 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[4]~288 at LCCOMB_X34_Y13_N28
V1L53 = V1L55Q & V1L51 & VCC # !V1L55Q & !V1L51;

--V1L54 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[4]~289 at LCCOMB_X34_Y13_N28
V1L54 = CARRY(!V1L55Q & !V1L51);


--V1L56 is I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[5]~290 at LCCOMB_X34_Y13_N30
V1L56 = V1L54 $ V1L58Q;


--J1_mI2C_CLK_DIV[12] is I2C_AV_Config:u7|mI2C_CLK_DIV[12] at LCFF_X36_Y14_N25
J1_mI2C_CLK_DIV[12] = DFFEAS(J1L60, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[13] is I2C_AV_Config:u7|mI2C_CLK_DIV[13] at LCFF_X36_Y14_N27
J1_mI2C_CLK_DIV[13] = DFFEAS(J1L63, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[14] is I2C_AV_Config:u7|mI2C_CLK_DIV[14] at LCFF_X36_Y14_N29
J1_mI2C_CLK_DIV[14] = DFFEAS(J1L66, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[15] is I2C_AV_Config:u7|mI2C_CLK_DIV[15] at LCFF_X36_Y14_N31
J1_mI2C_CLK_DIV[15] = DFFEAS(J1L69, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1L14 is I2C_AV_Config:u7|LessThan~226 at LCCOMB_X35_Y14_N26
J1L14 = !J1_mI2C_CLK_DIV[15] & !J1_mI2C_CLK_DIV[14] & !J1_mI2C_CLK_DIV[13] & !J1_mI2C_CLK_DIV[12];


--J1_mI2C_CLK_DIV[2] is I2C_AV_Config:u7|mI2C_CLK_DIV[2] at LCFF_X36_Y14_N5
J1_mI2C_CLK_DIV[2] = DFFEAS(J1L30, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[3] is I2C_AV_Config:u7|mI2C_CLK_DIV[3] at LCFF_X36_Y14_N7
J1_mI2C_CLK_DIV[3] = DFFEAS(J1L33, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[4] is I2C_AV_Config:u7|mI2C_CLK_DIV[4] at LCFF_X36_Y14_N9
J1_mI2C_CLK_DIV[4] = DFFEAS(J1L36, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[5] is I2C_AV_Config:u7|mI2C_CLK_DIV[5] at LCFF_X36_Y14_N11
J1_mI2C_CLK_DIV[5] = DFFEAS(J1L39, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1L15 is I2C_AV_Config:u7|LessThan~227 at LCCOMB_X35_Y14_N0
J1L15 = !J1_mI2C_CLK_DIV[3] & !J1_mI2C_CLK_DIV[5] & !J1_mI2C_CLK_DIV[4] & !J1_mI2C_CLK_DIV[2];


--J1_mI2C_CLK_DIV[6] is I2C_AV_Config:u7|mI2C_CLK_DIV[6] at LCFF_X36_Y14_N13
J1_mI2C_CLK_DIV[6] = DFFEAS(J1L42, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[7] is I2C_AV_Config:u7|mI2C_CLK_DIV[7] at LCFF_X36_Y14_N15
J1_mI2C_CLK_DIV[7] = DFFEAS(J1L45, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[8] is I2C_AV_Config:u7|mI2C_CLK_DIV[8] at LCFF_X36_Y14_N17
J1_mI2C_CLK_DIV[8] = DFFEAS(J1L48, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1L16 is I2C_AV_Config:u7|LessThan~228 at LCCOMB_X35_Y14_N6
J1L16 = J1L15 # !J1_mI2C_CLK_DIV[6] # !J1_mI2C_CLK_DIV[7] # !J1_mI2C_CLK_DIV[8];


--J1_mI2C_CLK_DIV[9] is I2C_AV_Config:u7|mI2C_CLK_DIV[9] at LCFF_X36_Y14_N19
J1_mI2C_CLK_DIV[9] = DFFEAS(J1L51, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[10] is I2C_AV_Config:u7|mI2C_CLK_DIV[10] at LCFF_X36_Y14_N21
J1_mI2C_CLK_DIV[10] = DFFEAS(J1L54, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1L17 is I2C_AV_Config:u7|LessThan~229 at LCCOMB_X35_Y14_N16
J1L17 = !J1_mI2C_CLK_DIV[10] & !J1_mI2C_CLK_DIV[9];


--J1_mI2C_CLK_DIV[11] is I2C_AV_Config:u7|mI2C_CLK_DIV[11] at LCFF_X36_Y14_N23
J1_mI2C_CLK_DIV[11] = DFFEAS(J1L57, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1L18 is I2C_AV_Config:u7|LessThan~230 at LCCOMB_X35_Y14_N14
J1L18 = J1_mI2C_CLK_DIV[11] & (!J1L17 # !J1L16) # !J1L14;


--J1L72 is I2C_AV_Config:u7|mI2C_CTRL_CLK~79 at LCCOMB_X35_Y14_N2
J1L72 = J1L18 $ J1_mI2C_CTRL_CLK;


--V1L20 is I2C_AV_Config:u7|I2C_Controller:u0|SCLK~145 at LCCOMB_X35_Y14_N20
V1L20 = V1L46Q & (!V1L52Q) # !V1L46Q & V1L49Q;


--V1L21 is I2C_AV_Config:u7|I2C_Controller:u0|SCLK~146 at LCCOMB_X35_Y14_N12
V1L21 = V1L55Q & (!V1L52Q # !V1L20 # !V1L43Q) # !V1L55Q & (V1L20 # V1L52Q);


--V1L40 is I2C_AV_Config:u7|I2C_Controller:u0|SD[12]~381 at LCCOMB_X31_Y12_N18
V1L40 = V1L49Q & V1L55Q & V1L52Q & V1L46Q;


--V1L22 is I2C_AV_Config:u7|I2C_Controller:u0|SCLK~147 at LCCOMB_X31_Y12_N2
V1L22 = V1L43Q & (V1L40 $ !V1L21);


--V1L23 is I2C_AV_Config:u7|I2C_Controller:u0|SCLK~148 at LCCOMB_X35_Y14_N24
V1L23 = V1L58Q & (V1L22 & (!V1L21) # !V1L22 & V1_SCLK & V1L21) # !V1L58Q & (V1_SCLK);


--F1L56 is VGA_Controller:u4|LessThan~1170 at LCCOMB_X30_Y11_N24
F1L56 = F1_H_Cont[7] # F1_H_Cont[6] & F1_H_Cont[5] # !F1L16;


--F1L17 is VGA_Controller:u4|Equal~112 at LCCOMB_X30_Y9_N24
F1L17 = !F1_H_Cont[3] & !F1_H_Cont[2];


--F1L18 is VGA_Controller:u4|Equal~113 at LCCOMB_X29_Y10_N22
F1L18 = !F1_H_Cont[4] & F1L17 & !F1_H_Cont[7] & F1L15;


--F1L19 is VGA_Controller:u4|Equal~114 at LCCOMB_X29_Y10_N30
F1L19 = !F1_H_Cont[1] & F1L18 & F1L16 & !F1_H_Cont[0];


--F1L267 is VGA_Controller:u4|oVGA_V_SYNC~174 at LCCOMB_X24_Y11_N24
F1L267 = F1L19 & (F1_V_Cont[9] # F1L55) # !F1L19 & (F1_oVGA_V_SYNC);


--G1_oRed[7] is VGA_Pattern:u5|oRed[7] at LCFF_X26_Y10_N23
G1_oRed[7] = DFFEAS(G1L49, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--H1_oRed[8] is VGA_OSD_RAM:u6|oRed[8] at LCFF_X31_Y11_N9
H1_oRed[8] = DFFEAS(H1L142, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--A1L402 is mVGA_R[7]~123 at LCCOMB_X25_Y11_N30
A1L402 = SW[0] & (G1_oRed[7]) # !SW[0] & H1_oRed[8];


--F1L22 is VGA_Controller:u4|H_Cont[0]~235 at LCCOMB_X30_Y9_N2
F1L22 = F1_H_Cont[0] $ VCC;

--F1L23 is VGA_Controller:u4|H_Cont[0]~236 at LCCOMB_X30_Y9_N2
F1L23 = CARRY(F1_H_Cont[0]);


--F1L25 is VGA_Controller:u4|H_Cont[1]~237 at LCCOMB_X30_Y9_N4
F1L25 = F1_H_Cont[1] & !F1L23 # !F1_H_Cont[1] & (F1L23 # GND);

--F1L26 is VGA_Controller:u4|H_Cont[1]~238 at LCCOMB_X30_Y9_N4
F1L26 = CARRY(!F1L23 # !F1_H_Cont[1]);


--F1L28 is VGA_Controller:u4|H_Cont[2]~239 at LCCOMB_X30_Y9_N6
F1L28 = F1_H_Cont[2] & (F1L26 $ GND) # !F1_H_Cont[2] & !F1L26 & VCC;

--F1L29 is VGA_Controller:u4|H_Cont[2]~240 at LCCOMB_X30_Y9_N6
F1L29 = CARRY(F1_H_Cont[2] & !F1L26);


--F1L31 is VGA_Controller:u4|H_Cont[3]~241 at LCCOMB_X30_Y9_N8
F1L31 = F1_H_Cont[3] & !F1L29 # !F1_H_Cont[3] & (F1L29 # GND);

--F1L32 is VGA_Controller:u4|H_Cont[3]~242 at LCCOMB_X30_Y9_N8
F1L32 = CARRY(!F1L29 # !F1_H_Cont[3]);


--F1L34 is VGA_Controller:u4|H_Cont[4]~243 at LCCOMB_X30_Y9_N10
F1L34 = F1_H_Cont[4] & (F1L32 $ GND) # !F1_H_Cont[4] & !F1L32 & VCC;

--F1L35 is VGA_Controller:u4|H_Cont[4]~244 at LCCOMB_X30_Y9_N10
F1L35 = CARRY(F1_H_Cont[4] & !F1L32);


--F1L37 is VGA_Controller:u4|H_Cont[5]~245 at LCCOMB_X30_Y9_N12
F1L37 = F1_H_Cont[5] & !F1L35 # !F1_H_Cont[5] & (F1L35 # GND);

--F1L38 is VGA_Controller:u4|H_Cont[5]~246 at LCCOMB_X30_Y9_N12
F1L38 = CARRY(!F1L35 # !F1_H_Cont[5]);


--F1L57 is VGA_Controller:u4|LessThan~1171 at LCCOMB_X30_Y11_N26
F1L57 = F1_H_Cont[8] & F1_H_Cont[9] & (F1_H_Cont[7] # !F1L15);


--F1L40 is VGA_Controller:u4|H_Cont[6]~247 at LCCOMB_X30_Y9_N14
F1L40 = F1_H_Cont[6] & (F1L38 $ GND) # !F1_H_Cont[6] & !F1L38 & VCC;

--F1L41 is VGA_Controller:u4|H_Cont[6]~248 at LCCOMB_X30_Y9_N14
F1L41 = CARRY(F1_H_Cont[6] & !F1L38);


--F1L43 is VGA_Controller:u4|H_Cont[7]~249 at LCCOMB_X30_Y9_N16
F1L43 = F1_H_Cont[7] & !F1L41 # !F1_H_Cont[7] & (F1L41 # GND);

--F1L44 is VGA_Controller:u4|H_Cont[7]~250 at LCCOMB_X30_Y9_N16
F1L44 = CARRY(!F1L41 # !F1_H_Cont[7]);


--F1L46 is VGA_Controller:u4|H_Cont[8]~251 at LCCOMB_X30_Y9_N18
F1L46 = F1_H_Cont[8] & (F1L44 $ GND) # !F1_H_Cont[8] & !F1L44 & VCC;

--F1L47 is VGA_Controller:u4|H_Cont[8]~252 at LCCOMB_X30_Y9_N18
F1L47 = CARRY(F1_H_Cont[8] & !F1L44);


--F1L49 is VGA_Controller:u4|H_Cont[9]~253 at LCCOMB_X30_Y9_N20
F1L49 = F1_H_Cont[9] $ F1L47;


--F1_V_Cont[0] is VGA_Controller:u4|V_Cont[0] at LCFF_X24_Y11_N3
F1_V_Cont[0] = DFFEAS(F1L66, GLOBAL(M1L2), KEY[0],  , F1L19,  ,  , F1L60,  );


--F1L66 is VGA_Controller:u4|V_Cont[0]~564 at LCCOMB_X24_Y11_N2
F1L66 = F1_V_Cont[0] $ VCC;

--F1L67 is VGA_Controller:u4|V_Cont[0]~565 at LCCOMB_X24_Y11_N2
F1L67 = CARRY(F1_V_Cont[0]);


--F1L69 is VGA_Controller:u4|V_Cont[1]~566 at LCCOMB_X24_Y11_N4
F1L69 = F1_V_Cont[1] & !F1L67 # !F1_V_Cont[1] & (F1L67 # GND);

--F1L70 is VGA_Controller:u4|V_Cont[1]~567 at LCCOMB_X24_Y11_N4
F1L70 = CARRY(!F1L67 # !F1_V_Cont[1]);


--F1L72 is VGA_Controller:u4|V_Cont[2]~568 at LCCOMB_X24_Y11_N6
F1L72 = F1_V_Cont[2] & (F1L70 $ GND) # !F1_V_Cont[2] & !F1L70 & VCC;

--F1L73 is VGA_Controller:u4|V_Cont[2]~569 at LCCOMB_X24_Y11_N6
F1L73 = CARRY(F1_V_Cont[2] & !F1L70);


--F1L75 is VGA_Controller:u4|V_Cont[3]~570 at LCCOMB_X24_Y11_N8
F1L75 = F1_V_Cont[3] & !F1L73 # !F1_V_Cont[3] & (F1L73 # GND);

--F1L76 is VGA_Controller:u4|V_Cont[3]~571 at LCCOMB_X24_Y11_N8
F1L76 = CARRY(!F1L73 # !F1_V_Cont[3]);


--F1L78 is VGA_Controller:u4|V_Cont[4]~572 at LCCOMB_X24_Y11_N10
F1L78 = F1_V_Cont[4] & (F1L76 $ GND) # !F1_V_Cont[4] & !F1L76 & VCC;

--F1L79 is VGA_Controller:u4|V_Cont[4]~573 at LCCOMB_X24_Y11_N10
F1L79 = CARRY(F1_V_Cont[4] & !F1L76);


--F1L81 is VGA_Controller:u4|V_Cont[5]~574 at LCCOMB_X24_Y11_N12
F1L81 = F1_V_Cont[5] & !F1L79 # !F1_V_Cont[5] & (F1L79 # GND);

--F1L82 is VGA_Controller:u4|V_Cont[5]~575 at LCCOMB_X24_Y11_N12
F1L82 = CARRY(!F1L79 # !F1_V_Cont[5]);


--F1L84 is VGA_Controller:u4|V_Cont[6]~576 at LCCOMB_X24_Y11_N14
F1L84 = F1_V_Cont[6] & (F1L82 $ GND) # !F1_V_Cont[6] & !F1L82 & VCC;

--F1L85 is VGA_Controller:u4|V_Cont[6]~577 at LCCOMB_X24_Y11_N14
F1L85 = CARRY(F1_V_Cont[6] & !F1L82);


--F1L58 is VGA_Controller:u4|LessThan~1172 at LCCOMB_X24_Y11_N0
F1L58 = !F1_V_Cont[4] & F1L52 & !F1_V_Cont[5];


--F1L59 is VGA_Controller:u4|LessThan~1173 at LCCOMB_X24_Y11_N28
F1L59 = !F1_V_Cont[1] & !F1_V_Cont[0] # !F1_V_Cont[3] # !F1_V_Cont[2];


--F1L60 is VGA_Controller:u4|LessThan~1174 at LCCOMB_X24_Y11_N26
F1L60 = F1_V_Cont[9] & (!F1L58 # !F1L59);


--F1L87 is VGA_Controller:u4|V_Cont[7]~578 at LCCOMB_X24_Y11_N16
F1L87 = F1_V_Cont[7] & !F1L85 # !F1_V_Cont[7] & (F1L85 # GND);

--F1L88 is VGA_Controller:u4|V_Cont[7]~579 at LCCOMB_X24_Y11_N16
F1L88 = CARRY(!F1L85 # !F1_V_Cont[7]);


--F1L90 is VGA_Controller:u4|V_Cont[8]~580 at LCCOMB_X24_Y11_N18
F1L90 = F1_V_Cont[8] & (F1L88 $ GND) # !F1_V_Cont[8] & !F1L88 & VCC;

--F1L91 is VGA_Controller:u4|V_Cont[8]~581 at LCCOMB_X24_Y11_N18
F1L91 = CARRY(F1_V_Cont[8] & !F1L88);


--F1L93 is VGA_Controller:u4|V_Cont[9]~582 at LCCOMB_X24_Y11_N20
F1L93 = F1_V_Cont[9] $ F1L91;


--G1_oRed[8] is VGA_Pattern:u5|oRed[8] at LCFF_X25_Y11_N7
G1_oRed[8] = DFFEAS(G1L50, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--A1L403 is mVGA_R[8]~124 at LCCOMB_X25_Y11_N14
A1L403 = SW[0] & (G1_oRed[8]) # !SW[0] & H1_oRed[8];


--G1_oRed[9] is VGA_Pattern:u5|oRed[9] at LCFF_X25_Y11_N29
G1_oRed[9] = DFFEAS(G1L5, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--A1L404 is mVGA_R[9]~125 at LCCOMB_X25_Y11_N24
A1L404 = SW[0] & (G1_oRed[9]) # !SW[0] & H1_oRed[8];


--G1_oGreen[6] is VGA_Pattern:u5|oGreen[6] at LCFF_X27_Y11_N7
G1_oGreen[6] = DFFEAS(G1L41, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--A1L398 is mVGA_G[6]~58 at LCCOMB_X25_Y11_N10
A1L398 = SW[0] & (G1_oGreen[6]) # !SW[0] & H1_oRed[8];


--G1_oGreen[7] is VGA_Pattern:u5|oGreen[7] at LCFF_X25_Y11_N13
G1_oGreen[7] = DFFEAS(G1L43, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--A1L399 is mVGA_G[7]~59 at LCCOMB_X25_Y11_N20
A1L399 = SW[0] & (G1_oGreen[7]) # !SW[0] & H1_oRed[8];


--G1_oGreen[8] is VGA_Pattern:u5|oGreen[8] at LCFF_X29_Y11_N3
G1_oGreen[8] = DFFEAS(G1L44, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--A1L400 is mVGA_G[8]~60 at LCCOMB_X24_Y11_N22
A1L400 = SW[0] & (G1_oGreen[8]) # !SW[0] & H1_oRed[8];


--G1_oGreen[9] is VGA_Pattern:u5|oGreen[9] at LCFF_X27_Y11_N1
G1_oGreen[9] = DFFEAS(G1L42, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--A1L401 is mVGA_G[9]~61 at LCCOMB_X31_Y12_N16
A1L401 = SW[0] & (G1_oGreen[9]) # !SW[0] & H1_oRed[8];


--G1_oBlue[6] is VGA_Pattern:u5|oBlue[6] at LCFF_X25_Y10_N25
G1_oBlue[6] = DFFEAS(G1L8, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--A1L394 is mVGA_B[6]~55 at LCCOMB_X31_Y12_N22
A1L394 = SW[0] & G1_oBlue[6] # !SW[0] & (H1_oRed[8]);


--G1_oBlue[7] is VGA_Pattern:u5|oBlue[7] at LCFF_X26_Y12_N23
G1_oBlue[7] = DFFEAS(G1L27, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--A1L395 is mVGA_B[7]~56 at LCCOMB_X26_Y12_N24
A1L395 = SW[0] & (G1_oBlue[7]) # !SW[0] & H1_oRed[8];


--G1_oBlue[8] is VGA_Pattern:u5|oBlue[8] at LCFF_X26_Y12_N31
G1_oBlue[8] = DFFEAS(G1L29, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--A1L396 is mVGA_B[8]~57 at LCCOMB_X26_Y12_N14
A1L396 = SW[0] & (G1_oBlue[8]) # !SW[0] & H1_oRed[8];


--G1_oBlue[9] is VGA_Pattern:u5|oBlue[9] at LCFF_X26_Y12_N19
G1_oBlue[9] = DFFEAS(G1L30, GLOBAL(M1L2), KEY[0],  ,  ,  ,  , F1_oCoord_Y[9],  );


--H1_oBlue[9] is VGA_OSD_RAM:u6|oBlue[9] at LCFF_X26_Y12_N17
H1_oBlue[9] = DFFEAS(H1L137, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--A1L397 is mVGA_B[9]~58 at LCCOMB_X26_Y12_N0
A1L397 = SW[0] & (G1_oBlue[9]) # !SW[0] & H1_oBlue[9];


--K1_LRCK_1X_DIV[0] is AUDIO_DAC:u8|LRCK_1X_DIV[0] at LCFF_X30_Y7_N1
K1_LRCK_1X_DIV[0] = DFFEAS(K1L11, GLOBAL(M1L4), KEY[0],  ,  ,  ,  , K1L41,  );


--K1_LRCK_1X_DIV[1] is AUDIO_DAC:u8|LRCK_1X_DIV[1] at LCFF_X30_Y7_N3
K1_LRCK_1X_DIV[1] = DFFEAS(K1L14, GLOBAL(M1L4), KEY[0],  ,  ,  ,  , K1L41,  );


--K1_LRCK_1X_DIV[2] is AUDIO_DAC:u8|LRCK_1X_DIV[2] at LCFF_X30_Y7_N5
K1_LRCK_1X_DIV[2] = DFFEAS(K1L17, GLOBAL(M1L4), KEY[0],  ,  ,  ,  , K1L41,  );


--K1_LRCK_1X_DIV[3] is AUDIO_DAC:u8|LRCK_1X_DIV[3] at LCFF_X30_Y7_N7
K1_LRCK_1X_DIV[3] = DFFEAS(K1L20, GLOBAL(M1L4), KEY[0],  ,  ,  ,  , K1L41,  );


--K1L39 is AUDIO_DAC:u8|LessThan~297 at LCCOMB_X30_Y7_N24
K1L39 = !K1_LRCK_1X_DIV[0] # !K1_LRCK_1X_DIV[2] # !K1_LRCK_1X_DIV[1] # !K1_LRCK_1X_DIV[3];


--K1_LRCK_1X_DIV[4] is AUDIO_DAC:u8|LRCK_1X_DIV[4] at LCFF_X30_Y7_N9
K1_LRCK_1X_DIV[4] = DFFEAS(K1L23, GLOBAL(M1L4), KEY[0],  ,  ,  ,  , K1L41,  );


--K1_LRCK_1X_DIV[5] is AUDIO_DAC:u8|LRCK_1X_DIV[5] at LCFF_X30_Y7_N11
K1_LRCK_1X_DIV[5] = DFFEAS(K1L26, GLOBAL(M1L4), KEY[0],  ,  ,  ,  , K1L41,  );


--K1L40 is AUDIO_DAC:u8|LessThan~298 at LCCOMB_X30_Y7_N30
K1L40 = K1L39 # !K1_LRCK_1X_DIV[5] # !K1_LRCK_1X_DIV[4];


--K1_LRCK_1X_DIV[6] is AUDIO_DAC:u8|LRCK_1X_DIV[6] at LCFF_X30_Y7_N13
K1_LRCK_1X_DIV[6] = DFFEAS(K1L29, GLOBAL(M1L4), KEY[0],  ,  ,  ,  , K1L41,  );


--K1_LRCK_1X_DIV[7] is AUDIO_DAC:u8|LRCK_1X_DIV[7] at LCFF_X30_Y7_N15
K1_LRCK_1X_DIV[7] = DFFEAS(K1L32, GLOBAL(M1L4), KEY[0],  ,  ,  ,  , K1L41,  );


--K1_LRCK_1X_DIV[8] is AUDIO_DAC:u8|LRCK_1X_DIV[8] at LCFF_X30_Y7_N17
K1_LRCK_1X_DIV[8] = DFFEAS(K1L35, GLOBAL(M1L4), KEY[0],  ,  ,  ,  , K1L41,  );


--K1L41 is AUDIO_DAC:u8|LessThan~299 at LCCOMB_X30_Y7_N26
K1L41 = K1_LRCK_1X_DIV[8] # K1_LRCK_1X_DIV[7] & (K1_LRCK_1X_DIV[6] # !K1L40);


--K1L37 is AUDIO_DAC:u8|LRCK_1X~51 at LCCOMB_X30_Y7_N20
K1L37 = K1_LRCK_1X $ K1L41;


--K1L135 is AUDIO_DAC:u8|rom~141 at LCCOMB_X29_Y20_N2
K1L135 = K1L129Q $ VCC;

--K1L136 is AUDIO_DAC:u8|rom~142 at LCCOMB_X29_Y20_N2
K1L136 = CARRY(K1L129Q);


--K1L137 is AUDIO_DAC:u8|rom~143 at LCCOMB_X29_Y20_N4
K1L137 = K1L130Q & !K1L136 # !K1L130Q & (K1L136 # GND);

--K1L138 is AUDIO_DAC:u8|rom~144 at LCCOMB_X29_Y20_N4
K1L138 = CARRY(!K1L136 # !K1L130Q);


--K1L139 is AUDIO_DAC:u8|rom~145 at LCCOMB_X29_Y20_N6
K1L139 = K1L131Q & (K1L138 $ GND) # !K1L131Q & !K1L138 & VCC;

--K1L140 is AUDIO_DAC:u8|rom~146 at LCCOMB_X29_Y20_N6
K1L140 = CARRY(K1L131Q & !K1L138);


--K1L141 is AUDIO_DAC:u8|rom~147 at LCCOMB_X29_Y20_N8
K1L141 = K1L132Q & !K1L140 # !K1L132Q & (K1L140 # GND);

--K1L142 is AUDIO_DAC:u8|rom~148 at LCCOMB_X29_Y20_N8
K1L142 = CARRY(!K1L140 # !K1L132Q);


--K1L143 is AUDIO_DAC:u8|rom~149 at LCCOMB_X29_Y20_N10
K1L143 = K1L133Q & (K1L142 $ GND) # !K1L133Q & !K1L142 & VCC;

--K1L144 is AUDIO_DAC:u8|rom~150 at LCCOMB_X29_Y20_N10
K1L144 = CARRY(K1L133Q & !K1L142);


--K1L42 is AUDIO_DAC:u8|LessThan~300 at LCCOMB_X29_Y20_N30
K1L42 = !K1L129Q # !K1L130Q # !K1L132Q # !K1L131Q;


--K1L43 is AUDIO_DAC:u8|LessThan~301 at LCCOMB_X29_Y20_N16
K1L43 = K1L134Q & (K1L133Q # !K1L42);


--K1L119 is AUDIO_DAC:u8|SEL_Cont[1]~50 at LCCOMB_X30_Y19_N10
K1L119 = K1_SEL_Cont[1] $ K1_SEL_Cont[0];


--K1_oAUD_BCK is AUDIO_DAC:u8|oAUD_BCK at LCFF_X34_Y13_N7
K1_oAUD_BCK = DFFEAS(K1L125, GLOBAL(M1L4), KEY[0],  ,  ,  ,  ,  ,  );


--K1L123 is AUDIO_DAC:u8|SEL_Cont[3]~51 at LCCOMB_X30_Y19_N0
K1L123 = K1_SEL_Cont[3] $ (K1_SEL_Cont[1] & K1_SEL_Cont[2] & K1_SEL_Cont[0]);


--K1L121 is AUDIO_DAC:u8|SEL_Cont[2]~52 at LCCOMB_X30_Y19_N18
K1L121 = K1_SEL_Cont[2] $ (K1_SEL_Cont[1] & K1_SEL_Cont[0]);


--K1L145 is AUDIO_DAC:u8|rom~151 at LCCOMB_X29_Y20_N12
K1L145 = K1L144 $ K1L134Q;


--D1L67 is LEDG_Driver:u2|DIR~102 at LCCOMB_X30_Y9_N28
D1L67 = D1_mLED[6] & (D1_mLED[2] # !D1_mLED[4]) # !D1_mLED[6] & D1_mLED[2] & !D1_mLED[4];


--D1L68 is LEDG_Driver:u2|DIR~103 at LCCOMB_X30_Y9_N0
D1L68 = D1_DIR & !D1_mLED[5] & D1_mLED[3] & !D1_mLED[4] # !D1_DIR & D1_mLED[5] & !D1_mLED[3] & D1_mLED[4];


--D1L69 is LEDG_Driver:u2|DIR~104 at LCCOMB_X30_Y9_N26
D1L69 = D1L68 & !D1_mLED[7] & D1_mLED[0];


--D1L70 is LEDG_Driver:u2|DIR~105 at LCCOMB_X30_Y9_N22
D1L70 = D1_mLED[1] & (D1_DIR # D1L69 & D1L67) # !D1_mLED[1] & D1_DIR & (D1L67 # !D1L69);


--D1_Cont[19] is LEDG_Driver:u2|Cont[19] at LCFF_X1_Y12_N19
D1_Cont[19] = DFFEAS(D1L60, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[18] is LEDG_Driver:u2|Cont[18] at LCFF_X1_Y12_N17
D1_Cont[18] = DFFEAS(D1L57, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[17] is LEDG_Driver:u2|Cont[17] at LCFF_X1_Y12_N15
D1_Cont[17] = DFFEAS(D1L54, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[16] is LEDG_Driver:u2|Cont[16] at LCFF_X1_Y12_N13
D1_Cont[16] = DFFEAS(D1L51, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[15] is LEDG_Driver:u2|Cont[15] at LCFF_X1_Y12_N11
D1_Cont[15] = DFFEAS(D1L48, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[14] is LEDG_Driver:u2|Cont[14] at LCFF_X1_Y12_N9
D1_Cont[14] = DFFEAS(D1L45, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[13] is LEDG_Driver:u2|Cont[13] at LCFF_X1_Y12_N7
D1_Cont[13] = DFFEAS(D1L42, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[12] is LEDG_Driver:u2|Cont[12] at LCFF_X1_Y12_N5
D1_Cont[12] = DFFEAS(D1L39, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[11] is LEDG_Driver:u2|Cont[11] at LCFF_X1_Y12_N3
D1_Cont[11] = DFFEAS(D1L36, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[10] is LEDG_Driver:u2|Cont[10] at LCFF_X1_Y12_N1
D1_Cont[10] = DFFEAS(D1L33, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[9] is LEDG_Driver:u2|Cont[9] at LCFF_X1_Y13_N31
D1_Cont[9] = DFFEAS(D1L30, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[8] is LEDG_Driver:u2|Cont[8] at LCFF_X1_Y13_N29
D1_Cont[8] = DFFEAS(D1L27, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[7] is LEDG_Driver:u2|Cont[7] at LCFF_X1_Y13_N27
D1_Cont[7] = DFFEAS(D1L24, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[6] is LEDG_Driver:u2|Cont[6] at LCFF_X1_Y13_N25
D1_Cont[6] = DFFEAS(D1L21, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[5] is LEDG_Driver:u2|Cont[5] at LCFF_X1_Y13_N23
D1_Cont[5] = DFFEAS(D1L18, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[4] is LEDG_Driver:u2|Cont[4] at LCFF_X1_Y13_N21
D1_Cont[4] = DFFEAS(D1L15, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[3] is LEDG_Driver:u2|Cont[3] at LCFF_X1_Y13_N19
D1_Cont[3] = DFFEAS(D1L12, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[2] is LEDG_Driver:u2|Cont[2] at LCFF_X1_Y13_N17
D1_Cont[2] = DFFEAS(D1L9, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[1] is LEDG_Driver:u2|Cont[1] at LCFF_X1_Y13_N15
D1_Cont[1] = DFFEAS(D1L6, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1_Cont[0] is LEDG_Driver:u2|Cont[0] at LCFF_X1_Y13_N13
D1_Cont[0] = DFFEAS(D1L3, GLOBAL(A1L9),  ,  ,  ,  ,  ,  ,  );


--D1L3 is LEDG_Driver:u2|Cont[0]~168 at LCCOMB_X1_Y13_N12
D1L3 = D1_Cont[0] $ VCC;

--D1L4 is LEDG_Driver:u2|Cont[0]~169 at LCCOMB_X1_Y13_N12
D1L4 = CARRY(D1_Cont[0]);


--D1L6 is LEDG_Driver:u2|Cont[1]~170 at LCCOMB_X1_Y13_N14
D1L6 = D1_Cont[1] & !D1L4 # !D1_Cont[1] & (D1L4 # GND);

--D1L7 is LEDG_Driver:u2|Cont[1]~171 at LCCOMB_X1_Y13_N14
D1L7 = CARRY(!D1L4 # !D1_Cont[1]);


--D1L9 is LEDG_Driver:u2|Cont[2]~172 at LCCOMB_X1_Y13_N16
D1L9 = D1_Cont[2] & (D1L7 $ GND) # !D1_Cont[2] & !D1L7 & VCC;

--D1L10 is LEDG_Driver:u2|Cont[2]~173 at LCCOMB_X1_Y13_N16
D1L10 = CARRY(D1_Cont[2] & !D1L7);


--D1L12 is LEDG_Driver:u2|Cont[3]~174 at LCCOMB_X1_Y13_N18
D1L12 = D1_Cont[3] & !D1L10 # !D1_Cont[3] & (D1L10 # GND);

--D1L13 is LEDG_Driver:u2|Cont[3]~175 at LCCOMB_X1_Y13_N18
D1L13 = CARRY(!D1L10 # !D1_Cont[3]);


--D1L15 is LEDG_Driver:u2|Cont[4]~176 at LCCOMB_X1_Y13_N20
D1L15 = D1_Cont[4] & (D1L13 $ GND) # !D1_Cont[4] & !D1L13 & VCC;

--D1L16 is LEDG_Driver:u2|Cont[4]~177 at LCCOMB_X1_Y13_N20
D1L16 = CARRY(D1_Cont[4] & !D1L13);


--D1L18 is LEDG_Driver:u2|Cont[5]~178 at LCCOMB_X1_Y13_N22
D1L18 = D1_Cont[5] & !D1L16 # !D1_Cont[5] & (D1L16 # GND);

--D1L19 is LEDG_Driver:u2|Cont[5]~179 at LCCOMB_X1_Y13_N22
D1L19 = CARRY(!D1L16 # !D1_Cont[5]);


--D1L21 is LEDG_Driver:u2|Cont[6]~180 at LCCOMB_X1_Y13_N24
D1L21 = D1_Cont[6] & (D1L19 $ GND) # !D1_Cont[6] & !D1L19 & VCC;

--D1L22 is LEDG_Driver:u2|Cont[6]~181 at LCCOMB_X1_Y13_N24
D1L22 = CARRY(D1_Cont[6] & !D1L19);


--D1L24 is LEDG_Driver:u2|Cont[7]~182 at LCCOMB_X1_Y13_N26
D1L24 = D1_Cont[7] & !D1L22 # !D1_Cont[7] & (D1L22 # GND);

--D1L25 is LEDG_Driver:u2|Cont[7]~183 at LCCOMB_X1_Y13_N26
D1L25 = CARRY(!D1L22 # !D1_Cont[7]);


--D1L27 is LEDG_Driver:u2|Cont[8]~184 at LCCOMB_X1_Y13_N28
D1L27 = D1_Cont[8] & (D1L25 $ GND) # !D1_Cont[8] & !D1L25 & VCC;

--D1L28 is LEDG_Driver:u2|Cont[8]~185 at LCCOMB_X1_Y13_N28
D1L28 = CARRY(D1_Cont[8] & !D1L25);


--D1L30 is LEDG_Driver:u2|Cont[9]~186 at LCCOMB_X1_Y13_N30
D1L30 = D1_Cont[9] & !D1L28 # !D1_Cont[9] & (D1L28 # GND);

--D1L31 is LEDG_Driver:u2|Cont[9]~187 at LCCOMB_X1_Y13_N30
D1L31 = CARRY(!D1L28 # !D1_Cont[9]);


--D1L33 is LEDG_Driver:u2|Cont[10]~188 at LCCOMB_X1_Y12_N0
D1L33 = D1_Cont[10] & (D1L31 $ GND) # !D1_Cont[10] & !D1L31 & VCC;

--D1L34 is LEDG_Driver:u2|Cont[10]~189 at LCCOMB_X1_Y12_N0
D1L34 = CARRY(D1_Cont[10] & !D1L31);


--D1L36 is LEDG_Driver:u2|Cont[11]~190 at LCCOMB_X1_Y12_N2
D1L36 = D1_Cont[11] & !D1L34 # !D1_Cont[11] & (D1L34 # GND);

--D1L37 is LEDG_Driver:u2|Cont[11]~191 at LCCOMB_X1_Y12_N2
D1L37 = CARRY(!D1L34 # !D1_Cont[11]);


--D1L39 is LEDG_Driver:u2|Cont[12]~192 at LCCOMB_X1_Y12_N4
D1L39 = D1_Cont[12] & (D1L37 $ GND) # !D1_Cont[12] & !D1L37 & VCC;

--D1L40 is LEDG_Driver:u2|Cont[12]~193 at LCCOMB_X1_Y12_N4
D1L40 = CARRY(D1_Cont[12] & !D1L37);


--D1L42 is LEDG_Driver:u2|Cont[13]~194 at LCCOMB_X1_Y12_N6
D1L42 = D1_Cont[13] & !D1L40 # !D1_Cont[13] & (D1L40 # GND);

--D1L43 is LEDG_Driver:u2|Cont[13]~195 at LCCOMB_X1_Y12_N6
D1L43 = CARRY(!D1L40 # !D1_Cont[13]);


--D1L45 is LEDG_Driver:u2|Cont[14]~196 at LCCOMB_X1_Y12_N8
D1L45 = D1_Cont[14] & (D1L43 $ GND) # !D1_Cont[14] & !D1L43 & VCC;

--D1L46 is LEDG_Driver:u2|Cont[14]~197 at LCCOMB_X1_Y12_N8
D1L46 = CARRY(D1_Cont[14] & !D1L43);


--D1L48 is LEDG_Driver:u2|Cont[15]~198 at LCCOMB_X1_Y12_N10
D1L48 = D1_Cont[15] & !D1L46 # !D1_Cont[15] & (D1L46 # GND);

--D1L49 is LEDG_Driver:u2|Cont[15]~199 at LCCOMB_X1_Y12_N10
D1L49 = CARRY(!D1L46 # !D1_Cont[15]);


--D1L51 is LEDG_Driver:u2|Cont[16]~200 at LCCOMB_X1_Y12_N12
D1L51 = D1_Cont[16] & (D1L49 $ GND) # !D1_Cont[16] & !D1L49 & VCC;

--D1L52 is LEDG_Driver:u2|Cont[16]~201 at LCCOMB_X1_Y12_N12
D1L52 = CARRY(D1_Cont[16] & !D1L49);


--D1L54 is LEDG_Driver:u2|Cont[17]~202 at LCCOMB_X1_Y12_N14
D1L54 = D1_Cont[17] & !D1L52 # !D1_Cont[17] & (D1L52 # GND);

--D1L55 is LEDG_Driver:u2|Cont[17]~203 at LCCOMB_X1_Y12_N14
D1L55 = CARRY(!D1L52 # !D1_Cont[17]);


--D1L57 is LEDG_Driver:u2|Cont[18]~204 at LCCOMB_X1_Y12_N16
D1L57 = D1_Cont[18] & (D1L55 $ GND) # !D1_Cont[18] & !D1L55 & VCC;

--D1L58 is LEDG_Driver:u2|Cont[18]~205 at LCCOMB_X1_Y12_N16
D1L58 = CARRY(D1_Cont[18] & !D1L55);


--D1L60 is LEDG_Driver:u2|Cont[19]~206 at LCCOMB_X1_Y12_N18
D1L60 = D1_Cont[19] & !D1L58 # !D1_Cont[19] & (D1L58 # GND);

--D1L61 is LEDG_Driver:u2|Cont[19]~207 at LCCOMB_X1_Y12_N18
D1L61 = CARRY(!D1L58 # !D1_Cont[19]);


--D1L63 is LEDG_Driver:u2|Cont[20]~208 at LCCOMB_X1_Y12_N20
D1L63 = D1_Cont[20] $ !D1L61;


--C1L70 is LEDR_Driver:u1|Equal~158 at LCCOMB_X49_Y7_N8
C1L70 = !C1_mLED[5] & !C1_mLED[4] & !C1_mLED[9] & C1_mLED[0];


--C1L67 is LEDR_Driver:u1|DIR~100 at LCCOMB_X49_Y7_N24
C1L67 = C1_mLED[3] & !C1_mLED[8] & C1_DIR & !C1_mLED[6] # !C1_mLED[3] & C1_mLED[8] & !C1_DIR & C1_mLED[6];


--C1L68 is LEDR_Driver:u1|DIR~101 at LCCOMB_X49_Y7_N12
C1L68 = C1_mLED[7] & (C1_DIR # C1_mLED[2] & C1_mLED[1]) # !C1_mLED[7] & C1_DIR & (C1_mLED[2] # C1_mLED[1]);


--C1L69 is LEDR_Driver:u1|DIR~102 at LCCOMB_X49_Y7_N14
C1L69 = C1L67 & (C1L70 & (C1L68) # !C1L70 & C1_DIR) # !C1L67 & (C1_DIR);


--C1_Cont[19] is LEDR_Driver:u1|Cont[19] at LCFF_X2_Y12_N19
C1_Cont[19] = DFFEAS(C1L60, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[18] is LEDR_Driver:u1|Cont[18] at LCFF_X2_Y12_N17
C1_Cont[18] = DFFEAS(C1L57, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[17] is LEDR_Driver:u1|Cont[17] at LCFF_X2_Y12_N15
C1_Cont[17] = DFFEAS(C1L54, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[16] is LEDR_Driver:u1|Cont[16] at LCFF_X2_Y12_N13
C1_Cont[16] = DFFEAS(C1L51, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[15] is LEDR_Driver:u1|Cont[15] at LCFF_X2_Y12_N11
C1_Cont[15] = DFFEAS(C1L48, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[14] is LEDR_Driver:u1|Cont[14] at LCFF_X2_Y12_N9
C1_Cont[14] = DFFEAS(C1L45, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[13] is LEDR_Driver:u1|Cont[13] at LCFF_X2_Y12_N7
C1_Cont[13] = DFFEAS(C1L42, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[12] is LEDR_Driver:u1|Cont[12] at LCFF_X2_Y12_N5
C1_Cont[12] = DFFEAS(C1L39, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[11] is LEDR_Driver:u1|Cont[11] at LCFF_X2_Y12_N3
C1_Cont[11] = DFFEAS(C1L36, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[10] is LEDR_Driver:u1|Cont[10] at LCFF_X2_Y12_N1
C1_Cont[10] = DFFEAS(C1L33, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[9] is LEDR_Driver:u1|Cont[9] at LCFF_X2_Y13_N31
C1_Cont[9] = DFFEAS(C1L30, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[8] is LEDR_Driver:u1|Cont[8] at LCFF_X2_Y13_N29
C1_Cont[8] = DFFEAS(C1L27, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[7] is LEDR_Driver:u1|Cont[7] at LCFF_X2_Y13_N27
C1_Cont[7] = DFFEAS(C1L24, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[6] is LEDR_Driver:u1|Cont[6] at LCFF_X2_Y13_N25
C1_Cont[6] = DFFEAS(C1L21, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[5] is LEDR_Driver:u1|Cont[5] at LCFF_X2_Y13_N23
C1_Cont[5] = DFFEAS(C1L18, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[4] is LEDR_Driver:u1|Cont[4] at LCFF_X2_Y13_N21
C1_Cont[4] = DFFEAS(C1L15, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[3] is LEDR_Driver:u1|Cont[3] at LCFF_X2_Y13_N19
C1_Cont[3] = DFFEAS(C1L12, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[2] is LEDR_Driver:u1|Cont[2] at LCFF_X2_Y13_N17
C1_Cont[2] = DFFEAS(C1L9, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[1] is LEDR_Driver:u1|Cont[1] at LCFF_X2_Y13_N15
C1_Cont[1] = DFFEAS(C1L6, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1_Cont[0] is LEDR_Driver:u1|Cont[0] at LCFF_X2_Y13_N13
C1_Cont[0] = DFFEAS(C1L3, GLOBAL(A1L13),  ,  ,  ,  ,  ,  ,  );


--C1L3 is LEDR_Driver:u1|Cont[0]~168 at LCCOMB_X2_Y13_N12
C1L3 = C1_Cont[0] $ VCC;

--C1L4 is LEDR_Driver:u1|Cont[0]~169 at LCCOMB_X2_Y13_N12
C1L4 = CARRY(C1_Cont[0]);


--C1L6 is LEDR_Driver:u1|Cont[1]~170 at LCCOMB_X2_Y13_N14
C1L6 = C1_Cont[1] & !C1L4 # !C1_Cont[1] & (C1L4 # GND);

--C1L7 is LEDR_Driver:u1|Cont[1]~171 at LCCOMB_X2_Y13_N14
C1L7 = CARRY(!C1L4 # !C1_Cont[1]);


--C1L9 is LEDR_Driver:u1|Cont[2]~172 at LCCOMB_X2_Y13_N16
C1L9 = C1_Cont[2] & (C1L7 $ GND) # !C1_Cont[2] & !C1L7 & VCC;

--C1L10 is LEDR_Driver:u1|Cont[2]~173 at LCCOMB_X2_Y13_N16
C1L10 = CARRY(C1_Cont[2] & !C1L7);


--C1L12 is LEDR_Driver:u1|Cont[3]~174 at LCCOMB_X2_Y13_N18
C1L12 = C1_Cont[3] & !C1L10 # !C1_Cont[3] & (C1L10 # GND);

--C1L13 is LEDR_Driver:u1|Cont[3]~175 at LCCOMB_X2_Y13_N18
C1L13 = CARRY(!C1L10 # !C1_Cont[3]);


--C1L15 is LEDR_Driver:u1|Cont[4]~176 at LCCOMB_X2_Y13_N20
C1L15 = C1_Cont[4] & (C1L13 $ GND) # !C1_Cont[4] & !C1L13 & VCC;

--C1L16 is LEDR_Driver:u1|Cont[4]~177 at LCCOMB_X2_Y13_N20
C1L16 = CARRY(C1_Cont[4] & !C1L13);


--C1L18 is LEDR_Driver:u1|Cont[5]~178 at LCCOMB_X2_Y13_N22
C1L18 = C1_Cont[5] & !C1L16 # !C1_Cont[5] & (C1L16 # GND);

--C1L19 is LEDR_Driver:u1|Cont[5]~179 at LCCOMB_X2_Y13_N22
C1L19 = CARRY(!C1L16 # !C1_Cont[5]);


--C1L21 is LEDR_Driver:u1|Cont[6]~180 at LCCOMB_X2_Y13_N24
C1L21 = C1_Cont[6] & (C1L19 $ GND) # !C1_Cont[6] & !C1L19 & VCC;

--C1L22 is LEDR_Driver:u1|Cont[6]~181 at LCCOMB_X2_Y13_N24
C1L22 = CARRY(C1_Cont[6] & !C1L19);


--C1L24 is LEDR_Driver:u1|Cont[7]~182 at LCCOMB_X2_Y13_N26
C1L24 = C1_Cont[7] & !C1L22 # !C1_Cont[7] & (C1L22 # GND);

--C1L25 is LEDR_Driver:u1|Cont[7]~183 at LCCOMB_X2_Y13_N26
C1L25 = CARRY(!C1L22 # !C1_Cont[7]);


--C1L27 is LEDR_Driver:u1|Cont[8]~184 at LCCOMB_X2_Y13_N28
C1L27 = C1_Cont[8] & (C1L25 $ GND) # !C1_Cont[8] & !C1L25 & VCC;

--C1L28 is LEDR_Driver:u1|Cont[8]~185 at LCCOMB_X2_Y13_N28
C1L28 = CARRY(C1_Cont[8] & !C1L25);


--C1L30 is LEDR_Driver:u1|Cont[9]~186 at LCCOMB_X2_Y13_N30
C1L30 = C1_Cont[9] & !C1L28 # !C1_Cont[9] & (C1L28 # GND);

--C1L31 is LEDR_Driver:u1|Cont[9]~187 at LCCOMB_X2_Y13_N30
C1L31 = CARRY(!C1L28 # !C1_Cont[9]);


--C1L33 is LEDR_Driver:u1|Cont[10]~188 at LCCOMB_X2_Y12_N0
C1L33 = C1_Cont[10] & (C1L31 $ GND) # !C1_Cont[10] & !C1L31 & VCC;

--C1L34 is LEDR_Driver:u1|Cont[10]~189 at LCCOMB_X2_Y12_N0
C1L34 = CARRY(C1_Cont[10] & !C1L31);


--C1L36 is LEDR_Driver:u1|Cont[11]~190 at LCCOMB_X2_Y12_N2
C1L36 = C1_Cont[11] & !C1L34 # !C1_Cont[11] & (C1L34 # GND);

--C1L37 is LEDR_Driver:u1|Cont[11]~191 at LCCOMB_X2_Y12_N2
C1L37 = CARRY(!C1L34 # !C1_Cont[11]);


--C1L39 is LEDR_Driver:u1|Cont[12]~192 at LCCOMB_X2_Y12_N4
C1L39 = C1_Cont[12] & (C1L37 $ GND) # !C1_Cont[12] & !C1L37 & VCC;

--C1L40 is LEDR_Driver:u1|Cont[12]~193 at LCCOMB_X2_Y12_N4
C1L40 = CARRY(C1_Cont[12] & !C1L37);


--C1L42 is LEDR_Driver:u1|Cont[13]~194 at LCCOMB_X2_Y12_N6
C1L42 = C1_Cont[13] & !C1L40 # !C1_Cont[13] & (C1L40 # GND);

--C1L43 is LEDR_Driver:u1|Cont[13]~195 at LCCOMB_X2_Y12_N6
C1L43 = CARRY(!C1L40 # !C1_Cont[13]);


--C1L45 is LEDR_Driver:u1|Cont[14]~196 at LCCOMB_X2_Y12_N8
C1L45 = C1_Cont[14] & (C1L43 $ GND) # !C1_Cont[14] & !C1L43 & VCC;

--C1L46 is LEDR_Driver:u1|Cont[14]~197 at LCCOMB_X2_Y12_N8
C1L46 = CARRY(C1_Cont[14] & !C1L43);


--C1L48 is LEDR_Driver:u1|Cont[15]~198 at LCCOMB_X2_Y12_N10
C1L48 = C1_Cont[15] & !C1L46 # !C1_Cont[15] & (C1L46 # GND);

--C1L49 is LEDR_Driver:u1|Cont[15]~199 at LCCOMB_X2_Y12_N10
C1L49 = CARRY(!C1L46 # !C1_Cont[15]);


--C1L51 is LEDR_Driver:u1|Cont[16]~200 at LCCOMB_X2_Y12_N12
C1L51 = C1_Cont[16] & (C1L49 $ GND) # !C1_Cont[16] & !C1L49 & VCC;

--C1L52 is LEDR_Driver:u1|Cont[16]~201 at LCCOMB_X2_Y12_N12
C1L52 = CARRY(C1_Cont[16] & !C1L49);


--C1L54 is LEDR_Driver:u1|Cont[17]~202 at LCCOMB_X2_Y12_N14
C1L54 = C1_Cont[17] & !C1L52 # !C1_Cont[17] & (C1L52 # GND);

--C1L55 is LEDR_Driver:u1|Cont[17]~203 at LCCOMB_X2_Y12_N14
C1L55 = CARRY(!C1L52 # !C1_Cont[17]);


--C1L57 is LEDR_Driver:u1|Cont[18]~204 at LCCOMB_X2_Y12_N16
C1L57 = C1_Cont[18] & (C1L55 $ GND) # !C1_Cont[18] & !C1L55 & VCC;

--C1L58 is LEDR_Driver:u1|Cont[18]~205 at LCCOMB_X2_Y12_N16
C1L58 = CARRY(C1_Cont[18] & !C1L55);


--C1L60 is LEDR_Driver:u1|Cont[19]~206 at LCCOMB_X2_Y12_N18
C1L60 = C1_Cont[19] & !C1L58 # !C1_Cont[19] & (C1L58 # GND);

--C1L61 is LEDR_Driver:u1|Cont[19]~207 at LCCOMB_X2_Y12_N18
C1L61 = CARRY(!C1L58 # !C1_Cont[19]);


--C1L63 is LEDR_Driver:u1|Cont[20]~208 at LCCOMB_X2_Y12_N20
C1L63 = C1_Cont[20] $ !C1L61;


--V1_END is I2C_AV_Config:u7|I2C_Controller:u0|END at LCFF_X35_Y14_N23
V1_END = DFFEAS(V1L14, GLOBAL(J1L73), KEY[0],  ,  ,  ,  ,  ,  );


--J1_mSetup_ST.10 is I2C_AV_Config:u7|mSetup_ST.10 at LCFF_X35_Y14_N31
J1_mSetup_ST.10 = DFFEAS(J1L91, GLOBAL(J1L73), KEY[0],  ,  ,  ,  ,  ,  );


--J1_mSetup_ST.01 is I2C_AV_Config:u7|mSetup_ST.01 at LCFF_X35_Y14_N5
J1_mSetup_ST.01 = DFFEAS(J1L20, GLOBAL(J1L73), KEY[0],  ,  ,  ,  ,  ,  );


--J1L19 is I2C_AV_Config:u7|Select~135 at LCCOMB_X34_Y14_N6
J1L19 = J1_mSetup_ST.01 & V1_END & J1_mI2C_GO # !J1_mSetup_ST.01 & (J1_mI2C_GO # !J1_mSetup_ST.10);


--J1_mI2C_CLK_DIV[1] is I2C_AV_Config:u7|mI2C_CLK_DIV[1] at LCFF_X36_Y14_N3
J1_mI2C_CLK_DIV[1] = DFFEAS(J1L27, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1_mI2C_CLK_DIV[0] is I2C_AV_Config:u7|mI2C_CLK_DIV[0] at LCFF_X36_Y14_N1
J1_mI2C_CLK_DIV[0] = DFFEAS(J1L24, GLOBAL(A1L16), KEY[0],  ,  ,  ,  , J1L18,  );


--J1L24 is I2C_AV_Config:u7|mI2C_CLK_DIV[0]~239 at LCCOMB_X36_Y14_N0
J1L24 = J1_mI2C_CLK_DIV[0] $ VCC;

--J1L25 is I2C_AV_Config:u7|mI2C_CLK_DIV[0]~240 at LCCOMB_X36_Y14_N0
J1L25 = CARRY(J1_mI2C_CLK_DIV[0]);


--J1L27 is I2C_AV_Config:u7|mI2C_CLK_DIV[1]~241 at LCCOMB_X36_Y14_N2
J1L27 = J1_mI2C_CLK_DIV[1] & !J1L25 # !J1_mI2C_CLK_DIV[1] & (J1L25 # GND);

--J1L28 is I2C_AV_Config:u7|mI2C_CLK_DIV[1]~242 at LCCOMB_X36_Y14_N2
J1L28 = CARRY(!J1L25 # !J1_mI2C_CLK_DIV[1]);


--J1L30 is I2C_AV_Config:u7|mI2C_CLK_DIV[2]~243 at LCCOMB_X36_Y14_N4
J1L30 = J1_mI2C_CLK_DIV[2] & (J1L28 $ GND) # !J1_mI2C_CLK_DIV[2] & !J1L28 & VCC;

--J1L31 is I2C_AV_Config:u7|mI2C_CLK_DIV[2]~244 at LCCOMB_X36_Y14_N4
J1L31 = CARRY(J1_mI2C_CLK_DIV[2] & !J1L28);


--J1L33 is I2C_AV_Config:u7|mI2C_CLK_DIV[3]~245 at LCCOMB_X36_Y14_N6
J1L33 = J1_mI2C_CLK_DIV[3] & !J1L31 # !J1_mI2C_CLK_DIV[3] & (J1L31 # GND);

--J1L34 is I2C_AV_Config:u7|mI2C_CLK_DIV[3]~246 at LCCOMB_X36_Y14_N6
J1L34 = CARRY(!J1L31 # !J1_mI2C_CLK_DIV[3]);


--J1L36 is I2C_AV_Config:u7|mI2C_CLK_DIV[4]~247 at LCCOMB_X36_Y14_N8
J1L36 = J1_mI2C_CLK_DIV[4] & (J1L34 $ GND) # !J1_mI2C_CLK_DIV[4] & !J1L34 & VCC;

--J1L37 is I2C_AV_Config:u7|mI2C_CLK_DIV[4]~248 at LCCOMB_X36_Y14_N8
J1L37 = CARRY(J1_mI2C_CLK_DIV[4] & !J1L34);


--J1L39 is I2C_AV_Config:u7|mI2C_CLK_DIV[5]~249 at LCCOMB_X36_Y14_N10
J1L39 = J1_mI2C_CLK_DIV[5] & !J1L37 # !J1_mI2C_CLK_DIV[5] & (J1L37 # GND);

--J1L40 is I2C_AV_Config:u7|mI2C_CLK_DIV[5]~250 at LCCOMB_X36_Y14_N10
J1L40 = CARRY(!J1L37 # !J1_mI2C_CLK_DIV[5]);


--J1L42 is I2C_AV_Config:u7|mI2C_CLK_DIV[6]~251 at LCCOMB_X36_Y14_N12
J1L42 = J1_mI2C_CLK_DIV[6] & (J1L40 $ GND) # !J1_mI2C_CLK_DIV[6] & !J1L40 & VCC;

--J1L43 is I2C_AV_Config:u7|mI2C_CLK_DIV[6]~252 at LCCOMB_X36_Y14_N12
J1L43 = CARRY(J1_mI2C_CLK_DIV[6] & !J1L40);


--J1L45 is I2C_AV_Config:u7|mI2C_CLK_DIV[7]~253 at LCCOMB_X36_Y14_N14
J1L45 = J1_mI2C_CLK_DIV[7] & !J1L43 # !J1_mI2C_CLK_DIV[7] & (J1L43 # GND);

--J1L46 is I2C_AV_Config:u7|mI2C_CLK_DIV[7]~254 at LCCOMB_X36_Y14_N14
J1L46 = CARRY(!J1L43 # !J1_mI2C_CLK_DIV[7]);


--J1L48 is I2C_AV_Config:u7|mI2C_CLK_DIV[8]~255 at LCCOMB_X36_Y14_N16
J1L48 = J1_mI2C_CLK_DIV[8] & (J1L46 $ GND) # !J1_mI2C_CLK_DIV[8] & !J1L46 & VCC;

--J1L49 is I2C_AV_Config:u7|mI2C_CLK_DIV[8]~256 at LCCOMB_X36_Y14_N16
J1L49 = CARRY(J1_mI2C_CLK_DIV[8] & !J1L46);


--J1L51 is I2C_AV_Config:u7|mI2C_CLK_DIV[9]~257 at LCCOMB_X36_Y14_N18
J1L51 = J1_mI2C_CLK_DIV[9] & !J1L49 # !J1_mI2C_CLK_DIV[9] & (J1L49 # GND);

--J1L52 is I2C_AV_Config:u7|mI2C_CLK_DIV[9]~258 at LCCOMB_X36_Y14_N18
J1L52 = CARRY(!J1L49 # !J1_mI2C_CLK_DIV[9]);


--J1L54 is I2C_AV_Config:u7|mI2C_CLK_DIV[10]~259 at LCCOMB_X36_Y14_N20
J1L54 = J1_mI2C_CLK_DIV[10] & (J1L52 $ GND) # !J1_mI2C_CLK_DIV[10] & !J1L52 & VCC;

--J1L55 is I2C_AV_Config:u7|mI2C_CLK_DIV[10]~260 at LCCOMB_X36_Y14_N20
J1L55 = CARRY(J1_mI2C_CLK_DIV[10] & !J1L52);


--J1L57 is I2C_AV_Config:u7|mI2C_CLK_DIV[11]~261 at LCCOMB_X36_Y14_N22
J1L57 = J1_mI2C_CLK_DIV[11] & !J1L55 # !J1_mI2C_CLK_DIV[11] & (J1L55 # GND);

--J1L58 is I2C_AV_Config:u7|mI2C_CLK_DIV[11]~262 at LCCOMB_X36_Y14_N22
J1L58 = CARRY(!J1L55 # !J1_mI2C_CLK_DIV[11]);


--J1L60 is I2C_AV_Config:u7|mI2C_CLK_DIV[12]~263 at LCCOMB_X36_Y14_N24
J1L60 = J1_mI2C_CLK_DIV[12] & (J1L58 $ GND) # !J1_mI2C_CLK_DIV[12] & !J1L58 & VCC;

--J1L61 is I2C_AV_Config:u7|mI2C_CLK_DIV[12]~264 at LCCOMB_X36_Y14_N24
J1L61 = CARRY(J1_mI2C_CLK_DIV[12] & !J1L58);


--J1L63 is I2C_AV_Config:u7|mI2C_CLK_DIV[13]~265 at LCCOMB_X36_Y14_N26
J1L63 = J1_mI2C_CLK_DIV[13] & !J1L61 # !J1_mI2C_CLK_DIV[13] & (J1L61 # GND);

--J1L64 is I2C_AV_Config:u7|mI2C_CLK_DIV[13]~266 at LCCOMB_X36_Y14_N26
J1L64 = CARRY(!J1L61 # !J1_mI2C_CLK_DIV[13]);


--J1L66 is I2C_AV_Config:u7|mI2C_CLK_DIV[14]~267 at LCCOMB_X36_Y14_N28
J1L66 = J1_mI2C_CLK_DIV[14] & (J1L64 $ GND) # !J1_mI2C_CLK_DIV[14] & !J1L64 & VCC;

--J1L67 is I2C_AV_Config:u7|mI2C_CLK_DIV[14]~268 at LCCOMB_X36_Y14_N28
J1L67 = CARRY(J1_mI2C_CLK_DIV[14] & !J1L64);


--J1L69 is I2C_AV_Config:u7|mI2C_CLK_DIV[15]~269 at LCCOMB_X36_Y14_N30
J1L69 = J1L67 $ J1_mI2C_CLK_DIV[15];


--F1_oCoord_Y[9] is VGA_Controller:u4|oCoord_Y[9] at LCFF_X24_Y10_N27
F1_oCoord_Y[9] = DFFEAS(F1L250, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_Y[8] is VGA_Controller:u4|oCoord_Y[8] at LCFF_X24_Y10_N25
F1_oCoord_Y[8] = DFFEAS(F1L247, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_Y[7] is VGA_Controller:u4|oCoord_Y[7] at LCFF_X24_Y10_N23
F1_oCoord_Y[7] = DFFEAS(F1L244, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_Y[4] is VGA_Controller:u4|oCoord_Y[4] at LCFF_X24_Y10_N17
F1_oCoord_Y[4] = DFFEAS(F1L235, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_Y[3] is VGA_Controller:u4|oCoord_Y[3] at LCFF_X24_Y10_N15
F1_oCoord_Y[3] = DFFEAS(F1L232, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_Y[6] is VGA_Controller:u4|oCoord_Y[6] at LCFF_X24_Y10_N21
F1_oCoord_Y[6] = DFFEAS(F1L241, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_Y[5] is VGA_Controller:u4|oCoord_Y[5] at LCFF_X24_Y10_N19
F1_oCoord_Y[5] = DFFEAS(F1L238, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--G1L1 is VGA_Pattern:u5|LessThan~2783 at LCCOMB_X26_Y10_N28
G1L1 = !F1_oCoord_Y[3] & !F1_oCoord_Y[4] # !F1_oCoord_Y[5] # !F1_oCoord_Y[6];


--G1L49 is VGA_Pattern:u5|oRed~94 at LCCOMB_X26_Y10_N22
G1L49 = F1_oCoord_Y[9] # F1_oCoord_Y[8] & (F1_oCoord_Y[7] # !G1L1);


--F1_oCoord_X[7] is VGA_Controller:u4|oCoord_X[7] at LCFF_X30_Y11_N13
F1_oCoord_X[7] = DFFEAS(F1L213, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_X[8] is VGA_Controller:u4|oCoord_X[8] at LCFF_X30_Y11_N15
F1_oCoord_X[8] = DFFEAS(F1L216, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--H1L13 is VGA_OSD_RAM:u6|LessThan~450 at LCCOMB_X29_Y12_N16
H1L13 = !F1_oCoord_X[7] & !F1_oCoord_X[8];


--F1_oCoord_X[4] is VGA_Controller:u4|oCoord_X[4] at LCFF_X30_Y11_N7
F1_oCoord_X[4] = DFFEAS(F1L204, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_X[5] is VGA_Controller:u4|oCoord_X[5] at LCFF_X30_Y11_N9
F1_oCoord_X[5] = DFFEAS(F1L207, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_X[2] is VGA_Controller:u4|oCoord_X[2] at LCFF_X30_Y11_N3
F1_oCoord_X[2] = DFFEAS(F1L198, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_X[3] is VGA_Controller:u4|oCoord_X[3] at LCFF_X30_Y11_N5
F1_oCoord_X[3] = DFFEAS(F1L201, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--H1L14 is VGA_OSD_RAM:u6|LessThan~451 at LCCOMB_X29_Y11_N0
H1L14 = !F1_oCoord_X[2] & !F1_oCoord_X[4] & !F1_oCoord_X[5] & !F1_oCoord_X[3];


--F1_oCoord_X[6] is VGA_Controller:u4|oCoord_X[6] at LCFF_X30_Y11_N11
F1_oCoord_X[6] = DFFEAS(F1L210, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_X[9] is VGA_Controller:u4|oCoord_X[9] at LCFF_X30_Y11_N17
F1_oCoord_X[9] = DFFEAS(F1L219, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--H1L15 is VGA_OSD_RAM:u6|LessThan~452 at LCCOMB_X29_Y11_N10
H1L15 = H1L13 & (H1L14 # !F1_oCoord_X[6]) # !F1_oCoord_X[9];


--F1_oCoord_Y[2] is VGA_Controller:u4|oCoord_Y[2] at LCFF_X24_Y10_N13
F1_oCoord_Y[2] = DFFEAS(F1L229, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1L227 is VGA_Controller:u4|oCoord_Y[2]~475 at LCCOMB_X24_Y10_N0
F1L227 = !F1_oCoord_Y[3] & !F1_oCoord_Y[2];


--F1_oCoord_Y[1] is VGA_Controller:u4|oCoord_Y[1] at LCFF_X24_Y10_N11
F1_oCoord_Y[1] = DFFEAS(F1L224, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--G1L2 is VGA_Pattern:u5|LessThan~2784 at LCCOMB_X25_Y11_N16
G1L2 = F1_oCoord_Y[5] & F1_oCoord_Y[4];


--H1L16 is VGA_OSD_RAM:u6|LessThan~453 at LCCOMB_X26_Y11_N4
H1L16 = !F1_oCoord_Y[7] & !F1_oCoord_Y[6];


--H1L140 is VGA_OSD_RAM:u6|oRed~81 at LCCOMB_X26_Y11_N10
H1L140 = !F1_oCoord_Y[9] & (F1_oCoord_Y[8] # !H1L16 # !H1L20);


--F1L228 is VGA_Controller:u4|oCoord_Y[2]~476 at LCCOMB_X26_Y11_N12
F1L228 = !F1_oCoord_Y[1] & !F1_oCoord_Y[5] & !F1_oCoord_Y[4] & F1L227;


--H1L17 is VGA_OSD_RAM:u6|LessThan~454 at LCCOMB_X26_Y11_N8
H1L17 = F1L228 # !F1_oCoord_Y[7] # !F1_oCoord_Y[8] # !F1_oCoord_Y[6];


--H1L18 is VGA_OSD_RAM:u6|LessThan~455 at LCCOMB_X27_Y11_N2
H1L18 = !F1_oCoord_X[8] & !F1_oCoord_X[9] & !F1_oCoord_X[6] & !F1_oCoord_X[7];


--G1L40 is VGA_Pattern:u5|oGreen~1204 at LCCOMB_X29_Y11_N12
G1L40 = F1_oCoord_X[5] & F1_oCoord_X[4];


--H1L19 is VGA_OSD_RAM:u6|LessThan~456 at LCCOMB_X27_Y11_N30
H1L19 = H1L18 & (!F1_oCoord_X[3] # !F1_oCoord_X[2] # !G1L40);


--H1L141 is VGA_OSD_RAM:u6|oRed~82 at LCCOMB_X26_Y11_N2
H1L141 = H1L140 & H1L17 & H1L15 & !H1L19;


--R1_address_reg_a[9] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[9] at LCFF_X40_Y11_N17
R1_address_reg_a[9] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(M1L2),  ,  ,  , R1_address_reg_a[3],  ,  , VCC);


--R1_address_reg_a[8] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[8] at LCFF_X38_Y12_N29
R1_address_reg_a[8] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(M1L2),  ,  ,  , R1_address_reg_a[2],  ,  , VCC);


--R1_address_reg_a[7] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[7] at LCFF_X40_Y12_N11
R1_address_reg_a[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(M1L2),  ,  ,  , R1_address_reg_a[1],  ,  , VCC);


--R1_ram_block2a50 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50 at M4K_X17_Y1
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = GLOBAL(M1L2);
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50 = R1_ram_block2a50_PORT_A_data_out_reg[0];

--R1M2695Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT1 at M4K_X17_Y1
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = GLOBAL(M1L2);
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1M2695Q = R1_ram_block2a50_PORT_A_data_out_reg[1];

--R1M2696Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT2 at M4K_X17_Y1
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = GLOBAL(M1L2);
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1M2696Q = R1_ram_block2a50_PORT_A_data_out_reg[2];

--R1M2697Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT3 at M4K_X17_Y1
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = GLOBAL(M1L2);
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1M2697Q = R1_ram_block2a50_PORT_A_data_out_reg[3];

--R1M2698Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT4 at M4K_X17_Y1
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = GLOBAL(M1L2);
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1M2698Q = R1_ram_block2a50_PORT_A_data_out_reg[4];

--R1M2699Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT5 at M4K_X17_Y1
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = GLOBAL(M1L2);
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1M2699Q = R1_ram_block2a50_PORT_A_data_out_reg[5];

--R1M2700Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT6 at M4K_X17_Y1
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = GLOBAL(M1L2);
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1M2700Q = R1_ram_block2a50_PORT_A_data_out_reg[6];

--R1M2701Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a50~PORTADATAOUT7 at M4K_X17_Y1
R1_ram_block2a50_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a50_PORT_A_data_in_reg = DFFE(R1_ram_block2a50_PORT_A_data_in, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_data_in = ~GND;
R1_ram_block2a50_PORT_B_data_in_reg = DFFE(R1_ram_block2a50_PORT_B_data_in, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a50_PORT_A_address_reg = DFFE(R1_ram_block2a50_PORT_A_address, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a50_PORT_B_address_reg = DFFE(R1_ram_block2a50_PORT_B_address, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_PORT_A_write_enable = GND;
R1_ram_block2a50_PORT_A_write_enable_reg = DFFE(R1_ram_block2a50_PORT_A_write_enable, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1_ram_block2a50_PORT_B_write_enable = GND;
R1_ram_block2a50_PORT_B_write_enable_reg = DFFE(R1_ram_block2a50_PORT_B_write_enable, R1_ram_block2a50_clock_1, , , R1_ram_block2a50_clock_enable_1);
R1_ram_block2a50_clock_0 = GLOBAL(M1L2);
R1_ram_block2a50_clock_1 = GND;
R1_ram_block2a50_clock_enable_0 = S3L106;
R1_ram_block2a50_clock_enable_1 = GND;
R1_ram_block2a50_PORT_A_data_out = MEMORY(R1_ram_block2a50_PORT_A_data_in_reg, R1_ram_block2a50_PORT_B_data_in_reg, R1_ram_block2a50_PORT_A_address_reg, R1_ram_block2a50_PORT_B_address_reg, R1_ram_block2a50_PORT_A_write_enable_reg, R1_ram_block2a50_PORT_B_write_enable_reg, , , R1_ram_block2a50_clock_0, R1_ram_block2a50_clock_1, R1_ram_block2a50_clock_enable_0, R1_ram_block2a50_clock_enable_1, , );
R1_ram_block2a50_PORT_A_data_out_reg = DFFE(R1_ram_block2a50_PORT_A_data_out, R1_ram_block2a50_clock_0, , , R1_ram_block2a50_clock_enable_0);
R1M2701Q = R1_ram_block2a50_PORT_A_data_out_reg[7];


--T1L46 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5031 at LCCOMB_X38_Y15_N0
T1L46 = R1_address_reg_a[8] & !R1_address_reg_a[7] # !R1_address_reg_a[8] & R1_address_reg_a[7] & R1M2699Q;


--R1_ram_block2a49 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49 at M4K_X41_Y21
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = GLOBAL(M1L2);
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49 = R1_ram_block2a49_PORT_A_data_out_reg[0];

--R1M2642Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT1 at M4K_X41_Y21
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = GLOBAL(M1L2);
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1M2642Q = R1_ram_block2a49_PORT_A_data_out_reg[1];

--R1M2643Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT2 at M4K_X41_Y21
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = GLOBAL(M1L2);
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1M2643Q = R1_ram_block2a49_PORT_A_data_out_reg[2];

--R1M2644Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT3 at M4K_X41_Y21
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = GLOBAL(M1L2);
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1M2644Q = R1_ram_block2a49_PORT_A_data_out_reg[3];

--R1M2645Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT4 at M4K_X41_Y21
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = GLOBAL(M1L2);
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1M2645Q = R1_ram_block2a49_PORT_A_data_out_reg[4];

--R1M2646Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT5 at M4K_X41_Y21
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = GLOBAL(M1L2);
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1M2646Q = R1_ram_block2a49_PORT_A_data_out_reg[5];

--R1M2647Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT6 at M4K_X41_Y21
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = GLOBAL(M1L2);
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1M2647Q = R1_ram_block2a49_PORT_A_data_out_reg[6];

--R1M2648Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a49~PORTADATAOUT7 at M4K_X41_Y21
R1_ram_block2a49_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a49_PORT_A_data_in_reg = DFFE(R1_ram_block2a49_PORT_A_data_in, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_data_in = ~GND;
R1_ram_block2a49_PORT_B_data_in_reg = DFFE(R1_ram_block2a49_PORT_B_data_in, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a49_PORT_A_address_reg = DFFE(R1_ram_block2a49_PORT_A_address, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a49_PORT_B_address_reg = DFFE(R1_ram_block2a49_PORT_B_address, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_PORT_A_write_enable = GND;
R1_ram_block2a49_PORT_A_write_enable_reg = DFFE(R1_ram_block2a49_PORT_A_write_enable, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1_ram_block2a49_PORT_B_write_enable = GND;
R1_ram_block2a49_PORT_B_write_enable_reg = DFFE(R1_ram_block2a49_PORT_B_write_enable, R1_ram_block2a49_clock_1, , , R1_ram_block2a49_clock_enable_1);
R1_ram_block2a49_clock_0 = GLOBAL(M1L2);
R1_ram_block2a49_clock_1 = GND;
R1_ram_block2a49_clock_enable_0 = S3L105;
R1_ram_block2a49_clock_enable_1 = GND;
R1_ram_block2a49_PORT_A_data_out = MEMORY(R1_ram_block2a49_PORT_A_data_in_reg, R1_ram_block2a49_PORT_B_data_in_reg, R1_ram_block2a49_PORT_A_address_reg, R1_ram_block2a49_PORT_B_address_reg, R1_ram_block2a49_PORT_A_write_enable_reg, R1_ram_block2a49_PORT_B_write_enable_reg, , , R1_ram_block2a49_clock_0, R1_ram_block2a49_clock_1, R1_ram_block2a49_clock_enable_0, R1_ram_block2a49_clock_enable_1, , );
R1_ram_block2a49_PORT_A_data_out_reg = DFFE(R1_ram_block2a49_PORT_A_data_out, R1_ram_block2a49_clock_0, , , R1_ram_block2a49_clock_enable_0);
R1M2648Q = R1_ram_block2a49_PORT_A_data_out_reg[7];


--R1_ram_block2a48 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48 at M4K_X41_Y20
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = GLOBAL(M1L2);
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48 = R1_ram_block2a48_PORT_A_data_out_reg[0];

--R1M2589Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT1 at M4K_X41_Y20
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = GLOBAL(M1L2);
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1M2589Q = R1_ram_block2a48_PORT_A_data_out_reg[1];

--R1M2590Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT2 at M4K_X41_Y20
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = GLOBAL(M1L2);
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1M2590Q = R1_ram_block2a48_PORT_A_data_out_reg[2];

--R1M2591Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT3 at M4K_X41_Y20
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = GLOBAL(M1L2);
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1M2591Q = R1_ram_block2a48_PORT_A_data_out_reg[3];

--R1M2592Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT4 at M4K_X41_Y20
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = GLOBAL(M1L2);
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1M2592Q = R1_ram_block2a48_PORT_A_data_out_reg[4];

--R1M2593Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT5 at M4K_X41_Y20
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = GLOBAL(M1L2);
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1M2593Q = R1_ram_block2a48_PORT_A_data_out_reg[5];

--R1M2594Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT6 at M4K_X41_Y20
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = GLOBAL(M1L2);
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1M2594Q = R1_ram_block2a48_PORT_A_data_out_reg[6];

--R1M2595Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a48~PORTADATAOUT7 at M4K_X41_Y20
R1_ram_block2a48_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a48_PORT_A_data_in_reg = DFFE(R1_ram_block2a48_PORT_A_data_in, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_data_in = ~GND;
R1_ram_block2a48_PORT_B_data_in_reg = DFFE(R1_ram_block2a48_PORT_B_data_in, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a48_PORT_A_address_reg = DFFE(R1_ram_block2a48_PORT_A_address, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a48_PORT_B_address_reg = DFFE(R1_ram_block2a48_PORT_B_address, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_PORT_A_write_enable = GND;
R1_ram_block2a48_PORT_A_write_enable_reg = DFFE(R1_ram_block2a48_PORT_A_write_enable, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1_ram_block2a48_PORT_B_write_enable = GND;
R1_ram_block2a48_PORT_B_write_enable_reg = DFFE(R1_ram_block2a48_PORT_B_write_enable, R1_ram_block2a48_clock_1, , , R1_ram_block2a48_clock_enable_1);
R1_ram_block2a48_clock_0 = GLOBAL(M1L2);
R1_ram_block2a48_clock_1 = GND;
R1_ram_block2a48_clock_enable_0 = S3L104;
R1_ram_block2a48_clock_enable_1 = GND;
R1_ram_block2a48_PORT_A_data_out = MEMORY(R1_ram_block2a48_PORT_A_data_in_reg, R1_ram_block2a48_PORT_B_data_in_reg, R1_ram_block2a48_PORT_A_address_reg, R1_ram_block2a48_PORT_B_address_reg, R1_ram_block2a48_PORT_A_write_enable_reg, R1_ram_block2a48_PORT_B_write_enable_reg, , , R1_ram_block2a48_clock_0, R1_ram_block2a48_clock_1, R1_ram_block2a48_clock_enable_0, R1_ram_block2a48_clock_enable_1, , );
R1_ram_block2a48_PORT_A_data_out_reg = DFFE(R1_ram_block2a48_PORT_A_data_out, R1_ram_block2a48_clock_0, , , R1_ram_block2a48_clock_enable_0);
R1M2595Q = R1_ram_block2a48_PORT_A_data_out_reg[7];


--R1_address_reg_a[6] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[6] at LCFF_X40_Y12_N25
R1_address_reg_a[6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(M1L2),  ,  ,  , R1_address_reg_a[0],  ,  , VCC);


--T1L47 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5032 at LCCOMB_X18_Y12_N0
T1L47 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M2646Q # !R1_address_reg_a[6] & (R1M2593Q));


--T1L48 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5033 at LCCOMB_X38_Y13_N0
T1L48 = !R1_address_reg_a[9] & (R1_address_reg_a[7] & !T1L47 & T1L46 # !R1_address_reg_a[7] & T1L47 & !T1L46);


--R1_ram_block2a30 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30 at M4K_X17_Y6
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = GLOBAL(M1L2);
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30 = R1_ram_block2a30_PORT_A_data_out_reg[0];

--R1M1635Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT1 at M4K_X17_Y6
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = GLOBAL(M1L2);
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1M1635Q = R1_ram_block2a30_PORT_A_data_out_reg[1];

--R1M1636Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT2 at M4K_X17_Y6
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = GLOBAL(M1L2);
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1M1636Q = R1_ram_block2a30_PORT_A_data_out_reg[2];

--R1M1637Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT3 at M4K_X17_Y6
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = GLOBAL(M1L2);
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1M1637Q = R1_ram_block2a30_PORT_A_data_out_reg[3];

--R1M1638Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT4 at M4K_X17_Y6
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = GLOBAL(M1L2);
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1M1638Q = R1_ram_block2a30_PORT_A_data_out_reg[4];

--R1M1639Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT5 at M4K_X17_Y6
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = GLOBAL(M1L2);
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1M1639Q = R1_ram_block2a30_PORT_A_data_out_reg[5];

--R1M1640Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT6 at M4K_X17_Y6
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = GLOBAL(M1L2);
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1M1640Q = R1_ram_block2a30_PORT_A_data_out_reg[6];

--R1M1641Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a30~PORTADATAOUT7 at M4K_X17_Y6
R1_ram_block2a30_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a30_PORT_A_data_in_reg = DFFE(R1_ram_block2a30_PORT_A_data_in, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_data_in = ~GND;
R1_ram_block2a30_PORT_B_data_in_reg = DFFE(R1_ram_block2a30_PORT_B_data_in, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a30_PORT_A_address_reg = DFFE(R1_ram_block2a30_PORT_A_address, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a30_PORT_B_address_reg = DFFE(R1_ram_block2a30_PORT_B_address, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_PORT_A_write_enable = GND;
R1_ram_block2a30_PORT_A_write_enable_reg = DFFE(R1_ram_block2a30_PORT_A_write_enable, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1_ram_block2a30_PORT_B_write_enable = GND;
R1_ram_block2a30_PORT_B_write_enable_reg = DFFE(R1_ram_block2a30_PORT_B_write_enable, R1_ram_block2a30_clock_1, , , R1_ram_block2a30_clock_enable_1);
R1_ram_block2a30_clock_0 = GLOBAL(M1L2);
R1_ram_block2a30_clock_1 = GND;
R1_ram_block2a30_clock_enable_0 = S3_w_anode3199w[3];
R1_ram_block2a30_clock_enable_1 = GND;
R1_ram_block2a30_PORT_A_data_out = MEMORY(R1_ram_block2a30_PORT_A_data_in_reg, R1_ram_block2a30_PORT_B_data_in_reg, R1_ram_block2a30_PORT_A_address_reg, R1_ram_block2a30_PORT_B_address_reg, R1_ram_block2a30_PORT_A_write_enable_reg, R1_ram_block2a30_PORT_B_write_enable_reg, , , R1_ram_block2a30_clock_0, R1_ram_block2a30_clock_1, R1_ram_block2a30_clock_enable_0, R1_ram_block2a30_clock_enable_1, , );
R1_ram_block2a30_PORT_A_data_out_reg = DFFE(R1_ram_block2a30_PORT_A_data_out, R1_ram_block2a30_clock_0, , , R1_ram_block2a30_clock_enable_0);
R1M1641Q = R1_ram_block2a30_PORT_A_data_out_reg[7];


--R1_ram_block2a29 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29 at M4K_X17_Y2
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = GLOBAL(M1L2);
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29 = R1_ram_block2a29_PORT_A_data_out_reg[0];

--R1M1582Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT1 at M4K_X17_Y2
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = GLOBAL(M1L2);
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1M1582Q = R1_ram_block2a29_PORT_A_data_out_reg[1];

--R1M1583Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT2 at M4K_X17_Y2
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = GLOBAL(M1L2);
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1M1583Q = R1_ram_block2a29_PORT_A_data_out_reg[2];

--R1M1584Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT3 at M4K_X17_Y2
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = GLOBAL(M1L2);
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1M1584Q = R1_ram_block2a29_PORT_A_data_out_reg[3];

--R1M1585Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT4 at M4K_X17_Y2
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = GLOBAL(M1L2);
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1M1585Q = R1_ram_block2a29_PORT_A_data_out_reg[4];

--R1M1586Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT5 at M4K_X17_Y2
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = GLOBAL(M1L2);
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1M1586Q = R1_ram_block2a29_PORT_A_data_out_reg[5];

--R1M1587Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT6 at M4K_X17_Y2
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = GLOBAL(M1L2);
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1M1587Q = R1_ram_block2a29_PORT_A_data_out_reg[6];

--R1M1588Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a29~PORTADATAOUT7 at M4K_X17_Y2
R1_ram_block2a29_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a29_PORT_A_data_in_reg = DFFE(R1_ram_block2a29_PORT_A_data_in, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_data_in = ~GND;
R1_ram_block2a29_PORT_B_data_in_reg = DFFE(R1_ram_block2a29_PORT_B_data_in, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a29_PORT_A_address_reg = DFFE(R1_ram_block2a29_PORT_A_address, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a29_PORT_B_address_reg = DFFE(R1_ram_block2a29_PORT_B_address, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_PORT_A_write_enable = GND;
R1_ram_block2a29_PORT_A_write_enable_reg = DFFE(R1_ram_block2a29_PORT_A_write_enable, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1_ram_block2a29_PORT_B_write_enable = GND;
R1_ram_block2a29_PORT_B_write_enable_reg = DFFE(R1_ram_block2a29_PORT_B_write_enable, R1_ram_block2a29_clock_1, , , R1_ram_block2a29_clock_enable_1);
R1_ram_block2a29_clock_0 = GLOBAL(M1L2);
R1_ram_block2a29_clock_1 = GND;
R1_ram_block2a29_clock_enable_0 = S3_w_anode3189w[3];
R1_ram_block2a29_clock_enable_1 = GND;
R1_ram_block2a29_PORT_A_data_out = MEMORY(R1_ram_block2a29_PORT_A_data_in_reg, R1_ram_block2a29_PORT_B_data_in_reg, R1_ram_block2a29_PORT_A_address_reg, R1_ram_block2a29_PORT_B_address_reg, R1_ram_block2a29_PORT_A_write_enable_reg, R1_ram_block2a29_PORT_B_write_enable_reg, , , R1_ram_block2a29_clock_0, R1_ram_block2a29_clock_1, R1_ram_block2a29_clock_enable_0, R1_ram_block2a29_clock_enable_1, , );
R1_ram_block2a29_PORT_A_data_out_reg = DFFE(R1_ram_block2a29_PORT_A_data_out, R1_ram_block2a29_clock_0, , , R1_ram_block2a29_clock_enable_0);
R1M1588Q = R1_ram_block2a29_PORT_A_data_out_reg[7];


--R1_ram_block2a28 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28 at M4K_X17_Y23
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = GLOBAL(M1L2);
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28 = R1_ram_block2a28_PORT_A_data_out_reg[0];

--R1M1529Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT1 at M4K_X17_Y23
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = GLOBAL(M1L2);
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1M1529Q = R1_ram_block2a28_PORT_A_data_out_reg[1];

--R1M1530Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT2 at M4K_X17_Y23
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = GLOBAL(M1L2);
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1M1530Q = R1_ram_block2a28_PORT_A_data_out_reg[2];

--R1M1531Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT3 at M4K_X17_Y23
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = GLOBAL(M1L2);
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1M1531Q = R1_ram_block2a28_PORT_A_data_out_reg[3];

--R1M1532Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT4 at M4K_X17_Y23
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = GLOBAL(M1L2);
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1M1532Q = R1_ram_block2a28_PORT_A_data_out_reg[4];

--R1M1533Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT5 at M4K_X17_Y23
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = GLOBAL(M1L2);
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1M1533Q = R1_ram_block2a28_PORT_A_data_out_reg[5];

--R1M1534Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT6 at M4K_X17_Y23
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = GLOBAL(M1L2);
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1M1534Q = R1_ram_block2a28_PORT_A_data_out_reg[6];

--R1M1535Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a28~PORTADATAOUT7 at M4K_X17_Y23
R1_ram_block2a28_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a28_PORT_A_data_in_reg = DFFE(R1_ram_block2a28_PORT_A_data_in, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_data_in = ~GND;
R1_ram_block2a28_PORT_B_data_in_reg = DFFE(R1_ram_block2a28_PORT_B_data_in, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a28_PORT_A_address_reg = DFFE(R1_ram_block2a28_PORT_A_address, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a28_PORT_B_address_reg = DFFE(R1_ram_block2a28_PORT_B_address, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_PORT_A_write_enable = GND;
R1_ram_block2a28_PORT_A_write_enable_reg = DFFE(R1_ram_block2a28_PORT_A_write_enable, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1_ram_block2a28_PORT_B_write_enable = GND;
R1_ram_block2a28_PORT_B_write_enable_reg = DFFE(R1_ram_block2a28_PORT_B_write_enable, R1_ram_block2a28_clock_1, , , R1_ram_block2a28_clock_enable_1);
R1_ram_block2a28_clock_0 = GLOBAL(M1L2);
R1_ram_block2a28_clock_1 = GND;
R1_ram_block2a28_clock_enable_0 = S3_w_anode3179w[3];
R1_ram_block2a28_clock_enable_1 = GND;
R1_ram_block2a28_PORT_A_data_out = MEMORY(R1_ram_block2a28_PORT_A_data_in_reg, R1_ram_block2a28_PORT_B_data_in_reg, R1_ram_block2a28_PORT_A_address_reg, R1_ram_block2a28_PORT_B_address_reg, R1_ram_block2a28_PORT_A_write_enable_reg, R1_ram_block2a28_PORT_B_write_enable_reg, , , R1_ram_block2a28_clock_0, R1_ram_block2a28_clock_1, R1_ram_block2a28_clock_enable_0, R1_ram_block2a28_clock_enable_1, , );
R1_ram_block2a28_PORT_A_data_out_reg = DFFE(R1_ram_block2a28_PORT_A_data_out, R1_ram_block2a28_clock_0, , , R1_ram_block2a28_clock_enable_0);
R1M1535Q = R1_ram_block2a28_PORT_A_data_out_reg[7];


--T1L222 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6493w~49 at LCCOMB_X18_Y12_N22
T1L222 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M1586Q) # !R1_address_reg_a[6] & R1M1533Q);


--R1_ram_block2a31 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31 at M4K_X17_Y4
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = GLOBAL(M1L2);
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31 = R1_ram_block2a31_PORT_A_data_out_reg[0];

--R1M1688Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT1 at M4K_X17_Y4
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = GLOBAL(M1L2);
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1M1688Q = R1_ram_block2a31_PORT_A_data_out_reg[1];

--R1M1689Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT2 at M4K_X17_Y4
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = GLOBAL(M1L2);
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1M1689Q = R1_ram_block2a31_PORT_A_data_out_reg[2];

--R1M1690Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT3 at M4K_X17_Y4
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = GLOBAL(M1L2);
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1M1690Q = R1_ram_block2a31_PORT_A_data_out_reg[3];

--R1M1691Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT4 at M4K_X17_Y4
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = GLOBAL(M1L2);
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1M1691Q = R1_ram_block2a31_PORT_A_data_out_reg[4];

--R1M1692Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT5 at M4K_X17_Y4
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = GLOBAL(M1L2);
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1M1692Q = R1_ram_block2a31_PORT_A_data_out_reg[5];

--R1M1693Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT6 at M4K_X17_Y4
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = GLOBAL(M1L2);
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1M1693Q = R1_ram_block2a31_PORT_A_data_out_reg[6];

--R1M1694Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a31~PORTADATAOUT7 at M4K_X17_Y4
R1_ram_block2a31_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a31_PORT_A_data_in_reg = DFFE(R1_ram_block2a31_PORT_A_data_in, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_data_in = ~GND;
R1_ram_block2a31_PORT_B_data_in_reg = DFFE(R1_ram_block2a31_PORT_B_data_in, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a31_PORT_A_address_reg = DFFE(R1_ram_block2a31_PORT_A_address, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a31_PORT_B_address_reg = DFFE(R1_ram_block2a31_PORT_B_address, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_PORT_A_write_enable = GND;
R1_ram_block2a31_PORT_A_write_enable_reg = DFFE(R1_ram_block2a31_PORT_A_write_enable, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1_ram_block2a31_PORT_B_write_enable = GND;
R1_ram_block2a31_PORT_B_write_enable_reg = DFFE(R1_ram_block2a31_PORT_B_write_enable, R1_ram_block2a31_clock_1, , , R1_ram_block2a31_clock_enable_1);
R1_ram_block2a31_clock_0 = GLOBAL(M1L2);
R1_ram_block2a31_clock_1 = GND;
R1_ram_block2a31_clock_enable_0 = S3_w_anode3209w[3];
R1_ram_block2a31_clock_enable_1 = GND;
R1_ram_block2a31_PORT_A_data_out = MEMORY(R1_ram_block2a31_PORT_A_data_in_reg, R1_ram_block2a31_PORT_B_data_in_reg, R1_ram_block2a31_PORT_A_address_reg, R1_ram_block2a31_PORT_B_address_reg, R1_ram_block2a31_PORT_A_write_enable_reg, R1_ram_block2a31_PORT_B_write_enable_reg, , , R1_ram_block2a31_clock_0, R1_ram_block2a31_clock_1, R1_ram_block2a31_clock_enable_0, R1_ram_block2a31_clock_enable_1, , );
R1_ram_block2a31_PORT_A_data_out_reg = DFFE(R1_ram_block2a31_PORT_A_data_out, R1_ram_block2a31_clock_0, , , R1_ram_block2a31_clock_enable_0);
R1M1694Q = R1_ram_block2a31_PORT_A_data_out_reg[7];


--T1L223 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6493w~50 at LCCOMB_X18_Y12_N10
T1L223 = T1L222 & (R1M1692Q # !R1_address_reg_a[7]) # !T1L222 & (R1_address_reg_a[7] & R1M1639Q);


--R1_ram_block2a21 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21 at M4K_X17_Y5
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = GLOBAL(M1L2);
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21 = R1_ram_block2a21_PORT_A_data_out_reg[0];

--R1M1158Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT1 at M4K_X17_Y5
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = GLOBAL(M1L2);
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1M1158Q = R1_ram_block2a21_PORT_A_data_out_reg[1];

--R1M1159Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT2 at M4K_X17_Y5
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = GLOBAL(M1L2);
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1M1159Q = R1_ram_block2a21_PORT_A_data_out_reg[2];

--R1M1160Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT3 at M4K_X17_Y5
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = GLOBAL(M1L2);
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1M1160Q = R1_ram_block2a21_PORT_A_data_out_reg[3];

--R1M1161Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT4 at M4K_X17_Y5
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = GLOBAL(M1L2);
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1M1161Q = R1_ram_block2a21_PORT_A_data_out_reg[4];

--R1M1162Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT5 at M4K_X17_Y5
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = GLOBAL(M1L2);
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1M1162Q = R1_ram_block2a21_PORT_A_data_out_reg[5];

--R1M1163Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT6 at M4K_X17_Y5
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = GLOBAL(M1L2);
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1M1163Q = R1_ram_block2a21_PORT_A_data_out_reg[6];

--R1M1164Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a21~PORTADATAOUT7 at M4K_X17_Y5
R1_ram_block2a21_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a21_PORT_A_data_in_reg = DFFE(R1_ram_block2a21_PORT_A_data_in, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_data_in = ~GND;
R1_ram_block2a21_PORT_B_data_in_reg = DFFE(R1_ram_block2a21_PORT_B_data_in, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a21_PORT_A_address_reg = DFFE(R1_ram_block2a21_PORT_A_address, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a21_PORT_B_address_reg = DFFE(R1_ram_block2a21_PORT_B_address, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_PORT_A_write_enable = GND;
R1_ram_block2a21_PORT_A_write_enable_reg = DFFE(R1_ram_block2a21_PORT_A_write_enable, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1_ram_block2a21_PORT_B_write_enable = GND;
R1_ram_block2a21_PORT_B_write_enable_reg = DFFE(R1_ram_block2a21_PORT_B_write_enable, R1_ram_block2a21_clock_1, , , R1_ram_block2a21_clock_enable_1);
R1_ram_block2a21_clock_0 = GLOBAL(M1L2);
R1_ram_block2a21_clock_1 = GND;
R1_ram_block2a21_clock_enable_0 = S3_w_anode3096w[3];
R1_ram_block2a21_clock_enable_1 = GND;
R1_ram_block2a21_PORT_A_data_out = MEMORY(R1_ram_block2a21_PORT_A_data_in_reg, R1_ram_block2a21_PORT_B_data_in_reg, R1_ram_block2a21_PORT_A_address_reg, R1_ram_block2a21_PORT_B_address_reg, R1_ram_block2a21_PORT_A_write_enable_reg, R1_ram_block2a21_PORT_B_write_enable_reg, , , R1_ram_block2a21_clock_0, R1_ram_block2a21_clock_1, R1_ram_block2a21_clock_enable_0, R1_ram_block2a21_clock_enable_1, , );
R1_ram_block2a21_PORT_A_data_out_reg = DFFE(R1_ram_block2a21_PORT_A_data_out, R1_ram_block2a21_clock_0, , , R1_ram_block2a21_clock_enable_0);
R1M1164Q = R1_ram_block2a21_PORT_A_data_out_reg[7];


--R1_ram_block2a22 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22 at M4K_X17_Y3
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = GLOBAL(M1L2);
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22 = R1_ram_block2a22_PORT_A_data_out_reg[0];

--R1M1211Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT1 at M4K_X17_Y3
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = GLOBAL(M1L2);
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1M1211Q = R1_ram_block2a22_PORT_A_data_out_reg[1];

--R1M1212Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT2 at M4K_X17_Y3
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = GLOBAL(M1L2);
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1M1212Q = R1_ram_block2a22_PORT_A_data_out_reg[2];

--R1M1213Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT3 at M4K_X17_Y3
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = GLOBAL(M1L2);
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1M1213Q = R1_ram_block2a22_PORT_A_data_out_reg[3];

--R1M1214Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT4 at M4K_X17_Y3
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = GLOBAL(M1L2);
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1M1214Q = R1_ram_block2a22_PORT_A_data_out_reg[4];

--R1M1215Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT5 at M4K_X17_Y3
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = GLOBAL(M1L2);
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1M1215Q = R1_ram_block2a22_PORT_A_data_out_reg[5];

--R1M1216Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT6 at M4K_X17_Y3
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = GLOBAL(M1L2);
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1M1216Q = R1_ram_block2a22_PORT_A_data_out_reg[6];

--R1M1217Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a22~PORTADATAOUT7 at M4K_X17_Y3
R1_ram_block2a22_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a22_PORT_A_data_in_reg = DFFE(R1_ram_block2a22_PORT_A_data_in, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_data_in = ~GND;
R1_ram_block2a22_PORT_B_data_in_reg = DFFE(R1_ram_block2a22_PORT_B_data_in, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a22_PORT_A_address_reg = DFFE(R1_ram_block2a22_PORT_A_address, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a22_PORT_B_address_reg = DFFE(R1_ram_block2a22_PORT_B_address, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_PORT_A_write_enable = GND;
R1_ram_block2a22_PORT_A_write_enable_reg = DFFE(R1_ram_block2a22_PORT_A_write_enable, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1_ram_block2a22_PORT_B_write_enable = GND;
R1_ram_block2a22_PORT_B_write_enable_reg = DFFE(R1_ram_block2a22_PORT_B_write_enable, R1_ram_block2a22_clock_1, , , R1_ram_block2a22_clock_enable_1);
R1_ram_block2a22_clock_0 = GLOBAL(M1L2);
R1_ram_block2a22_clock_1 = GND;
R1_ram_block2a22_clock_enable_0 = S3_w_anode3106w[3];
R1_ram_block2a22_clock_enable_1 = GND;
R1_ram_block2a22_PORT_A_data_out = MEMORY(R1_ram_block2a22_PORT_A_data_in_reg, R1_ram_block2a22_PORT_B_data_in_reg, R1_ram_block2a22_PORT_A_address_reg, R1_ram_block2a22_PORT_B_address_reg, R1_ram_block2a22_PORT_A_write_enable_reg, R1_ram_block2a22_PORT_B_write_enable_reg, , , R1_ram_block2a22_clock_0, R1_ram_block2a22_clock_1, R1_ram_block2a22_clock_enable_0, R1_ram_block2a22_clock_enable_1, , );
R1_ram_block2a22_PORT_A_data_out_reg = DFFE(R1_ram_block2a22_PORT_A_data_out, R1_ram_block2a22_clock_0, , , R1_ram_block2a22_clock_enable_0);
R1M1217Q = R1_ram_block2a22_PORT_A_data_out_reg[7];


--R1_ram_block2a20 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20 at M4K_X17_Y9
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = GLOBAL(M1L2);
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20 = R1_ram_block2a20_PORT_A_data_out_reg[0];

--R1M1105Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT1 at M4K_X17_Y9
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = GLOBAL(M1L2);
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1M1105Q = R1_ram_block2a20_PORT_A_data_out_reg[1];

--R1M1106Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT2 at M4K_X17_Y9
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = GLOBAL(M1L2);
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1M1106Q = R1_ram_block2a20_PORT_A_data_out_reg[2];

--R1M1107Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT3 at M4K_X17_Y9
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = GLOBAL(M1L2);
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1M1107Q = R1_ram_block2a20_PORT_A_data_out_reg[3];

--R1M1108Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT4 at M4K_X17_Y9
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = GLOBAL(M1L2);
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1M1108Q = R1_ram_block2a20_PORT_A_data_out_reg[4];

--R1M1109Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT5 at M4K_X17_Y9
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = GLOBAL(M1L2);
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1M1109Q = R1_ram_block2a20_PORT_A_data_out_reg[5];

--R1M1110Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT6 at M4K_X17_Y9
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = GLOBAL(M1L2);
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1M1110Q = R1_ram_block2a20_PORT_A_data_out_reg[6];

--R1M1111Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a20~PORTADATAOUT7 at M4K_X17_Y9
R1_ram_block2a20_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a20_PORT_A_data_in_reg = DFFE(R1_ram_block2a20_PORT_A_data_in, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_data_in = ~GND;
R1_ram_block2a20_PORT_B_data_in_reg = DFFE(R1_ram_block2a20_PORT_B_data_in, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a20_PORT_A_address_reg = DFFE(R1_ram_block2a20_PORT_A_address, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a20_PORT_B_address_reg = DFFE(R1_ram_block2a20_PORT_B_address, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_PORT_A_write_enable = GND;
R1_ram_block2a20_PORT_A_write_enable_reg = DFFE(R1_ram_block2a20_PORT_A_write_enable, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1_ram_block2a20_PORT_B_write_enable = GND;
R1_ram_block2a20_PORT_B_write_enable_reg = DFFE(R1_ram_block2a20_PORT_B_write_enable, R1_ram_block2a20_clock_1, , , R1_ram_block2a20_clock_enable_1);
R1_ram_block2a20_clock_0 = GLOBAL(M1L2);
R1_ram_block2a20_clock_1 = GND;
R1_ram_block2a20_clock_enable_0 = S3_w_anode3086w[3];
R1_ram_block2a20_clock_enable_1 = GND;
R1_ram_block2a20_PORT_A_data_out = MEMORY(R1_ram_block2a20_PORT_A_data_in_reg, R1_ram_block2a20_PORT_B_data_in_reg, R1_ram_block2a20_PORT_A_address_reg, R1_ram_block2a20_PORT_B_address_reg, R1_ram_block2a20_PORT_A_write_enable_reg, R1_ram_block2a20_PORT_B_write_enable_reg, , , R1_ram_block2a20_clock_0, R1_ram_block2a20_clock_1, R1_ram_block2a20_clock_enable_0, R1_ram_block2a20_clock_enable_1, , );
R1_ram_block2a20_PORT_A_data_out_reg = DFFE(R1_ram_block2a20_PORT_A_data_out, R1_ram_block2a20_clock_0, , , R1_ram_block2a20_clock_enable_0);
R1M1111Q = R1_ram_block2a20_PORT_A_data_out_reg[7];


--T1L220 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6491w~44 at LCCOMB_X18_Y12_N30
T1L220 = R1_address_reg_a[7] & (R1M1215Q # R1_address_reg_a[6]) # !R1_address_reg_a[7] & (!R1_address_reg_a[6] & R1M1109Q);


--R1_ram_block2a23 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23 at M4K_X17_Y10
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = GLOBAL(M1L2);
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23 = R1_ram_block2a23_PORT_A_data_out_reg[0];

--R1M1264Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT1 at M4K_X17_Y10
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = GLOBAL(M1L2);
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1M1264Q = R1_ram_block2a23_PORT_A_data_out_reg[1];

--R1M1265Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT2 at M4K_X17_Y10
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = GLOBAL(M1L2);
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1M1265Q = R1_ram_block2a23_PORT_A_data_out_reg[2];

--R1M1266Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT3 at M4K_X17_Y10
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = GLOBAL(M1L2);
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1M1266Q = R1_ram_block2a23_PORT_A_data_out_reg[3];

--R1M1267Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT4 at M4K_X17_Y10
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = GLOBAL(M1L2);
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1M1267Q = R1_ram_block2a23_PORT_A_data_out_reg[4];

--R1M1268Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT5 at M4K_X17_Y10
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = GLOBAL(M1L2);
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1M1268Q = R1_ram_block2a23_PORT_A_data_out_reg[5];

--R1M1269Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT6 at M4K_X17_Y10
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = GLOBAL(M1L2);
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1M1269Q = R1_ram_block2a23_PORT_A_data_out_reg[6];

--R1M1270Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a23~PORTADATAOUT7 at M4K_X17_Y10
R1_ram_block2a23_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a23_PORT_A_data_in_reg = DFFE(R1_ram_block2a23_PORT_A_data_in, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_data_in = ~GND;
R1_ram_block2a23_PORT_B_data_in_reg = DFFE(R1_ram_block2a23_PORT_B_data_in, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a23_PORT_A_address_reg = DFFE(R1_ram_block2a23_PORT_A_address, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a23_PORT_B_address_reg = DFFE(R1_ram_block2a23_PORT_B_address, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_PORT_A_write_enable = GND;
R1_ram_block2a23_PORT_A_write_enable_reg = DFFE(R1_ram_block2a23_PORT_A_write_enable, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1_ram_block2a23_PORT_B_write_enable = GND;
R1_ram_block2a23_PORT_B_write_enable_reg = DFFE(R1_ram_block2a23_PORT_B_write_enable, R1_ram_block2a23_clock_1, , , R1_ram_block2a23_clock_enable_1);
R1_ram_block2a23_clock_0 = GLOBAL(M1L2);
R1_ram_block2a23_clock_1 = GND;
R1_ram_block2a23_clock_enable_0 = S3_w_anode3116w[3];
R1_ram_block2a23_clock_enable_1 = GND;
R1_ram_block2a23_PORT_A_data_out = MEMORY(R1_ram_block2a23_PORT_A_data_in_reg, R1_ram_block2a23_PORT_B_data_in_reg, R1_ram_block2a23_PORT_A_address_reg, R1_ram_block2a23_PORT_B_address_reg, R1_ram_block2a23_PORT_A_write_enable_reg, R1_ram_block2a23_PORT_B_write_enable_reg, , , R1_ram_block2a23_clock_0, R1_ram_block2a23_clock_1, R1_ram_block2a23_clock_enable_0, R1_ram_block2a23_clock_enable_1, , );
R1_ram_block2a23_PORT_A_data_out_reg = DFFE(R1_ram_block2a23_PORT_A_data_out, R1_ram_block2a23_clock_0, , , R1_ram_block2a23_clock_enable_0);
R1M1270Q = R1_ram_block2a23_PORT_A_data_out_reg[7];


--T1L221 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6491w~45 at LCCOMB_X18_Y12_N12
T1L221 = T1L220 & (R1M1268Q # !R1_address_reg_a[6]) # !T1L220 & R1M1162Q & R1_address_reg_a[6];


--T1L49 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5034 at LCCOMB_X18_Y12_N4
T1L49 = R1_address_reg_a[9] & T1L223 # !R1_address_reg_a[9] & (T1L221);


--R1_ram_block2a17 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17 at M4K_X17_Y14
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = GLOBAL(M1L2);
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17 = R1_ram_block2a17_PORT_A_data_out_reg[0];

--R1M946Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT1 at M4K_X17_Y14
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = GLOBAL(M1L2);
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1M946Q = R1_ram_block2a17_PORT_A_data_out_reg[1];

--R1M947Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT2 at M4K_X17_Y14
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = GLOBAL(M1L2);
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1M947Q = R1_ram_block2a17_PORT_A_data_out_reg[2];

--R1M948Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT3 at M4K_X17_Y14
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = GLOBAL(M1L2);
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1M948Q = R1_ram_block2a17_PORT_A_data_out_reg[3];

--R1M949Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT4 at M4K_X17_Y14
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = GLOBAL(M1L2);
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1M949Q = R1_ram_block2a17_PORT_A_data_out_reg[4];

--R1M950Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT5 at M4K_X17_Y14
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = GLOBAL(M1L2);
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1M950Q = R1_ram_block2a17_PORT_A_data_out_reg[5];

--R1M951Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT6 at M4K_X17_Y14
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = GLOBAL(M1L2);
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1M951Q = R1_ram_block2a17_PORT_A_data_out_reg[6];

--R1M952Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a17~PORTADATAOUT7 at M4K_X17_Y14
R1_ram_block2a17_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a17_PORT_A_data_in_reg = DFFE(R1_ram_block2a17_PORT_A_data_in, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_data_in = ~GND;
R1_ram_block2a17_PORT_B_data_in_reg = DFFE(R1_ram_block2a17_PORT_B_data_in, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a17_PORT_A_address_reg = DFFE(R1_ram_block2a17_PORT_A_address, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a17_PORT_B_address_reg = DFFE(R1_ram_block2a17_PORT_B_address, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_PORT_A_write_enable = GND;
R1_ram_block2a17_PORT_A_write_enable_reg = DFFE(R1_ram_block2a17_PORT_A_write_enable, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1_ram_block2a17_PORT_B_write_enable = GND;
R1_ram_block2a17_PORT_B_write_enable_reg = DFFE(R1_ram_block2a17_PORT_B_write_enable, R1_ram_block2a17_clock_1, , , R1_ram_block2a17_clock_enable_1);
R1_ram_block2a17_clock_0 = GLOBAL(M1L2);
R1_ram_block2a17_clock_1 = GND;
R1_ram_block2a17_clock_enable_0 = S3_w_anode3056w[3];
R1_ram_block2a17_clock_enable_1 = GND;
R1_ram_block2a17_PORT_A_data_out = MEMORY(R1_ram_block2a17_PORT_A_data_in_reg, R1_ram_block2a17_PORT_B_data_in_reg, R1_ram_block2a17_PORT_A_address_reg, R1_ram_block2a17_PORT_B_address_reg, R1_ram_block2a17_PORT_A_write_enable_reg, R1_ram_block2a17_PORT_B_write_enable_reg, , , R1_ram_block2a17_clock_0, R1_ram_block2a17_clock_1, R1_ram_block2a17_clock_enable_0, R1_ram_block2a17_clock_enable_1, , );
R1_ram_block2a17_PORT_A_data_out_reg = DFFE(R1_ram_block2a17_PORT_A_data_out, R1_ram_block2a17_clock_0, , , R1_ram_block2a17_clock_enable_0);
R1M952Q = R1_ram_block2a17_PORT_A_data_out_reg[7];


--R1_ram_block2a18 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18 at M4K_X17_Y13
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = GLOBAL(M1L2);
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18 = R1_ram_block2a18_PORT_A_data_out_reg[0];

--R1M999Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT1 at M4K_X17_Y13
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = GLOBAL(M1L2);
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1M999Q = R1_ram_block2a18_PORT_A_data_out_reg[1];

--R1M1000Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT2 at M4K_X17_Y13
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = GLOBAL(M1L2);
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1M1000Q = R1_ram_block2a18_PORT_A_data_out_reg[2];

--R1M1001Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT3 at M4K_X17_Y13
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = GLOBAL(M1L2);
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1M1001Q = R1_ram_block2a18_PORT_A_data_out_reg[3];

--R1M1002Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT4 at M4K_X17_Y13
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = GLOBAL(M1L2);
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1M1002Q = R1_ram_block2a18_PORT_A_data_out_reg[4];

--R1M1003Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT5 at M4K_X17_Y13
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = GLOBAL(M1L2);
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1M1003Q = R1_ram_block2a18_PORT_A_data_out_reg[5];

--R1M1004Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT6 at M4K_X17_Y13
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = GLOBAL(M1L2);
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1M1004Q = R1_ram_block2a18_PORT_A_data_out_reg[6];

--R1M1005Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a18~PORTADATAOUT7 at M4K_X17_Y13
R1_ram_block2a18_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a18_PORT_A_data_in_reg = DFFE(R1_ram_block2a18_PORT_A_data_in, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_data_in = ~GND;
R1_ram_block2a18_PORT_B_data_in_reg = DFFE(R1_ram_block2a18_PORT_B_data_in, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a18_PORT_A_address_reg = DFFE(R1_ram_block2a18_PORT_A_address, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a18_PORT_B_address_reg = DFFE(R1_ram_block2a18_PORT_B_address, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_PORT_A_write_enable = GND;
R1_ram_block2a18_PORT_A_write_enable_reg = DFFE(R1_ram_block2a18_PORT_A_write_enable, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1_ram_block2a18_PORT_B_write_enable = GND;
R1_ram_block2a18_PORT_B_write_enable_reg = DFFE(R1_ram_block2a18_PORT_B_write_enable, R1_ram_block2a18_clock_1, , , R1_ram_block2a18_clock_enable_1);
R1_ram_block2a18_clock_0 = GLOBAL(M1L2);
R1_ram_block2a18_clock_1 = GND;
R1_ram_block2a18_clock_enable_0 = S3_w_anode3066w[3];
R1_ram_block2a18_clock_enable_1 = GND;
R1_ram_block2a18_PORT_A_data_out = MEMORY(R1_ram_block2a18_PORT_A_data_in_reg, R1_ram_block2a18_PORT_B_data_in_reg, R1_ram_block2a18_PORT_A_address_reg, R1_ram_block2a18_PORT_B_address_reg, R1_ram_block2a18_PORT_A_write_enable_reg, R1_ram_block2a18_PORT_B_write_enable_reg, , , R1_ram_block2a18_clock_0, R1_ram_block2a18_clock_1, R1_ram_block2a18_clock_enable_0, R1_ram_block2a18_clock_enable_1, , );
R1_ram_block2a18_PORT_A_data_out_reg = DFFE(R1_ram_block2a18_PORT_A_data_out, R1_ram_block2a18_clock_0, , , R1_ram_block2a18_clock_enable_0);
R1M1005Q = R1_ram_block2a18_PORT_A_data_out_reg[7];


--R1_ram_block2a16 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16 at M4K_X17_Y12
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = GLOBAL(M1L2);
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16 = R1_ram_block2a16_PORT_A_data_out_reg[0];

--R1M893Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT1 at M4K_X17_Y12
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = GLOBAL(M1L2);
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1M893Q = R1_ram_block2a16_PORT_A_data_out_reg[1];

--R1M894Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT2 at M4K_X17_Y12
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = GLOBAL(M1L2);
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1M894Q = R1_ram_block2a16_PORT_A_data_out_reg[2];

--R1M895Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT3 at M4K_X17_Y12
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = GLOBAL(M1L2);
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1M895Q = R1_ram_block2a16_PORT_A_data_out_reg[3];

--R1M896Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT4 at M4K_X17_Y12
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = GLOBAL(M1L2);
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1M896Q = R1_ram_block2a16_PORT_A_data_out_reg[4];

--R1M897Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT5 at M4K_X17_Y12
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = GLOBAL(M1L2);
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1M897Q = R1_ram_block2a16_PORT_A_data_out_reg[5];

--R1M898Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT6 at M4K_X17_Y12
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = GLOBAL(M1L2);
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1M898Q = R1_ram_block2a16_PORT_A_data_out_reg[6];

--R1M899Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a16~PORTADATAOUT7 at M4K_X17_Y12
R1_ram_block2a16_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a16_PORT_A_data_in_reg = DFFE(R1_ram_block2a16_PORT_A_data_in, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_data_in = ~GND;
R1_ram_block2a16_PORT_B_data_in_reg = DFFE(R1_ram_block2a16_PORT_B_data_in, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a16_PORT_A_address_reg = DFFE(R1_ram_block2a16_PORT_A_address, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a16_PORT_B_address_reg = DFFE(R1_ram_block2a16_PORT_B_address, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_PORT_A_write_enable = GND;
R1_ram_block2a16_PORT_A_write_enable_reg = DFFE(R1_ram_block2a16_PORT_A_write_enable, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1_ram_block2a16_PORT_B_write_enable = GND;
R1_ram_block2a16_PORT_B_write_enable_reg = DFFE(R1_ram_block2a16_PORT_B_write_enable, R1_ram_block2a16_clock_1, , , R1_ram_block2a16_clock_enable_1);
R1_ram_block2a16_clock_0 = GLOBAL(M1L2);
R1_ram_block2a16_clock_1 = GND;
R1_ram_block2a16_clock_enable_0 = S3_w_anode3045w[3];
R1_ram_block2a16_clock_enable_1 = GND;
R1_ram_block2a16_PORT_A_data_out = MEMORY(R1_ram_block2a16_PORT_A_data_in_reg, R1_ram_block2a16_PORT_B_data_in_reg, R1_ram_block2a16_PORT_A_address_reg, R1_ram_block2a16_PORT_B_address_reg, R1_ram_block2a16_PORT_A_write_enable_reg, R1_ram_block2a16_PORT_B_write_enable_reg, , , R1_ram_block2a16_clock_0, R1_ram_block2a16_clock_1, R1_ram_block2a16_clock_enable_0, R1_ram_block2a16_clock_enable_1, , );
R1_ram_block2a16_PORT_A_data_out_reg = DFFE(R1_ram_block2a16_PORT_A_data_out, R1_ram_block2a16_clock_0, , , R1_ram_block2a16_clock_enable_0);
R1M899Q = R1_ram_block2a16_PORT_A_data_out_reg[7];


--T1L224 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6575w~407 at LCCOMB_X18_Y12_N26
T1L224 = R1_address_reg_a[7] & (R1M1003Q # R1_address_reg_a[6]) # !R1_address_reg_a[7] & (!R1_address_reg_a[6] & R1M897Q);


--R1_ram_block2a19 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19 at M4K_X17_Y7
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = GLOBAL(M1L2);
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19 = R1_ram_block2a19_PORT_A_data_out_reg[0];

--R1M1052Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT1 at M4K_X17_Y7
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = GLOBAL(M1L2);
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1M1052Q = R1_ram_block2a19_PORT_A_data_out_reg[1];

--R1M1053Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT2 at M4K_X17_Y7
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = GLOBAL(M1L2);
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1M1053Q = R1_ram_block2a19_PORT_A_data_out_reg[2];

--R1M1054Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT3 at M4K_X17_Y7
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = GLOBAL(M1L2);
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1M1054Q = R1_ram_block2a19_PORT_A_data_out_reg[3];

--R1M1055Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT4 at M4K_X17_Y7
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = GLOBAL(M1L2);
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1M1055Q = R1_ram_block2a19_PORT_A_data_out_reg[4];

--R1M1056Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT5 at M4K_X17_Y7
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = GLOBAL(M1L2);
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1M1056Q = R1_ram_block2a19_PORT_A_data_out_reg[5];

--R1M1057Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT6 at M4K_X17_Y7
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = GLOBAL(M1L2);
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1M1057Q = R1_ram_block2a19_PORT_A_data_out_reg[6];

--R1M1058Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a19~PORTADATAOUT7 at M4K_X17_Y7
R1_ram_block2a19_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a19_PORT_A_data_in_reg = DFFE(R1_ram_block2a19_PORT_A_data_in, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_data_in = ~GND;
R1_ram_block2a19_PORT_B_data_in_reg = DFFE(R1_ram_block2a19_PORT_B_data_in, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a19_PORT_A_address_reg = DFFE(R1_ram_block2a19_PORT_A_address, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a19_PORT_B_address_reg = DFFE(R1_ram_block2a19_PORT_B_address, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_PORT_A_write_enable = GND;
R1_ram_block2a19_PORT_A_write_enable_reg = DFFE(R1_ram_block2a19_PORT_A_write_enable, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1_ram_block2a19_PORT_B_write_enable = GND;
R1_ram_block2a19_PORT_B_write_enable_reg = DFFE(R1_ram_block2a19_PORT_B_write_enable, R1_ram_block2a19_clock_1, , , R1_ram_block2a19_clock_enable_1);
R1_ram_block2a19_clock_0 = GLOBAL(M1L2);
R1_ram_block2a19_clock_1 = GND;
R1_ram_block2a19_clock_enable_0 = S3_w_anode3076w[3];
R1_ram_block2a19_clock_enable_1 = GND;
R1_ram_block2a19_PORT_A_data_out = MEMORY(R1_ram_block2a19_PORT_A_data_in_reg, R1_ram_block2a19_PORT_B_data_in_reg, R1_ram_block2a19_PORT_A_address_reg, R1_ram_block2a19_PORT_B_address_reg, R1_ram_block2a19_PORT_A_write_enable_reg, R1_ram_block2a19_PORT_B_write_enable_reg, , , R1_ram_block2a19_clock_0, R1_ram_block2a19_clock_1, R1_ram_block2a19_clock_enable_0, R1_ram_block2a19_clock_enable_1, , );
R1_ram_block2a19_PORT_A_data_out_reg = DFFE(R1_ram_block2a19_PORT_A_data_out, R1_ram_block2a19_clock_0, , , R1_ram_block2a19_clock_enable_0);
R1M1058Q = R1_ram_block2a19_PORT_A_data_out_reg[7];


--T1L225 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6575w~408 at LCCOMB_X18_Y12_N18
T1L225 = R1_address_reg_a[6] & (T1L224 & R1M1056Q # !T1L224 & (R1M950Q)) # !R1_address_reg_a[6] & T1L224;


--R1_ram_block2a27 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27 at M4K_X17_Y8
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = GLOBAL(M1L2);
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27 = R1_ram_block2a27_PORT_A_data_out_reg[0];

--R1M1476Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT1 at M4K_X17_Y8
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = GLOBAL(M1L2);
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1M1476Q = R1_ram_block2a27_PORT_A_data_out_reg[1];

--R1M1477Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT2 at M4K_X17_Y8
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = GLOBAL(M1L2);
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1M1477Q = R1_ram_block2a27_PORT_A_data_out_reg[2];

--R1M1478Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT3 at M4K_X17_Y8
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = GLOBAL(M1L2);
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1M1478Q = R1_ram_block2a27_PORT_A_data_out_reg[3];

--R1M1479Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT4 at M4K_X17_Y8
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = GLOBAL(M1L2);
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1M1479Q = R1_ram_block2a27_PORT_A_data_out_reg[4];

--R1M1480Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT5 at M4K_X17_Y8
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = GLOBAL(M1L2);
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1M1480Q = R1_ram_block2a27_PORT_A_data_out_reg[5];

--R1M1481Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT6 at M4K_X17_Y8
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = GLOBAL(M1L2);
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1M1481Q = R1_ram_block2a27_PORT_A_data_out_reg[6];

--R1M1482Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a27~PORTADATAOUT7 at M4K_X17_Y8
R1_ram_block2a27_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a27_PORT_A_data_in_reg = DFFE(R1_ram_block2a27_PORT_A_data_in, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_data_in = ~GND;
R1_ram_block2a27_PORT_B_data_in_reg = DFFE(R1_ram_block2a27_PORT_B_data_in, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a27_PORT_A_address_reg = DFFE(R1_ram_block2a27_PORT_A_address, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a27_PORT_B_address_reg = DFFE(R1_ram_block2a27_PORT_B_address, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_PORT_A_write_enable = GND;
R1_ram_block2a27_PORT_A_write_enable_reg = DFFE(R1_ram_block2a27_PORT_A_write_enable, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1_ram_block2a27_PORT_B_write_enable = GND;
R1_ram_block2a27_PORT_B_write_enable_reg = DFFE(R1_ram_block2a27_PORT_B_write_enable, R1_ram_block2a27_clock_1, , , R1_ram_block2a27_clock_enable_1);
R1_ram_block2a27_clock_0 = GLOBAL(M1L2);
R1_ram_block2a27_clock_1 = GND;
R1_ram_block2a27_clock_enable_0 = S3_w_anode3169w[3];
R1_ram_block2a27_clock_enable_1 = GND;
R1_ram_block2a27_PORT_A_data_out = MEMORY(R1_ram_block2a27_PORT_A_data_in_reg, R1_ram_block2a27_PORT_B_data_in_reg, R1_ram_block2a27_PORT_A_address_reg, R1_ram_block2a27_PORT_B_address_reg, R1_ram_block2a27_PORT_A_write_enable_reg, R1_ram_block2a27_PORT_B_write_enable_reg, , , R1_ram_block2a27_clock_0, R1_ram_block2a27_clock_1, R1_ram_block2a27_clock_enable_0, R1_ram_block2a27_clock_enable_1, , );
R1_ram_block2a27_PORT_A_data_out_reg = DFFE(R1_ram_block2a27_PORT_A_data_out, R1_ram_block2a27_clock_0, , , R1_ram_block2a27_clock_enable_0);
R1M1482Q = R1_ram_block2a27_PORT_A_data_out_reg[7];


--R1_ram_block2a26 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26 at M4K_X17_Y11
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = GLOBAL(M1L2);
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26 = R1_ram_block2a26_PORT_A_data_out_reg[0];

--R1M1423Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT1 at M4K_X17_Y11
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = GLOBAL(M1L2);
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1M1423Q = R1_ram_block2a26_PORT_A_data_out_reg[1];

--R1M1424Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT2 at M4K_X17_Y11
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = GLOBAL(M1L2);
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1M1424Q = R1_ram_block2a26_PORT_A_data_out_reg[2];

--R1M1425Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT3 at M4K_X17_Y11
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = GLOBAL(M1L2);
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1M1425Q = R1_ram_block2a26_PORT_A_data_out_reg[3];

--R1M1426Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT4 at M4K_X17_Y11
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = GLOBAL(M1L2);
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1M1426Q = R1_ram_block2a26_PORT_A_data_out_reg[4];

--R1M1427Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT5 at M4K_X17_Y11
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = GLOBAL(M1L2);
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1M1427Q = R1_ram_block2a26_PORT_A_data_out_reg[5];

--R1M1428Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT6 at M4K_X17_Y11
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = GLOBAL(M1L2);
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1M1428Q = R1_ram_block2a26_PORT_A_data_out_reg[6];

--R1M1429Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a26~PORTADATAOUT7 at M4K_X17_Y11
R1_ram_block2a26_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a26_PORT_A_data_in_reg = DFFE(R1_ram_block2a26_PORT_A_data_in, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_data_in = ~GND;
R1_ram_block2a26_PORT_B_data_in_reg = DFFE(R1_ram_block2a26_PORT_B_data_in, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a26_PORT_A_address_reg = DFFE(R1_ram_block2a26_PORT_A_address, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a26_PORT_B_address_reg = DFFE(R1_ram_block2a26_PORT_B_address, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_PORT_A_write_enable = GND;
R1_ram_block2a26_PORT_A_write_enable_reg = DFFE(R1_ram_block2a26_PORT_A_write_enable, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1_ram_block2a26_PORT_B_write_enable = GND;
R1_ram_block2a26_PORT_B_write_enable_reg = DFFE(R1_ram_block2a26_PORT_B_write_enable, R1_ram_block2a26_clock_1, , , R1_ram_block2a26_clock_enable_1);
R1_ram_block2a26_clock_0 = GLOBAL(M1L2);
R1_ram_block2a26_clock_1 = GND;
R1_ram_block2a26_clock_enable_0 = S3_w_anode3159w[3];
R1_ram_block2a26_clock_enable_1 = GND;
R1_ram_block2a26_PORT_A_data_out = MEMORY(R1_ram_block2a26_PORT_A_data_in_reg, R1_ram_block2a26_PORT_B_data_in_reg, R1_ram_block2a26_PORT_A_address_reg, R1_ram_block2a26_PORT_B_address_reg, R1_ram_block2a26_PORT_A_write_enable_reg, R1_ram_block2a26_PORT_B_write_enable_reg, , , R1_ram_block2a26_clock_0, R1_ram_block2a26_clock_1, R1_ram_block2a26_clock_enable_0, R1_ram_block2a26_clock_enable_1, , );
R1_ram_block2a26_PORT_A_data_out_reg = DFFE(R1_ram_block2a26_PORT_A_data_out, R1_ram_block2a26_clock_0, , , R1_ram_block2a26_clock_enable_0);
R1M1429Q = R1_ram_block2a26_PORT_A_data_out_reg[7];


--T1L50 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5035 at LCCOMB_X18_Y12_N2
T1L50 = R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M1480Q) # !R1_address_reg_a[6] & R1M1427Q);


--R1_ram_block2a25 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25 at M4K_X17_Y16
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = GLOBAL(M1L2);
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25 = R1_ram_block2a25_PORT_A_data_out_reg[0];

--R1M1370Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT1 at M4K_X17_Y16
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = GLOBAL(M1L2);
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1M1370Q = R1_ram_block2a25_PORT_A_data_out_reg[1];

--R1M1371Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT2 at M4K_X17_Y16
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = GLOBAL(M1L2);
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1M1371Q = R1_ram_block2a25_PORT_A_data_out_reg[2];

--R1M1372Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT3 at M4K_X17_Y16
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = GLOBAL(M1L2);
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1M1372Q = R1_ram_block2a25_PORT_A_data_out_reg[3];

--R1M1373Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT4 at M4K_X17_Y16
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = GLOBAL(M1L2);
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1M1373Q = R1_ram_block2a25_PORT_A_data_out_reg[4];

--R1M1374Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT5 at M4K_X17_Y16
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = GLOBAL(M1L2);
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1M1374Q = R1_ram_block2a25_PORT_A_data_out_reg[5];

--R1M1375Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT6 at M4K_X17_Y16
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = GLOBAL(M1L2);
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1M1375Q = R1_ram_block2a25_PORT_A_data_out_reg[6];

--R1M1376Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a25~PORTADATAOUT7 at M4K_X17_Y16
R1_ram_block2a25_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a25_PORT_A_data_in_reg = DFFE(R1_ram_block2a25_PORT_A_data_in, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_data_in = ~GND;
R1_ram_block2a25_PORT_B_data_in_reg = DFFE(R1_ram_block2a25_PORT_B_data_in, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a25_PORT_A_address_reg = DFFE(R1_ram_block2a25_PORT_A_address, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a25_PORT_B_address_reg = DFFE(R1_ram_block2a25_PORT_B_address, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_PORT_A_write_enable = GND;
R1_ram_block2a25_PORT_A_write_enable_reg = DFFE(R1_ram_block2a25_PORT_A_write_enable, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1_ram_block2a25_PORT_B_write_enable = GND;
R1_ram_block2a25_PORT_B_write_enable_reg = DFFE(R1_ram_block2a25_PORT_B_write_enable, R1_ram_block2a25_clock_1, , , R1_ram_block2a25_clock_enable_1);
R1_ram_block2a25_clock_0 = GLOBAL(M1L2);
R1_ram_block2a25_clock_1 = GND;
R1_ram_block2a25_clock_enable_0 = S3_w_anode3149w[3];
R1_ram_block2a25_clock_enable_1 = GND;
R1_ram_block2a25_PORT_A_data_out = MEMORY(R1_ram_block2a25_PORT_A_data_in_reg, R1_ram_block2a25_PORT_B_data_in_reg, R1_ram_block2a25_PORT_A_address_reg, R1_ram_block2a25_PORT_B_address_reg, R1_ram_block2a25_PORT_A_write_enable_reg, R1_ram_block2a25_PORT_B_write_enable_reg, , , R1_ram_block2a25_clock_0, R1_ram_block2a25_clock_1, R1_ram_block2a25_clock_enable_0, R1_ram_block2a25_clock_enable_1, , );
R1_ram_block2a25_PORT_A_data_out_reg = DFFE(R1_ram_block2a25_PORT_A_data_out, R1_ram_block2a25_clock_0, , , R1_ram_block2a25_clock_enable_0);
R1M1376Q = R1_ram_block2a25_PORT_A_data_out_reg[7];


--R1_ram_block2a24 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24 at M4K_X17_Y15
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = GLOBAL(M1L2);
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24 = R1_ram_block2a24_PORT_A_data_out_reg[0];

--R1M1317Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT1 at M4K_X17_Y15
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = GLOBAL(M1L2);
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1M1317Q = R1_ram_block2a24_PORT_A_data_out_reg[1];

--R1M1318Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT2 at M4K_X17_Y15
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = GLOBAL(M1L2);
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1M1318Q = R1_ram_block2a24_PORT_A_data_out_reg[2];

--R1M1319Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT3 at M4K_X17_Y15
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = GLOBAL(M1L2);
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1M1319Q = R1_ram_block2a24_PORT_A_data_out_reg[3];

--R1M1320Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT4 at M4K_X17_Y15
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = GLOBAL(M1L2);
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1M1320Q = R1_ram_block2a24_PORT_A_data_out_reg[4];

--R1M1321Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT5 at M4K_X17_Y15
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = GLOBAL(M1L2);
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1M1321Q = R1_ram_block2a24_PORT_A_data_out_reg[5];

--R1M1322Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT6 at M4K_X17_Y15
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = GLOBAL(M1L2);
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1M1322Q = R1_ram_block2a24_PORT_A_data_out_reg[6];

--R1M1323Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a24~PORTADATAOUT7 at M4K_X17_Y15
R1_ram_block2a24_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a24_PORT_A_data_in_reg = DFFE(R1_ram_block2a24_PORT_A_data_in, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_data_in = ~GND;
R1_ram_block2a24_PORT_B_data_in_reg = DFFE(R1_ram_block2a24_PORT_B_data_in, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a24_PORT_A_address_reg = DFFE(R1_ram_block2a24_PORT_A_address, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a24_PORT_B_address_reg = DFFE(R1_ram_block2a24_PORT_B_address, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_PORT_A_write_enable = GND;
R1_ram_block2a24_PORT_A_write_enable_reg = DFFE(R1_ram_block2a24_PORT_A_write_enable, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1_ram_block2a24_PORT_B_write_enable = GND;
R1_ram_block2a24_PORT_B_write_enable_reg = DFFE(R1_ram_block2a24_PORT_B_write_enable, R1_ram_block2a24_clock_1, , , R1_ram_block2a24_clock_enable_1);
R1_ram_block2a24_clock_0 = GLOBAL(M1L2);
R1_ram_block2a24_clock_1 = GND;
R1_ram_block2a24_clock_enable_0 = S3_w_anode3138w[3];
R1_ram_block2a24_clock_enable_1 = GND;
R1_ram_block2a24_PORT_A_data_out = MEMORY(R1_ram_block2a24_PORT_A_data_in_reg, R1_ram_block2a24_PORT_B_data_in_reg, R1_ram_block2a24_PORT_A_address_reg, R1_ram_block2a24_PORT_B_address_reg, R1_ram_block2a24_PORT_A_write_enable_reg, R1_ram_block2a24_PORT_B_write_enable_reg, , , R1_ram_block2a24_clock_0, R1_ram_block2a24_clock_1, R1_ram_block2a24_clock_enable_0, R1_ram_block2a24_clock_enable_1, , );
R1_ram_block2a24_PORT_A_data_out_reg = DFFE(R1_ram_block2a24_PORT_A_data_out, R1_ram_block2a24_clock_0, , , R1_ram_block2a24_clock_enable_0);
R1M1323Q = R1_ram_block2a24_PORT_A_data_out_reg[7];


--T1L51 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5036 at LCCOMB_X18_Y12_N6
T1L51 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1374Q # !R1_address_reg_a[6] & (R1M1321Q));


--T1L52 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5037 at LCCOMB_X18_Y12_N28
T1L52 = R1_address_reg_a[9] & (T1L51 # T1L50) # !R1_address_reg_a[9] & (T1L225);


--T1L53 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5038 at LCCOMB_X18_Y12_N24
T1L53 = R1_address_reg_a[8] & T1L49 # !R1_address_reg_a[8] & (T1L52);


--R1_address_reg_a[11] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[11] at LCFF_X38_Y12_N23
R1_address_reg_a[11] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(M1L2),  ,  ,  , R1_address_reg_a[5],  ,  , VCC);


--R1_address_reg_a[10] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[10] at LCFF_X38_Y12_N27
R1_address_reg_a[10] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(M1L2),  ,  ,  , R1_address_reg_a[4],  ,  , VCC);


--T1L147 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~608 at LCCOMB_X38_Y12_N26
T1L147 = R1_address_reg_a[11] & R1_address_reg_a[10];


--T1L232 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~573 at LCCOMB_X38_Y12_N28
T1L232 = R1_address_reg_a[8] & !R1_address_reg_a[10];


--R1_ram_block2a46 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46 at M4K_X41_Y1
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = GLOBAL(M1L2);
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46 = R1_ram_block2a46_PORT_A_data_out_reg[0];

--R1M2483Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT1 at M4K_X41_Y1
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = GLOBAL(M1L2);
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1M2483Q = R1_ram_block2a46_PORT_A_data_out_reg[1];

--R1M2484Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT2 at M4K_X41_Y1
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = GLOBAL(M1L2);
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1M2484Q = R1_ram_block2a46_PORT_A_data_out_reg[2];

--R1M2485Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT3 at M4K_X41_Y1
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = GLOBAL(M1L2);
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1M2485Q = R1_ram_block2a46_PORT_A_data_out_reg[3];

--R1M2486Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT4 at M4K_X41_Y1
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = GLOBAL(M1L2);
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1M2486Q = R1_ram_block2a46_PORT_A_data_out_reg[4];

--R1M2487Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT5 at M4K_X41_Y1
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = GLOBAL(M1L2);
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1M2487Q = R1_ram_block2a46_PORT_A_data_out_reg[5];

--R1M2488Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT6 at M4K_X41_Y1
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = GLOBAL(M1L2);
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1M2488Q = R1_ram_block2a46_PORT_A_data_out_reg[6];

--R1M2489Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a46~PORTADATAOUT7 at M4K_X41_Y1
R1_ram_block2a46_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a46_PORT_A_data_in_reg = DFFE(R1_ram_block2a46_PORT_A_data_in, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_data_in = ~GND;
R1_ram_block2a46_PORT_B_data_in_reg = DFFE(R1_ram_block2a46_PORT_B_data_in, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a46_PORT_A_address_reg = DFFE(R1_ram_block2a46_PORT_A_address, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a46_PORT_B_address_reg = DFFE(R1_ram_block2a46_PORT_B_address, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_PORT_A_write_enable = GND;
R1_ram_block2a46_PORT_A_write_enable_reg = DFFE(R1_ram_block2a46_PORT_A_write_enable, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1_ram_block2a46_PORT_B_write_enable = GND;
R1_ram_block2a46_PORT_B_write_enable_reg = DFFE(R1_ram_block2a46_PORT_B_write_enable, R1_ram_block2a46_clock_1, , , R1_ram_block2a46_clock_enable_1);
R1_ram_block2a46_clock_0 = GLOBAL(M1L2);
R1_ram_block2a46_clock_1 = GND;
R1_ram_block2a46_clock_enable_0 = S3_w_anode3385w[3];
R1_ram_block2a46_clock_enable_1 = GND;
R1_ram_block2a46_PORT_A_data_out = MEMORY(R1_ram_block2a46_PORT_A_data_in_reg, R1_ram_block2a46_PORT_B_data_in_reg, R1_ram_block2a46_PORT_A_address_reg, R1_ram_block2a46_PORT_B_address_reg, R1_ram_block2a46_PORT_A_write_enable_reg, R1_ram_block2a46_PORT_B_write_enable_reg, , , R1_ram_block2a46_clock_0, R1_ram_block2a46_clock_1, R1_ram_block2a46_clock_enable_0, R1_ram_block2a46_clock_enable_1, , );
R1_ram_block2a46_PORT_A_data_out_reg = DFFE(R1_ram_block2a46_PORT_A_data_out, R1_ram_block2a46_clock_0, , , R1_ram_block2a46_clock_enable_0);
R1M2489Q = R1_ram_block2a46_PORT_A_data_out_reg[7];


--R1_ram_block2a45 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45 at M4K_X41_Y12
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = GLOBAL(M1L2);
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45 = R1_ram_block2a45_PORT_A_data_out_reg[0];

--R1M2430Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT1 at M4K_X41_Y12
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = GLOBAL(M1L2);
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1M2430Q = R1_ram_block2a45_PORT_A_data_out_reg[1];

--R1M2431Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT2 at M4K_X41_Y12
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = GLOBAL(M1L2);
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1M2431Q = R1_ram_block2a45_PORT_A_data_out_reg[2];

--R1M2432Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT3 at M4K_X41_Y12
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = GLOBAL(M1L2);
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1M2432Q = R1_ram_block2a45_PORT_A_data_out_reg[3];

--R1M2433Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT4 at M4K_X41_Y12
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = GLOBAL(M1L2);
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1M2433Q = R1_ram_block2a45_PORT_A_data_out_reg[4];

--R1M2434Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT5 at M4K_X41_Y12
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = GLOBAL(M1L2);
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1M2434Q = R1_ram_block2a45_PORT_A_data_out_reg[5];

--R1M2435Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT6 at M4K_X41_Y12
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = GLOBAL(M1L2);
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1M2435Q = R1_ram_block2a45_PORT_A_data_out_reg[6];

--R1M2436Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a45~PORTADATAOUT7 at M4K_X41_Y12
R1_ram_block2a45_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a45_PORT_A_data_in_reg = DFFE(R1_ram_block2a45_PORT_A_data_in, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_data_in = ~GND;
R1_ram_block2a45_PORT_B_data_in_reg = DFFE(R1_ram_block2a45_PORT_B_data_in, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a45_PORT_A_address_reg = DFFE(R1_ram_block2a45_PORT_A_address, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a45_PORT_B_address_reg = DFFE(R1_ram_block2a45_PORT_B_address, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_PORT_A_write_enable = GND;
R1_ram_block2a45_PORT_A_write_enable_reg = DFFE(R1_ram_block2a45_PORT_A_write_enable, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1_ram_block2a45_PORT_B_write_enable = GND;
R1_ram_block2a45_PORT_B_write_enable_reg = DFFE(R1_ram_block2a45_PORT_B_write_enable, R1_ram_block2a45_clock_1, , , R1_ram_block2a45_clock_enable_1);
R1_ram_block2a45_clock_0 = GLOBAL(M1L2);
R1_ram_block2a45_clock_1 = GND;
R1_ram_block2a45_clock_enable_0 = S3_w_anode3375w[3];
R1_ram_block2a45_clock_enable_1 = GND;
R1_ram_block2a45_PORT_A_data_out = MEMORY(R1_ram_block2a45_PORT_A_data_in_reg, R1_ram_block2a45_PORT_B_data_in_reg, R1_ram_block2a45_PORT_A_address_reg, R1_ram_block2a45_PORT_B_address_reg, R1_ram_block2a45_PORT_A_write_enable_reg, R1_ram_block2a45_PORT_B_write_enable_reg, , , R1_ram_block2a45_clock_0, R1_ram_block2a45_clock_1, R1_ram_block2a45_clock_enable_0, R1_ram_block2a45_clock_enable_1, , );
R1_ram_block2a45_PORT_A_data_out_reg = DFFE(R1_ram_block2a45_PORT_A_data_out, R1_ram_block2a45_clock_0, , , R1_ram_block2a45_clock_enable_0);
R1M2436Q = R1_ram_block2a45_PORT_A_data_out_reg[7];


--R1_ram_block2a44 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44 at M4K_X41_Y10
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = GLOBAL(M1L2);
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44 = R1_ram_block2a44_PORT_A_data_out_reg[0];

--R1M2377Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT1 at M4K_X41_Y10
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = GLOBAL(M1L2);
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1M2377Q = R1_ram_block2a44_PORT_A_data_out_reg[1];

--R1M2378Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT2 at M4K_X41_Y10
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = GLOBAL(M1L2);
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1M2378Q = R1_ram_block2a44_PORT_A_data_out_reg[2];

--R1M2379Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT3 at M4K_X41_Y10
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = GLOBAL(M1L2);
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1M2379Q = R1_ram_block2a44_PORT_A_data_out_reg[3];

--R1M2380Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT4 at M4K_X41_Y10
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = GLOBAL(M1L2);
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1M2380Q = R1_ram_block2a44_PORT_A_data_out_reg[4];

--R1M2381Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT5 at M4K_X41_Y10
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = GLOBAL(M1L2);
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1M2381Q = R1_ram_block2a44_PORT_A_data_out_reg[5];

--R1M2382Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT6 at M4K_X41_Y10
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = GLOBAL(M1L2);
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1M2382Q = R1_ram_block2a44_PORT_A_data_out_reg[6];

--R1M2383Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a44~PORTADATAOUT7 at M4K_X41_Y10
R1_ram_block2a44_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a44_PORT_A_data_in_reg = DFFE(R1_ram_block2a44_PORT_A_data_in, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_data_in = ~GND;
R1_ram_block2a44_PORT_B_data_in_reg = DFFE(R1_ram_block2a44_PORT_B_data_in, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a44_PORT_A_address_reg = DFFE(R1_ram_block2a44_PORT_A_address, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a44_PORT_B_address_reg = DFFE(R1_ram_block2a44_PORT_B_address, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_PORT_A_write_enable = GND;
R1_ram_block2a44_PORT_A_write_enable_reg = DFFE(R1_ram_block2a44_PORT_A_write_enable, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1_ram_block2a44_PORT_B_write_enable = GND;
R1_ram_block2a44_PORT_B_write_enable_reg = DFFE(R1_ram_block2a44_PORT_B_write_enable, R1_ram_block2a44_clock_1, , , R1_ram_block2a44_clock_enable_1);
R1_ram_block2a44_clock_0 = GLOBAL(M1L2);
R1_ram_block2a44_clock_1 = GND;
R1_ram_block2a44_clock_enable_0 = S3_w_anode3365w[3];
R1_ram_block2a44_clock_enable_1 = GND;
R1_ram_block2a44_PORT_A_data_out = MEMORY(R1_ram_block2a44_PORT_A_data_in_reg, R1_ram_block2a44_PORT_B_data_in_reg, R1_ram_block2a44_PORT_A_address_reg, R1_ram_block2a44_PORT_B_address_reg, R1_ram_block2a44_PORT_A_write_enable_reg, R1_ram_block2a44_PORT_B_write_enable_reg, , , R1_ram_block2a44_clock_0, R1_ram_block2a44_clock_1, R1_ram_block2a44_clock_enable_0, R1_ram_block2a44_clock_enable_1, , );
R1_ram_block2a44_PORT_A_data_out_reg = DFFE(R1_ram_block2a44_PORT_A_data_out, R1_ram_block2a44_clock_0, , , R1_ram_block2a44_clock_enable_0);
R1M2383Q = R1_ram_block2a44_PORT_A_data_out_reg[7];


--T1L228 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6591w~47 at LCCOMB_X38_Y13_N10
T1L228 = R1_address_reg_a[6] & (R1_address_reg_a[7] # R1M2434Q) # !R1_address_reg_a[6] & !R1_address_reg_a[7] & (R1M2381Q);


--R1_ram_block2a47 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47 at M4K_X41_Y4
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = GLOBAL(M1L2);
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47 = R1_ram_block2a47_PORT_A_data_out_reg[0];

--R1M2536Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT1 at M4K_X41_Y4
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = GLOBAL(M1L2);
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1M2536Q = R1_ram_block2a47_PORT_A_data_out_reg[1];

--R1M2537Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT2 at M4K_X41_Y4
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = GLOBAL(M1L2);
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1M2537Q = R1_ram_block2a47_PORT_A_data_out_reg[2];

--R1M2538Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT3 at M4K_X41_Y4
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = GLOBAL(M1L2);
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1M2538Q = R1_ram_block2a47_PORT_A_data_out_reg[3];

--R1M2539Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT4 at M4K_X41_Y4
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = GLOBAL(M1L2);
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1M2539Q = R1_ram_block2a47_PORT_A_data_out_reg[4];

--R1M2540Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT5 at M4K_X41_Y4
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = GLOBAL(M1L2);
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1M2540Q = R1_ram_block2a47_PORT_A_data_out_reg[5];

--R1M2541Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT6 at M4K_X41_Y4
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = GLOBAL(M1L2);
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1M2541Q = R1_ram_block2a47_PORT_A_data_out_reg[6];

--R1M2542Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a47~PORTADATAOUT7 at M4K_X41_Y4
R1_ram_block2a47_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a47_PORT_A_data_in_reg = DFFE(R1_ram_block2a47_PORT_A_data_in, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_data_in = ~GND;
R1_ram_block2a47_PORT_B_data_in_reg = DFFE(R1_ram_block2a47_PORT_B_data_in, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a47_PORT_A_address_reg = DFFE(R1_ram_block2a47_PORT_A_address, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a47_PORT_B_address_reg = DFFE(R1_ram_block2a47_PORT_B_address, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_PORT_A_write_enable = GND;
R1_ram_block2a47_PORT_A_write_enable_reg = DFFE(R1_ram_block2a47_PORT_A_write_enable, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1_ram_block2a47_PORT_B_write_enable = GND;
R1_ram_block2a47_PORT_B_write_enable_reg = DFFE(R1_ram_block2a47_PORT_B_write_enable, R1_ram_block2a47_clock_1, , , R1_ram_block2a47_clock_enable_1);
R1_ram_block2a47_clock_0 = GLOBAL(M1L2);
R1_ram_block2a47_clock_1 = GND;
R1_ram_block2a47_clock_enable_0 = S3_w_anode3395w[3];
R1_ram_block2a47_clock_enable_1 = GND;
R1_ram_block2a47_PORT_A_data_out = MEMORY(R1_ram_block2a47_PORT_A_data_in_reg, R1_ram_block2a47_PORT_B_data_in_reg, R1_ram_block2a47_PORT_A_address_reg, R1_ram_block2a47_PORT_B_address_reg, R1_ram_block2a47_PORT_A_write_enable_reg, R1_ram_block2a47_PORT_B_write_enable_reg, , , R1_ram_block2a47_clock_0, R1_ram_block2a47_clock_1, R1_ram_block2a47_clock_enable_0, R1_ram_block2a47_clock_enable_1, , );
R1_ram_block2a47_PORT_A_data_out_reg = DFFE(R1_ram_block2a47_PORT_A_data_out, R1_ram_block2a47_clock_0, , , R1_ram_block2a47_clock_enable_0);
R1M2542Q = R1_ram_block2a47_PORT_A_data_out_reg[7];


--T1L229 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6591w~48 at LCCOMB_X38_Y13_N2
T1L229 = T1L228 & (R1M2540Q # !R1_address_reg_a[7]) # !T1L228 & R1_address_reg_a[7] & R1M2487Q;


--R1_ram_block2a13 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13 at M4K_X41_Y26
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = GLOBAL(M1L2);
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13 = R1_ram_block2a13_PORT_A_data_out_reg[0];

--R1M734Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT1 at M4K_X41_Y26
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = GLOBAL(M1L2);
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1M734Q = R1_ram_block2a13_PORT_A_data_out_reg[1];

--R1M735Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT2 at M4K_X41_Y26
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = GLOBAL(M1L2);
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1M735Q = R1_ram_block2a13_PORT_A_data_out_reg[2];

--R1M736Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT3 at M4K_X41_Y26
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = GLOBAL(M1L2);
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1M736Q = R1_ram_block2a13_PORT_A_data_out_reg[3];

--R1M737Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT4 at M4K_X41_Y26
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = GLOBAL(M1L2);
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1M737Q = R1_ram_block2a13_PORT_A_data_out_reg[4];

--R1M738Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT5 at M4K_X41_Y26
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = GLOBAL(M1L2);
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1M738Q = R1_ram_block2a13_PORT_A_data_out_reg[5];

--R1M739Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT6 at M4K_X41_Y26
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = GLOBAL(M1L2);
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1M739Q = R1_ram_block2a13_PORT_A_data_out_reg[6];

--R1M740Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a13~PORTADATAOUT7 at M4K_X41_Y26
R1_ram_block2a13_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a13_PORT_A_data_in_reg = DFFE(R1_ram_block2a13_PORT_A_data_in, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_data_in = ~GND;
R1_ram_block2a13_PORT_B_data_in_reg = DFFE(R1_ram_block2a13_PORT_B_data_in, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a13_PORT_A_address_reg = DFFE(R1_ram_block2a13_PORT_A_address, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a13_PORT_B_address_reg = DFFE(R1_ram_block2a13_PORT_B_address, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_PORT_A_write_enable = GND;
R1_ram_block2a13_PORT_A_write_enable_reg = DFFE(R1_ram_block2a13_PORT_A_write_enable, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1_ram_block2a13_PORT_B_write_enable = GND;
R1_ram_block2a13_PORT_B_write_enable_reg = DFFE(R1_ram_block2a13_PORT_B_write_enable, R1_ram_block2a13_clock_1, , , R1_ram_block2a13_clock_enable_1);
R1_ram_block2a13_clock_0 = GLOBAL(M1L2);
R1_ram_block2a13_clock_1 = GND;
R1_ram_block2a13_clock_enable_0 = S3_w_anode3003w[3];
R1_ram_block2a13_clock_enable_1 = GND;
R1_ram_block2a13_PORT_A_data_out = MEMORY(R1_ram_block2a13_PORT_A_data_in_reg, R1_ram_block2a13_PORT_B_data_in_reg, R1_ram_block2a13_PORT_A_address_reg, R1_ram_block2a13_PORT_B_address_reg, R1_ram_block2a13_PORT_A_write_enable_reg, R1_ram_block2a13_PORT_B_write_enable_reg, , , R1_ram_block2a13_clock_0, R1_ram_block2a13_clock_1, R1_ram_block2a13_clock_enable_0, R1_ram_block2a13_clock_enable_1, , );
R1_ram_block2a13_PORT_A_data_out_reg = DFFE(R1_ram_block2a13_PORT_A_data_out, R1_ram_block2a13_clock_0, , , R1_ram_block2a13_clock_enable_0);
R1M740Q = R1_ram_block2a13_PORT_A_data_out_reg[7];


--R1_ram_block2a14 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14 at M4K_X41_Y13
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = GLOBAL(M1L2);
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14 = R1_ram_block2a14_PORT_A_data_out_reg[0];

--R1M787Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT1 at M4K_X41_Y13
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = GLOBAL(M1L2);
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1M787Q = R1_ram_block2a14_PORT_A_data_out_reg[1];

--R1M788Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT2 at M4K_X41_Y13
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = GLOBAL(M1L2);
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1M788Q = R1_ram_block2a14_PORT_A_data_out_reg[2];

--R1M789Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT3 at M4K_X41_Y13
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = GLOBAL(M1L2);
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1M789Q = R1_ram_block2a14_PORT_A_data_out_reg[3];

--R1M790Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT4 at M4K_X41_Y13
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = GLOBAL(M1L2);
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1M790Q = R1_ram_block2a14_PORT_A_data_out_reg[4];

--R1M791Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT5 at M4K_X41_Y13
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = GLOBAL(M1L2);
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1M791Q = R1_ram_block2a14_PORT_A_data_out_reg[5];

--R1M792Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT6 at M4K_X41_Y13
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = GLOBAL(M1L2);
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1M792Q = R1_ram_block2a14_PORT_A_data_out_reg[6];

--R1M793Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a14~PORTADATAOUT7 at M4K_X41_Y13
R1_ram_block2a14_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a14_PORT_A_data_in_reg = DFFE(R1_ram_block2a14_PORT_A_data_in, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_data_in = ~GND;
R1_ram_block2a14_PORT_B_data_in_reg = DFFE(R1_ram_block2a14_PORT_B_data_in, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a14_PORT_A_address_reg = DFFE(R1_ram_block2a14_PORT_A_address, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a14_PORT_B_address_reg = DFFE(R1_ram_block2a14_PORT_B_address, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_PORT_A_write_enable = GND;
R1_ram_block2a14_PORT_A_write_enable_reg = DFFE(R1_ram_block2a14_PORT_A_write_enable, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1_ram_block2a14_PORT_B_write_enable = GND;
R1_ram_block2a14_PORT_B_write_enable_reg = DFFE(R1_ram_block2a14_PORT_B_write_enable, R1_ram_block2a14_clock_1, , , R1_ram_block2a14_clock_enable_1);
R1_ram_block2a14_clock_0 = GLOBAL(M1L2);
R1_ram_block2a14_clock_1 = GND;
R1_ram_block2a14_clock_enable_0 = S3_w_anode3013w[3];
R1_ram_block2a14_clock_enable_1 = GND;
R1_ram_block2a14_PORT_A_data_out = MEMORY(R1_ram_block2a14_PORT_A_data_in_reg, R1_ram_block2a14_PORT_B_data_in_reg, R1_ram_block2a14_PORT_A_address_reg, R1_ram_block2a14_PORT_B_address_reg, R1_ram_block2a14_PORT_A_write_enable_reg, R1_ram_block2a14_PORT_B_write_enable_reg, , , R1_ram_block2a14_clock_0, R1_ram_block2a14_clock_1, R1_ram_block2a14_clock_enable_0, R1_ram_block2a14_clock_enable_1, , );
R1_ram_block2a14_PORT_A_data_out_reg = DFFE(R1_ram_block2a14_PORT_A_data_out, R1_ram_block2a14_clock_0, , , R1_ram_block2a14_clock_enable_0);
R1M793Q = R1_ram_block2a14_PORT_A_data_out_reg[7];


--R1_ram_block2a12 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12 at M4K_X41_Y15
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = GLOBAL(M1L2);
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12 = R1_ram_block2a12_PORT_A_data_out_reg[0];

--R1M681Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT1 at M4K_X41_Y15
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = GLOBAL(M1L2);
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1M681Q = R1_ram_block2a12_PORT_A_data_out_reg[1];

--R1M682Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT2 at M4K_X41_Y15
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = GLOBAL(M1L2);
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1M682Q = R1_ram_block2a12_PORT_A_data_out_reg[2];

--R1M683Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT3 at M4K_X41_Y15
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = GLOBAL(M1L2);
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1M683Q = R1_ram_block2a12_PORT_A_data_out_reg[3];

--R1M684Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT4 at M4K_X41_Y15
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = GLOBAL(M1L2);
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1M684Q = R1_ram_block2a12_PORT_A_data_out_reg[4];

--R1M685Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT5 at M4K_X41_Y15
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = GLOBAL(M1L2);
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1M685Q = R1_ram_block2a12_PORT_A_data_out_reg[5];

--R1M686Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT6 at M4K_X41_Y15
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = GLOBAL(M1L2);
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1M686Q = R1_ram_block2a12_PORT_A_data_out_reg[6];

--R1M687Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a12~PORTADATAOUT7 at M4K_X41_Y15
R1_ram_block2a12_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a12_PORT_A_data_in_reg = DFFE(R1_ram_block2a12_PORT_A_data_in, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_data_in = ~GND;
R1_ram_block2a12_PORT_B_data_in_reg = DFFE(R1_ram_block2a12_PORT_B_data_in, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a12_PORT_A_address_reg = DFFE(R1_ram_block2a12_PORT_A_address, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a12_PORT_B_address_reg = DFFE(R1_ram_block2a12_PORT_B_address, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_PORT_A_write_enable = GND;
R1_ram_block2a12_PORT_A_write_enable_reg = DFFE(R1_ram_block2a12_PORT_A_write_enable, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1_ram_block2a12_PORT_B_write_enable = GND;
R1_ram_block2a12_PORT_B_write_enable_reg = DFFE(R1_ram_block2a12_PORT_B_write_enable, R1_ram_block2a12_clock_1, , , R1_ram_block2a12_clock_enable_1);
R1_ram_block2a12_clock_0 = GLOBAL(M1L2);
R1_ram_block2a12_clock_1 = GND;
R1_ram_block2a12_clock_enable_0 = S3_w_anode2993w[3];
R1_ram_block2a12_clock_enable_1 = GND;
R1_ram_block2a12_PORT_A_data_out = MEMORY(R1_ram_block2a12_PORT_A_data_in_reg, R1_ram_block2a12_PORT_B_data_in_reg, R1_ram_block2a12_PORT_A_address_reg, R1_ram_block2a12_PORT_B_address_reg, R1_ram_block2a12_PORT_A_write_enable_reg, R1_ram_block2a12_PORT_B_write_enable_reg, , , R1_ram_block2a12_clock_0, R1_ram_block2a12_clock_1, R1_ram_block2a12_clock_enable_0, R1_ram_block2a12_clock_enable_1, , );
R1_ram_block2a12_PORT_A_data_out_reg = DFFE(R1_ram_block2a12_PORT_A_data_out, R1_ram_block2a12_clock_0, , , R1_ram_block2a12_clock_enable_0);
R1M687Q = R1_ram_block2a12_PORT_A_data_out_reg[7];


--T1L216 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6390w~47 at LCCOMB_X38_Y13_N30
T1L216 = R1_address_reg_a[6] & R1_address_reg_a[7] # !R1_address_reg_a[6] & (R1_address_reg_a[7] & (R1M791Q) # !R1_address_reg_a[7] & R1M685Q);


--R1_ram_block2a15 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15 at M4K_X41_Y14
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = GLOBAL(M1L2);
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15 = R1_ram_block2a15_PORT_A_data_out_reg[0];

--R1M840Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT1 at M4K_X41_Y14
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = GLOBAL(M1L2);
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1M840Q = R1_ram_block2a15_PORT_A_data_out_reg[1];

--R1M841Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT2 at M4K_X41_Y14
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = GLOBAL(M1L2);
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1M841Q = R1_ram_block2a15_PORT_A_data_out_reg[2];

--R1M842Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT3 at M4K_X41_Y14
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = GLOBAL(M1L2);
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1M842Q = R1_ram_block2a15_PORT_A_data_out_reg[3];

--R1M843Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT4 at M4K_X41_Y14
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = GLOBAL(M1L2);
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1M843Q = R1_ram_block2a15_PORT_A_data_out_reg[4];

--R1M844Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT5 at M4K_X41_Y14
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = GLOBAL(M1L2);
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1M844Q = R1_ram_block2a15_PORT_A_data_out_reg[5];

--R1M845Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT6 at M4K_X41_Y14
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = GLOBAL(M1L2);
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1M845Q = R1_ram_block2a15_PORT_A_data_out_reg[6];

--R1M846Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a15~PORTADATAOUT7 at M4K_X41_Y14
R1_ram_block2a15_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a15_PORT_A_data_in_reg = DFFE(R1_ram_block2a15_PORT_A_data_in, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_data_in = ~GND;
R1_ram_block2a15_PORT_B_data_in_reg = DFFE(R1_ram_block2a15_PORT_B_data_in, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a15_PORT_A_address_reg = DFFE(R1_ram_block2a15_PORT_A_address, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a15_PORT_B_address_reg = DFFE(R1_ram_block2a15_PORT_B_address, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_PORT_A_write_enable = GND;
R1_ram_block2a15_PORT_A_write_enable_reg = DFFE(R1_ram_block2a15_PORT_A_write_enable, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1_ram_block2a15_PORT_B_write_enable = GND;
R1_ram_block2a15_PORT_B_write_enable_reg = DFFE(R1_ram_block2a15_PORT_B_write_enable, R1_ram_block2a15_clock_1, , , R1_ram_block2a15_clock_enable_1);
R1_ram_block2a15_clock_0 = GLOBAL(M1L2);
R1_ram_block2a15_clock_1 = GND;
R1_ram_block2a15_clock_enable_0 = S3_w_anode3023w[3];
R1_ram_block2a15_clock_enable_1 = GND;
R1_ram_block2a15_PORT_A_data_out = MEMORY(R1_ram_block2a15_PORT_A_data_in_reg, R1_ram_block2a15_PORT_B_data_in_reg, R1_ram_block2a15_PORT_A_address_reg, R1_ram_block2a15_PORT_B_address_reg, R1_ram_block2a15_PORT_A_write_enable_reg, R1_ram_block2a15_PORT_B_write_enable_reg, , , R1_ram_block2a15_clock_0, R1_ram_block2a15_clock_1, R1_ram_block2a15_clock_enable_0, R1_ram_block2a15_clock_enable_1, , );
R1_ram_block2a15_PORT_A_data_out_reg = DFFE(R1_ram_block2a15_PORT_A_data_out, R1_ram_block2a15_clock_0, , , R1_ram_block2a15_clock_enable_0);
R1M846Q = R1_ram_block2a15_PORT_A_data_out_reg[7];


--T1L217 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6390w~48 at LCCOMB_X38_Y13_N6
T1L217 = R1_address_reg_a[6] & (T1L216 & (R1M844Q) # !T1L216 & R1M738Q) # !R1_address_reg_a[6] & T1L216;


--T1L233 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~574 at LCCOMB_X38_Y13_N26
T1L233 = R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L229 # !R1_address_reg_a[11] & (T1L217));


--R1_ram_block2a37 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37 at M4K_X41_Y7
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = GLOBAL(M1L2);
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37 = R1_ram_block2a37_PORT_A_data_out_reg[0];

--R1M2006Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT1 at M4K_X41_Y7
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = GLOBAL(M1L2);
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1M2006Q = R1_ram_block2a37_PORT_A_data_out_reg[1];

--R1M2007Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT2 at M4K_X41_Y7
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = GLOBAL(M1L2);
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1M2007Q = R1_ram_block2a37_PORT_A_data_out_reg[2];

--R1M2008Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT3 at M4K_X41_Y7
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = GLOBAL(M1L2);
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1M2008Q = R1_ram_block2a37_PORT_A_data_out_reg[3];

--R1M2009Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT4 at M4K_X41_Y7
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = GLOBAL(M1L2);
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1M2009Q = R1_ram_block2a37_PORT_A_data_out_reg[4];

--R1M2010Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT5 at M4K_X41_Y7
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = GLOBAL(M1L2);
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1M2010Q = R1_ram_block2a37_PORT_A_data_out_reg[5];

--R1M2011Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT6 at M4K_X41_Y7
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = GLOBAL(M1L2);
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1M2011Q = R1_ram_block2a37_PORT_A_data_out_reg[6];

--R1M2012Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a37~PORTADATAOUT7 at M4K_X41_Y7
R1_ram_block2a37_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a37_PORT_A_data_in_reg = DFFE(R1_ram_block2a37_PORT_A_data_in, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_data_in = ~GND;
R1_ram_block2a37_PORT_B_data_in_reg = DFFE(R1_ram_block2a37_PORT_B_data_in, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a37_PORT_A_address_reg = DFFE(R1_ram_block2a37_PORT_A_address, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a37_PORT_B_address_reg = DFFE(R1_ram_block2a37_PORT_B_address, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_PORT_A_write_enable = GND;
R1_ram_block2a37_PORT_A_write_enable_reg = DFFE(R1_ram_block2a37_PORT_A_write_enable, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1_ram_block2a37_PORT_B_write_enable = GND;
R1_ram_block2a37_PORT_B_write_enable_reg = DFFE(R1_ram_block2a37_PORT_B_write_enable, R1_ram_block2a37_clock_1, , , R1_ram_block2a37_clock_enable_1);
R1_ram_block2a37_clock_0 = GLOBAL(M1L2);
R1_ram_block2a37_clock_1 = GND;
R1_ram_block2a37_clock_enable_0 = S3_w_anode3282w[3];
R1_ram_block2a37_clock_enable_1 = GND;
R1_ram_block2a37_PORT_A_data_out = MEMORY(R1_ram_block2a37_PORT_A_data_in_reg, R1_ram_block2a37_PORT_B_data_in_reg, R1_ram_block2a37_PORT_A_address_reg, R1_ram_block2a37_PORT_B_address_reg, R1_ram_block2a37_PORT_A_write_enable_reg, R1_ram_block2a37_PORT_B_write_enable_reg, , , R1_ram_block2a37_clock_0, R1_ram_block2a37_clock_1, R1_ram_block2a37_clock_enable_0, R1_ram_block2a37_clock_enable_1, , );
R1_ram_block2a37_PORT_A_data_out_reg = DFFE(R1_ram_block2a37_PORT_A_data_out, R1_ram_block2a37_clock_0, , , R1_ram_block2a37_clock_enable_0);
R1M2012Q = R1_ram_block2a37_PORT_A_data_out_reg[7];


--R1_ram_block2a38 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38 at M4K_X41_Y2
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = GLOBAL(M1L2);
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38 = R1_ram_block2a38_PORT_A_data_out_reg[0];

--R1M2059Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT1 at M4K_X41_Y2
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = GLOBAL(M1L2);
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1M2059Q = R1_ram_block2a38_PORT_A_data_out_reg[1];

--R1M2060Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT2 at M4K_X41_Y2
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = GLOBAL(M1L2);
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1M2060Q = R1_ram_block2a38_PORT_A_data_out_reg[2];

--R1M2061Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT3 at M4K_X41_Y2
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = GLOBAL(M1L2);
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1M2061Q = R1_ram_block2a38_PORT_A_data_out_reg[3];

--R1M2062Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT4 at M4K_X41_Y2
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = GLOBAL(M1L2);
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1M2062Q = R1_ram_block2a38_PORT_A_data_out_reg[4];

--R1M2063Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT5 at M4K_X41_Y2
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = GLOBAL(M1L2);
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1M2063Q = R1_ram_block2a38_PORT_A_data_out_reg[5];

--R1M2064Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT6 at M4K_X41_Y2
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = GLOBAL(M1L2);
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1M2064Q = R1_ram_block2a38_PORT_A_data_out_reg[6];

--R1M2065Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a38~PORTADATAOUT7 at M4K_X41_Y2
R1_ram_block2a38_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a38_PORT_A_data_in_reg = DFFE(R1_ram_block2a38_PORT_A_data_in, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_data_in = ~GND;
R1_ram_block2a38_PORT_B_data_in_reg = DFFE(R1_ram_block2a38_PORT_B_data_in, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a38_PORT_A_address_reg = DFFE(R1_ram_block2a38_PORT_A_address, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a38_PORT_B_address_reg = DFFE(R1_ram_block2a38_PORT_B_address, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_PORT_A_write_enable = GND;
R1_ram_block2a38_PORT_A_write_enable_reg = DFFE(R1_ram_block2a38_PORT_A_write_enable, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1_ram_block2a38_PORT_B_write_enable = GND;
R1_ram_block2a38_PORT_B_write_enable_reg = DFFE(R1_ram_block2a38_PORT_B_write_enable, R1_ram_block2a38_clock_1, , , R1_ram_block2a38_clock_enable_1);
R1_ram_block2a38_clock_0 = GLOBAL(M1L2);
R1_ram_block2a38_clock_1 = GND;
R1_ram_block2a38_clock_enable_0 = S3_w_anode3292w[3];
R1_ram_block2a38_clock_enable_1 = GND;
R1_ram_block2a38_PORT_A_data_out = MEMORY(R1_ram_block2a38_PORT_A_data_in_reg, R1_ram_block2a38_PORT_B_data_in_reg, R1_ram_block2a38_PORT_A_address_reg, R1_ram_block2a38_PORT_B_address_reg, R1_ram_block2a38_PORT_A_write_enable_reg, R1_ram_block2a38_PORT_B_write_enable_reg, , , R1_ram_block2a38_clock_0, R1_ram_block2a38_clock_1, R1_ram_block2a38_clock_enable_0, R1_ram_block2a38_clock_enable_1, , );
R1_ram_block2a38_PORT_A_data_out_reg = DFFE(R1_ram_block2a38_PORT_A_data_out, R1_ram_block2a38_clock_0, , , R1_ram_block2a38_clock_enable_0);
R1M2065Q = R1_ram_block2a38_PORT_A_data_out_reg[7];


--R1_ram_block2a36 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36 at M4K_X41_Y3
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = GLOBAL(M1L2);
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36 = R1_ram_block2a36_PORT_A_data_out_reg[0];

--R1M1953Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT1 at M4K_X41_Y3
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = GLOBAL(M1L2);
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1M1953Q = R1_ram_block2a36_PORT_A_data_out_reg[1];

--R1M1954Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT2 at M4K_X41_Y3
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = GLOBAL(M1L2);
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1M1954Q = R1_ram_block2a36_PORT_A_data_out_reg[2];

--R1M1955Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT3 at M4K_X41_Y3
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = GLOBAL(M1L2);
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1M1955Q = R1_ram_block2a36_PORT_A_data_out_reg[3];

--R1M1956Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT4 at M4K_X41_Y3
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = GLOBAL(M1L2);
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1M1956Q = R1_ram_block2a36_PORT_A_data_out_reg[4];

--R1M1957Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT5 at M4K_X41_Y3
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = GLOBAL(M1L2);
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1M1957Q = R1_ram_block2a36_PORT_A_data_out_reg[5];

--R1M1958Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT6 at M4K_X41_Y3
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = GLOBAL(M1L2);
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1M1958Q = R1_ram_block2a36_PORT_A_data_out_reg[6];

--R1M1959Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a36~PORTADATAOUT7 at M4K_X41_Y3
R1_ram_block2a36_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a36_PORT_A_data_in_reg = DFFE(R1_ram_block2a36_PORT_A_data_in, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_data_in = ~GND;
R1_ram_block2a36_PORT_B_data_in_reg = DFFE(R1_ram_block2a36_PORT_B_data_in, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a36_PORT_A_address_reg = DFFE(R1_ram_block2a36_PORT_A_address, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a36_PORT_B_address_reg = DFFE(R1_ram_block2a36_PORT_B_address, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_PORT_A_write_enable = GND;
R1_ram_block2a36_PORT_A_write_enable_reg = DFFE(R1_ram_block2a36_PORT_A_write_enable, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1_ram_block2a36_PORT_B_write_enable = GND;
R1_ram_block2a36_PORT_B_write_enable_reg = DFFE(R1_ram_block2a36_PORT_B_write_enable, R1_ram_block2a36_clock_1, , , R1_ram_block2a36_clock_enable_1);
R1_ram_block2a36_clock_0 = GLOBAL(M1L2);
R1_ram_block2a36_clock_1 = GND;
R1_ram_block2a36_clock_enable_0 = S3_w_anode3272w[3];
R1_ram_block2a36_clock_enable_1 = GND;
R1_ram_block2a36_PORT_A_data_out = MEMORY(R1_ram_block2a36_PORT_A_data_in_reg, R1_ram_block2a36_PORT_B_data_in_reg, R1_ram_block2a36_PORT_A_address_reg, R1_ram_block2a36_PORT_B_address_reg, R1_ram_block2a36_PORT_A_write_enable_reg, R1_ram_block2a36_PORT_B_write_enable_reg, , , R1_ram_block2a36_clock_0, R1_ram_block2a36_clock_1, R1_ram_block2a36_clock_enable_0, R1_ram_block2a36_clock_enable_1, , );
R1_ram_block2a36_PORT_A_data_out_reg = DFFE(R1_ram_block2a36_PORT_A_data_out, R1_ram_block2a36_clock_0, , , R1_ram_block2a36_clock_enable_0);
R1M1959Q = R1_ram_block2a36_PORT_A_data_out_reg[7];


--T1L226 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6589w~44 at LCCOMB_X18_Y12_N8
T1L226 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2063Q # !R1_address_reg_a[7] & (R1M1957Q));


--R1_ram_block2a39 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39 at M4K_X41_Y9
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = GLOBAL(M1L2);
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39 = R1_ram_block2a39_PORT_A_data_out_reg[0];

--R1M2112Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT1 at M4K_X41_Y9
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = GLOBAL(M1L2);
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1M2112Q = R1_ram_block2a39_PORT_A_data_out_reg[1];

--R1M2113Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT2 at M4K_X41_Y9
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = GLOBAL(M1L2);
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1M2113Q = R1_ram_block2a39_PORT_A_data_out_reg[2];

--R1M2114Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT3 at M4K_X41_Y9
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = GLOBAL(M1L2);
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1M2114Q = R1_ram_block2a39_PORT_A_data_out_reg[3];

--R1M2115Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT4 at M4K_X41_Y9
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = GLOBAL(M1L2);
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1M2115Q = R1_ram_block2a39_PORT_A_data_out_reg[4];

--R1M2116Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT5 at M4K_X41_Y9
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = GLOBAL(M1L2);
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1M2116Q = R1_ram_block2a39_PORT_A_data_out_reg[5];

--R1M2117Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT6 at M4K_X41_Y9
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = GLOBAL(M1L2);
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1M2117Q = R1_ram_block2a39_PORT_A_data_out_reg[6];

--R1M2118Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a39~PORTADATAOUT7 at M4K_X41_Y9
R1_ram_block2a39_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a39_PORT_A_data_in_reg = DFFE(R1_ram_block2a39_PORT_A_data_in, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_data_in = ~GND;
R1_ram_block2a39_PORT_B_data_in_reg = DFFE(R1_ram_block2a39_PORT_B_data_in, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a39_PORT_A_address_reg = DFFE(R1_ram_block2a39_PORT_A_address, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a39_PORT_B_address_reg = DFFE(R1_ram_block2a39_PORT_B_address, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_PORT_A_write_enable = GND;
R1_ram_block2a39_PORT_A_write_enable_reg = DFFE(R1_ram_block2a39_PORT_A_write_enable, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1_ram_block2a39_PORT_B_write_enable = GND;
R1_ram_block2a39_PORT_B_write_enable_reg = DFFE(R1_ram_block2a39_PORT_B_write_enable, R1_ram_block2a39_clock_1, , , R1_ram_block2a39_clock_enable_1);
R1_ram_block2a39_clock_0 = GLOBAL(M1L2);
R1_ram_block2a39_clock_1 = GND;
R1_ram_block2a39_clock_enable_0 = S3_w_anode3302w[3];
R1_ram_block2a39_clock_enable_1 = GND;
R1_ram_block2a39_PORT_A_data_out = MEMORY(R1_ram_block2a39_PORT_A_data_in_reg, R1_ram_block2a39_PORT_B_data_in_reg, R1_ram_block2a39_PORT_A_address_reg, R1_ram_block2a39_PORT_B_address_reg, R1_ram_block2a39_PORT_A_write_enable_reg, R1_ram_block2a39_PORT_B_write_enable_reg, , , R1_ram_block2a39_clock_0, R1_ram_block2a39_clock_1, R1_ram_block2a39_clock_enable_0, R1_ram_block2a39_clock_enable_1, , );
R1_ram_block2a39_PORT_A_data_out_reg = DFFE(R1_ram_block2a39_PORT_A_data_out, R1_ram_block2a39_clock_0, , , R1_ram_block2a39_clock_enable_0);
R1M2118Q = R1_ram_block2a39_PORT_A_data_out_reg[7];


--T1L227 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6589w~45 at LCCOMB_X18_Y12_N16
T1L227 = T1L226 & (R1M2116Q # !R1_address_reg_a[6]) # !T1L226 & R1M2010Q & R1_address_reg_a[6];


--R1_ram_block2a6 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6 at M4K_X41_Y8
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = GLOBAL(M1L2);
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6 = R1_ram_block2a6_PORT_A_data_out_reg[0];

--R1M363Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT1 at M4K_X41_Y8
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = GLOBAL(M1L2);
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1M363Q = R1_ram_block2a6_PORT_A_data_out_reg[1];

--R1M364Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT2 at M4K_X41_Y8
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = GLOBAL(M1L2);
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1M364Q = R1_ram_block2a6_PORT_A_data_out_reg[2];

--R1M365Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT3 at M4K_X41_Y8
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = GLOBAL(M1L2);
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1M365Q = R1_ram_block2a6_PORT_A_data_out_reg[3];

--R1M366Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT4 at M4K_X41_Y8
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = GLOBAL(M1L2);
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1M366Q = R1_ram_block2a6_PORT_A_data_out_reg[4];

--R1M367Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT5 at M4K_X41_Y8
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = GLOBAL(M1L2);
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1M367Q = R1_ram_block2a6_PORT_A_data_out_reg[5];

--R1M368Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT6 at M4K_X41_Y8
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = GLOBAL(M1L2);
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1M368Q = R1_ram_block2a6_PORT_A_data_out_reg[6];

--R1M369Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a6~PORTADATAOUT7 at M4K_X41_Y8
R1_ram_block2a6_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a6_PORT_A_data_in_reg = DFFE(R1_ram_block2a6_PORT_A_data_in, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_data_in = ~GND;
R1_ram_block2a6_PORT_B_data_in_reg = DFFE(R1_ram_block2a6_PORT_B_data_in, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a6_PORT_A_address_reg = DFFE(R1_ram_block2a6_PORT_A_address, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a6_PORT_B_address_reg = DFFE(R1_ram_block2a6_PORT_B_address, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_PORT_A_write_enable = GND;
R1_ram_block2a6_PORT_A_write_enable_reg = DFFE(R1_ram_block2a6_PORT_A_write_enable, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1_ram_block2a6_PORT_B_write_enable = GND;
R1_ram_block2a6_PORT_B_write_enable_reg = DFFE(R1_ram_block2a6_PORT_B_write_enable, R1_ram_block2a6_clock_1, , , R1_ram_block2a6_clock_enable_1);
R1_ram_block2a6_clock_0 = GLOBAL(M1L2);
R1_ram_block2a6_clock_1 = GND;
R1_ram_block2a6_clock_enable_0 = S3L14;
R1_ram_block2a6_clock_enable_1 = GND;
R1_ram_block2a6_PORT_A_data_out = MEMORY(R1_ram_block2a6_PORT_A_data_in_reg, R1_ram_block2a6_PORT_B_data_in_reg, R1_ram_block2a6_PORT_A_address_reg, R1_ram_block2a6_PORT_B_address_reg, R1_ram_block2a6_PORT_A_write_enable_reg, R1_ram_block2a6_PORT_B_write_enable_reg, , , R1_ram_block2a6_clock_0, R1_ram_block2a6_clock_1, R1_ram_block2a6_clock_enable_0, R1_ram_block2a6_clock_enable_1, , );
R1_ram_block2a6_PORT_A_data_out_reg = DFFE(R1_ram_block2a6_PORT_A_data_out, R1_ram_block2a6_clock_0, , , R1_ram_block2a6_clock_enable_0);
R1M369Q = R1_ram_block2a6_PORT_A_data_out_reg[7];


--R1_ram_block2a5 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5 at M4K_X41_Y11
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = GLOBAL(M1L2);
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5 = R1_ram_block2a5_PORT_A_data_out_reg[0];

--R1M310Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT1 at M4K_X41_Y11
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = GLOBAL(M1L2);
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1M310Q = R1_ram_block2a5_PORT_A_data_out_reg[1];

--R1M311Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT2 at M4K_X41_Y11
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = GLOBAL(M1L2);
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1M311Q = R1_ram_block2a5_PORT_A_data_out_reg[2];

--R1M312Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT3 at M4K_X41_Y11
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = GLOBAL(M1L2);
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1M312Q = R1_ram_block2a5_PORT_A_data_out_reg[3];

--R1M313Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT4 at M4K_X41_Y11
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = GLOBAL(M1L2);
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1M313Q = R1_ram_block2a5_PORT_A_data_out_reg[4];

--R1M314Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT5 at M4K_X41_Y11
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = GLOBAL(M1L2);
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1M314Q = R1_ram_block2a5_PORT_A_data_out_reg[5];

--R1M315Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT6 at M4K_X41_Y11
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = GLOBAL(M1L2);
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1M315Q = R1_ram_block2a5_PORT_A_data_out_reg[6];

--R1M316Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a5~PORTADATAOUT7 at M4K_X41_Y11
R1_ram_block2a5_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a5_PORT_A_data_in_reg = DFFE(R1_ram_block2a5_PORT_A_data_in, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_data_in = ~GND;
R1_ram_block2a5_PORT_B_data_in_reg = DFFE(R1_ram_block2a5_PORT_B_data_in, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a5_PORT_A_address_reg = DFFE(R1_ram_block2a5_PORT_A_address, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a5_PORT_B_address_reg = DFFE(R1_ram_block2a5_PORT_B_address, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_PORT_A_write_enable = GND;
R1_ram_block2a5_PORT_A_write_enable_reg = DFFE(R1_ram_block2a5_PORT_A_write_enable, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1_ram_block2a5_PORT_B_write_enable = GND;
R1_ram_block2a5_PORT_B_write_enable_reg = DFFE(R1_ram_block2a5_PORT_B_write_enable, R1_ram_block2a5_clock_1, , , R1_ram_block2a5_clock_enable_1);
R1_ram_block2a5_clock_0 = GLOBAL(M1L2);
R1_ram_block2a5_clock_1 = GND;
R1_ram_block2a5_clock_enable_0 = S3_w_anode2909w[3];
R1_ram_block2a5_clock_enable_1 = GND;
R1_ram_block2a5_PORT_A_data_out = MEMORY(R1_ram_block2a5_PORT_A_data_in_reg, R1_ram_block2a5_PORT_B_data_in_reg, R1_ram_block2a5_PORT_A_address_reg, R1_ram_block2a5_PORT_B_address_reg, R1_ram_block2a5_PORT_A_write_enable_reg, R1_ram_block2a5_PORT_B_write_enable_reg, , , R1_ram_block2a5_clock_0, R1_ram_block2a5_clock_1, R1_ram_block2a5_clock_enable_0, R1_ram_block2a5_clock_enable_1, , );
R1_ram_block2a5_PORT_A_data_out_reg = DFFE(R1_ram_block2a5_PORT_A_data_out, R1_ram_block2a5_clock_0, , , R1_ram_block2a5_clock_enable_0);
R1M316Q = R1_ram_block2a5_PORT_A_data_out_reg[7];


--R1_ram_block2a4 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4 at M4K_X41_Y6
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = GLOBAL(M1L2);
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4 = R1_ram_block2a4_PORT_A_data_out_reg[0];

--R1M257Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT1 at M4K_X41_Y6
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = GLOBAL(M1L2);
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1M257Q = R1_ram_block2a4_PORT_A_data_out_reg[1];

--R1M258Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT2 at M4K_X41_Y6
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = GLOBAL(M1L2);
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1M258Q = R1_ram_block2a4_PORT_A_data_out_reg[2];

--R1M259Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT3 at M4K_X41_Y6
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = GLOBAL(M1L2);
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1M259Q = R1_ram_block2a4_PORT_A_data_out_reg[3];

--R1M260Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT4 at M4K_X41_Y6
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = GLOBAL(M1L2);
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1M260Q = R1_ram_block2a4_PORT_A_data_out_reg[4];

--R1M261Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT5 at M4K_X41_Y6
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = GLOBAL(M1L2);
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1M261Q = R1_ram_block2a4_PORT_A_data_out_reg[5];

--R1M262Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT6 at M4K_X41_Y6
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = GLOBAL(M1L2);
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1M262Q = R1_ram_block2a4_PORT_A_data_out_reg[6];

--R1M263Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a4~PORTADATAOUT7 at M4K_X41_Y6
R1_ram_block2a4_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a4_PORT_A_data_in_reg = DFFE(R1_ram_block2a4_PORT_A_data_in, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_data_in = ~GND;
R1_ram_block2a4_PORT_B_data_in_reg = DFFE(R1_ram_block2a4_PORT_B_data_in, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a4_PORT_A_address_reg = DFFE(R1_ram_block2a4_PORT_A_address, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a4_PORT_B_address_reg = DFFE(R1_ram_block2a4_PORT_B_address, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_PORT_A_write_enable = GND;
R1_ram_block2a4_PORT_A_write_enable_reg = DFFE(R1_ram_block2a4_PORT_A_write_enable, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1_ram_block2a4_PORT_B_write_enable = GND;
R1_ram_block2a4_PORT_B_write_enable_reg = DFFE(R1_ram_block2a4_PORT_B_write_enable, R1_ram_block2a4_clock_1, , , R1_ram_block2a4_clock_enable_1);
R1_ram_block2a4_clock_0 = GLOBAL(M1L2);
R1_ram_block2a4_clock_1 = GND;
R1_ram_block2a4_clock_enable_0 = S3L10;
R1_ram_block2a4_clock_enable_1 = GND;
R1_ram_block2a4_PORT_A_data_out = MEMORY(R1_ram_block2a4_PORT_A_data_in_reg, R1_ram_block2a4_PORT_B_data_in_reg, R1_ram_block2a4_PORT_A_address_reg, R1_ram_block2a4_PORT_B_address_reg, R1_ram_block2a4_PORT_A_write_enable_reg, R1_ram_block2a4_PORT_B_write_enable_reg, , , R1_ram_block2a4_clock_0, R1_ram_block2a4_clock_1, R1_ram_block2a4_clock_enable_0, R1_ram_block2a4_clock_enable_1, , );
R1_ram_block2a4_PORT_A_data_out_reg = DFFE(R1_ram_block2a4_PORT_A_data_out, R1_ram_block2a4_clock_0, , , R1_ram_block2a4_clock_enable_0);
R1M263Q = R1_ram_block2a4_PORT_A_data_out_reg[7];


--T1L214 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6388w~44 at LCCOMB_X38_Y13_N20
T1L214 = R1_address_reg_a[6] & (R1_address_reg_a[7] # R1M314Q) # !R1_address_reg_a[6] & !R1_address_reg_a[7] & R1M261Q;


--R1_ram_block2a7 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7 at M4K_X41_Y5
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = GLOBAL(M1L2);
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7 = R1_ram_block2a7_PORT_A_data_out_reg[0];

--R1M416Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT1 at M4K_X41_Y5
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = GLOBAL(M1L2);
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1M416Q = R1_ram_block2a7_PORT_A_data_out_reg[1];

--R1M417Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT2 at M4K_X41_Y5
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = GLOBAL(M1L2);
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1M417Q = R1_ram_block2a7_PORT_A_data_out_reg[2];

--R1M418Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT3 at M4K_X41_Y5
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = GLOBAL(M1L2);
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1M418Q = R1_ram_block2a7_PORT_A_data_out_reg[3];

--R1M419Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT4 at M4K_X41_Y5
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = GLOBAL(M1L2);
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1M419Q = R1_ram_block2a7_PORT_A_data_out_reg[4];

--R1M420Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT5 at M4K_X41_Y5
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = GLOBAL(M1L2);
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1M420Q = R1_ram_block2a7_PORT_A_data_out_reg[5];

--R1M421Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT6 at M4K_X41_Y5
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = GLOBAL(M1L2);
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1M421Q = R1_ram_block2a7_PORT_A_data_out_reg[6];

--R1M422Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a7~PORTADATAOUT7 at M4K_X41_Y5
R1_ram_block2a7_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a7_PORT_A_data_in_reg = DFFE(R1_ram_block2a7_PORT_A_data_in, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_data_in = ~GND;
R1_ram_block2a7_PORT_B_data_in_reg = DFFE(R1_ram_block2a7_PORT_B_data_in, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a7_PORT_A_address_reg = DFFE(R1_ram_block2a7_PORT_A_address, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a7_PORT_B_address_reg = DFFE(R1_ram_block2a7_PORT_B_address, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_PORT_A_write_enable = GND;
R1_ram_block2a7_PORT_A_write_enable_reg = DFFE(R1_ram_block2a7_PORT_A_write_enable, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1_ram_block2a7_PORT_B_write_enable = GND;
R1_ram_block2a7_PORT_B_write_enable_reg = DFFE(R1_ram_block2a7_PORT_B_write_enable, R1_ram_block2a7_clock_1, , , R1_ram_block2a7_clock_enable_1);
R1_ram_block2a7_clock_0 = GLOBAL(M1L2);
R1_ram_block2a7_clock_1 = GND;
R1_ram_block2a7_clock_enable_0 = S3_w_anode2929w[3];
R1_ram_block2a7_clock_enable_1 = GND;
R1_ram_block2a7_PORT_A_data_out = MEMORY(R1_ram_block2a7_PORT_A_data_in_reg, R1_ram_block2a7_PORT_B_data_in_reg, R1_ram_block2a7_PORT_A_address_reg, R1_ram_block2a7_PORT_B_address_reg, R1_ram_block2a7_PORT_A_write_enable_reg, R1_ram_block2a7_PORT_B_write_enable_reg, , , R1_ram_block2a7_clock_0, R1_ram_block2a7_clock_1, R1_ram_block2a7_clock_enable_0, R1_ram_block2a7_clock_enable_1, , );
R1_ram_block2a7_PORT_A_data_out_reg = DFFE(R1_ram_block2a7_PORT_A_data_out, R1_ram_block2a7_clock_0, , , R1_ram_block2a7_clock_enable_0);
R1M422Q = R1_ram_block2a7_PORT_A_data_out_reg[7];


--T1L215 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6388w~45 at LCCOMB_X38_Y13_N28
T1L215 = R1_address_reg_a[7] & (T1L214 & R1M420Q # !T1L214 & (R1M367Q)) # !R1_address_reg_a[7] & (T1L214);


--T1L234 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~575 at LCCOMB_X38_Y13_N14
T1L234 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L227 # !R1_address_reg_a[11] & (T1L215));


--T1L235 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~576 at LCCOMB_X38_Y13_N16
T1L235 = T1L147 # T1L232 & (T1L233 # T1L234);


--T1L236 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~577 at LCCOMB_X38_Y12_N18
T1L236 = !R1_address_reg_a[8] & !R1_address_reg_a[9] & !R1_address_reg_a[10];


--R1_ram_block2a33 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33 at M4K_X17_Y21
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = GLOBAL(M1L2);
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33 = R1_ram_block2a33_PORT_A_data_out_reg[0];

--R1M1794Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT1 at M4K_X17_Y21
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = GLOBAL(M1L2);
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1M1794Q = R1_ram_block2a33_PORT_A_data_out_reg[1];

--R1M1795Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT2 at M4K_X17_Y21
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = GLOBAL(M1L2);
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1M1795Q = R1_ram_block2a33_PORT_A_data_out_reg[2];

--R1M1796Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT3 at M4K_X17_Y21
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = GLOBAL(M1L2);
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1M1796Q = R1_ram_block2a33_PORT_A_data_out_reg[3];

--R1M1797Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT4 at M4K_X17_Y21
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = GLOBAL(M1L2);
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1M1797Q = R1_ram_block2a33_PORT_A_data_out_reg[4];

--R1M1798Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT5 at M4K_X17_Y21
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = GLOBAL(M1L2);
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1M1798Q = R1_ram_block2a33_PORT_A_data_out_reg[5];

--R1M1799Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT6 at M4K_X17_Y21
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = GLOBAL(M1L2);
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1M1799Q = R1_ram_block2a33_PORT_A_data_out_reg[6];

--R1M1800Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a33~PORTADATAOUT7 at M4K_X17_Y21
R1_ram_block2a33_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a33_PORT_A_data_in_reg = DFFE(R1_ram_block2a33_PORT_A_data_in, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_data_in = ~GND;
R1_ram_block2a33_PORT_B_data_in_reg = DFFE(R1_ram_block2a33_PORT_B_data_in, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a33_PORT_A_address_reg = DFFE(R1_ram_block2a33_PORT_A_address, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a33_PORT_B_address_reg = DFFE(R1_ram_block2a33_PORT_B_address, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_PORT_A_write_enable = GND;
R1_ram_block2a33_PORT_A_write_enable_reg = DFFE(R1_ram_block2a33_PORT_A_write_enable, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1_ram_block2a33_PORT_B_write_enable = GND;
R1_ram_block2a33_PORT_B_write_enable_reg = DFFE(R1_ram_block2a33_PORT_B_write_enable, R1_ram_block2a33_clock_1, , , R1_ram_block2a33_clock_enable_1);
R1_ram_block2a33_clock_0 = GLOBAL(M1L2);
R1_ram_block2a33_clock_1 = GND;
R1_ram_block2a33_clock_enable_0 = S3_w_anode3242w[3];
R1_ram_block2a33_clock_enable_1 = GND;
R1_ram_block2a33_PORT_A_data_out = MEMORY(R1_ram_block2a33_PORT_A_data_in_reg, R1_ram_block2a33_PORT_B_data_in_reg, R1_ram_block2a33_PORT_A_address_reg, R1_ram_block2a33_PORT_B_address_reg, R1_ram_block2a33_PORT_A_write_enable_reg, R1_ram_block2a33_PORT_B_write_enable_reg, , , R1_ram_block2a33_clock_0, R1_ram_block2a33_clock_1, R1_ram_block2a33_clock_enable_0, R1_ram_block2a33_clock_enable_1, , );
R1_ram_block2a33_PORT_A_data_out_reg = DFFE(R1_ram_block2a33_PORT_A_data_out, R1_ram_block2a33_clock_0, , , R1_ram_block2a33_clock_enable_0);
R1M1800Q = R1_ram_block2a33_PORT_A_data_out_reg[7];


--R1_ram_block2a34 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34 at M4K_X17_Y22
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = GLOBAL(M1L2);
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34 = R1_ram_block2a34_PORT_A_data_out_reg[0];

--R1M1847Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT1 at M4K_X17_Y22
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = GLOBAL(M1L2);
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1M1847Q = R1_ram_block2a34_PORT_A_data_out_reg[1];

--R1M1848Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT2 at M4K_X17_Y22
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = GLOBAL(M1L2);
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1M1848Q = R1_ram_block2a34_PORT_A_data_out_reg[2];

--R1M1849Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT3 at M4K_X17_Y22
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = GLOBAL(M1L2);
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1M1849Q = R1_ram_block2a34_PORT_A_data_out_reg[3];

--R1M1850Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT4 at M4K_X17_Y22
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = GLOBAL(M1L2);
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1M1850Q = R1_ram_block2a34_PORT_A_data_out_reg[4];

--R1M1851Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT5 at M4K_X17_Y22
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = GLOBAL(M1L2);
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1M1851Q = R1_ram_block2a34_PORT_A_data_out_reg[5];

--R1M1852Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT6 at M4K_X17_Y22
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = GLOBAL(M1L2);
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1M1852Q = R1_ram_block2a34_PORT_A_data_out_reg[6];

--R1M1853Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a34~PORTADATAOUT7 at M4K_X17_Y22
R1_ram_block2a34_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a34_PORT_A_data_in_reg = DFFE(R1_ram_block2a34_PORT_A_data_in, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_data_in = ~GND;
R1_ram_block2a34_PORT_B_data_in_reg = DFFE(R1_ram_block2a34_PORT_B_data_in, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a34_PORT_A_address_reg = DFFE(R1_ram_block2a34_PORT_A_address, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a34_PORT_B_address_reg = DFFE(R1_ram_block2a34_PORT_B_address, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_PORT_A_write_enable = GND;
R1_ram_block2a34_PORT_A_write_enable_reg = DFFE(R1_ram_block2a34_PORT_A_write_enable, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1_ram_block2a34_PORT_B_write_enable = GND;
R1_ram_block2a34_PORT_B_write_enable_reg = DFFE(R1_ram_block2a34_PORT_B_write_enable, R1_ram_block2a34_clock_1, , , R1_ram_block2a34_clock_enable_1);
R1_ram_block2a34_clock_0 = GLOBAL(M1L2);
R1_ram_block2a34_clock_1 = GND;
R1_ram_block2a34_clock_enable_0 = S3_w_anode3252w[3];
R1_ram_block2a34_clock_enable_1 = GND;
R1_ram_block2a34_PORT_A_data_out = MEMORY(R1_ram_block2a34_PORT_A_data_in_reg, R1_ram_block2a34_PORT_B_data_in_reg, R1_ram_block2a34_PORT_A_address_reg, R1_ram_block2a34_PORT_B_address_reg, R1_ram_block2a34_PORT_A_write_enable_reg, R1_ram_block2a34_PORT_B_write_enable_reg, , , R1_ram_block2a34_clock_0, R1_ram_block2a34_clock_1, R1_ram_block2a34_clock_enable_0, R1_ram_block2a34_clock_enable_1, , );
R1_ram_block2a34_PORT_A_data_out_reg = DFFE(R1_ram_block2a34_PORT_A_data_out, R1_ram_block2a34_clock_0, , , R1_ram_block2a34_clock_enable_0);
R1M1853Q = R1_ram_block2a34_PORT_A_data_out_reg[7];


--R1_ram_block2a32 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32 at M4K_X17_Y24
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = GLOBAL(M1L2);
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32 = R1_ram_block2a32_PORT_A_data_out_reg[0];

--R1M1741Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT1 at M4K_X17_Y24
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = GLOBAL(M1L2);
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1M1741Q = R1_ram_block2a32_PORT_A_data_out_reg[1];

--R1M1742Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT2 at M4K_X17_Y24
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = GLOBAL(M1L2);
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1M1742Q = R1_ram_block2a32_PORT_A_data_out_reg[2];

--R1M1743Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT3 at M4K_X17_Y24
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = GLOBAL(M1L2);
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1M1743Q = R1_ram_block2a32_PORT_A_data_out_reg[3];

--R1M1744Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT4 at M4K_X17_Y24
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = GLOBAL(M1L2);
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1M1744Q = R1_ram_block2a32_PORT_A_data_out_reg[4];

--R1M1745Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT5 at M4K_X17_Y24
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = GLOBAL(M1L2);
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1M1745Q = R1_ram_block2a32_PORT_A_data_out_reg[5];

--R1M1746Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT6 at M4K_X17_Y24
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = GLOBAL(M1L2);
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1M1746Q = R1_ram_block2a32_PORT_A_data_out_reg[6];

--R1M1747Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a32~PORTADATAOUT7 at M4K_X17_Y24
R1_ram_block2a32_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a32_PORT_A_data_in_reg = DFFE(R1_ram_block2a32_PORT_A_data_in, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_data_in = ~GND;
R1_ram_block2a32_PORT_B_data_in_reg = DFFE(R1_ram_block2a32_PORT_B_data_in, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a32_PORT_A_address_reg = DFFE(R1_ram_block2a32_PORT_A_address, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a32_PORT_B_address_reg = DFFE(R1_ram_block2a32_PORT_B_address, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_PORT_A_write_enable = GND;
R1_ram_block2a32_PORT_A_write_enable_reg = DFFE(R1_ram_block2a32_PORT_A_write_enable, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1_ram_block2a32_PORT_B_write_enable = GND;
R1_ram_block2a32_PORT_B_write_enable_reg = DFFE(R1_ram_block2a32_PORT_B_write_enable, R1_ram_block2a32_clock_1, , , R1_ram_block2a32_clock_enable_1);
R1_ram_block2a32_clock_0 = GLOBAL(M1L2);
R1_ram_block2a32_clock_1 = GND;
R1_ram_block2a32_clock_enable_0 = S3_w_anode3231w[3];
R1_ram_block2a32_clock_enable_1 = GND;
R1_ram_block2a32_PORT_A_data_out = MEMORY(R1_ram_block2a32_PORT_A_data_in_reg, R1_ram_block2a32_PORT_B_data_in_reg, R1_ram_block2a32_PORT_A_address_reg, R1_ram_block2a32_PORT_B_address_reg, R1_ram_block2a32_PORT_A_write_enable_reg, R1_ram_block2a32_PORT_B_write_enable_reg, , , R1_ram_block2a32_clock_0, R1_ram_block2a32_clock_1, R1_ram_block2a32_clock_enable_0, R1_ram_block2a32_clock_enable_1, , );
R1_ram_block2a32_PORT_A_data_out_reg = DFFE(R1_ram_block2a32_PORT_A_data_out, R1_ram_block2a32_clock_0, , , R1_ram_block2a32_clock_enable_0);
R1M1747Q = R1_ram_block2a32_PORT_A_data_out_reg[7];


--T1L230 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6673w~281 at LCCOMB_X38_Y15_N24
T1L230 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & (R1M1851Q) # !R1_address_reg_a[7] & R1M1745Q);


--R1_ram_block2a35 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35 at M4K_X41_Y25
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = GLOBAL(M1L2);
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35 = R1_ram_block2a35_PORT_A_data_out_reg[0];

--R1M1900Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT1 at M4K_X41_Y25
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = GLOBAL(M1L2);
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1M1900Q = R1_ram_block2a35_PORT_A_data_out_reg[1];

--R1M1901Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT2 at M4K_X41_Y25
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = GLOBAL(M1L2);
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1M1901Q = R1_ram_block2a35_PORT_A_data_out_reg[2];

--R1M1902Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT3 at M4K_X41_Y25
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = GLOBAL(M1L2);
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1M1902Q = R1_ram_block2a35_PORT_A_data_out_reg[3];

--R1M1903Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT4 at M4K_X41_Y25
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = GLOBAL(M1L2);
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1M1903Q = R1_ram_block2a35_PORT_A_data_out_reg[4];

--R1M1904Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT5 at M4K_X41_Y25
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = GLOBAL(M1L2);
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1M1904Q = R1_ram_block2a35_PORT_A_data_out_reg[5];

--R1M1905Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT6 at M4K_X41_Y25
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = GLOBAL(M1L2);
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1M1905Q = R1_ram_block2a35_PORT_A_data_out_reg[6];

--R1M1906Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a35~PORTADATAOUT7 at M4K_X41_Y25
R1_ram_block2a35_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a35_PORT_A_data_in_reg = DFFE(R1_ram_block2a35_PORT_A_data_in, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_data_in = ~GND;
R1_ram_block2a35_PORT_B_data_in_reg = DFFE(R1_ram_block2a35_PORT_B_data_in, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a35_PORT_A_address_reg = DFFE(R1_ram_block2a35_PORT_A_address, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a35_PORT_B_address_reg = DFFE(R1_ram_block2a35_PORT_B_address, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_PORT_A_write_enable = GND;
R1_ram_block2a35_PORT_A_write_enable_reg = DFFE(R1_ram_block2a35_PORT_A_write_enable, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1_ram_block2a35_PORT_B_write_enable = GND;
R1_ram_block2a35_PORT_B_write_enable_reg = DFFE(R1_ram_block2a35_PORT_B_write_enable, R1_ram_block2a35_clock_1, , , R1_ram_block2a35_clock_enable_1);
R1_ram_block2a35_clock_0 = GLOBAL(M1L2);
R1_ram_block2a35_clock_1 = GND;
R1_ram_block2a35_clock_enable_0 = S3_w_anode3262w[3];
R1_ram_block2a35_clock_enable_1 = GND;
R1_ram_block2a35_PORT_A_data_out = MEMORY(R1_ram_block2a35_PORT_A_data_in_reg, R1_ram_block2a35_PORT_B_data_in_reg, R1_ram_block2a35_PORT_A_address_reg, R1_ram_block2a35_PORT_B_address_reg, R1_ram_block2a35_PORT_A_write_enable_reg, R1_ram_block2a35_PORT_B_write_enable_reg, , , R1_ram_block2a35_clock_0, R1_ram_block2a35_clock_1, R1_ram_block2a35_clock_enable_0, R1_ram_block2a35_clock_enable_1, , );
R1_ram_block2a35_PORT_A_data_out_reg = DFFE(R1_ram_block2a35_PORT_A_data_out, R1_ram_block2a35_clock_0, , , R1_ram_block2a35_clock_enable_0);
R1M1906Q = R1_ram_block2a35_PORT_A_data_out_reg[7];


--T1L231 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6673w~282 at LCCOMB_X38_Y15_N14
T1L231 = R1_address_reg_a[6] & (T1L230 & R1M1904Q # !T1L230 & (R1M1798Q)) # !R1_address_reg_a[6] & (T1L230);


--R1_ram_block2a2 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2 at M4K_X41_Y22
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = GLOBAL(M1L2);
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2 = R1_ram_block2a2_PORT_A_data_out_reg[0];

--R1M151Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT1 at M4K_X41_Y22
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = GLOBAL(M1L2);
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1M151Q = R1_ram_block2a2_PORT_A_data_out_reg[1];

--R1M152Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT2 at M4K_X41_Y22
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = GLOBAL(M1L2);
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1M152Q = R1_ram_block2a2_PORT_A_data_out_reg[2];

--R1M153Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT3 at M4K_X41_Y22
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = GLOBAL(M1L2);
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1M153Q = R1_ram_block2a2_PORT_A_data_out_reg[3];

--R1M154Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT4 at M4K_X41_Y22
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = GLOBAL(M1L2);
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1M154Q = R1_ram_block2a2_PORT_A_data_out_reg[4];

--R1M155Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT5 at M4K_X41_Y22
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = GLOBAL(M1L2);
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1M155Q = R1_ram_block2a2_PORT_A_data_out_reg[5];

--R1M156Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT6 at M4K_X41_Y22
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = GLOBAL(M1L2);
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1M156Q = R1_ram_block2a2_PORT_A_data_out_reg[6];

--R1M157Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a2~PORTADATAOUT7 at M4K_X41_Y22
R1_ram_block2a2_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a2_PORT_A_data_in_reg = DFFE(R1_ram_block2a2_PORT_A_data_in, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_data_in = ~GND;
R1_ram_block2a2_PORT_B_data_in_reg = DFFE(R1_ram_block2a2_PORT_B_data_in, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a2_PORT_A_address_reg = DFFE(R1_ram_block2a2_PORT_A_address, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a2_PORT_B_address_reg = DFFE(R1_ram_block2a2_PORT_B_address, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_PORT_A_write_enable = GND;
R1_ram_block2a2_PORT_A_write_enable_reg = DFFE(R1_ram_block2a2_PORT_A_write_enable, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1_ram_block2a2_PORT_B_write_enable = GND;
R1_ram_block2a2_PORT_B_write_enable_reg = DFFE(R1_ram_block2a2_PORT_B_write_enable, R1_ram_block2a2_clock_1, , , R1_ram_block2a2_clock_enable_1);
R1_ram_block2a2_clock_0 = GLOBAL(M1L2);
R1_ram_block2a2_clock_1 = GND;
R1_ram_block2a2_clock_enable_0 = S3L6;
R1_ram_block2a2_clock_enable_1 = GND;
R1_ram_block2a2_PORT_A_data_out = MEMORY(R1_ram_block2a2_PORT_A_data_in_reg, R1_ram_block2a2_PORT_B_data_in_reg, R1_ram_block2a2_PORT_A_address_reg, R1_ram_block2a2_PORT_B_address_reg, R1_ram_block2a2_PORT_A_write_enable_reg, R1_ram_block2a2_PORT_B_write_enable_reg, , , R1_ram_block2a2_clock_0, R1_ram_block2a2_clock_1, R1_ram_block2a2_clock_enable_0, R1_ram_block2a2_clock_enable_1, , );
R1_ram_block2a2_PORT_A_data_out_reg = DFFE(R1_ram_block2a2_PORT_A_data_out, R1_ram_block2a2_clock_0, , , R1_ram_block2a2_clock_enable_0);
R1M157Q = R1_ram_block2a2_PORT_A_data_out_reg[7];


--R1_ram_block2a1 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1 at M4K_X41_Y17
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = GLOBAL(M1L2);
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1 = R1_ram_block2a1_PORT_A_data_out_reg[0];

--R1M98Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT1 at M4K_X41_Y17
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = GLOBAL(M1L2);
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1M98Q = R1_ram_block2a1_PORT_A_data_out_reg[1];

--R1M99Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT2 at M4K_X41_Y17
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = GLOBAL(M1L2);
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1M99Q = R1_ram_block2a1_PORT_A_data_out_reg[2];

--R1M100Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT3 at M4K_X41_Y17
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = GLOBAL(M1L2);
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1M100Q = R1_ram_block2a1_PORT_A_data_out_reg[3];

--R1M101Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT4 at M4K_X41_Y17
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = GLOBAL(M1L2);
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1M101Q = R1_ram_block2a1_PORT_A_data_out_reg[4];

--R1M102Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT5 at M4K_X41_Y17
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = GLOBAL(M1L2);
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1M102Q = R1_ram_block2a1_PORT_A_data_out_reg[5];

--R1M103Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT6 at M4K_X41_Y17
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = GLOBAL(M1L2);
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1M103Q = R1_ram_block2a1_PORT_A_data_out_reg[6];

--R1M104Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a1~PORTADATAOUT7 at M4K_X41_Y17
R1_ram_block2a1_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a1_PORT_A_data_in_reg = DFFE(R1_ram_block2a1_PORT_A_data_in, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_data_in = ~GND;
R1_ram_block2a1_PORT_B_data_in_reg = DFFE(R1_ram_block2a1_PORT_B_data_in, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a1_PORT_A_address_reg = DFFE(R1_ram_block2a1_PORT_A_address, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a1_PORT_B_address_reg = DFFE(R1_ram_block2a1_PORT_B_address, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_PORT_A_write_enable = GND;
R1_ram_block2a1_PORT_A_write_enable_reg = DFFE(R1_ram_block2a1_PORT_A_write_enable, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1_ram_block2a1_PORT_B_write_enable = GND;
R1_ram_block2a1_PORT_B_write_enable_reg = DFFE(R1_ram_block2a1_PORT_B_write_enable, R1_ram_block2a1_clock_1, , , R1_ram_block2a1_clock_enable_1);
R1_ram_block2a1_clock_0 = GLOBAL(M1L2);
R1_ram_block2a1_clock_1 = GND;
R1_ram_block2a1_clock_enable_0 = S3_w_anode2869w[3];
R1_ram_block2a1_clock_enable_1 = GND;
R1_ram_block2a1_PORT_A_data_out = MEMORY(R1_ram_block2a1_PORT_A_data_in_reg, R1_ram_block2a1_PORT_B_data_in_reg, R1_ram_block2a1_PORT_A_address_reg, R1_ram_block2a1_PORT_B_address_reg, R1_ram_block2a1_PORT_A_write_enable_reg, R1_ram_block2a1_PORT_B_write_enable_reg, , , R1_ram_block2a1_clock_0, R1_ram_block2a1_clock_1, R1_ram_block2a1_clock_enable_0, R1_ram_block2a1_clock_enable_1, , );
R1_ram_block2a1_PORT_A_data_out_reg = DFFE(R1_ram_block2a1_PORT_A_data_out, R1_ram_block2a1_clock_0, , , R1_ram_block2a1_clock_enable_0);
R1M104Q = R1_ram_block2a1_PORT_A_data_out_reg[7];


--R1_ram_block2a0 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0 at M4K_X17_Y17
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = GLOBAL(M1L2);
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0 = R1_ram_block2a0_PORT_A_data_out_reg[0];

--R1M45Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT1 at M4K_X17_Y17
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = GLOBAL(M1L2);
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1M45Q = R1_ram_block2a0_PORT_A_data_out_reg[1];

--R1M46Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT2 at M4K_X17_Y17
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = GLOBAL(M1L2);
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1M46Q = R1_ram_block2a0_PORT_A_data_out_reg[2];

--R1M47Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT3 at M4K_X17_Y17
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = GLOBAL(M1L2);
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1M47Q = R1_ram_block2a0_PORT_A_data_out_reg[3];

--R1M48Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT4 at M4K_X17_Y17
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = GLOBAL(M1L2);
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1M48Q = R1_ram_block2a0_PORT_A_data_out_reg[4];

--R1M49Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT5 at M4K_X17_Y17
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = GLOBAL(M1L2);
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1M49Q = R1_ram_block2a0_PORT_A_data_out_reg[5];

--R1M50Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT6 at M4K_X17_Y17
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = GLOBAL(M1L2);
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1M50Q = R1_ram_block2a0_PORT_A_data_out_reg[6];

--R1M51Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a0~PORTADATAOUT7 at M4K_X17_Y17
R1_ram_block2a0_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a0_PORT_A_data_in_reg = DFFE(R1_ram_block2a0_PORT_A_data_in, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_data_in = ~GND;
R1_ram_block2a0_PORT_B_data_in_reg = DFFE(R1_ram_block2a0_PORT_B_data_in, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a0_PORT_A_address_reg = DFFE(R1_ram_block2a0_PORT_A_address, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a0_PORT_B_address_reg = DFFE(R1_ram_block2a0_PORT_B_address, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_PORT_A_write_enable = GND;
R1_ram_block2a0_PORT_A_write_enable_reg = DFFE(R1_ram_block2a0_PORT_A_write_enable, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1_ram_block2a0_PORT_B_write_enable = GND;
R1_ram_block2a0_PORT_B_write_enable_reg = DFFE(R1_ram_block2a0_PORT_B_write_enable, R1_ram_block2a0_clock_1, , , );
R1_ram_block2a0_clock_0 = GLOBAL(M1L2);
R1_ram_block2a0_clock_1 = GND;
R1_ram_block2a0_clock_enable_0 = S3_w_anode2852w[3];
R1_ram_block2a0_PORT_A_data_out = MEMORY(R1_ram_block2a0_PORT_A_data_in_reg, R1_ram_block2a0_PORT_B_data_in_reg, R1_ram_block2a0_PORT_A_address_reg, R1_ram_block2a0_PORT_B_address_reg, R1_ram_block2a0_PORT_A_write_enable_reg, R1_ram_block2a0_PORT_B_write_enable_reg, , , R1_ram_block2a0_clock_0, R1_ram_block2a0_clock_1, R1_ram_block2a0_clock_enable_0, , , );
R1_ram_block2a0_PORT_A_data_out_reg = DFFE(R1_ram_block2a0_PORT_A_data_out, R1_ram_block2a0_clock_0, , , R1_ram_block2a0_clock_enable_0);
R1M51Q = R1_ram_block2a0_PORT_A_data_out_reg[7];


--T1L218 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6473w~281 at LCCOMB_X38_Y15_N8
T1L218 = R1_address_reg_a[6] & (R1_address_reg_a[7] # R1M102Q) # !R1_address_reg_a[6] & R1M49Q & !R1_address_reg_a[7];


--R1_ram_block2a3 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3 at M4K_X41_Y24
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = GLOBAL(M1L2);
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3 = R1_ram_block2a3_PORT_A_data_out_reg[0];

--R1M204Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT1 at M4K_X41_Y24
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = GLOBAL(M1L2);
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1M204Q = R1_ram_block2a3_PORT_A_data_out_reg[1];

--R1M205Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT2 at M4K_X41_Y24
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = GLOBAL(M1L2);
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1M205Q = R1_ram_block2a3_PORT_A_data_out_reg[2];

--R1M206Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT3 at M4K_X41_Y24
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = GLOBAL(M1L2);
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1M206Q = R1_ram_block2a3_PORT_A_data_out_reg[3];

--R1M207Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT4 at M4K_X41_Y24
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = GLOBAL(M1L2);
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1M207Q = R1_ram_block2a3_PORT_A_data_out_reg[4];

--R1M208Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT5 at M4K_X41_Y24
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = GLOBAL(M1L2);
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1M208Q = R1_ram_block2a3_PORT_A_data_out_reg[5];

--R1M209Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT6 at M4K_X41_Y24
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = GLOBAL(M1L2);
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1M209Q = R1_ram_block2a3_PORT_A_data_out_reg[6];

--R1M210Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a3~PORTADATAOUT7 at M4K_X41_Y24
R1_ram_block2a3_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a3_PORT_A_data_in_reg = DFFE(R1_ram_block2a3_PORT_A_data_in, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_data_in = ~GND;
R1_ram_block2a3_PORT_B_data_in_reg = DFFE(R1_ram_block2a3_PORT_B_data_in, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a3_PORT_A_address_reg = DFFE(R1_ram_block2a3_PORT_A_address, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a3_PORT_B_address_reg = DFFE(R1_ram_block2a3_PORT_B_address, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_PORT_A_write_enable = GND;
R1_ram_block2a3_PORT_A_write_enable_reg = DFFE(R1_ram_block2a3_PORT_A_write_enable, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1_ram_block2a3_PORT_B_write_enable = GND;
R1_ram_block2a3_PORT_B_write_enable_reg = DFFE(R1_ram_block2a3_PORT_B_write_enable, R1_ram_block2a3_clock_1, , , R1_ram_block2a3_clock_enable_1);
R1_ram_block2a3_clock_0 = GLOBAL(M1L2);
R1_ram_block2a3_clock_1 = GND;
R1_ram_block2a3_clock_enable_0 = S3_w_anode2889w[3];
R1_ram_block2a3_clock_enable_1 = GND;
R1_ram_block2a3_PORT_A_data_out = MEMORY(R1_ram_block2a3_PORT_A_data_in_reg, R1_ram_block2a3_PORT_B_data_in_reg, R1_ram_block2a3_PORT_A_address_reg, R1_ram_block2a3_PORT_B_address_reg, R1_ram_block2a3_PORT_A_write_enable_reg, R1_ram_block2a3_PORT_B_write_enable_reg, , , R1_ram_block2a3_clock_0, R1_ram_block2a3_clock_1, R1_ram_block2a3_clock_enable_0, R1_ram_block2a3_clock_enable_1, , );
R1_ram_block2a3_PORT_A_data_out_reg = DFFE(R1_ram_block2a3_PORT_A_data_out, R1_ram_block2a3_clock_0, , , R1_ram_block2a3_clock_enable_0);
R1M210Q = R1_ram_block2a3_PORT_A_data_out_reg[7];


--T1L219 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6473w~282 at LCCOMB_X38_Y15_N18
T1L219 = T1L218 & (R1M208Q # !R1_address_reg_a[7]) # !T1L218 & (R1_address_reg_a[7] & R1M155Q);


--T1L237 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~578 at LCCOMB_X38_Y13_N12
T1L237 = T1L236 & (R1_address_reg_a[11] & (T1L231) # !R1_address_reg_a[11] & T1L219);


--R1_ram_block2a41 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41 at M4K_X17_Y19
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = GLOBAL(M1L2);
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41 = R1_ram_block2a41_PORT_A_data_out_reg[0];

--R1M2218Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT1 at M4K_X17_Y19
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = GLOBAL(M1L2);
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1M2218Q = R1_ram_block2a41_PORT_A_data_out_reg[1];

--R1M2219Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT2 at M4K_X17_Y19
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = GLOBAL(M1L2);
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1M2219Q = R1_ram_block2a41_PORT_A_data_out_reg[2];

--R1M2220Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT3 at M4K_X17_Y19
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = GLOBAL(M1L2);
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1M2220Q = R1_ram_block2a41_PORT_A_data_out_reg[3];

--R1M2221Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT4 at M4K_X17_Y19
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = GLOBAL(M1L2);
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1M2221Q = R1_ram_block2a41_PORT_A_data_out_reg[4];

--R1M2222Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT5 at M4K_X17_Y19
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = GLOBAL(M1L2);
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1M2222Q = R1_ram_block2a41_PORT_A_data_out_reg[5];

--R1M2223Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT6 at M4K_X17_Y19
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = GLOBAL(M1L2);
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1M2223Q = R1_ram_block2a41_PORT_A_data_out_reg[6];

--R1M2224Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a41~PORTADATAOUT7 at M4K_X17_Y19
R1_ram_block2a41_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a41_PORT_A_data_in_reg = DFFE(R1_ram_block2a41_PORT_A_data_in, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_data_in = ~GND;
R1_ram_block2a41_PORT_B_data_in_reg = DFFE(R1_ram_block2a41_PORT_B_data_in, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a41_PORT_A_address_reg = DFFE(R1_ram_block2a41_PORT_A_address, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a41_PORT_B_address_reg = DFFE(R1_ram_block2a41_PORT_B_address, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_PORT_A_write_enable = GND;
R1_ram_block2a41_PORT_A_write_enable_reg = DFFE(R1_ram_block2a41_PORT_A_write_enable, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1_ram_block2a41_PORT_B_write_enable = GND;
R1_ram_block2a41_PORT_B_write_enable_reg = DFFE(R1_ram_block2a41_PORT_B_write_enable, R1_ram_block2a41_clock_1, , , R1_ram_block2a41_clock_enable_1);
R1_ram_block2a41_clock_0 = GLOBAL(M1L2);
R1_ram_block2a41_clock_1 = GND;
R1_ram_block2a41_clock_enable_0 = S3_w_anode3335w[3];
R1_ram_block2a41_clock_enable_1 = GND;
R1_ram_block2a41_PORT_A_data_out = MEMORY(R1_ram_block2a41_PORT_A_data_in_reg, R1_ram_block2a41_PORT_B_data_in_reg, R1_ram_block2a41_PORT_A_address_reg, R1_ram_block2a41_PORT_B_address_reg, R1_ram_block2a41_PORT_A_write_enable_reg, R1_ram_block2a41_PORT_B_write_enable_reg, , , R1_ram_block2a41_clock_0, R1_ram_block2a41_clock_1, R1_ram_block2a41_clock_enable_0, R1_ram_block2a41_clock_enable_1, , );
R1_ram_block2a41_PORT_A_data_out_reg = DFFE(R1_ram_block2a41_PORT_A_data_out, R1_ram_block2a41_clock_0, , , R1_ram_block2a41_clock_enable_0);
R1M2224Q = R1_ram_block2a41_PORT_A_data_out_reg[7];


--R1_ram_block2a40 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40 at M4K_X17_Y20
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = GLOBAL(M1L2);
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40 = R1_ram_block2a40_PORT_A_data_out_reg[0];

--R1M2165Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT1 at M4K_X17_Y20
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = GLOBAL(M1L2);
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1M2165Q = R1_ram_block2a40_PORT_A_data_out_reg[1];

--R1M2166Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT2 at M4K_X17_Y20
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = GLOBAL(M1L2);
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1M2166Q = R1_ram_block2a40_PORT_A_data_out_reg[2];

--R1M2167Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT3 at M4K_X17_Y20
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = GLOBAL(M1L2);
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1M2167Q = R1_ram_block2a40_PORT_A_data_out_reg[3];

--R1M2168Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT4 at M4K_X17_Y20
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = GLOBAL(M1L2);
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1M2168Q = R1_ram_block2a40_PORT_A_data_out_reg[4];

--R1M2169Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT5 at M4K_X17_Y20
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = GLOBAL(M1L2);
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1M2169Q = R1_ram_block2a40_PORT_A_data_out_reg[5];

--R1M2170Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT6 at M4K_X17_Y20
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = GLOBAL(M1L2);
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1M2170Q = R1_ram_block2a40_PORT_A_data_out_reg[6];

--R1M2171Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a40~PORTADATAOUT7 at M4K_X17_Y20
R1_ram_block2a40_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a40_PORT_A_data_in_reg = DFFE(R1_ram_block2a40_PORT_A_data_in, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_data_in = ~GND;
R1_ram_block2a40_PORT_B_data_in_reg = DFFE(R1_ram_block2a40_PORT_B_data_in, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a40_PORT_A_address_reg = DFFE(R1_ram_block2a40_PORT_A_address, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a40_PORT_B_address_reg = DFFE(R1_ram_block2a40_PORT_B_address, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_PORT_A_write_enable = GND;
R1_ram_block2a40_PORT_A_write_enable_reg = DFFE(R1_ram_block2a40_PORT_A_write_enable, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1_ram_block2a40_PORT_B_write_enable = GND;
R1_ram_block2a40_PORT_B_write_enable_reg = DFFE(R1_ram_block2a40_PORT_B_write_enable, R1_ram_block2a40_clock_1, , , R1_ram_block2a40_clock_enable_1);
R1_ram_block2a40_clock_0 = GLOBAL(M1L2);
R1_ram_block2a40_clock_1 = GND;
R1_ram_block2a40_clock_enable_0 = S3_w_anode3324w[3];
R1_ram_block2a40_clock_enable_1 = GND;
R1_ram_block2a40_PORT_A_data_out = MEMORY(R1_ram_block2a40_PORT_A_data_in_reg, R1_ram_block2a40_PORT_B_data_in_reg, R1_ram_block2a40_PORT_A_address_reg, R1_ram_block2a40_PORT_B_address_reg, R1_ram_block2a40_PORT_A_write_enable_reg, R1_ram_block2a40_PORT_B_write_enable_reg, , , R1_ram_block2a40_clock_0, R1_ram_block2a40_clock_1, R1_ram_block2a40_clock_enable_0, R1_ram_block2a40_clock_enable_1, , );
R1_ram_block2a40_PORT_A_data_out_reg = DFFE(R1_ram_block2a40_PORT_A_data_out, R1_ram_block2a40_clock_0, , , R1_ram_block2a40_clock_enable_0);
R1M2171Q = R1_ram_block2a40_PORT_A_data_out_reg[7];


--R1_ram_block2a43 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43 at M4K_X17_Y25
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = GLOBAL(M1L2);
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43 = R1_ram_block2a43_PORT_A_data_out_reg[0];

--R1M2324Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT1 at M4K_X17_Y25
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = GLOBAL(M1L2);
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1M2324Q = R1_ram_block2a43_PORT_A_data_out_reg[1];

--R1M2325Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT2 at M4K_X17_Y25
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = GLOBAL(M1L2);
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1M2325Q = R1_ram_block2a43_PORT_A_data_out_reg[2];

--R1M2326Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT3 at M4K_X17_Y25
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = GLOBAL(M1L2);
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1M2326Q = R1_ram_block2a43_PORT_A_data_out_reg[3];

--R1M2327Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT4 at M4K_X17_Y25
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = GLOBAL(M1L2);
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1M2327Q = R1_ram_block2a43_PORT_A_data_out_reg[4];

--R1M2328Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT5 at M4K_X17_Y25
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = GLOBAL(M1L2);
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1M2328Q = R1_ram_block2a43_PORT_A_data_out_reg[5];

--R1M2329Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT6 at M4K_X17_Y25
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = GLOBAL(M1L2);
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1M2329Q = R1_ram_block2a43_PORT_A_data_out_reg[6];

--R1M2330Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a43~PORTADATAOUT7 at M4K_X17_Y25
R1_ram_block2a43_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a43_PORT_A_data_in_reg = DFFE(R1_ram_block2a43_PORT_A_data_in, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_data_in = ~GND;
R1_ram_block2a43_PORT_B_data_in_reg = DFFE(R1_ram_block2a43_PORT_B_data_in, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a43_PORT_A_address_reg = DFFE(R1_ram_block2a43_PORT_A_address, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a43_PORT_B_address_reg = DFFE(R1_ram_block2a43_PORT_B_address, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_PORT_A_write_enable = GND;
R1_ram_block2a43_PORT_A_write_enable_reg = DFFE(R1_ram_block2a43_PORT_A_write_enable, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1_ram_block2a43_PORT_B_write_enable = GND;
R1_ram_block2a43_PORT_B_write_enable_reg = DFFE(R1_ram_block2a43_PORT_B_write_enable, R1_ram_block2a43_clock_1, , , R1_ram_block2a43_clock_enable_1);
R1_ram_block2a43_clock_0 = GLOBAL(M1L2);
R1_ram_block2a43_clock_1 = GND;
R1_ram_block2a43_clock_enable_0 = S3_w_anode3355w[3];
R1_ram_block2a43_clock_enable_1 = GND;
R1_ram_block2a43_PORT_A_data_out = MEMORY(R1_ram_block2a43_PORT_A_data_in_reg, R1_ram_block2a43_PORT_B_data_in_reg, R1_ram_block2a43_PORT_A_address_reg, R1_ram_block2a43_PORT_B_address_reg, R1_ram_block2a43_PORT_A_write_enable_reg, R1_ram_block2a43_PORT_B_write_enable_reg, , , R1_ram_block2a43_clock_0, R1_ram_block2a43_clock_1, R1_ram_block2a43_clock_enable_0, R1_ram_block2a43_clock_enable_1, , );
R1_ram_block2a43_PORT_A_data_out_reg = DFFE(R1_ram_block2a43_PORT_A_data_out, R1_ram_block2a43_clock_0, , , R1_ram_block2a43_clock_enable_0);
R1M2330Q = R1_ram_block2a43_PORT_A_data_out_reg[7];


--R1_ram_block2a42 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42 at M4K_X17_Y18
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = GLOBAL(M1L2);
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42 = R1_ram_block2a42_PORT_A_data_out_reg[0];

--R1M2271Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT1 at M4K_X17_Y18
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = GLOBAL(M1L2);
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1M2271Q = R1_ram_block2a42_PORT_A_data_out_reg[1];

--R1M2272Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT2 at M4K_X17_Y18
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = GLOBAL(M1L2);
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1M2272Q = R1_ram_block2a42_PORT_A_data_out_reg[2];

--R1M2273Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT3 at M4K_X17_Y18
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = GLOBAL(M1L2);
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1M2273Q = R1_ram_block2a42_PORT_A_data_out_reg[3];

--R1M2274Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT4 at M4K_X17_Y18
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = GLOBAL(M1L2);
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1M2274Q = R1_ram_block2a42_PORT_A_data_out_reg[4];

--R1M2275Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT5 at M4K_X17_Y18
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = GLOBAL(M1L2);
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1M2275Q = R1_ram_block2a42_PORT_A_data_out_reg[5];

--R1M2276Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT6 at M4K_X17_Y18
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = GLOBAL(M1L2);
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1M2276Q = R1_ram_block2a42_PORT_A_data_out_reg[6];

--R1M2277Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a42~PORTADATAOUT7 at M4K_X17_Y18
R1_ram_block2a42_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a42_PORT_A_data_in_reg = DFFE(R1_ram_block2a42_PORT_A_data_in, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_data_in = ~GND;
R1_ram_block2a42_PORT_B_data_in_reg = DFFE(R1_ram_block2a42_PORT_B_data_in, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a42_PORT_A_address_reg = DFFE(R1_ram_block2a42_PORT_A_address, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a42_PORT_B_address_reg = DFFE(R1_ram_block2a42_PORT_B_address, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_PORT_A_write_enable = GND;
R1_ram_block2a42_PORT_A_write_enable_reg = DFFE(R1_ram_block2a42_PORT_A_write_enable, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1_ram_block2a42_PORT_B_write_enable = GND;
R1_ram_block2a42_PORT_B_write_enable_reg = DFFE(R1_ram_block2a42_PORT_B_write_enable, R1_ram_block2a42_clock_1, , , R1_ram_block2a42_clock_enable_1);
R1_ram_block2a42_clock_0 = GLOBAL(M1L2);
R1_ram_block2a42_clock_1 = GND;
R1_ram_block2a42_clock_enable_0 = S3_w_anode3345w[3];
R1_ram_block2a42_clock_enable_1 = GND;
R1_ram_block2a42_PORT_A_data_out = MEMORY(R1_ram_block2a42_PORT_A_data_in_reg, R1_ram_block2a42_PORT_B_data_in_reg, R1_ram_block2a42_PORT_A_address_reg, R1_ram_block2a42_PORT_B_address_reg, R1_ram_block2a42_PORT_A_write_enable_reg, R1_ram_block2a42_PORT_B_write_enable_reg, , , R1_ram_block2a42_clock_0, R1_ram_block2a42_clock_1, R1_ram_block2a42_clock_enable_0, R1_ram_block2a42_clock_enable_1, , );
R1_ram_block2a42_PORT_A_data_out_reg = DFFE(R1_ram_block2a42_PORT_A_data_out, R1_ram_block2a42_clock_0, , , R1_ram_block2a42_clock_enable_0);
R1M2277Q = R1_ram_block2a42_PORT_A_data_out_reg[7];


--T1L238 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~579 at LCCOMB_X38_Y15_N30
T1L238 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M2328Q # !R1_address_reg_a[6] & (R1M2275Q)) # !R1_address_reg_a[7] & (R1_address_reg_a[6]);


--T1L239 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~580 at LCCOMB_X38_Y15_N20
T1L239 = R1_address_reg_a[7] & (T1L238) # !R1_address_reg_a[7] & (T1L238 & (R1M2222Q) # !T1L238 & R1M2169Q);


--R1_ram_block2a10 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10 at M4K_X41_Y19
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = GLOBAL(M1L2);
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10 = R1_ram_block2a10_PORT_A_data_out_reg[0];

--R1M575Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT1 at M4K_X41_Y19
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = GLOBAL(M1L2);
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1M575Q = R1_ram_block2a10_PORT_A_data_out_reg[1];

--R1M576Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT2 at M4K_X41_Y19
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = GLOBAL(M1L2);
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1M576Q = R1_ram_block2a10_PORT_A_data_out_reg[2];

--R1M577Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT3 at M4K_X41_Y19
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = GLOBAL(M1L2);
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1M577Q = R1_ram_block2a10_PORT_A_data_out_reg[3];

--R1M578Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT4 at M4K_X41_Y19
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = GLOBAL(M1L2);
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1M578Q = R1_ram_block2a10_PORT_A_data_out_reg[4];

--R1M579Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT5 at M4K_X41_Y19
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = GLOBAL(M1L2);
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1M579Q = R1_ram_block2a10_PORT_A_data_out_reg[5];

--R1M580Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT6 at M4K_X41_Y19
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = GLOBAL(M1L2);
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1M580Q = R1_ram_block2a10_PORT_A_data_out_reg[6];

--R1M581Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a10~PORTADATAOUT7 at M4K_X41_Y19
R1_ram_block2a10_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a10_PORT_A_data_in_reg = DFFE(R1_ram_block2a10_PORT_A_data_in, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_data_in = ~GND;
R1_ram_block2a10_PORT_B_data_in_reg = DFFE(R1_ram_block2a10_PORT_B_data_in, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a10_PORT_A_address_reg = DFFE(R1_ram_block2a10_PORT_A_address, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a10_PORT_B_address_reg = DFFE(R1_ram_block2a10_PORT_B_address, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_PORT_A_write_enable = GND;
R1_ram_block2a10_PORT_A_write_enable_reg = DFFE(R1_ram_block2a10_PORT_A_write_enable, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1_ram_block2a10_PORT_B_write_enable = GND;
R1_ram_block2a10_PORT_B_write_enable_reg = DFFE(R1_ram_block2a10_PORT_B_write_enable, R1_ram_block2a10_clock_1, , , R1_ram_block2a10_clock_enable_1);
R1_ram_block2a10_clock_0 = GLOBAL(M1L2);
R1_ram_block2a10_clock_1 = GND;
R1_ram_block2a10_clock_enable_0 = S3_w_anode2973w[3];
R1_ram_block2a10_clock_enable_1 = GND;
R1_ram_block2a10_PORT_A_data_out = MEMORY(R1_ram_block2a10_PORT_A_data_in_reg, R1_ram_block2a10_PORT_B_data_in_reg, R1_ram_block2a10_PORT_A_address_reg, R1_ram_block2a10_PORT_B_address_reg, R1_ram_block2a10_PORT_A_write_enable_reg, R1_ram_block2a10_PORT_B_write_enable_reg, , , R1_ram_block2a10_clock_0, R1_ram_block2a10_clock_1, R1_ram_block2a10_clock_enable_0, R1_ram_block2a10_clock_enable_1, , );
R1_ram_block2a10_PORT_A_data_out_reg = DFFE(R1_ram_block2a10_PORT_A_data_out, R1_ram_block2a10_clock_0, , , R1_ram_block2a10_clock_enable_0);
R1M581Q = R1_ram_block2a10_PORT_A_data_out_reg[7];


--R1_ram_block2a8 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8 at M4K_X41_Y16
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = GLOBAL(M1L2);
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8 = R1_ram_block2a8_PORT_A_data_out_reg[0];

--R1M469Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT1 at M4K_X41_Y16
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = GLOBAL(M1L2);
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1M469Q = R1_ram_block2a8_PORT_A_data_out_reg[1];

--R1M470Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT2 at M4K_X41_Y16
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = GLOBAL(M1L2);
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1M470Q = R1_ram_block2a8_PORT_A_data_out_reg[2];

--R1M471Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT3 at M4K_X41_Y16
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = GLOBAL(M1L2);
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1M471Q = R1_ram_block2a8_PORT_A_data_out_reg[3];

--R1M472Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT4 at M4K_X41_Y16
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = GLOBAL(M1L2);
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1M472Q = R1_ram_block2a8_PORT_A_data_out_reg[4];

--R1M473Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT5 at M4K_X41_Y16
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = GLOBAL(M1L2);
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1M473Q = R1_ram_block2a8_PORT_A_data_out_reg[5];

--R1M474Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT6 at M4K_X41_Y16
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = GLOBAL(M1L2);
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1M474Q = R1_ram_block2a8_PORT_A_data_out_reg[6];

--R1M475Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a8~PORTADATAOUT7 at M4K_X41_Y16
R1_ram_block2a8_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a8_PORT_A_data_in_reg = DFFE(R1_ram_block2a8_PORT_A_data_in, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_data_in = ~GND;
R1_ram_block2a8_PORT_B_data_in_reg = DFFE(R1_ram_block2a8_PORT_B_data_in, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a8_PORT_A_address_reg = DFFE(R1_ram_block2a8_PORT_A_address, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a8_PORT_B_address_reg = DFFE(R1_ram_block2a8_PORT_B_address, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_PORT_A_write_enable = GND;
R1_ram_block2a8_PORT_A_write_enable_reg = DFFE(R1_ram_block2a8_PORT_A_write_enable, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1_ram_block2a8_PORT_B_write_enable = GND;
R1_ram_block2a8_PORT_B_write_enable_reg = DFFE(R1_ram_block2a8_PORT_B_write_enable, R1_ram_block2a8_clock_1, , , R1_ram_block2a8_clock_enable_1);
R1_ram_block2a8_clock_0 = GLOBAL(M1L2);
R1_ram_block2a8_clock_1 = GND;
R1_ram_block2a8_clock_enable_0 = S3_w_anode2952w[3];
R1_ram_block2a8_clock_enable_1 = GND;
R1_ram_block2a8_PORT_A_data_out = MEMORY(R1_ram_block2a8_PORT_A_data_in_reg, R1_ram_block2a8_PORT_B_data_in_reg, R1_ram_block2a8_PORT_A_address_reg, R1_ram_block2a8_PORT_B_address_reg, R1_ram_block2a8_PORT_A_write_enable_reg, R1_ram_block2a8_PORT_B_write_enable_reg, , , R1_ram_block2a8_clock_0, R1_ram_block2a8_clock_1, R1_ram_block2a8_clock_enable_0, R1_ram_block2a8_clock_enable_1, , );
R1_ram_block2a8_PORT_A_data_out_reg = DFFE(R1_ram_block2a8_PORT_A_data_out, R1_ram_block2a8_clock_0, , , R1_ram_block2a8_clock_enable_0);
R1M475Q = R1_ram_block2a8_PORT_A_data_out_reg[7];


--T1L240 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~581 at LCCOMB_X38_Y15_N22
T1L240 = !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M579Q # !R1_address_reg_a[7] & (R1M473Q));


--R1_ram_block2a11 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11 at M4K_X41_Y23
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = GLOBAL(M1L2);
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11 = R1_ram_block2a11_PORT_A_data_out_reg[0];

--R1M628Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT1 at M4K_X41_Y23
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = GLOBAL(M1L2);
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1M628Q = R1_ram_block2a11_PORT_A_data_out_reg[1];

--R1M629Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT2 at M4K_X41_Y23
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = GLOBAL(M1L2);
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1M629Q = R1_ram_block2a11_PORT_A_data_out_reg[2];

--R1M630Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT3 at M4K_X41_Y23
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = GLOBAL(M1L2);
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1M630Q = R1_ram_block2a11_PORT_A_data_out_reg[3];

--R1M631Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT4 at M4K_X41_Y23
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = GLOBAL(M1L2);
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1M631Q = R1_ram_block2a11_PORT_A_data_out_reg[4];

--R1M632Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT5 at M4K_X41_Y23
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = GLOBAL(M1L2);
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1M632Q = R1_ram_block2a11_PORT_A_data_out_reg[5];

--R1M633Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT6 at M4K_X41_Y23
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = GLOBAL(M1L2);
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1M633Q = R1_ram_block2a11_PORT_A_data_out_reg[6];

--R1M634Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a11~PORTADATAOUT7 at M4K_X41_Y23
R1_ram_block2a11_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a11_PORT_A_data_in_reg = DFFE(R1_ram_block2a11_PORT_A_data_in, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_data_in = ~GND;
R1_ram_block2a11_PORT_B_data_in_reg = DFFE(R1_ram_block2a11_PORT_B_data_in, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a11_PORT_A_address_reg = DFFE(R1_ram_block2a11_PORT_A_address, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a11_PORT_B_address_reg = DFFE(R1_ram_block2a11_PORT_B_address, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_PORT_A_write_enable = GND;
R1_ram_block2a11_PORT_A_write_enable_reg = DFFE(R1_ram_block2a11_PORT_A_write_enable, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1_ram_block2a11_PORT_B_write_enable = GND;
R1_ram_block2a11_PORT_B_write_enable_reg = DFFE(R1_ram_block2a11_PORT_B_write_enable, R1_ram_block2a11_clock_1, , , R1_ram_block2a11_clock_enable_1);
R1_ram_block2a11_clock_0 = GLOBAL(M1L2);
R1_ram_block2a11_clock_1 = GND;
R1_ram_block2a11_clock_enable_0 = S3_w_anode2983w[3];
R1_ram_block2a11_clock_enable_1 = GND;
R1_ram_block2a11_PORT_A_data_out = MEMORY(R1_ram_block2a11_PORT_A_data_in_reg, R1_ram_block2a11_PORT_B_data_in_reg, R1_ram_block2a11_PORT_A_address_reg, R1_ram_block2a11_PORT_B_address_reg, R1_ram_block2a11_PORT_A_write_enable_reg, R1_ram_block2a11_PORT_B_write_enable_reg, , , R1_ram_block2a11_clock_0, R1_ram_block2a11_clock_1, R1_ram_block2a11_clock_enable_0, R1_ram_block2a11_clock_enable_1, , );
R1_ram_block2a11_PORT_A_data_out_reg = DFFE(R1_ram_block2a11_PORT_A_data_out, R1_ram_block2a11_clock_0, , , R1_ram_block2a11_clock_enable_0);
R1M634Q = R1_ram_block2a11_PORT_A_data_out_reg[7];


--R1_ram_block2a9 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9 at M4K_X41_Y18
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 26000, Port A Logical Width: 8, Port B Logical Depth: 208000, Port B Logical Width: 1
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = GLOBAL(M1L2);
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9 = R1_ram_block2a9_PORT_A_data_out_reg[0];

--R1M522Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT1 at M4K_X41_Y18
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = GLOBAL(M1L2);
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1M522Q = R1_ram_block2a9_PORT_A_data_out_reg[1];

--R1M523Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT2 at M4K_X41_Y18
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = GLOBAL(M1L2);
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1M523Q = R1_ram_block2a9_PORT_A_data_out_reg[2];

--R1M524Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT3 at M4K_X41_Y18
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = GLOBAL(M1L2);
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1M524Q = R1_ram_block2a9_PORT_A_data_out_reg[3];

--R1M525Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT4 at M4K_X41_Y18
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = GLOBAL(M1L2);
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1M525Q = R1_ram_block2a9_PORT_A_data_out_reg[4];

--R1M526Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT5 at M4K_X41_Y18
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = GLOBAL(M1L2);
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1M526Q = R1_ram_block2a9_PORT_A_data_out_reg[5];

--R1M527Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT6 at M4K_X41_Y18
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = GLOBAL(M1L2);
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1M527Q = R1_ram_block2a9_PORT_A_data_out_reg[6];

--R1M528Q is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|ram_block2a9~PORTADATAOUT7 at M4K_X41_Y18
R1_ram_block2a9_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
R1_ram_block2a9_PORT_A_data_in_reg = DFFE(R1_ram_block2a9_PORT_A_data_in, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_data_in = ~GND;
R1_ram_block2a9_PORT_B_data_in_reg = DFFE(R1_ram_block2a9_PORT_B_data_in, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_address = BUS(H1L105, H1L107, H1L109, H1L111, H1L113, H1L115, H1L117, H1L119, H1L121);
R1_ram_block2a9_PORT_A_address_reg = DFFE(R1_ram_block2a9_PORT_A_address, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_address = BUS(VCC, VCC, VCC, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
R1_ram_block2a9_PORT_B_address_reg = DFFE(R1_ram_block2a9_PORT_B_address, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_PORT_A_write_enable = GND;
R1_ram_block2a9_PORT_A_write_enable_reg = DFFE(R1_ram_block2a9_PORT_A_write_enable, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1_ram_block2a9_PORT_B_write_enable = GND;
R1_ram_block2a9_PORT_B_write_enable_reg = DFFE(R1_ram_block2a9_PORT_B_write_enable, R1_ram_block2a9_clock_1, , , R1_ram_block2a9_clock_enable_1);
R1_ram_block2a9_clock_0 = GLOBAL(M1L2);
R1_ram_block2a9_clock_1 = GND;
R1_ram_block2a9_clock_enable_0 = S3_w_anode2963w[3];
R1_ram_block2a9_clock_enable_1 = GND;
R1_ram_block2a9_PORT_A_data_out = MEMORY(R1_ram_block2a9_PORT_A_data_in_reg, R1_ram_block2a9_PORT_B_data_in_reg, R1_ram_block2a9_PORT_A_address_reg, R1_ram_block2a9_PORT_B_address_reg, R1_ram_block2a9_PORT_A_write_enable_reg, R1_ram_block2a9_PORT_B_write_enable_reg, , , R1_ram_block2a9_clock_0, R1_ram_block2a9_clock_1, R1_ram_block2a9_clock_enable_0, R1_ram_block2a9_clock_enable_1, , );
R1_ram_block2a9_PORT_A_data_out_reg = DFFE(R1_ram_block2a9_PORT_A_data_out, R1_ram_block2a9_clock_0, , , R1_ram_block2a9_clock_enable_0);
R1M528Q = R1_ram_block2a9_PORT_A_data_out_reg[7];


--T1L241 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~582 at LCCOMB_X38_Y15_N26
T1L241 = R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M632Q # !R1_address_reg_a[7] & (R1M526Q));


--T1L242 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~583 at LCCOMB_X38_Y13_N22
T1L242 = R1_address_reg_a[11] & (T1L239) # !R1_address_reg_a[11] & (T1L240 # T1L241);


--T1L243 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~584 at LCCOMB_X38_Y12_N12
T1L243 = !R1_address_reg_a[8] & R1_address_reg_a[9] & !R1_address_reg_a[10];


--T1L244 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6783w~585 at LCCOMB_X38_Y13_N18
T1L244 = T1L235 # T1L237 # T1L242 & T1L243;


--T1L54 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[5]~5039 at LCCOMB_X38_Y13_N24
T1L54 = T1L244 & (T1L48 # !R1_address_reg_a[10]) # !T1L244 & T1L53 & R1_address_reg_a[10];


--H1_ADDR_dd[0] is VGA_OSD_RAM:u6|ADDR_dd[0] at LCFF_X31_Y12_N1
H1_ADDR_dd[0] = DFFEAS(H1L8, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--T1L55 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5040 at LCCOMB_X38_Y15_N2
T1L55 = R1_address_reg_a[7] & R1M2700Q & !R1_address_reg_a[8] # !R1_address_reg_a[7] & (R1_address_reg_a[8]);


--T1L56 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5041 at LCCOMB_X38_Y15_N12
T1L56 = R1_address_reg_a[6] & (R1_address_reg_a[7] # R1M2647Q) # !R1_address_reg_a[6] & R1M2594Q & !R1_address_reg_a[7];


--T1L57 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5042 at LCCOMB_X38_Y15_N28
T1L57 = !R1_address_reg_a[9] & (T1L55 & R1_address_reg_a[7] & !T1L56 # !T1L55 & !R1_address_reg_a[7] & T1L56);


--T1L253 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7024w~49 at LCCOMB_X38_Y15_N16
T1L253 = R1_address_reg_a[7] & (R1M1640Q # R1_address_reg_a[6]) # !R1_address_reg_a[7] & R1M1534Q & (!R1_address_reg_a[6]);


--T1L254 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7024w~50 at LCCOMB_X18_Y14_N4
T1L254 = R1_address_reg_a[6] & (T1L253 & (R1M1693Q) # !T1L253 & R1M1587Q) # !R1_address_reg_a[6] & (T1L253);


--T1L251 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7022w~44 at LCCOMB_X18_Y14_N30
T1L251 = R1_address_reg_a[7] & R1_address_reg_a[6] # !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M1163Q) # !R1_address_reg_a[6] & R1M1110Q);


--T1L252 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7022w~45 at LCCOMB_X18_Y14_N10
T1L252 = R1_address_reg_a[7] & (T1L251 & (R1M1269Q) # !T1L251 & R1M1216Q) # !R1_address_reg_a[7] & T1L251;


--T1L58 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5043 at LCCOMB_X18_Y14_N16
T1L58 = R1_address_reg_a[9] & T1L254 # !R1_address_reg_a[9] & (T1L252);


--T1L255 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7106w~407 at LCCOMB_X18_Y14_N28
T1L255 = R1_address_reg_a[6] & (R1_address_reg_a[7] # R1M951Q) # !R1_address_reg_a[6] & R1M898Q & !R1_address_reg_a[7];


--T1L256 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7106w~408 at LCCOMB_X18_Y14_N26
T1L256 = R1_address_reg_a[7] & (T1L255 & R1M1057Q # !T1L255 & (R1M1004Q)) # !R1_address_reg_a[7] & T1L255;


--T1L59 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5044 at LCCOMB_X18_Y14_N18
T1L59 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1481Q # !R1_address_reg_a[6] & (R1M1428Q));


--T1L60 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5045 at LCCOMB_X18_Y14_N12
T1L60 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1375Q # !R1_address_reg_a[6] & (R1M1322Q));


--T1L61 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5046 at LCCOMB_X18_Y14_N8
T1L61 = R1_address_reg_a[9] & (T1L60 # T1L59) # !R1_address_reg_a[9] & (T1L256);


--T1L62 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5047 at LCCOMB_X18_Y14_N20
T1L62 = R1_address_reg_a[8] & T1L58 # !R1_address_reg_a[8] & (T1L61);


--T1L259 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7122w~47 at LCCOMB_X40_Y13_N26
T1L259 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2488Q # !R1_address_reg_a[7] & (R1M2382Q));


--T1L260 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7122w~48 at LCCOMB_X40_Y13_N6
T1L260 = R1_address_reg_a[6] & (T1L259 & (R1M2541Q) # !T1L259 & R1M2435Q) # !R1_address_reg_a[6] & (T1L259);


--T1L247 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6921w~47 at LCCOMB_X40_Y13_N0
T1L247 = R1_address_reg_a[6] & (R1M739Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1M686Q & !R1_address_reg_a[7]);


--T1L248 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6921w~48 at LCCOMB_X40_Y13_N16
T1L248 = R1_address_reg_a[7] & (T1L247 & R1M845Q # !T1L247 & (R1M792Q)) # !R1_address_reg_a[7] & (T1L247);


--T1L263 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~566 at LCCOMB_X40_Y13_N8
T1L263 = R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L260 # !R1_address_reg_a[11] & (T1L248));


--T1L257 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7120w~44 at LCCOMB_X40_Y13_N24
T1L257 = R1_address_reg_a[6] & (R1M2011Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & R1M1958Q & (!R1_address_reg_a[7]);


--T1L258 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7120w~45 at LCCOMB_X40_Y13_N20
T1L258 = R1_address_reg_a[7] & (T1L257 & R1M2117Q # !T1L257 & (R1M2064Q)) # !R1_address_reg_a[7] & (T1L257);


--T1L245 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6919w~44 at LCCOMB_X40_Y13_N4
T1L245 = R1_address_reg_a[7] & (R1M368Q # R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1M262Q & !R1_address_reg_a[6]);


--T1L246 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6919w~45 at LCCOMB_X40_Y13_N30
T1L246 = R1_address_reg_a[6] & (T1L245 & R1M421Q # !T1L245 & (R1M315Q)) # !R1_address_reg_a[6] & (T1L245);


--T1L264 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~567 at LCCOMB_X40_Y13_N10
T1L264 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & (T1L258) # !R1_address_reg_a[11] & T1L246);


--T1L265 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~568 at LCCOMB_X40_Y13_N12
T1L265 = T1L147 # T1L232 & (T1L264 # T1L263);


--T1L261 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7204w~281 at LCCOMB_X18_Y14_N2
T1L261 = R1_address_reg_a[6] & (R1_address_reg_a[7] # R1M1799Q) # !R1_address_reg_a[6] & R1M1746Q & !R1_address_reg_a[7];


--T1L262 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7204w~282 at LCCOMB_X18_Y14_N6
T1L262 = R1_address_reg_a[7] & (T1L261 & R1M1905Q # !T1L261 & (R1M1852Q)) # !R1_address_reg_a[7] & T1L261;


--T1L249 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7004w~281 at LCCOMB_X18_Y14_N14
T1L249 = R1_address_reg_a[7] & (R1_address_reg_a[6] # R1M156Q) # !R1_address_reg_a[7] & !R1_address_reg_a[6] & (R1M50Q);


--T1L250 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7004w~282 at LCCOMB_X19_Y14_N24
T1L250 = T1L249 & (R1M209Q # !R1_address_reg_a[6]) # !T1L249 & (R1M103Q & R1_address_reg_a[6]);


--T1L266 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~569 at LCCOMB_X40_Y13_N14
T1L266 = T1L236 & (R1_address_reg_a[11] & T1L262 # !R1_address_reg_a[11] & (T1L250));


--T1L267 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~570 at LCCOMB_X18_Y15_N8
T1L267 = R1_address_reg_a[7] & (R1M2329Q # !R1_address_reg_a[6]) # !R1_address_reg_a[7] & R1_address_reg_a[6] & (R1M2223Q);


--T1L268 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~571 at LCCOMB_X18_Y15_N16
T1L268 = T1L267 & (R1M2276Q # R1_address_reg_a[6]) # !T1L267 & R1M2170Q & (!R1_address_reg_a[6]);


--T1L269 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~572 at LCCOMB_X18_Y15_N24
T1L269 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M527Q) # !R1_address_reg_a[6] & R1M474Q);


--T1L270 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~573 at LCCOMB_X40_Y13_N22
T1L270 = R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M633Q) # !R1_address_reg_a[6] & R1M580Q);


--T1L271 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~574 at LCCOMB_X40_Y13_N18
T1L271 = R1_address_reg_a[11] & (T1L268) # !R1_address_reg_a[11] & (T1L269 # T1L270);


--T1L272 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7314w~575 at LCCOMB_X40_Y13_N28
T1L272 = T1L265 # T1L266 # T1L271 & T1L243;


--T1L63 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[6]~5048 at LCCOMB_X31_Y11_N0
T1L63 = T1L272 & (T1L57 # !R1_address_reg_a[10]) # !T1L272 & (T1L62 & R1_address_reg_a[10]);


--H1_ADDR_dd[1] is VGA_OSD_RAM:u6|ADDR_dd[1] at LCFF_X31_Y12_N13
H1_ADDR_dd[1] = DFFEAS(H1L10, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--T1L37 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5049 at LCCOMB_X18_Y14_N0
T1L37 = R1_address_reg_a[8] & (!R1_address_reg_a[7]) # !R1_address_reg_a[8] & R1M2698Q & R1_address_reg_a[7];


--T1L38 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5050 at LCCOMB_X18_Y15_N18
T1L38 = R1_address_reg_a[7] & R1_address_reg_a[6] # !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M2645Q) # !R1_address_reg_a[6] & R1M2592Q);


--T1L39 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5051 at LCCOMB_X18_Y15_N28
T1L39 = !R1_address_reg_a[9] & (R1_address_reg_a[7] & T1L37 & !T1L38 # !R1_address_reg_a[7] & !T1L37 & T1L38);


--T1L194 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5962w~49 at LCCOMB_X18_Y15_N10
T1L194 = R1_address_reg_a[7] & (R1_address_reg_a[6] # R1M1638Q) # !R1_address_reg_a[7] & !R1_address_reg_a[6] & (R1M1532Q);


--T1L195 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5962w~50 at LCCOMB_X18_Y15_N26
T1L195 = T1L194 & (R1M1691Q # !R1_address_reg_a[6]) # !T1L194 & R1_address_reg_a[6] & (R1M1585Q);


--T1L192 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5960w~44 at LCCOMB_X18_Y15_N22
T1L192 = R1_address_reg_a[7] & R1_address_reg_a[6] # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1161Q # !R1_address_reg_a[6] & (R1M1108Q));


--T1L193 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5960w~45 at LCCOMB_X18_Y15_N6
T1L193 = R1_address_reg_a[7] & (T1L192 & (R1M1267Q) # !T1L192 & R1M1214Q) # !R1_address_reg_a[7] & T1L192;


--T1L40 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5052 at LCCOMB_X18_Y15_N12
T1L40 = R1_address_reg_a[9] & (T1L195) # !R1_address_reg_a[9] & T1L193;


--T1L196 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6044w~407 at LCCOMB_X40_Y15_N14
T1L196 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M949Q) # !R1_address_reg_a[6] & R1M896Q);


--T1L197 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6044w~408 at LCCOMB_X40_Y15_N16
T1L197 = T1L196 & (R1M1055Q # !R1_address_reg_a[7]) # !T1L196 & (R1_address_reg_a[7] & R1M1002Q);


--T1L41 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5053 at LCCOMB_X18_Y15_N30
T1L41 = R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M1479Q) # !R1_address_reg_a[6] & R1M1426Q);


--T1L42 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5054 at LCCOMB_X18_Y15_N2
T1L42 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M1373Q) # !R1_address_reg_a[6] & R1M1320Q);


--T1L43 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5055 at LCCOMB_X18_Y15_N0
T1L43 = R1_address_reg_a[9] & (T1L42 # T1L41) # !R1_address_reg_a[9] & T1L197;


--T1L44 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5056 at LCCOMB_X18_Y15_N4
T1L44 = R1_address_reg_a[8] & (T1L40) # !R1_address_reg_a[8] & T1L43;


--T1L200 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6060w~47 at LCCOMB_X40_Y11_N14
T1L200 = R1_address_reg_a[6] & R1_address_reg_a[7] # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2486Q # !R1_address_reg_a[7] & (R1M2380Q));


--T1L201 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6060w~48 at LCCOMB_X40_Y11_N10
T1L201 = R1_address_reg_a[6] & (T1L200 & R1M2539Q # !T1L200 & (R1M2433Q)) # !R1_address_reg_a[6] & (T1L200);


--T1L188 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5859w~47 at LCCOMB_X40_Y11_N26
T1L188 = R1_address_reg_a[6] & (R1_address_reg_a[7] # R1M737Q) # !R1_address_reg_a[6] & !R1_address_reg_a[7] & R1M684Q;


--T1L189 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5859w~48 at LCCOMB_X40_Y11_N12
T1L189 = R1_address_reg_a[7] & (T1L188 & (R1M843Q) # !T1L188 & R1M790Q) # !R1_address_reg_a[7] & (T1L188);


--T1L204 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~566 at LCCOMB_X40_Y11_N16
T1L204 = R1_address_reg_a[9] & (R1_address_reg_a[11] & (T1L201) # !R1_address_reg_a[11] & T1L189);


--T1L198 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6058w~44 at LCCOMB_X40_Y11_N4
T1L198 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M2009Q) # !R1_address_reg_a[6] & R1M1956Q);


--T1L199 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6058w~45 at LCCOMB_X40_Y11_N6
T1L199 = R1_address_reg_a[7] & (T1L198 & (R1M2115Q) # !T1L198 & R1M2062Q) # !R1_address_reg_a[7] & (T1L198);


--T1L186 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5857w~44 at LCCOMB_X40_Y11_N30
T1L186 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & (R1M366Q) # !R1_address_reg_a[7] & R1M260Q);


--T1L187 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5857w~45 at LCCOMB_X40_Y11_N22
T1L187 = T1L186 & (R1M419Q # !R1_address_reg_a[6]) # !T1L186 & (R1_address_reg_a[6] & R1M313Q);


--T1L205 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~567 at LCCOMB_X40_Y11_N18
T1L205 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L199 # !R1_address_reg_a[11] & (T1L187));


--T1L206 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~568 at LCCOMB_X40_Y11_N28
T1L206 = T1L147 # T1L232 & (T1L204 # T1L205);


--T1L202 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6142w~281 at LCCOMB_X40_Y15_N22
T1L202 = R1_address_reg_a[6] & (R1_address_reg_a[7] # R1M1797Q) # !R1_address_reg_a[6] & !R1_address_reg_a[7] & (R1M1744Q);


--T1L203 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6142w~282 at LCCOMB_X40_Y15_N10
T1L203 = T1L202 & (R1M1903Q # !R1_address_reg_a[7]) # !T1L202 & (R1_address_reg_a[7] & R1M1850Q);


--T1L190 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5942w~281 at LCCOMB_X40_Y15_N2
T1L190 = R1_address_reg_a[6] & R1_address_reg_a[7] # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M154Q # !R1_address_reg_a[7] & (R1M48Q));


--T1L191 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5942w~282 at LCCOMB_X40_Y15_N18
T1L191 = R1_address_reg_a[6] & (T1L190 & (R1M207Q) # !T1L190 & R1M101Q) # !R1_address_reg_a[6] & T1L190;


--T1L207 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~569 at LCCOMB_X40_Y11_N24
T1L207 = T1L236 & (R1_address_reg_a[11] & (T1L203) # !R1_address_reg_a[11] & T1L191);


--T1L208 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~570 at LCCOMB_X18_Y15_N14
T1L208 = R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2327Q # !R1_address_reg_a[7] & (R1M2221Q)) # !R1_address_reg_a[6] & (R1_address_reg_a[7]);


--T1L209 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~571 at LCCOMB_X18_Y15_N20
T1L209 = R1_address_reg_a[6] & (T1L208) # !R1_address_reg_a[6] & (T1L208 & (R1M2274Q) # !T1L208 & R1M2168Q);


--T1L210 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~572 at LCCOMB_X40_Y15_N12
T1L210 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M525Q # !R1_address_reg_a[6] & (R1M472Q));


--T1L211 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~573 at LCCOMB_X40_Y15_N6
T1L211 = R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M631Q) # !R1_address_reg_a[6] & R1M578Q);


--T1L212 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~574 at LCCOMB_X40_Y11_N8
T1L212 = R1_address_reg_a[11] & (T1L209) # !R1_address_reg_a[11] & (T1L210 # T1L211);


--T1L213 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result6252w~575 at LCCOMB_X40_Y11_N20
T1L213 = T1L207 # T1L206 # T1L212 & T1L243;


--T1L45 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[4]~5057 at LCCOMB_X31_Y11_N12
T1L45 = T1L213 & (T1L39 # !R1_address_reg_a[10]) # !T1L213 & (T1L44 & R1_address_reg_a[10]);


--H1L21 is VGA_OSD_RAM:u6|Mux~32 at LCCOMB_X31_Y11_N10
H1L21 = H1_ADDR_dd[1] & (T1L63 # H1_ADDR_dd[0]) # !H1_ADDR_dd[1] & (!H1_ADDR_dd[0] & T1L45);


--T1L64 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5058 at LCCOMB_X19_Y13_N16
T1L64 = R1_address_reg_a[7] & !R1_address_reg_a[8] & R1M2701Q # !R1_address_reg_a[7] & R1_address_reg_a[8];


--T1L65 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5059 at LCCOMB_X40_Y15_N26
T1L65 = R1_address_reg_a[6] & (R1_address_reg_a[7] # R1M2648Q) # !R1_address_reg_a[6] & !R1_address_reg_a[7] & R1M2595Q;


--T1L66 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5060 at LCCOMB_X39_Y12_N30
T1L66 = !R1_address_reg_a[9] & (T1L64 & R1_address_reg_a[7] & !T1L65 # !T1L64 & !R1_address_reg_a[7] & T1L65);


--T1L281 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7555w~49 at LCCOMB_X40_Y15_N30
T1L281 = R1_address_reg_a[6] & (R1M1588Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (!R1_address_reg_a[7] & R1M1535Q);


--T1L282 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7555w~50 at LCCOMB_X40_Y15_N0
T1L282 = R1_address_reg_a[7] & (T1L281 & R1M1694Q # !T1L281 & (R1M1641Q)) # !R1_address_reg_a[7] & (T1L281);


--T1L279 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7553w~44 at LCCOMB_X19_Y13_N0
T1L279 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M1217Q # !R1_address_reg_a[7] & (R1M1111Q));


--T1L280 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7553w~45 at LCCOMB_X19_Y13_N24
T1L280 = T1L279 & (R1M1270Q # !R1_address_reg_a[6]) # !T1L279 & R1M1164Q & R1_address_reg_a[6];


--T1L67 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5061 at LCCOMB_X40_Y15_N20
T1L67 = R1_address_reg_a[9] & T1L282 # !R1_address_reg_a[9] & (T1L280);


--T1L283 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7637w~407 at LCCOMB_X19_Y13_N12
T1L283 = R1_address_reg_a[7] & (R1M1005Q # R1_address_reg_a[6]) # !R1_address_reg_a[7] & (!R1_address_reg_a[6] & R1M899Q);


--T1L284 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7637w~408 at LCCOMB_X19_Y13_N8
T1L284 = T1L283 & (R1M1058Q # !R1_address_reg_a[6]) # !T1L283 & R1_address_reg_a[6] & R1M952Q;


--T1L68 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5062 at LCCOMB_X19_Y13_N18
T1L68 = R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M1482Q) # !R1_address_reg_a[6] & R1M1429Q);


--T1L69 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5063 at LCCOMB_X19_Y13_N10
T1L69 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1376Q # !R1_address_reg_a[6] & (R1M1323Q));


--T1L70 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5064 at LCCOMB_X19_Y13_N30
T1L70 = R1_address_reg_a[9] & (T1L69 # T1L68) # !R1_address_reg_a[9] & (T1L284);


--T1L71 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5065 at LCCOMB_X19_Y13_N22
T1L71 = R1_address_reg_a[8] & T1L67 # !R1_address_reg_a[8] & (T1L70);


--T1L287 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7653w~47 at LCCOMB_X39_Y12_N18
T1L287 = R1_address_reg_a[6] & (R1M2436Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & R1M2383Q & (!R1_address_reg_a[7]);


--T1L288 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7653w~48 at LCCOMB_X39_Y12_N2
T1L288 = T1L287 & (R1M2542Q # !R1_address_reg_a[7]) # !T1L287 & (R1M2489Q & R1_address_reg_a[7]);


--T1L275 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7452w~47 at LCCOMB_X40_Y15_N28
T1L275 = R1_address_reg_a[6] & R1_address_reg_a[7] # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M793Q # !R1_address_reg_a[7] & (R1M687Q));


--T1L276 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7452w~48 at LCCOMB_X40_Y15_N24
T1L276 = R1_address_reg_a[6] & (T1L275 & (R1M846Q) # !T1L275 & R1M740Q) # !R1_address_reg_a[6] & T1L275;


--T1L291 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~545 at LCCOMB_X39_Y12_N10
T1L291 = R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L288 # !R1_address_reg_a[11] & (T1L276));


--T1L285 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7651w~44 at LCCOMB_X39_Y12_N22
T1L285 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2065Q # !R1_address_reg_a[7] & (R1M1959Q));


--T1L286 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7651w~45 at LCCOMB_X39_Y12_N26
T1L286 = T1L285 & (R1M2118Q # !R1_address_reg_a[6]) # !T1L285 & R1M2012Q & (R1_address_reg_a[6]);


--T1L273 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7450w~44 at LCCOMB_X39_Y12_N6
T1L273 = R1_address_reg_a[6] & (R1M316Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1M263Q & !R1_address_reg_a[7]);


--T1L274 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7450w~45 at LCCOMB_X39_Y12_N12
T1L274 = T1L273 & (R1M422Q # !R1_address_reg_a[7]) # !T1L273 & R1M369Q & (R1_address_reg_a[7]);


--T1L292 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~546 at LCCOMB_X39_Y12_N14
T1L292 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & (T1L286) # !R1_address_reg_a[11] & T1L274);


--T1L293 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~547 at LCCOMB_X39_Y12_N24
T1L293 = T1L147 # T1L232 & (T1L291 # T1L292);


--T1L289 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7735w~281 at LCCOMB_X19_Y13_N26
T1L289 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & (R1M1853Q) # !R1_address_reg_a[7] & R1M1747Q);


--T1L290 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7735w~282 at LCCOMB_X19_Y13_N14
T1L290 = T1L289 & (R1M1906Q # !R1_address_reg_a[6]) # !T1L289 & (R1_address_reg_a[6] & R1M1800Q);


--T1L277 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7535w~281 at LCCOMB_X19_Y13_N28
T1L277 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M104Q) # !R1_address_reg_a[6] & R1M51Q);


--T1L278 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7535w~282 at LCCOMB_X19_Y13_N6
T1L278 = T1L277 & (R1M210Q # !R1_address_reg_a[7]) # !T1L277 & (R1_address_reg_a[7] & R1M157Q);


--T1L294 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~548 at LCCOMB_X39_Y12_N28
T1L294 = T1L236 & (R1_address_reg_a[11] & T1L290 # !R1_address_reg_a[11] & (T1L278));


--T1L295 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~549 at LCCOMB_X19_Y13_N2
T1L295 = R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2330Q # !R1_address_reg_a[7] & (R1M2224Q)) # !R1_address_reg_a[6] & (R1_address_reg_a[7]);


--T1L296 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~550 at LCCOMB_X19_Y14_N6
T1L296 = T1L295 & (R1M2277Q # R1_address_reg_a[6]) # !T1L295 & (R1M2171Q & !R1_address_reg_a[6]);


--T1L297 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~551 at LCCOMB_X18_Y13_N6
T1L297 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M528Q # !R1_address_reg_a[6] & (R1M475Q));


--T1L298 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~552 at LCCOMB_X18_Y13_N16
T1L298 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M634Q # !R1_address_reg_a[6] & (R1M581Q));


--T1L299 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~553 at LCCOMB_X39_Y12_N20
T1L299 = R1_address_reg_a[11] & T1L296 # !R1_address_reg_a[11] & (T1L298 # T1L297);


--T1L300 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result7845w~554 at LCCOMB_X39_Y12_N16
T1L300 = T1L293 # T1L294 # T1L299 & T1L243;


--T1L72 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[7]~5066 at LCCOMB_X39_Y12_N4
T1L72 = T1L300 & (T1L66 # !R1_address_reg_a[10]) # !T1L300 & (T1L71 & R1_address_reg_a[10]);


--H1L22 is VGA_OSD_RAM:u6|Mux~33 at LCCOMB_X31_Y11_N4
H1L22 = H1_ADDR_dd[0] & (H1L21 & T1L72 # !H1L21 & (T1L54)) # !H1_ADDR_dd[0] & (H1L21);


--T1L19 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5067 at LCCOMB_X39_Y13_N2
T1L19 = R1_address_reg_a[7] & !R1_address_reg_a[8] & R1M2696Q # !R1_address_reg_a[7] & R1_address_reg_a[8];


--T1L20 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5068 at LCCOMB_X39_Y13_N30
T1L20 = R1_address_reg_a[7] & R1_address_reg_a[6] # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M2643Q # !R1_address_reg_a[6] & (R1M2590Q));


--T1L21 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5069 at LCCOMB_X39_Y13_N18
T1L21 = !R1_address_reg_a[9] & (T1L19 & R1_address_reg_a[7] & !T1L20 # !T1L19 & !R1_address_reg_a[7] & T1L20);


--T1L137 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4900w~49 at LCCOMB_X18_Y13_N0
T1L137 = R1_address_reg_a[7] & (R1M1636Q # R1_address_reg_a[6]) # !R1_address_reg_a[7] & R1M1530Q & (!R1_address_reg_a[6]);


--T1L138 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4900w~50 at LCCOMB_X18_Y13_N28
T1L138 = R1_address_reg_a[6] & (T1L137 & (R1M1689Q) # !T1L137 & R1M1583Q) # !R1_address_reg_a[6] & T1L137;


--T1L135 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4898w~44 at LCCOMB_X18_Y13_N30
T1L135 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1159Q # !R1_address_reg_a[6] & (R1M1106Q));


--T1L136 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4898w~45 at LCCOMB_X18_Y13_N8
T1L136 = T1L135 & (R1M1265Q # !R1_address_reg_a[7]) # !T1L135 & R1M1212Q & R1_address_reg_a[7];


--T1L22 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5070 at LCCOMB_X18_Y11_N0
T1L22 = R1_address_reg_a[9] & (T1L138) # !R1_address_reg_a[9] & T1L136;


--T1L139 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4982w~407 at LCCOMB_X18_Y13_N18
T1L139 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M947Q # !R1_address_reg_a[6] & (R1M894Q));


--T1L140 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4982w~408 at LCCOMB_X18_Y13_N2
T1L140 = R1_address_reg_a[7] & (T1L139 & (R1M1053Q) # !T1L139 & R1M1000Q) # !R1_address_reg_a[7] & T1L139;


--T1L23 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5071 at LCCOMB_X18_Y13_N12
T1L23 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1477Q # !R1_address_reg_a[6] & (R1M1424Q));


--T1L24 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5072 at LCCOMB_X18_Y13_N26
T1L24 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1371Q # !R1_address_reg_a[6] & (R1M1318Q));


--T1L25 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5073 at LCCOMB_X18_Y13_N22
T1L25 = R1_address_reg_a[9] & (T1L23 # T1L24) # !R1_address_reg_a[9] & (T1L140);


--T1L26 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5074 at LCCOMB_X18_Y11_N4
T1L26 = R1_address_reg_a[8] & T1L22 # !R1_address_reg_a[8] & (T1L25);


--T1L143 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4998w~47 at LCCOMB_X19_Y13_N20
T1L143 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & (R1M2484Q) # !R1_address_reg_a[7] & R1M2378Q);


--T1L144 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4998w~48 at LCCOMB_X40_Y12_N4
T1L144 = R1_address_reg_a[6] & (T1L143 & (R1M2537Q) # !T1L143 & R1M2431Q) # !R1_address_reg_a[6] & T1L143;


--T1L131 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4797w~47 at LCCOMB_X40_Y12_N28
T1L131 = R1_address_reg_a[6] & (R1M735Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1M682Q & !R1_address_reg_a[7]);


--T1L132 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4797w~48 at LCCOMB_X40_Y12_N18
T1L132 = R1_address_reg_a[7] & (T1L131 & R1M841Q # !T1L131 & (R1M788Q)) # !R1_address_reg_a[7] & T1L131;


--T1L148 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~609 at LCCOMB_X40_Y12_N20
T1L148 = R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L144 # !R1_address_reg_a[11] & (T1L132));


--T1L141 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4996w~44 at LCCOMB_X39_Y13_N24
T1L141 = R1_address_reg_a[7] & R1_address_reg_a[6] # !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M2007Q) # !R1_address_reg_a[6] & R1M1954Q);


--T1L142 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4996w~45 at LCCOMB_X39_Y13_N28
T1L142 = R1_address_reg_a[7] & (T1L141 & (R1M2113Q) # !T1L141 & R1M2060Q) # !R1_address_reg_a[7] & (T1L141);


--T1L129 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4795w~44 at LCCOMB_X39_Y13_N12
T1L129 = R1_address_reg_a[7] & (R1_address_reg_a[6] # R1M364Q) # !R1_address_reg_a[7] & !R1_address_reg_a[6] & R1M258Q;


--T1L130 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4795w~45 at LCCOMB_X39_Y13_N26
T1L130 = T1L129 & (R1M417Q # !R1_address_reg_a[6]) # !T1L129 & R1M311Q & (R1_address_reg_a[6]);


--T1L149 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~610 at LCCOMB_X39_Y13_N16
T1L149 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L142 # !R1_address_reg_a[11] & (T1L130));


--T1L150 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~611 at LCCOMB_X39_Y13_N14
T1L150 = T1L147 # T1L232 & (T1L149 # T1L148);


--T1L145 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5080w~281 at LCCOMB_X18_Y13_N24
T1L145 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M1795Q) # !R1_address_reg_a[6] & R1M1742Q);


--T1L146 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5080w~282 at LCCOMB_X38_Y17_N10
T1L146 = T1L145 & (R1M1901Q # !R1_address_reg_a[7]) # !T1L145 & R1_address_reg_a[7] & (R1M1848Q);


--T1L133 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4880w~281 at LCCOMB_X39_Y17_N28
T1L133 = R1_address_reg_a[7] & (R1_address_reg_a[6] # R1M152Q) # !R1_address_reg_a[7] & R1M46Q & !R1_address_reg_a[6];


--T1L134 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4880w~282 at LCCOMB_X39_Y17_N22
T1L134 = R1_address_reg_a[6] & (T1L133 & (R1M205Q) # !T1L133 & R1M99Q) # !R1_address_reg_a[6] & (T1L133);


--T1L151 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~612 at LCCOMB_X39_Y13_N6
T1L151 = T1L236 & (R1_address_reg_a[11] & T1L146 # !R1_address_reg_a[11] & (T1L134));


--T1L152 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~613 at LCCOMB_X39_Y17_N26
T1L152 = R1_address_reg_a[7] & (R1M2325Q # !R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M2219Q);


--T1L153 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~614 at LCCOMB_X39_Y17_N30
T1L153 = R1_address_reg_a[6] & (T1L152) # !R1_address_reg_a[6] & (T1L152 & R1M2272Q # !T1L152 & (R1M2166Q));


--T1L154 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~615 at LCCOMB_X39_Y13_N0
T1L154 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M523Q # !R1_address_reg_a[6] & (R1M470Q));


--T1L155 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~616 at LCCOMB_X39_Y13_N10
T1L155 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M629Q # !R1_address_reg_a[6] & (R1M576Q));


--T1L156 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~617 at LCCOMB_X39_Y13_N22
T1L156 = R1_address_reg_a[11] & (T1L153) # !R1_address_reg_a[11] & (T1L155 # T1L154);


--T1L157 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5190w~618 at LCCOMB_X39_Y13_N20
T1L157 = T1L151 # T1L150 # T1L243 & T1L156;


--T1L27 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[2]~5075 at LCCOMB_X39_Y13_N4
T1L27 = R1_address_reg_a[10] & (T1L157 & (T1L21) # !T1L157 & T1L26) # !R1_address_reg_a[10] & (T1L157);


--T1L10 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5076 at LCCOMB_X18_Y11_N22
T1L10 = R1_address_reg_a[7] & !R1_address_reg_a[8] & R1M2695Q # !R1_address_reg_a[7] & R1_address_reg_a[8];


--T1L11 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5077 at LCCOMB_X39_Y17_N10
T1L11 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M2642Q # !R1_address_reg_a[6] & (R1M2589Q));


--T1L12 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5078 at LCCOMB_X39_Y11_N18
T1L12 = !R1_address_reg_a[9] & (T1L10 & R1_address_reg_a[7] & !T1L11 # !T1L10 & !R1_address_reg_a[7] & T1L11);


--T1L109 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4369w~49 at LCCOMB_X18_Y11_N30
T1L109 = R1_address_reg_a[6] & (R1M1582Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (!R1_address_reg_a[7] & R1M1529Q);


--T1L110 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4369w~50 at LCCOMB_X18_Y11_N8
T1L110 = T1L109 & (R1M1688Q # !R1_address_reg_a[7]) # !T1L109 & R1M1635Q & R1_address_reg_a[7];


--T1L107 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4367w~44 at LCCOMB_X18_Y11_N12
T1L107 = R1_address_reg_a[7] & (R1_address_reg_a[6] # R1M1211Q) # !R1_address_reg_a[7] & !R1_address_reg_a[6] & R1M1105Q;


--T1L108 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4367w~45 at LCCOMB_X18_Y11_N28
T1L108 = T1L107 & (R1M1264Q # !R1_address_reg_a[6]) # !T1L107 & R1M1158Q & (R1_address_reg_a[6]);


--T1L13 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5079 at LCCOMB_X18_Y11_N14
T1L13 = R1_address_reg_a[9] & (T1L110) # !R1_address_reg_a[9] & T1L108;


--T1L111 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4451w~407 at LCCOMB_X18_Y11_N24
T1L111 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M999Q # !R1_address_reg_a[7] & (R1M893Q));


--T1L112 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4451w~408 at LCCOMB_X18_Y11_N16
T1L112 = R1_address_reg_a[6] & (T1L111 & R1M1052Q # !T1L111 & (R1M946Q)) # !R1_address_reg_a[6] & (T1L111);


--T1L14 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5080 at LCCOMB_X18_Y11_N2
T1L14 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1476Q # !R1_address_reg_a[6] & (R1M1423Q));


--T1L15 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5081 at LCCOMB_X18_Y11_N18
T1L15 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1370Q # !R1_address_reg_a[6] & (R1M1317Q));


--T1L16 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5082 at LCCOMB_X18_Y11_N6
T1L16 = R1_address_reg_a[9] & (T1L14 # T1L15) # !R1_address_reg_a[9] & (T1L112);


--T1L17 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5083 at LCCOMB_X18_Y11_N20
T1L17 = R1_address_reg_a[8] & T1L13 # !R1_address_reg_a[8] & (T1L16);


--T1L115 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4467w~47 at LCCOMB_X39_Y11_N2
T1L115 = R1_address_reg_a[6] & (R1M2430Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1M2377Q & !R1_address_reg_a[7]);


--T1L116 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4467w~48 at LCCOMB_X39_Y11_N0
T1L116 = T1L115 & (R1M2536Q # !R1_address_reg_a[7]) # !T1L115 & R1M2483Q & R1_address_reg_a[7];


--T1L103 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4266w~47 at LCCOMB_X40_Y12_N30
T1L103 = R1_address_reg_a[7] & (R1_address_reg_a[6] # R1M787Q) # !R1_address_reg_a[7] & R1M681Q & !R1_address_reg_a[6];


--T1L104 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4266w~48 at LCCOMB_X40_Y12_N16
T1L104 = T1L103 & (R1M840Q # !R1_address_reg_a[6]) # !T1L103 & R1M734Q & R1_address_reg_a[6];


--T1L119 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~566 at LCCOMB_X39_Y11_N22
T1L119 = R1_address_reg_a[9] & (R1_address_reg_a[11] & (T1L116) # !R1_address_reg_a[11] & T1L104);


--T1L113 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4465w~44 at LCCOMB_X39_Y11_N12
T1L113 = R1_address_reg_a[6] & (R1_address_reg_a[7]) # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2059Q # !R1_address_reg_a[7] & (R1M1953Q));


--T1L114 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4465w~45 at LCCOMB_X39_Y11_N20
T1L114 = T1L113 & (R1M2112Q # !R1_address_reg_a[6]) # !T1L113 & R1_address_reg_a[6] & (R1M2006Q);


--T1L101 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4264w~44 at LCCOMB_X39_Y11_N28
T1L101 = R1_address_reg_a[6] & (R1M310Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & R1M257Q & (!R1_address_reg_a[7]);


--T1L102 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4264w~45 at LCCOMB_X39_Y11_N30
T1L102 = T1L101 & (R1M416Q # !R1_address_reg_a[7]) # !T1L101 & (R1_address_reg_a[7] & R1M363Q);


--T1L120 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~567 at LCCOMB_X39_Y11_N10
T1L120 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L114 # !R1_address_reg_a[11] & (T1L102));


--T1L121 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~568 at LCCOMB_X39_Y11_N6
T1L121 = T1L147 # T1L232 & (T1L120 # T1L119);


--T1L117 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4549w~281 at LCCOMB_X39_Y17_N24
T1L117 = R1_address_reg_a[7] & (R1M1847Q # R1_address_reg_a[6]) # !R1_address_reg_a[7] & (!R1_address_reg_a[6] & R1M1741Q);


--T1L118 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4549w~282 at LCCOMB_X39_Y17_N2
T1L118 = T1L117 & (R1M1900Q # !R1_address_reg_a[6]) # !T1L117 & R1_address_reg_a[6] & (R1M1794Q);


--T1L105 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4349w~281 at LCCOMB_X39_Y17_N14
T1L105 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M98Q) # !R1_address_reg_a[6] & R1M45Q);


--T1L106 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4349w~282 at LCCOMB_X39_Y17_N18
T1L106 = R1_address_reg_a[7] & (T1L105 & R1M204Q # !T1L105 & (R1M151Q)) # !R1_address_reg_a[7] & (T1L105);


--T1L122 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~569 at LCCOMB_X39_Y11_N4
T1L122 = T1L236 & (R1_address_reg_a[11] & (T1L118) # !R1_address_reg_a[11] & T1L106);


--T1L123 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~570 at LCCOMB_X18_Y14_N22
T1L123 = R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2324Q # !R1_address_reg_a[7] & (R1M2218Q)) # !R1_address_reg_a[6] & (R1_address_reg_a[7]);


--T1L124 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~571 at LCCOMB_X18_Y14_N24
T1L124 = T1L123 & (R1_address_reg_a[6] # R1M2271Q) # !T1L123 & R1M2165Q & !R1_address_reg_a[6];


--T1L125 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~572 at LCCOMB_X39_Y17_N4
T1L125 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M522Q # !R1_address_reg_a[6] & (R1M469Q));


--T1L126 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~573 at LCCOMB_X39_Y17_N12
T1L126 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M628Q # !R1_address_reg_a[6] & (R1M575Q));


--T1L127 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~574 at LCCOMB_X39_Y11_N24
T1L127 = R1_address_reg_a[11] & (T1L124) # !R1_address_reg_a[11] & (T1L125 # T1L126);


--T1L128 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4659w~575 at LCCOMB_X39_Y11_N16
T1L128 = T1L122 # T1L121 # T1L127 & T1L243;


--T1L18 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[1]~5084 at LCCOMB_X39_Y11_N26
T1L18 = R1_address_reg_a[10] & (T1L128 & (T1L12) # !T1L128 & T1L17) # !R1_address_reg_a[10] & (T1L128);


--T1L1 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5085 at LCCOMB_X18_Y11_N10
T1L1 = R1_address_reg_a[7] & !R1_address_reg_a[8] & R1_ram_block2a50 # !R1_address_reg_a[7] & R1_address_reg_a[8];


--T1L2 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5086 at LCCOMB_X39_Y17_N16
T1L2 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1_ram_block2a49 # !R1_address_reg_a[6] & (R1_ram_block2a48));


--T1L3 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5087 at LCCOMB_X38_Y12_N16
T1L3 = !R1_address_reg_a[9] & (R1_address_reg_a[7] & T1L1 & !T1L2 # !R1_address_reg_a[7] & !T1L1 & T1L2);


--T1L81 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3833w~49 at LCCOMB_X39_Y17_N20
T1L81 = R1_address_reg_a[7] & (R1_ram_block2a30 # R1_address_reg_a[6]) # !R1_address_reg_a[7] & (!R1_address_reg_a[6] & R1_ram_block2a28);


--T1L82 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3833w~50 at LCCOMB_X39_Y17_N0
T1L82 = T1L81 & (R1_ram_block2a31 # !R1_address_reg_a[6]) # !T1L81 & R1_address_reg_a[6] & (R1_ram_block2a29);


--T1L79 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3831w~44 at LCCOMB_X19_Y12_N30
T1L79 = R1_address_reg_a[6] & (R1_address_reg_a[7] # R1_ram_block2a21) # !R1_address_reg_a[6] & R1_ram_block2a20 & !R1_address_reg_a[7];


--T1L80 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3831w~45 at LCCOMB_X19_Y12_N24
T1L80 = T1L79 & (R1_ram_block2a23 # !R1_address_reg_a[7]) # !T1L79 & R1_ram_block2a22 & R1_address_reg_a[7];


--T1L4 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5088 at LCCOMB_X38_Y12_N8
T1L4 = R1_address_reg_a[9] & T1L82 # !R1_address_reg_a[9] & (T1L80);


--T1L83 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3915w~407 at LCCOMB_X19_Y12_N6
T1L83 = R1_address_reg_a[6] & (R1_ram_block2a17 # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (!R1_address_reg_a[7] & R1_ram_block2a16);


--T1L84 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3915w~408 at LCCOMB_X19_Y12_N20
T1L84 = T1L83 & (R1_ram_block2a19 # !R1_address_reg_a[7]) # !T1L83 & R1_address_reg_a[7] & R1_ram_block2a18;


--T1L5 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5089 at LCCOMB_X19_Y12_N10
T1L5 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1_ram_block2a27 # !R1_address_reg_a[6] & (R1_ram_block2a26));


--T1L6 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5090 at LCCOMB_X19_Y12_N12
T1L6 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1_ram_block2a25) # !R1_address_reg_a[6] & R1_ram_block2a24);


--T1L7 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5091 at LCCOMB_X38_Y12_N20
T1L7 = R1_address_reg_a[9] & (T1L6 # T1L5) # !R1_address_reg_a[9] & (T1L84);


--T1L8 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5092 at LCCOMB_X38_Y12_N2
T1L8 = R1_address_reg_a[8] & T1L4 # !R1_address_reg_a[8] & (T1L7);


--T1L87 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3931w~47 at LCCOMB_X40_Y12_N0
T1L87 = R1_address_reg_a[6] & R1_address_reg_a[7] # !R1_address_reg_a[6] & (R1_address_reg_a[7] & R1_ram_block2a46 # !R1_address_reg_a[7] & (R1_ram_block2a44));


--T1L88 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3931w~48 at LCCOMB_X40_Y12_N22
T1L88 = T1L87 & (R1_ram_block2a47 # !R1_address_reg_a[6]) # !T1L87 & (R1_address_reg_a[6] & R1_ram_block2a45);


--T1L75 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3730w~47 at LCCOMB_X40_Y12_N24
T1L75 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1_ram_block2a13 # !R1_address_reg_a[6] & (R1_ram_block2a12));


--T1L76 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3730w~48 at LCCOMB_X40_Y12_N12
T1L76 = T1L75 & (R1_ram_block2a15 # !R1_address_reg_a[7]) # !T1L75 & R1_address_reg_a[7] & R1_ram_block2a14;


--T1L91 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~566 at LCCOMB_X38_Y12_N22
T1L91 = R1_address_reg_a[9] & (R1_address_reg_a[11] & (T1L88) # !R1_address_reg_a[11] & T1L76);


--T1L85 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3929w~44 at LCCOMB_X40_Y12_N10
T1L85 = R1_address_reg_a[6] & (R1_address_reg_a[7] # R1_ram_block2a37) # !R1_address_reg_a[6] & R1_ram_block2a36 & !R1_address_reg_a[7];


--T1L86 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3929w~45 at LCCOMB_X38_Y12_N10
T1L86 = R1_address_reg_a[7] & (T1L85 & (R1_ram_block2a39) # !T1L85 & R1_ram_block2a38) # !R1_address_reg_a[7] & (T1L85);


--T1L73 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3728w~44 at LCCOMB_X40_Y12_N26
T1L73 = R1_address_reg_a[7] & (R1_address_reg_a[6] # R1_ram_block2a6) # !R1_address_reg_a[7] & R1_ram_block2a4 & !R1_address_reg_a[6];


--T1L74 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3728w~45 at LCCOMB_X40_Y12_N8
T1L74 = T1L73 & (R1_ram_block2a7 # !R1_address_reg_a[6]) # !T1L73 & (R1_address_reg_a[6] & R1_ram_block2a5);


--T1L92 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~567 at LCCOMB_X38_Y12_N4
T1L92 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & (T1L86) # !R1_address_reg_a[11] & T1L74);


--T1L93 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~568 at LCCOMB_X38_Y12_N24
T1L93 = T1L147 # T1L232 & (T1L91 # T1L92);


--T1L89 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4013w~281 at LCCOMB_X19_Y12_N14
T1L89 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1_ram_block2a33) # !R1_address_reg_a[6] & R1_ram_block2a32);


--T1L90 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4013w~282 at LCCOMB_X19_Y12_N18
T1L90 = T1L89 & (R1_ram_block2a35 # !R1_address_reg_a[7]) # !T1L89 & (R1_address_reg_a[7] & R1_ram_block2a34);


--T1L77 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3813w~281 at LCCOMB_X18_Y13_N10
T1L77 = R1_address_reg_a[7] & (R1_ram_block2a2 # R1_address_reg_a[6]) # !R1_address_reg_a[7] & (!R1_address_reg_a[6] & R1_ram_block2a0);


--T1L78 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result3813w~282 at LCCOMB_X18_Y13_N20
T1L78 = T1L77 & (R1_ram_block2a3 # !R1_address_reg_a[6]) # !T1L77 & (R1_address_reg_a[6] & R1_ram_block2a1);


--T1L94 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~569 at LCCOMB_X38_Y12_N0
T1L94 = T1L236 & (R1_address_reg_a[11] & T1L90 # !R1_address_reg_a[11] & (T1L78));


--T1L95 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~570 at LCCOMB_X18_Y12_N14
T1L95 = R1_address_reg_a[7] & (R1_ram_block2a43 # !R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1_ram_block2a41);


--T1L96 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~571 at LCCOMB_X18_Y12_N20
T1L96 = R1_address_reg_a[6] & T1L95 # !R1_address_reg_a[6] & (T1L95 & (R1_ram_block2a42) # !T1L95 & R1_ram_block2a40);


--T1L97 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~572 at LCCOMB_X19_Y12_N28
T1L97 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1_ram_block2a9 # !R1_address_reg_a[6] & (R1_ram_block2a8));


--T1L98 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~573 at LCCOMB_X19_Y12_N2
T1L98 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1_ram_block2a11 # !R1_address_reg_a[6] & (R1_ram_block2a10));


--T1L99 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~574 at LCCOMB_X38_Y12_N6
T1L99 = R1_address_reg_a[11] & (T1L96) # !R1_address_reg_a[11] & (T1L97 # T1L98);


--T1L100 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result4123w~575 at LCCOMB_X38_Y12_N14
T1L100 = T1L94 # T1L93 # T1L99 & T1L243;


--T1L9 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[0]~5093 at LCCOMB_X38_Y12_N30
T1L9 = T1L100 & (T1L3 # !R1_address_reg_a[10]) # !T1L100 & (T1L8 & R1_address_reg_a[10]);


--H1L23 is VGA_OSD_RAM:u6|Mux~34 at LCCOMB_X31_Y11_N6
H1L23 = H1_ADDR_dd[1] & (H1_ADDR_dd[0]) # !H1_ADDR_dd[1] & (H1_ADDR_dd[0] & (T1L18) # !H1_ADDR_dd[0] & T1L9);


--T1L28 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5094 at LCCOMB_X18_Y11_N26
T1L28 = R1_address_reg_a[7] & R1M2697Q & !R1_address_reg_a[8] # !R1_address_reg_a[7] & (R1_address_reg_a[8]);


--T1L29 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5095 at LCCOMB_X19_Y12_N16
T1L29 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M2644Q) # !R1_address_reg_a[6] & R1M2591Q);


--T1L30 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5096 at LCCOMB_X38_Y11_N18
T1L30 = !R1_address_reg_a[9] & (T1L29 & !R1_address_reg_a[7] & !T1L28 # !T1L29 & R1_address_reg_a[7] & T1L28);


--T1L166 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5431w~49 at LCCOMB_X19_Y12_N22
T1L166 = R1_address_reg_a[6] & (R1M1584Q # R1_address_reg_a[7]) # !R1_address_reg_a[6] & (!R1_address_reg_a[7] & R1M1531Q);


--T1L167 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5431w~50 at LCCOMB_X19_Y12_N26
T1L167 = T1L166 & (R1M1690Q # !R1_address_reg_a[7]) # !T1L166 & R1M1637Q & R1_address_reg_a[7];


--T1L164 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5429w~44 at LCCOMB_X19_Y14_N2
T1L164 = R1_address_reg_a[7] & (R1M1213Q # R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1M1107Q & !R1_address_reg_a[6]);


--T1L165 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5429w~45 at LCCOMB_X19_Y14_N30
T1L165 = T1L164 & (R1M1266Q # !R1_address_reg_a[6]) # !T1L164 & R1M1160Q & (R1_address_reg_a[6]);


--T1L31 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5097 at LCCOMB_X19_Y12_N4
T1L31 = R1_address_reg_a[9] & (T1L167) # !R1_address_reg_a[9] & T1L165;


--T1L168 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5513w~407 at LCCOMB_X19_Y14_N20
T1L168 = R1_address_reg_a[7] & (R1M1001Q # R1_address_reg_a[6]) # !R1_address_reg_a[7] & R1M895Q & (!R1_address_reg_a[6]);


--T1L169 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5513w~408 at LCCOMB_X19_Y14_N28
T1L169 = R1_address_reg_a[6] & (T1L168 & R1M1054Q # !T1L168 & (R1M948Q)) # !R1_address_reg_a[6] & (T1L168);


--T1L32 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5098 at LCCOMB_X19_Y14_N18
T1L32 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1478Q # !R1_address_reg_a[6] & (R1M1425Q));


--T1L33 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5099 at LCCOMB_X19_Y14_N26
T1L33 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M1372Q # !R1_address_reg_a[6] & (R1M1319Q));


--T1L34 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5100 at LCCOMB_X19_Y14_N0
T1L34 = R1_address_reg_a[9] & (T1L33 # T1L32) # !R1_address_reg_a[9] & T1L169;


--T1L35 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5101 at LCCOMB_X19_Y14_N16
T1L35 = R1_address_reg_a[8] & T1L31 # !R1_address_reg_a[8] & (T1L34);


--T1L172 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5529w~47 at LCCOMB_X38_Y11_N6
T1L172 = R1_address_reg_a[6] & (R1_address_reg_a[7] # R1M2432Q) # !R1_address_reg_a[6] & R1M2379Q & !R1_address_reg_a[7];


--T1L173 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5529w~48 at LCCOMB_X38_Y11_N0
T1L173 = T1L172 & (R1M2538Q # !R1_address_reg_a[7]) # !T1L172 & R1M2485Q & R1_address_reg_a[7];


--T1L160 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5328w~47 at LCCOMB_X38_Y15_N10
T1L160 = R1_address_reg_a[7] & (R1M789Q # R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1M683Q & !R1_address_reg_a[6]);


--T1L161 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5328w~48 at LCCOMB_X38_Y15_N6
T1L161 = T1L160 & (R1M842Q # !R1_address_reg_a[6]) # !T1L160 & R1_address_reg_a[6] & R1M736Q;


--T1L176 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~545 at LCCOMB_X38_Y11_N8
T1L176 = R1_address_reg_a[9] & (R1_address_reg_a[11] & (T1L173) # !R1_address_reg_a[11] & T1L161);


--T1L170 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5527w~44 at LCCOMB_X38_Y11_N12
T1L170 = R1_address_reg_a[6] & R1_address_reg_a[7] # !R1_address_reg_a[6] & (R1_address_reg_a[7] & (R1M2061Q) # !R1_address_reg_a[7] & R1M1955Q);


--T1L171 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5527w~45 at LCCOMB_X38_Y11_N24
T1L171 = T1L170 & (R1M2114Q # !R1_address_reg_a[6]) # !T1L170 & R1M2008Q & R1_address_reg_a[6];


--T1L158 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5326w~44 at LCCOMB_X38_Y11_N26
T1L158 = R1_address_reg_a[6] & (R1_address_reg_a[7] # R1M312Q) # !R1_address_reg_a[6] & !R1_address_reg_a[7] & (R1M259Q);


--T1L159 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5326w~45 at LCCOMB_X38_Y11_N30
T1L159 = R1_address_reg_a[7] & (T1L158 & R1M418Q # !T1L158 & (R1M365Q)) # !R1_address_reg_a[7] & T1L158;


--T1L177 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~546 at LCCOMB_X38_Y11_N2
T1L177 = !R1_address_reg_a[9] & (R1_address_reg_a[11] & T1L171 # !R1_address_reg_a[11] & (T1L159));


--T1L178 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~547 at LCCOMB_X38_Y11_N22
T1L178 = T1L147 # T1L232 & (T1L177 # T1L176);


--T1L174 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5611w~281 at LCCOMB_X19_Y14_N10
T1L174 = R1_address_reg_a[7] & (R1M1849Q # R1_address_reg_a[6]) # !R1_address_reg_a[7] & R1M1743Q & (!R1_address_reg_a[6]);


--T1L175 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5611w~282 at LCCOMB_X19_Y14_N22
T1L175 = T1L174 & (R1M1902Q # !R1_address_reg_a[6]) # !T1L174 & (R1M1796Q & R1_address_reg_a[6]);


--T1L162 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5411w~281 at LCCOMB_X19_Y14_N12
T1L162 = R1_address_reg_a[7] & (R1_address_reg_a[6]) # !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M100Q) # !R1_address_reg_a[6] & R1M47Q);


--T1L163 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5411w~282 at LCCOMB_X38_Y17_N22
T1L163 = R1_address_reg_a[7] & (T1L162 & R1M206Q # !T1L162 & (R1M153Q)) # !R1_address_reg_a[7] & (T1L162);


--T1L179 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~548 at LCCOMB_X38_Y11_N14
T1L179 = T1L236 & (R1_address_reg_a[11] & T1L175 # !R1_address_reg_a[11] & (T1L163));


--T1L180 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~549 at LCCOMB_X38_Y17_N16
T1L180 = R1_address_reg_a[6] & (R1_address_reg_a[7] & R1M2326Q # !R1_address_reg_a[7] & (R1M2220Q)) # !R1_address_reg_a[6] & R1_address_reg_a[7];


--T1L181 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~550 at LCCOMB_X38_Y17_N12
T1L181 = R1_address_reg_a[6] & (T1L180) # !R1_address_reg_a[6] & (T1L180 & (R1M2273Q) # !T1L180 & R1M2167Q);


--T1L182 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~551 at LCCOMB_X38_Y17_N4
T1L182 = !R1_address_reg_a[7] & (R1_address_reg_a[6] & (R1M524Q) # !R1_address_reg_a[6] & R1M471Q);


--T1L183 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~552 at LCCOMB_X38_Y17_N0
T1L183 = R1_address_reg_a[7] & (R1_address_reg_a[6] & R1M630Q # !R1_address_reg_a[6] & (R1M577Q));


--T1L184 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~553 at LCCOMB_X38_Y11_N10
T1L184 = R1_address_reg_a[11] & (T1L181) # !R1_address_reg_a[11] & (T1L183 # T1L182);


--T1L185 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|w_result5721w~554 at LCCOMB_X38_Y11_N16
T1L185 = T1L178 # T1L179 # T1L184 & T1L243;


--T1L36 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|mux_akb:mux5|result_node[3]~5102 at LCCOMB_X38_Y11_N20
T1L36 = T1L185 & (T1L30 # !R1_address_reg_a[10]) # !T1L185 & (T1L35 & R1_address_reg_a[10]);


--H1L24 is VGA_OSD_RAM:u6|Mux~35 at LCCOMB_X31_Y11_N14
H1L24 = H1_ADDR_dd[1] & (H1L23 & T1L36 # !H1L23 & (T1L27)) # !H1_ADDR_dd[1] & (H1L23);


--H1_ADDR_dd[2] is VGA_OSD_RAM:u6|ADDR_dd[2] at LCFF_X31_Y11_N3
H1_ADDR_dd[2] = DFFEAS(H1L12, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--H1L142 is VGA_OSD_RAM:u6|oRed~83 at LCCOMB_X31_Y11_N8
H1L142 = H1L141 & (H1_ADDR_dd[2] & (H1L22) # !H1_ADDR_dd[2] & H1L24);


--G1L3 is VGA_Pattern:u5|LessThan~2785 at LCCOMB_X25_Y11_N4
G1L3 = F1_oCoord_Y[4] & F1_oCoord_Y[5] & F1_oCoord_Y[6];


--G1L4 is VGA_Pattern:u5|LessThan~2786 at LCCOMB_X25_Y12_N16
G1L4 = !F1_oCoord_Y[8] & !F1_oCoord_Y[9];


--G1L50 is VGA_Pattern:u5|oRed~95 at LCCOMB_X25_Y11_N6
G1L50 = F1_oCoord_Y[7] & (G1L3) # !F1_oCoord_Y[7] & (!G1L3 # !F1_oCoord_Y[3]) # !G1L4;


--G1L5 is VGA_Pattern:u5|LessThan~2787 at LCCOMB_X25_Y11_N28
G1L5 = F1_oCoord_Y[7] # F1_oCoord_Y[3] & G1L3 # !G1L4;


--G1L41 is VGA_Pattern:u5|oGreen~1205 at LCCOMB_X27_Y11_N6
G1L41 = F1_oCoord_X[9] & (F1_oCoord_X[6] # G1L40 # !H1L13);


--G1L6 is VGA_Pattern:u5|LessThan~2788 at LCCOMB_X27_Y11_N4
G1L6 = !F1_oCoord_X[8] & (!G1L40 # !F1_oCoord_X[7] # !F1_oCoord_X[6]);


--G1L42 is VGA_Pattern:u5|oGreen~1206 at LCCOMB_X27_Y11_N0
G1L42 = F1_oCoord_X[9] # !G1L6;


--G1L7 is VGA_Pattern:u5|LessThan~2789 at LCCOMB_X24_Y10_N8
G1L7 = F1_oCoord_Y[3] & F1_oCoord_Y[2];


--G1L8 is VGA_Pattern:u5|LessThan~2790 at LCCOMB_X25_Y10_N24
G1L8 = !F1_oCoord_Y[7] & !F1_oCoord_Y[8] & !F1_oCoord_Y[9] & G1L13;


--G1L21 is VGA_Pattern:u5|oBlue~1287 at LCCOMB_X26_Y10_N26
G1L21 = F1_oCoord_Y[6] # F1_oCoord_Y[5] & (F1_oCoord_Y[4] # !F1L227);


--G1L51 is VGA_Pattern:u5|oRed~96 at LCCOMB_X26_Y10_N30
G1L51 = F1_oCoord_Y[8] & (F1_oCoord_Y[7] # !G1L1);


--G1L22 is VGA_Pattern:u5|oBlue~1288 at LCCOMB_X26_Y10_N24
G1L22 = F1_oCoord_Y[9] # F1_oCoord_Y[7] & G1L21 # !G1L51;


--G1L9 is VGA_Pattern:u5|LessThan~2791 at LCCOMB_X26_Y11_N0
G1L9 = F1_oCoord_Y[7] & (F1_oCoord_Y[6] # G1L2 & !F1L227);


--G1L10 is VGA_Pattern:u5|LessThan~2792 at LCCOMB_X25_Y10_N30
G1L10 = F1_oCoord_Y[7] # F1_oCoord_Y[6] & F1_oCoord_Y[3] & G1L2;


--G1L23 is VGA_Pattern:u5|oBlue~1289 at LCCOMB_X26_Y12_N8
G1L23 = F1_oCoord_Y[9] # F1_oCoord_Y[8] # G1L9 # !G1L10;


--G1L11 is VGA_Pattern:u5|LessThan~2793 at LCCOMB_X26_Y12_N26
G1L11 = F1_oCoord_Y[5] & (F1_oCoord_Y[4] # G1L7) # !H1L16;


--G1L24 is VGA_Pattern:u5|oBlue~1290 at LCCOMB_X26_Y12_N12
G1L24 = F1_oCoord_Y[8] & (G1L11) # !F1_oCoord_Y[8] & (!G1L3 # !F1_oCoord_Y[7]);


--G1L12 is VGA_Pattern:u5|LessThan~2794 at LCCOMB_X26_Y12_N28
G1L12 = !F1_oCoord_Y[8] & !G1L3 & G1L9;


--G1L25 is VGA_Pattern:u5|oBlue~1291 at LCCOMB_X26_Y12_N2
G1L25 = G1L23 & (F1_oCoord_Y[9] # G1L12 # G1L24);


--G1L17 is VGA_Pattern:u5|oBlue[7]~1292 at LCCOMB_X26_Y12_N20
G1L17 = !G1L10 & !F1_oCoord_Y[8] & !G1L9;


--G1L18 is VGA_Pattern:u5|oBlue[7]~1293 at LCCOMB_X26_Y12_N10
G1L18 = G1L17 # F1_oCoord_Y[9] # G1L11 & G1L51;


--G1L26 is VGA_Pattern:u5|oBlue~1294 at LCCOMB_X25_Y10_N28
G1L26 = G1L13 & F1_oCoord_Y[7] # !G1L13 & (G1L10) # !G1L4;


--G1L27 is VGA_Pattern:u5|oBlue~1295 at LCCOMB_X26_Y12_N22
G1L27 = G1L18 & (G1L22) # !G1L18 & G1L25 # !G1L26;


--G1L28 is VGA_Pattern:u5|oBlue~1296 at LCCOMB_X26_Y12_N6
G1L28 = F1_oCoord_Y[9] # !G1L12 & G1L24 # !G1L23;


--G1L29 is VGA_Pattern:u5|oBlue~1297 at LCCOMB_X26_Y12_N30
G1L29 = G1L18 & !G1L22 # !G1L18 & (G1L28) # !G1L26;


--G1L30 is VGA_Pattern:u5|oBlue~1298 at LCCOMB_X26_Y12_N18
G1L30 = !F1_oCoord_Y[8] & (!G1L9 # !G1L3) # !G1L24;


--K1L11 is AUDIO_DAC:u8|LRCK_1X_DIV[0]~145 at LCCOMB_X30_Y7_N0
K1L11 = K1_LRCK_1X_DIV[0] $ VCC;

--K1L12 is AUDIO_DAC:u8|LRCK_1X_DIV[0]~146 at LCCOMB_X30_Y7_N0
K1L12 = CARRY(K1_LRCK_1X_DIV[0]);


--K1L14 is AUDIO_DAC:u8|LRCK_1X_DIV[1]~147 at LCCOMB_X30_Y7_N2
K1L14 = K1_LRCK_1X_DIV[1] & !K1L12 # !K1_LRCK_1X_DIV[1] & (K1L12 # GND);

--K1L15 is AUDIO_DAC:u8|LRCK_1X_DIV[1]~148 at LCCOMB_X30_Y7_N2
K1L15 = CARRY(!K1L12 # !K1_LRCK_1X_DIV[1]);


--K1L17 is AUDIO_DAC:u8|LRCK_1X_DIV[2]~149 at LCCOMB_X30_Y7_N4
K1L17 = K1_LRCK_1X_DIV[2] & (K1L15 $ GND) # !K1_LRCK_1X_DIV[2] & !K1L15 & VCC;

--K1L18 is AUDIO_DAC:u8|LRCK_1X_DIV[2]~150 at LCCOMB_X30_Y7_N4
K1L18 = CARRY(K1_LRCK_1X_DIV[2] & !K1L15);


--K1L20 is AUDIO_DAC:u8|LRCK_1X_DIV[3]~151 at LCCOMB_X30_Y7_N6
K1L20 = K1_LRCK_1X_DIV[3] & !K1L18 # !K1_LRCK_1X_DIV[3] & (K1L18 # GND);

--K1L21 is AUDIO_DAC:u8|LRCK_1X_DIV[3]~152 at LCCOMB_X30_Y7_N6
K1L21 = CARRY(!K1L18 # !K1_LRCK_1X_DIV[3]);


--K1L23 is AUDIO_DAC:u8|LRCK_1X_DIV[4]~153 at LCCOMB_X30_Y7_N8
K1L23 = K1_LRCK_1X_DIV[4] & (K1L21 $ GND) # !K1_LRCK_1X_DIV[4] & !K1L21 & VCC;

--K1L24 is AUDIO_DAC:u8|LRCK_1X_DIV[4]~154 at LCCOMB_X30_Y7_N8
K1L24 = CARRY(K1_LRCK_1X_DIV[4] & !K1L21);


--K1L26 is AUDIO_DAC:u8|LRCK_1X_DIV[5]~155 at LCCOMB_X30_Y7_N10
K1L26 = K1_LRCK_1X_DIV[5] & !K1L24 # !K1_LRCK_1X_DIV[5] & (K1L24 # GND);

--K1L27 is AUDIO_DAC:u8|LRCK_1X_DIV[5]~156 at LCCOMB_X30_Y7_N10
K1L27 = CARRY(!K1L24 # !K1_LRCK_1X_DIV[5]);


--K1L29 is AUDIO_DAC:u8|LRCK_1X_DIV[6]~157 at LCCOMB_X30_Y7_N12
K1L29 = K1_LRCK_1X_DIV[6] & (K1L27 $ GND) # !K1_LRCK_1X_DIV[6] & !K1L27 & VCC;

--K1L30 is AUDIO_DAC:u8|LRCK_1X_DIV[6]~158 at LCCOMB_X30_Y7_N12
K1L30 = CARRY(K1_LRCK_1X_DIV[6] & !K1L27);


--K1L32 is AUDIO_DAC:u8|LRCK_1X_DIV[7]~159 at LCCOMB_X30_Y7_N14
K1L32 = K1_LRCK_1X_DIV[7] & !K1L30 # !K1_LRCK_1X_DIV[7] & (K1L30 # GND);

--K1L33 is AUDIO_DAC:u8|LRCK_1X_DIV[7]~160 at LCCOMB_X30_Y7_N14
K1L33 = CARRY(!K1L30 # !K1_LRCK_1X_DIV[7]);


--K1L35 is AUDIO_DAC:u8|LRCK_1X_DIV[8]~161 at LCCOMB_X30_Y7_N16
K1L35 = K1_LRCK_1X_DIV[8] $ !K1L33;


--K1_BCK_DIV[2] is AUDIO_DAC:u8|BCK_DIV[2] at LCFF_X34_Y13_N5
K1_BCK_DIV[2] = DFFEAS(K1L5, GLOBAL(M1L4), KEY[0],  ,  ,  ,  ,  ,  );


--K1_BCK_DIV[1] is AUDIO_DAC:u8|BCK_DIV[1] at LCFF_X34_Y13_N11
K1_BCK_DIV[1] = DFFEAS(K1L6, GLOBAL(M1L4), KEY[0],  ,  ,  ,  ,  ,  );


--K1_BCK_DIV[0] is AUDIO_DAC:u8|BCK_DIV[0] at LCFF_X34_Y13_N13
K1_BCK_DIV[0] = DFFEAS(K1L7, GLOBAL(M1L4), KEY[0],  ,  ,  ,  ,  ,  );


--K1L125 is AUDIO_DAC:u8|oAUD_BCK~37 at LCCOMB_X34_Y13_N6
K1L125 = K1_oAUD_BCK $ (K1_BCK_DIV[2] & (K1_BCK_DIV[0] # K1_BCK_DIV[1]));


--V1L25Q is I2C_AV_Config:u7|I2C_Controller:u0|SDO~reg0 at LCFF_X32_Y14_N25
V1L25Q = DFFEAS(V1L73, GLOBAL(J1L73), KEY[0],  ,  ,  ,  ,  ,  );


--V1L13 is I2C_AV_Config:u7|I2C_Controller:u0|END~124 at LCCOMB_X35_Y14_N18
V1L13 = V1L43Q & V1L55Q & V1L49Q & V1L52Q;


--V1L14 is I2C_AV_Config:u7|I2C_Controller:u0|END~125 at LCCOMB_X35_Y14_N22
V1L14 = V1L46Q & (V1L13 & V1L58Q # !V1L13 & (V1_END)) # !V1L46Q & (V1_END);


--V1_ACK3 is I2C_AV_Config:u7|I2C_Controller:u0|ACK3 at LCFF_X34_Y14_N11
V1_ACK3 = DFFEAS(V1L11, GLOBAL(J1L73), KEY[0],  ,  ,  ,  ,  ,  );


--V1_ACK1 is I2C_AV_Config:u7|I2C_Controller:u0|ACK1 at LCFF_X32_Y14_N15
V1_ACK1 = DFFEAS(V1L3, GLOBAL(J1L73), KEY[0],  ,  ,  ,  ,  ,  );


--V1_ACK2 is I2C_AV_Config:u7|I2C_Controller:u0|ACK2 at LCFF_X34_Y13_N1
V1_ACK2 = DFFEAS(V1L8, GLOBAL(J1L73), KEY[0],  ,  ,  ,  ,  ,  );


--J1L90 is I2C_AV_Config:u7|mSetup_ST~58 at LCCOMB_X34_Y14_N14
J1L90 = !V1_ACK3 & !V1_ACK1 & !V1_ACK2;


--J1L91 is I2C_AV_Config:u7|mSetup_ST~59 at LCCOMB_X35_Y14_N30
J1L91 = J1L90 & !V1_END & J1_mSetup_ST.01;


--J1_mSetup_ST.00 is I2C_AV_Config:u7|mSetup_ST.00 at LCFF_X35_Y14_N11
J1_mSetup_ST.00 = DFFEAS(J1L21, GLOBAL(J1L73), KEY[0],  ,  ,  ,  ,  ,  );


--J1L20 is I2C_AV_Config:u7|Select~136 at LCCOMB_X35_Y14_N4
J1L20 = V1_END & J1_mSetup_ST.01 # !J1_mSetup_ST.00;


--F1L224 is VGA_Controller:u4|oCoord_Y[1]~477 at LCCOMB_X24_Y10_N10
F1L224 = F1_V_Cont[1] $ VCC;

--F1L225 is VGA_Controller:u4|oCoord_Y[1]~478 at LCCOMB_X24_Y10_N10
F1L225 = CARRY(F1_V_Cont[1]);


--F1L229 is VGA_Controller:u4|oCoord_Y[2]~479 at LCCOMB_X24_Y10_N12
F1L229 = F1_V_Cont[2] & F1L225 & VCC # !F1_V_Cont[2] & !F1L225;

--F1L230 is VGA_Controller:u4|oCoord_Y[2]~480 at LCCOMB_X24_Y10_N12
F1L230 = CARRY(!F1_V_Cont[2] & !F1L225);


--F1L232 is VGA_Controller:u4|oCoord_Y[3]~481 at LCCOMB_X24_Y10_N14
F1L232 = F1_V_Cont[3] & (GND # !F1L230) # !F1_V_Cont[3] & (F1L230 $ GND);

--F1L233 is VGA_Controller:u4|oCoord_Y[3]~482 at LCCOMB_X24_Y10_N14
F1L233 = CARRY(F1_V_Cont[3] # !F1L230);


--F1L235 is VGA_Controller:u4|oCoord_Y[4]~483 at LCCOMB_X24_Y10_N16
F1L235 = F1_V_Cont[4] & F1L233 & VCC # !F1_V_Cont[4] & !F1L233;

--F1L236 is VGA_Controller:u4|oCoord_Y[4]~484 at LCCOMB_X24_Y10_N16
F1L236 = CARRY(!F1_V_Cont[4] & !F1L233);


--F1L238 is VGA_Controller:u4|oCoord_Y[5]~485 at LCCOMB_X24_Y10_N18
F1L238 = F1_V_Cont[5] & (F1L236 $ GND) # !F1_V_Cont[5] & !F1L236 & VCC;

--F1L239 is VGA_Controller:u4|oCoord_Y[5]~486 at LCCOMB_X24_Y10_N18
F1L239 = CARRY(F1_V_Cont[5] & !F1L236);


--F1L241 is VGA_Controller:u4|oCoord_Y[6]~487 at LCCOMB_X24_Y10_N20
F1L241 = F1_V_Cont[6] & F1L239 & VCC # !F1_V_Cont[6] & !F1L239;

--F1L242 is VGA_Controller:u4|oCoord_Y[6]~488 at LCCOMB_X24_Y10_N20
F1L242 = CARRY(!F1_V_Cont[6] & !F1L239);


--F1L244 is VGA_Controller:u4|oCoord_Y[7]~489 at LCCOMB_X24_Y10_N22
F1L244 = F1_V_Cont[7] & (GND # !F1L242) # !F1_V_Cont[7] & (F1L242 $ GND);

--F1L245 is VGA_Controller:u4|oCoord_Y[7]~490 at LCCOMB_X24_Y10_N22
F1L245 = CARRY(F1_V_Cont[7] # !F1L242);


--F1L247 is VGA_Controller:u4|oCoord_Y[8]~491 at LCCOMB_X24_Y10_N24
F1L247 = F1_V_Cont[8] & F1L245 & VCC # !F1_V_Cont[8] & !F1L245;

--F1L248 is VGA_Controller:u4|oCoord_Y[8]~492 at LCCOMB_X24_Y10_N24
F1L248 = CARRY(!F1_V_Cont[8] & !F1L245);


--F1L250 is VGA_Controller:u4|oCoord_Y[9]~493 at LCCOMB_X24_Y10_N26
F1L250 = F1_V_Cont[9] $ F1L248;


--F1L135 is VGA_Controller:u4|always0~249 at LCCOMB_X30_Y11_N18
F1L135 = F1_H_Cont[8] & (F1L63 & !F1_H_Cont[7] # !F1_H_Cont[9]) # !F1_H_Cont[8] & (F1_H_Cont[9] # !F1L63 & F1_H_Cont[7]);


--F1L136 is VGA_Controller:u4|always0~250 at LCCOMB_X30_Y11_N30
F1L136 = F1L265 & F1L135;


--F1L198 is VGA_Controller:u4|oCoord_X[2]~1422 at LCCOMB_X30_Y11_N2
F1L198 = F1_H_Cont[2] $ VCC;

--F1L199 is VGA_Controller:u4|oCoord_X[2]~1423 at LCCOMB_X30_Y11_N2
F1L199 = CARRY(F1_H_Cont[2]);


--F1L201 is VGA_Controller:u4|oCoord_X[3]~1424 at LCCOMB_X30_Y11_N4
F1L201 = F1_H_Cont[3] & F1L199 & VCC # !F1_H_Cont[3] & !F1L199;

--F1L202 is VGA_Controller:u4|oCoord_X[3]~1425 at LCCOMB_X30_Y11_N4
F1L202 = CARRY(!F1_H_Cont[3] & !F1L199);


--F1L204 is VGA_Controller:u4|oCoord_X[4]~1426 at LCCOMB_X30_Y11_N6
F1L204 = F1_H_Cont[4] & (F1L202 $ GND) # !F1_H_Cont[4] & !F1L202 & VCC;

--F1L205 is VGA_Controller:u4|oCoord_X[4]~1427 at LCCOMB_X30_Y11_N6
F1L205 = CARRY(F1_H_Cont[4] & !F1L202);


--F1L207 is VGA_Controller:u4|oCoord_X[5]~1428 at LCCOMB_X30_Y11_N8
F1L207 = F1_H_Cont[5] & F1L205 & VCC # !F1_H_Cont[5] & !F1L205;

--F1L208 is VGA_Controller:u4|oCoord_X[5]~1429 at LCCOMB_X30_Y11_N8
F1L208 = CARRY(!F1_H_Cont[5] & !F1L205);


--F1L210 is VGA_Controller:u4|oCoord_X[6]~1430 at LCCOMB_X30_Y11_N10
F1L210 = F1_H_Cont[6] & (GND # !F1L208) # !F1_H_Cont[6] & (F1L208 $ GND);

--F1L211 is VGA_Controller:u4|oCoord_X[6]~1431 at LCCOMB_X30_Y11_N10
F1L211 = CARRY(F1_H_Cont[6] # !F1L208);


--F1L213 is VGA_Controller:u4|oCoord_X[7]~1432 at LCCOMB_X30_Y11_N12
F1L213 = F1_H_Cont[7] & !F1L211 # !F1_H_Cont[7] & (F1L211 # GND);

--F1L214 is VGA_Controller:u4|oCoord_X[7]~1433 at LCCOMB_X30_Y11_N12
F1L214 = CARRY(!F1L211 # !F1_H_Cont[7]);


--F1L216 is VGA_Controller:u4|oCoord_X[8]~1434 at LCCOMB_X30_Y11_N14
F1L216 = F1_H_Cont[8] & (GND # !F1L214) # !F1_H_Cont[8] & (F1L214 $ GND);

--F1L217 is VGA_Controller:u4|oCoord_X[8]~1435 at LCCOMB_X30_Y11_N14
F1L217 = CARRY(F1_H_Cont[8] # !F1L214);


--F1L219 is VGA_Controller:u4|oCoord_X[9]~1436 at LCCOMB_X30_Y11_N16
F1L219 = F1L217 $ !F1_H_Cont[9];


--R1_address_reg_a[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[3] at LCFF_X31_Y10_N13
R1_address_reg_a[3] = DFFEAS(H1L129, GLOBAL(M1L2),  ,  ,  ,  ,  ,  ,  );


--R1_address_reg_a[2] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[2] at LCFF_X31_Y10_N11
R1_address_reg_a[2] = DFFEAS(H1L127, GLOBAL(M1L2),  ,  ,  ,  ,  ,  ,  );


--R1_address_reg_a[1] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[1] at LCFF_X31_Y10_N9
R1_address_reg_a[1] = DFFEAS(H1L125, GLOBAL(M1L2),  ,  ,  ,  ,  ,  ,  );


--F1_oCoord_Y[0] is VGA_Controller:u4|oCoord_Y[0] at LCFF_X25_Y10_N1
F1_oCoord_Y[0] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(M1L2), KEY[0],  , F1L136, F1_V_Cont[0],  ,  , VCC);


--H1L26 is VGA_OSD_RAM:u6|add~1377 at LCCOMB_X25_Y10_N0
H1L26 = CARRY(!F1_oCoord_Y[0]);


--H1L27 is VGA_OSD_RAM:u6|add~1378 at LCCOMB_X25_Y10_N2
H1L27 = F1_oCoord_Y[1] & (H1L26 # GND) # !F1_oCoord_Y[1] & !H1L26;

--H1L28 is VGA_OSD_RAM:u6|add~1379 at LCCOMB_X25_Y10_N2
H1L28 = CARRY(F1_oCoord_Y[1] # !H1L26);


--H1L29 is VGA_OSD_RAM:u6|add~1380 at LCCOMB_X25_Y10_N4
H1L29 = F1_oCoord_Y[2] & !H1L28 & VCC # !F1_oCoord_Y[2] & (H1L28 $ GND);

--H1L30 is VGA_OSD_RAM:u6|add~1381 at LCCOMB_X25_Y10_N4
H1L30 = CARRY(!F1_oCoord_Y[2] & !H1L28);


--H1L31 is VGA_OSD_RAM:u6|add~1382 at LCCOMB_X25_Y10_N6
H1L31 = F1_oCoord_Y[3] & (H1L30 # GND) # !F1_oCoord_Y[3] & !H1L30;

--H1L32 is VGA_OSD_RAM:u6|add~1383 at LCCOMB_X25_Y10_N6
H1L32 = CARRY(F1_oCoord_Y[3] # !H1L30);


--H1L33 is VGA_OSD_RAM:u6|add~1384 at LCCOMB_X25_Y10_N8
H1L33 = F1_oCoord_Y[4] & !H1L32 & VCC # !F1_oCoord_Y[4] & (H1L32 $ GND);

--H1L34 is VGA_OSD_RAM:u6|add~1385 at LCCOMB_X25_Y10_N8
H1L34 = CARRY(!F1_oCoord_Y[4] & !H1L32);


--H1L35 is VGA_OSD_RAM:u6|add~1386 at LCCOMB_X25_Y10_N10
H1L35 = F1_oCoord_Y[5] & (H1L34 # GND) # !F1_oCoord_Y[5] & !H1L34;

--H1L36 is VGA_OSD_RAM:u6|add~1387 at LCCOMB_X25_Y10_N10
H1L36 = CARRY(F1_oCoord_Y[5] # !H1L34);


--H1L37 is VGA_OSD_RAM:u6|add~1388 at LCCOMB_X25_Y10_N12
H1L37 = F1_oCoord_Y[6] & !H1L36 & VCC # !F1_oCoord_Y[6] & (H1L36 $ GND);

--H1L38 is VGA_OSD_RAM:u6|add~1389 at LCCOMB_X25_Y10_N12
H1L38 = CARRY(!F1_oCoord_Y[6] & !H1L36);


--H1L39 is VGA_OSD_RAM:u6|add~1390 at LCCOMB_X25_Y10_N14
H1L39 = F1_oCoord_Y[7] & (H1L38 # GND) # !F1_oCoord_Y[7] & !H1L38;

--H1L40 is VGA_OSD_RAM:u6|add~1391 at LCCOMB_X25_Y10_N14
H1L40 = CARRY(F1_oCoord_Y[7] # !H1L38);


--H1L41 is VGA_OSD_RAM:u6|add~1392 at LCCOMB_X25_Y10_N16
H1L41 = F1_oCoord_Y[8] & !H1L40 & VCC # !F1_oCoord_Y[8] & (H1L40 $ GND);

--H1L42 is VGA_OSD_RAM:u6|add~1393 at LCCOMB_X25_Y10_N16
H1L42 = CARRY(!F1_oCoord_Y[8] & !H1L40);


--H1L43 is VGA_OSD_RAM:u6|add~1394 at LCCOMB_X25_Y10_N18
H1L43 = F1_oCoord_Y[9] & (H1L42 # GND) # !F1_oCoord_Y[9] & !H1L42;

--H1L44 is VGA_OSD_RAM:u6|add~1395 at LCCOMB_X25_Y10_N18
H1L44 = CARRY(F1_oCoord_Y[9] # !H1L42);


--H1L45 is VGA_OSD_RAM:u6|add~1396 at LCCOMB_X25_Y10_N20
H1L45 = H1L44 $ GND;

--H1L46 is VGA_OSD_RAM:u6|add~1397 at LCCOMB_X25_Y10_N20
H1L46 = CARRY(!H1L44);


--H1L47 is VGA_OSD_RAM:u6|add~1398 at LCCOMB_X25_Y10_N22
H1L47 = !H1L46;


--H1L49 is VGA_OSD_RAM:u6|add~1400 at LCCOMB_X26_Y10_N0
H1L49 = H1L33 & (F1_oCoord_Y[0] $ VCC) # !H1L33 & F1_oCoord_Y[0] & VCC;

--H1L50 is VGA_OSD_RAM:u6|add~1401 at LCCOMB_X26_Y10_N0
H1L50 = CARRY(H1L33 & F1_oCoord_Y[0]);


--H1L51 is VGA_OSD_RAM:u6|add~1402 at LCCOMB_X26_Y10_N2
H1L51 = H1L35 & (F1_oCoord_Y[1] & H1L50 & VCC # !F1_oCoord_Y[1] & !H1L50) # !H1L35 & (F1_oCoord_Y[1] & !H1L50 # !F1_oCoord_Y[1] & (H1L50 # GND));

--H1L52 is VGA_OSD_RAM:u6|add~1403 at LCCOMB_X26_Y10_N2
H1L52 = CARRY(H1L35 & !F1_oCoord_Y[1] & !H1L50 # !H1L35 & (!H1L50 # !F1_oCoord_Y[1]));


--H1L53 is VGA_OSD_RAM:u6|add~1404 at LCCOMB_X26_Y10_N4
H1L53 = (F1_oCoord_Y[2] $ H1L37 $ !H1L52) # GND;

--H1L54 is VGA_OSD_RAM:u6|add~1405 at LCCOMB_X26_Y10_N4
H1L54 = CARRY(F1_oCoord_Y[2] & (H1L37 # !H1L52) # !F1_oCoord_Y[2] & H1L37 & !H1L52);


--H1L55 is VGA_OSD_RAM:u6|add~1406 at LCCOMB_X26_Y10_N6
H1L55 = H1L39 & (F1_oCoord_Y[3] & H1L54 & VCC # !F1_oCoord_Y[3] & !H1L54) # !H1L39 & (F1_oCoord_Y[3] & !H1L54 # !F1_oCoord_Y[3] & (H1L54 # GND));

--H1L56 is VGA_OSD_RAM:u6|add~1407 at LCCOMB_X26_Y10_N6
H1L56 = CARRY(H1L39 & !F1_oCoord_Y[3] & !H1L54 # !H1L39 & (!H1L54 # !F1_oCoord_Y[3]));


--H1L57 is VGA_OSD_RAM:u6|add~1408 at LCCOMB_X26_Y10_N8
H1L57 = (H1L41 $ F1_oCoord_Y[4] $ !H1L56) # GND;

--H1L58 is VGA_OSD_RAM:u6|add~1409 at LCCOMB_X26_Y10_N8
H1L58 = CARRY(H1L41 & (F1_oCoord_Y[4] # !H1L56) # !H1L41 & F1_oCoord_Y[4] & !H1L56);


--H1L59 is VGA_OSD_RAM:u6|add~1410 at LCCOMB_X26_Y10_N10
H1L59 = H1L43 & (F1_oCoord_Y[5] & H1L58 & VCC # !F1_oCoord_Y[5] & !H1L58) # !H1L43 & (F1_oCoord_Y[5] & !H1L58 # !F1_oCoord_Y[5] & (H1L58 # GND));

--H1L60 is VGA_OSD_RAM:u6|add~1411 at LCCOMB_X26_Y10_N10
H1L60 = CARRY(H1L43 & !F1_oCoord_Y[5] & !H1L58 # !H1L43 & (!H1L58 # !F1_oCoord_Y[5]));


--H1L61 is VGA_OSD_RAM:u6|add~1412 at LCCOMB_X26_Y10_N12
H1L61 = (H1L45 $ F1_oCoord_Y[6] $ !H1L60) # GND;

--H1L62 is VGA_OSD_RAM:u6|add~1413 at LCCOMB_X26_Y10_N12
H1L62 = CARRY(H1L45 & (F1_oCoord_Y[6] # !H1L60) # !H1L45 & F1_oCoord_Y[6] & !H1L60);


--H1L63 is VGA_OSD_RAM:u6|add~1414 at LCCOMB_X26_Y10_N14
H1L63 = F1_oCoord_Y[7] & (H1L47 & H1L62 & VCC # !H1L47 & !H1L62) # !F1_oCoord_Y[7] & (H1L47 & !H1L62 # !H1L47 & (H1L62 # GND));

--H1L64 is VGA_OSD_RAM:u6|add~1415 at LCCOMB_X26_Y10_N14
H1L64 = CARRY(F1_oCoord_Y[7] & !H1L47 & !H1L62 # !F1_oCoord_Y[7] & (!H1L62 # !H1L47));


--H1L65 is VGA_OSD_RAM:u6|add~1416 at LCCOMB_X26_Y10_N16
H1L65 = (F1_oCoord_Y[8] $ H1L47 $ !H1L64) # GND;

--H1L66 is VGA_OSD_RAM:u6|add~1417 at LCCOMB_X26_Y10_N16
H1L66 = CARRY(F1_oCoord_Y[8] & (H1L47 # !H1L64) # !F1_oCoord_Y[8] & H1L47 & !H1L64);


--H1L67 is VGA_OSD_RAM:u6|add~1418 at LCCOMB_X26_Y10_N18
H1L67 = F1_oCoord_Y[9] & (H1L47 & H1L66 & VCC # !H1L47 & !H1L66) # !F1_oCoord_Y[9] & (H1L47 & !H1L66 # !H1L47 & (H1L66 # GND));

--H1L68 is VGA_OSD_RAM:u6|add~1419 at LCCOMB_X26_Y10_N18
H1L68 = CARRY(F1_oCoord_Y[9] & !H1L47 & !H1L66 # !F1_oCoord_Y[9] & (!H1L66 # !H1L47));


--H1L69 is VGA_OSD_RAM:u6|add~1420 at LCCOMB_X26_Y10_N20
H1L69 = H1L68 $ !H1L47;


--F1_oAddress[17] is VGA_Controller:u4|oAddress[17] at LCFF_X29_Y10_N17
F1_oAddress[17] = DFFEAS(F1L190, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[16] is VGA_Controller:u4|oAddress[16] at LCFF_X29_Y10_N15
F1_oAddress[16] = DFFEAS(F1L187, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[15] is VGA_Controller:u4|oAddress[15] at LCFF_X29_Y10_N13
F1_oAddress[15] = DFFEAS(F1L184, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[14] is VGA_Controller:u4|oAddress[14] at LCFF_X29_Y10_N11
F1_oAddress[14] = DFFEAS(F1L181, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[13] is VGA_Controller:u4|oAddress[13] at LCFF_X29_Y10_N9
F1_oAddress[13] = DFFEAS(F1L178, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[12] is VGA_Controller:u4|oAddress[12] at LCFF_X29_Y10_N7
F1_oAddress[12] = DFFEAS(F1L175, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[11] is VGA_Controller:u4|oAddress[11] at LCFF_X29_Y10_N5
F1_oAddress[11] = DFFEAS(F1L172, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[10] is VGA_Controller:u4|oAddress[10] at LCFF_X29_Y10_N3
F1_oAddress[10] = DFFEAS(F1L169, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[9] is VGA_Controller:u4|oAddress[9] at LCFF_X29_Y10_N1
F1_oAddress[9] = DFFEAS(F1L166, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[8] is VGA_Controller:u4|oAddress[8] at LCFF_X29_Y11_N31
F1_oAddress[8] = DFFEAS(F1L163, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[7] is VGA_Controller:u4|oAddress[7] at LCFF_X29_Y11_N29
F1_oAddress[7] = DFFEAS(F1L160, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[6] is VGA_Controller:u4|oAddress[6] at LCFF_X29_Y11_N27
F1_oAddress[6] = DFFEAS(F1L157, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[5] is VGA_Controller:u4|oAddress[5] at LCFF_X29_Y11_N25
F1_oAddress[5] = DFFEAS(F1L154, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[4] is VGA_Controller:u4|oAddress[4] at LCFF_X29_Y11_N23
F1_oAddress[4] = DFFEAS(F1L151, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[3] is VGA_Controller:u4|oAddress[3] at LCFF_X29_Y11_N21
F1_oAddress[3] = DFFEAS(F1L148, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--H1L71 is VGA_OSD_RAM:u6|add~1422 at LCCOMB_X27_Y10_N2
H1L71 = F1_oCoord_Y[0] & (F1_oAddress[3] $ VCC) # !F1_oCoord_Y[0] & (F1_oAddress[3] # GND);

--H1L72 is VGA_OSD_RAM:u6|add~1423 at LCCOMB_X27_Y10_N2
H1L72 = CARRY(F1_oAddress[3] # !F1_oCoord_Y[0]);


--H1L73 is VGA_OSD_RAM:u6|add~1424 at LCCOMB_X27_Y10_N4
H1L73 = F1_oAddress[4] & (H1L27 & !H1L72 # !H1L27 & H1L72 & VCC) # !F1_oAddress[4] & (H1L27 & (H1L72 # GND) # !H1L27 & !H1L72);

--H1L74 is VGA_OSD_RAM:u6|add~1425 at LCCOMB_X27_Y10_N4
H1L74 = CARRY(F1_oAddress[4] & H1L27 & !H1L72 # !F1_oAddress[4] & (H1L27 # !H1L72));


--H1L75 is VGA_OSD_RAM:u6|add~1426 at LCCOMB_X27_Y10_N6
H1L75 = (H1L29 $ F1_oAddress[5] $ H1L74) # GND;

--H1L76 is VGA_OSD_RAM:u6|add~1427 at LCCOMB_X27_Y10_N6
H1L76 = CARRY(H1L29 & F1_oAddress[5] & !H1L74 # !H1L29 & (F1_oAddress[5] # !H1L74));


--H1L77 is VGA_OSD_RAM:u6|add~1428 at LCCOMB_X27_Y10_N8
H1L77 = F1_oAddress[6] & (H1L31 & !H1L76 # !H1L31 & H1L76 & VCC) # !F1_oAddress[6] & (H1L31 & (H1L76 # GND) # !H1L31 & !H1L76);

--H1L78 is VGA_OSD_RAM:u6|add~1429 at LCCOMB_X27_Y10_N8
H1L78 = CARRY(F1_oAddress[6] & H1L31 & !H1L76 # !F1_oAddress[6] & (H1L31 # !H1L76));


--H1L79 is VGA_OSD_RAM:u6|add~1430 at LCCOMB_X27_Y10_N10
H1L79 = (H1L49 $ F1_oAddress[7] $ H1L78) # GND;

--H1L80 is VGA_OSD_RAM:u6|add~1431 at LCCOMB_X27_Y10_N10
H1L80 = CARRY(H1L49 & F1_oAddress[7] & !H1L78 # !H1L49 & (F1_oAddress[7] # !H1L78));


--H1L81 is VGA_OSD_RAM:u6|add~1432 at LCCOMB_X27_Y10_N12
H1L81 = H1L51 & (F1_oAddress[8] & !H1L80 # !F1_oAddress[8] & (H1L80 # GND)) # !H1L51 & (F1_oAddress[8] & H1L80 & VCC # !F1_oAddress[8] & !H1L80);

--H1L82 is VGA_OSD_RAM:u6|add~1433 at LCCOMB_X27_Y10_N12
H1L82 = CARRY(H1L51 & (!H1L80 # !F1_oAddress[8]) # !H1L51 & !F1_oAddress[8] & !H1L80);


--H1L83 is VGA_OSD_RAM:u6|add~1434 at LCCOMB_X27_Y10_N14
H1L83 = (F1_oAddress[9] $ H1L53 $ H1L82) # GND;

--H1L84 is VGA_OSD_RAM:u6|add~1435 at LCCOMB_X27_Y10_N14
H1L84 = CARRY(F1_oAddress[9] & (!H1L82 # !H1L53) # !F1_oAddress[9] & !H1L53 & !H1L82);


--H1L85 is VGA_OSD_RAM:u6|add~1436 at LCCOMB_X27_Y10_N16
H1L85 = F1_oAddress[10] & (H1L55 & !H1L84 # !H1L55 & H1L84 & VCC) # !F1_oAddress[10] & (H1L55 & (H1L84 # GND) # !H1L55 & !H1L84);

--H1L86 is VGA_OSD_RAM:u6|add~1437 at LCCOMB_X27_Y10_N16
H1L86 = CARRY(F1_oAddress[10] & H1L55 & !H1L84 # !F1_oAddress[10] & (H1L55 # !H1L84));


--H1L87 is VGA_OSD_RAM:u6|add~1438 at LCCOMB_X27_Y10_N18
H1L87 = (H1L57 $ F1_oAddress[11] $ H1L86) # GND;

--H1L88 is VGA_OSD_RAM:u6|add~1439 at LCCOMB_X27_Y10_N18
H1L88 = CARRY(H1L57 & F1_oAddress[11] & !H1L86 # !H1L57 & (F1_oAddress[11] # !H1L86));


--H1L89 is VGA_OSD_RAM:u6|add~1440 at LCCOMB_X27_Y10_N20
H1L89 = F1_oAddress[12] & (H1L59 & !H1L88 # !H1L59 & H1L88 & VCC) # !F1_oAddress[12] & (H1L59 & (H1L88 # GND) # !H1L59 & !H1L88);

--H1L90 is VGA_OSD_RAM:u6|add~1441 at LCCOMB_X27_Y10_N20
H1L90 = CARRY(F1_oAddress[12] & H1L59 & !H1L88 # !F1_oAddress[12] & (H1L59 # !H1L88));


--H1L91 is VGA_OSD_RAM:u6|add~1442 at LCCOMB_X27_Y10_N22
H1L91 = (H1L61 $ F1_oAddress[13] $ H1L90) # GND;

--H1L92 is VGA_OSD_RAM:u6|add~1443 at LCCOMB_X27_Y10_N22
H1L92 = CARRY(H1L61 & F1_oAddress[13] & !H1L90 # !H1L61 & (F1_oAddress[13] # !H1L90));


--H1L93 is VGA_OSD_RAM:u6|add~1444 at LCCOMB_X27_Y10_N24
H1L93 = H1L63 & (F1_oAddress[14] & !H1L92 # !F1_oAddress[14] & (H1L92 # GND)) # !H1L63 & (F1_oAddress[14] & H1L92 & VCC # !F1_oAddress[14] & !H1L92);

--H1L94 is VGA_OSD_RAM:u6|add~1445 at LCCOMB_X27_Y10_N24
H1L94 = CARRY(H1L63 & (!H1L92 # !F1_oAddress[14]) # !H1L63 & !F1_oAddress[14] & !H1L92);


--H1L95 is VGA_OSD_RAM:u6|add~1446 at LCCOMB_X27_Y10_N26
H1L95 = (F1_oAddress[15] $ H1L65 $ H1L94) # GND;

--H1L96 is VGA_OSD_RAM:u6|add~1447 at LCCOMB_X27_Y10_N26
H1L96 = CARRY(F1_oAddress[15] & (!H1L94 # !H1L65) # !F1_oAddress[15] & !H1L65 & !H1L94);


--H1L97 is VGA_OSD_RAM:u6|add~1448 at LCCOMB_X27_Y10_N28
H1L97 = F1_oAddress[16] & (H1L67 & !H1L96 # !H1L67 & H1L96 & VCC) # !F1_oAddress[16] & (H1L67 & (H1L96 # GND) # !H1L67 & !H1L96);

--H1L98 is VGA_OSD_RAM:u6|add~1449 at LCCOMB_X27_Y10_N28
H1L98 = CARRY(F1_oAddress[16] & H1L67 & !H1L96 # !F1_oAddress[16] & (H1L67 # !H1L96));


--H1L99 is VGA_OSD_RAM:u6|add~1450 at LCCOMB_X27_Y10_N30
H1L99 = H1L69 $ H1L98 $ F1_oAddress[17];


--F1_oAddress[2] is VGA_Controller:u4|oAddress[2] at LCFF_X29_Y11_N19
F1_oAddress[2] = DFFEAS(F1L145, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oAddress[1] is VGA_Controller:u4|oAddress[1] at LCFF_X29_Y11_N17
F1_oAddress[1] = DFFEAS(F1L142, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--H1L101 is VGA_OSD_RAM:u6|add~1452 at LCCOMB_X31_Y11_N16
H1L101 = F1_oAddress[1] $ VCC;

--H1L102 is VGA_OSD_RAM:u6|add~1453 at LCCOMB_X31_Y11_N16
H1L102 = CARRY(F1_oAddress[1]);


--H1L103 is VGA_OSD_RAM:u6|add~1454 at LCCOMB_X31_Y11_N18
H1L103 = F1_oAddress[2] & H1L102 & VCC # !F1_oAddress[2] & !H1L102;

--H1L104 is VGA_OSD_RAM:u6|add~1455 at LCCOMB_X31_Y11_N18
H1L104 = CARRY(!F1_oAddress[2] & !H1L102);


--H1L105 is VGA_OSD_RAM:u6|add~1456 at LCCOMB_X31_Y11_N20
H1L105 = H1L71 & (GND # !H1L104) # !H1L71 & (H1L104 $ GND);

--H1L106 is VGA_OSD_RAM:u6|add~1457 at LCCOMB_X31_Y11_N20
H1L106 = CARRY(H1L71 # !H1L104);


--H1L107 is VGA_OSD_RAM:u6|add~1458 at LCCOMB_X31_Y11_N22
H1L107 = H1L73 & H1L106 & VCC # !H1L73 & !H1L106;

--H1L108 is VGA_OSD_RAM:u6|add~1459 at LCCOMB_X31_Y11_N22
H1L108 = CARRY(!H1L73 & !H1L106);


--H1L109 is VGA_OSD_RAM:u6|add~1460 at LCCOMB_X31_Y11_N24
H1L109 = H1L75 & (GND # !H1L108) # !H1L75 & (H1L108 $ GND);

--H1L110 is VGA_OSD_RAM:u6|add~1461 at LCCOMB_X31_Y11_N24
H1L110 = CARRY(H1L75 # !H1L108);


--H1L111 is VGA_OSD_RAM:u6|add~1462 at LCCOMB_X31_Y11_N26
H1L111 = H1L77 & !H1L110 # !H1L77 & (H1L110 # GND);

--H1L112 is VGA_OSD_RAM:u6|add~1463 at LCCOMB_X31_Y11_N26
H1L112 = CARRY(!H1L110 # !H1L77);


--H1L113 is VGA_OSD_RAM:u6|add~1464 at LCCOMB_X31_Y11_N28
H1L113 = H1L79 & (H1L112 $ GND) # !H1L79 & !H1L112 & VCC;

--H1L114 is VGA_OSD_RAM:u6|add~1465 at LCCOMB_X31_Y11_N28
H1L114 = CARRY(H1L79 & !H1L112);


--H1L115 is VGA_OSD_RAM:u6|add~1466 at LCCOMB_X31_Y11_N30
H1L115 = H1L81 & !H1L114 # !H1L81 & (H1L114 # GND);

--H1L116 is VGA_OSD_RAM:u6|add~1467 at LCCOMB_X31_Y11_N30
H1L116 = CARRY(!H1L114 # !H1L81);


--H1L117 is VGA_OSD_RAM:u6|add~1468 at LCCOMB_X31_Y10_N0
H1L117 = H1L83 & (GND # !H1L116) # !H1L83 & (H1L116 $ GND);

--H1L118 is VGA_OSD_RAM:u6|add~1469 at LCCOMB_X31_Y10_N0
H1L118 = CARRY(H1L83 # !H1L116);


--H1L119 is VGA_OSD_RAM:u6|add~1470 at LCCOMB_X31_Y10_N2
H1L119 = H1L85 & !H1L118 # !H1L85 & (H1L118 # GND);

--H1L120 is VGA_OSD_RAM:u6|add~1471 at LCCOMB_X31_Y10_N2
H1L120 = CARRY(!H1L118 # !H1L85);


--H1L121 is VGA_OSD_RAM:u6|add~1472 at LCCOMB_X31_Y10_N4
H1L121 = H1L87 & (GND # !H1L120) # !H1L87 & (H1L120 $ GND);

--H1L122 is VGA_OSD_RAM:u6|add~1473 at LCCOMB_X31_Y10_N4
H1L122 = CARRY(H1L87 # !H1L120);


--H1L123 is VGA_OSD_RAM:u6|add~1474 at LCCOMB_X31_Y10_N6
H1L123 = H1L89 & H1L122 & VCC # !H1L89 & !H1L122;

--H1L124 is VGA_OSD_RAM:u6|add~1475 at LCCOMB_X31_Y10_N6
H1L124 = CARRY(!H1L89 & !H1L122);


--H1L125 is VGA_OSD_RAM:u6|add~1476 at LCCOMB_X31_Y10_N8
H1L125 = H1L91 & (H1L124 $ GND) # !H1L91 & !H1L124 & VCC;

--H1L126 is VGA_OSD_RAM:u6|add~1477 at LCCOMB_X31_Y10_N8
H1L126 = CARRY(H1L91 & !H1L124);


--H1L127 is VGA_OSD_RAM:u6|add~1478 at LCCOMB_X31_Y10_N10
H1L127 = H1L93 & !H1L126 # !H1L93 & (H1L126 # GND);

--H1L128 is VGA_OSD_RAM:u6|add~1479 at LCCOMB_X31_Y10_N10
H1L128 = CARRY(!H1L126 # !H1L93);


--H1L129 is VGA_OSD_RAM:u6|add~1480 at LCCOMB_X31_Y10_N12
H1L129 = H1L95 & (GND # !H1L128) # !H1L95 & (H1L128 $ GND);

--H1L130 is VGA_OSD_RAM:u6|add~1481 at LCCOMB_X31_Y10_N12
H1L130 = CARRY(H1L95 # !H1L128);


--H1L131 is VGA_OSD_RAM:u6|add~1482 at LCCOMB_X31_Y10_N14
H1L131 = H1L97 & H1L130 & VCC # !H1L97 & !H1L130;

--H1L132 is VGA_OSD_RAM:u6|add~1483 at LCCOMB_X31_Y10_N14
H1L132 = CARRY(!H1L97 & !H1L130);


--H1L133 is VGA_OSD_RAM:u6|add~1484 at LCCOMB_X31_Y10_N16
H1L133 = H1L99 $ H1L132;


--S3L93 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3345w[3]~15 at LCCOMB_X31_Y10_N22
S3L93 = !H1L127 & H1L125 & !H1L123;


--S3L106 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3438w[3]~24 at LCCOMB_X26_Y14_N10
S3L106 = !H1L129 & H1L133 & S3L93 & H1L131;


--S3L23 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2963w[3]~14 at LCCOMB_X26_Y14_N2
S3L23 = !H1L127 & !H1L125 & H1L123;


--S3L105 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3428w[3]~10 at LCCOMB_X26_Y14_N22
S3L105 = !H1L129 & H1L133 & H1L131 & S3L23;


--S3L88 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3324w[3]~15 at LCCOMB_X26_Y14_N18
S3L88 = !H1L127 & !H1L125 & !H1L123;


--S3L104 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3417w[3]~11 at LCCOMB_X26_Y14_N24
S3L104 = !H1L129 & S3L88 & H1L131 & H1L133;


--R1_address_reg_a[0] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[0] at LCFF_X31_Y10_N7
R1_address_reg_a[0] = DFFEAS(H1L123, GLOBAL(M1L2),  ,  ,  ,  ,  ,  ,  );


--S3L17 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2929w[3]~21 at LCCOMB_X31_Y10_N18
S3L17 = H1L125 & H1L127;


--S3L52 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3127w[3]~18 at LCCOMB_X31_Y10_N30
S3L52 = H1L131 & !H1L133;


--S3_w_anode3199w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3199w[3] at LCCOMB_X31_Y10_N28
S3_w_anode3199w[3] = H1L129 & S3L52 & !H1L123 & S3L17;


--S3L13 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2909w[3]~22 at LCCOMB_X31_Y10_N24
S3L13 = !H1L125 & H1L127;


--S3_w_anode3189w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3189w[3] at LCCOMB_X32_Y10_N2
S3_w_anode3189w[3] = H1L123 & H1L129 & S3L52 & S3L13;


--S3_w_anode3179w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3179w[3] at LCCOMB_X32_Y10_N22
S3_w_anode3179w[3] = !H1L123 & H1L129 & S3L52 & S3L13;


--S3_w_anode3209w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3209w[3] at LCCOMB_X32_Y10_N24
S3_w_anode3209w[3] = S3L52 & H1L129 & S3L17 & H1L123;


--S3_w_anode3096w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3096w[3] at LCCOMB_X32_Y10_N4
S3_w_anode3096w[3] = H1L123 & !H1L129 & S3L52 & S3L13;


--S3_w_anode3106w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3106w[3] at LCCOMB_X32_Y10_N18
S3_w_anode3106w[3] = S3L52 & !H1L129 & S3L17 & !H1L123;


--S3_w_anode3086w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3086w[3] at LCCOMB_X32_Y10_N16
S3_w_anode3086w[3] = !H1L123 & !H1L129 & S3L52 & S3L13;


--S3_w_anode3116w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3116w[3] at LCCOMB_X32_Y10_N30
S3_w_anode3116w[3] = S3L52 & !H1L129 & S3L17 & H1L123;


--S3L9 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2889w[3]~16 at LCCOMB_X32_Y10_N14
S3L9 = !H1L127 & H1L125;


--S3_w_anode3076w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3076w[3] at LCCOMB_X32_Y10_N10
S3_w_anode3076w[3] = S3L52 & !H1L129 & S3L9 & H1L123;


--S3_w_anode3169w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3169w[3] at LCCOMB_X32_Y10_N8
S3_w_anode3169w[3] = S3L52 & H1L129 & S3L9 & H1L123;


--R1_address_reg_a[5] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[5] at LCFF_X31_Y10_N17
R1_address_reg_a[5] = DFFEAS(H1L133, GLOBAL(M1L2),  ,  ,  ,  ,  ,  ,  );


--R1_address_reg_a[4] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|address_reg_a[4] at LCFF_X31_Y10_N15
R1_address_reg_a[4] = DFFEAS(H1L131, GLOBAL(M1L2),  ,  ,  ,  ,  ,  ,  );


--S3L18 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2941w[3]~20 at LCCOMB_X31_Y10_N20
S3L18 = !H1L131 & H1L129;


--S3_w_anode3385w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3385w[3] at LCCOMB_X40_Y10_N22
S3_w_anode3385w[3] = !H1L123 & H1L133 & S3L18 & S3L17;


--S3_w_anode3375w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3375w[3] at LCCOMB_X40_Y10_N12
S3_w_anode3375w[3] = H1L123 & H1L133 & S3L18 & S3L13;


--S3_w_anode3365w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3365w[3] at LCCOMB_X40_Y10_N6
S3_w_anode3365w[3] = !H1L123 & H1L133 & S3L18 & S3L13;


--S3_w_anode3395w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3395w[3] at LCCOMB_X40_Y10_N4
S3_w_anode3395w[3] = H1L123 & H1L133 & S3L18 & S3L17;


--S3_w_anode3003w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3003w[3] at LCCOMB_X40_Y10_N2
S3_w_anode3003w[3] = H1L123 & !H1L133 & S3L18 & S3L13;


--S3_w_anode3013w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3013w[3] at LCCOMB_X40_Y10_N28
S3_w_anode3013w[3] = !H1L123 & !H1L133 & S3L18 & S3L17;


--S3_w_anode2993w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2993w[3] at LCCOMB_X40_Y10_N10
S3_w_anode2993w[3] = !H1L123 & !H1L133 & S3L18 & S3L13;


--S3_w_anode3023w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3023w[3] at LCCOMB_X40_Y10_N20
S3_w_anode3023w[3] = H1L123 & !H1L133 & S3L18 & S3L17;


--S3L69 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3220w[3]~28 at LCCOMB_X31_Y10_N26
S3L69 = !H1L131 & !H1L129;


--S3_w_anode3282w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3282w[3] at LCCOMB_X32_Y10_N0
S3_w_anode3282w[3] = H1L123 & S3L13 & H1L133 & S3L69;


--S3_w_anode3292w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3292w[3] at LCCOMB_X40_Y10_N18
S3_w_anode3292w[3] = !H1L123 & S3L17 & H1L133 & S3L69;


--S3_w_anode3272w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3272w[3] at LCCOMB_X32_Y10_N12
S3_w_anode3272w[3] = !H1L123 & S3L13 & H1L133 & S3L69;


--S3_w_anode3302w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3302w[3] at LCCOMB_X40_Y10_N16
S3_w_anode3302w[3] = H1L123 & S3L17 & H1L133 & S3L69;


--S3L14 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2919w[3]~16 at LCCOMB_X40_Y10_N8
S3L14 = !H1L123 & S3L17 & !H1L133 & S3L69;


--S3_w_anode2909w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2909w[3] at LCCOMB_X40_Y10_N0
S3_w_anode2909w[3] = H1L123 & S3L13 & !H1L133 & S3L69;


--S3L10 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2899w[3]~25 at LCCOMB_X40_Y10_N30
S3L10 = !H1L123 & S3L13 & !H1L133 & S3L69;


--S3_w_anode2929w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2929w[3] at LCCOMB_X40_Y10_N14
S3_w_anode2929w[3] = H1L123 & S3L17 & !H1L133 & S3L69;


--S3_w_anode3262w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3262w[3] at LCCOMB_X32_Y10_N20
S3_w_anode3262w[3] = H1L123 & H1L133 & S3L9 & S3L69;


--S3L5 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2869w[3]~21 at LCCOMB_X40_Y10_N26
S3L5 = !H1L127 & !H1L125;


--S3_w_anode2869w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2869w[3] at LCCOMB_X40_Y10_N24
S3_w_anode2869w[3] = H1L123 & S3L69 & !H1L133 & S3L5;


--S3_w_anode2889w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2889w[3] at LCCOMB_X32_Y10_N6
S3_w_anode2889w[3] = H1L123 & !H1L133 & S3L9 & S3L69;


--S3_w_anode3355w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3355w[3] at LCCOMB_X32_Y10_N28
S3_w_anode3355w[3] = S3L18 & H1L133 & S3L9 & H1L123;


--S3_w_anode2983w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2983w[3] at LCCOMB_X32_Y10_N26
S3_w_anode2983w[3] = S3L18 & !H1L133 & S3L9 & H1L123;


--H1_ADDR_d[0] is VGA_OSD_RAM:u6|ADDR_d[0] at LCFF_X31_Y12_N31
H1_ADDR_d[0] = DFFEAS(H1L3, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--H1_ADDR_d[1] is VGA_OSD_RAM:u6|ADDR_d[1] at LCFF_X31_Y11_N17
H1_ADDR_d[1] = DFFEAS(H1L101, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--H1_ADDR_d[2] is VGA_OSD_RAM:u6|ADDR_d[2] at LCFF_X31_Y11_N19
H1_ADDR_d[2] = DFFEAS(H1L103, GLOBAL(M1L2), KEY[0],  ,  ,  ,  ,  ,  );


--K1L5 is AUDIO_DAC:u8|BCK_DIV~127 at LCCOMB_X34_Y13_N4
K1L5 = K1_BCK_DIV[0] & !K1_BCK_DIV[2] & K1_BCK_DIV[1] # !K1_BCK_DIV[0] & K1_BCK_DIV[2] & !K1_BCK_DIV[1];


--K1L6 is AUDIO_DAC:u8|BCK_DIV~128 at LCCOMB_X34_Y13_N10
K1L6 = !K1_BCK_DIV[2] & (K1_BCK_DIV[0] $ K1_BCK_DIV[1]);


--K1L7 is AUDIO_DAC:u8|BCK_DIV~129 at LCCOMB_X34_Y13_N12
K1L7 = !K1_BCK_DIV[0] & (!K1_BCK_DIV[1] # !K1_BCK_DIV[2]);


--V1L60 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1104 at LCCOMB_X32_Y14_N18
V1L60 = V1L49Q & V1L43Q & V1L46Q & V1L52Q;


--V1_SD[9] is I2C_AV_Config:u7|I2C_Controller:u0|SD[9] at LCFF_X33_Y14_N31
V1_SD[9] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(J1L73),  ,  , V1L39, J1_mI2C_DATA[9],  ,  , VCC);


--V1_SD[2] is I2C_AV_Config:u7|I2C_Controller:u0|SD[2] at LCFF_X33_Y14_N7
V1_SD[2] = DFFEAS(V1L30, GLOBAL(J1L73),  ,  , V1L39,  ,  ,  ,  );


--V1L61 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1105 at LCCOMB_X33_Y14_N30
V1L61 = V1L52Q & (V1_SD[9]) # !V1L52Q & V1_SD[2];


--V1_SD[1] is I2C_AV_Config:u7|I2C_Controller:u0|SD[1] at LCFF_X32_Y14_N7
V1_SD[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(J1L73),  ,  , V1L39, J1_mI2C_DATA[1],  ,  , VCC);


--V1L62 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1106 at LCCOMB_X32_Y14_N6
V1L62 = V1L43Q & V1L61 # !V1L43Q & (V1_SD[1] & !V1L52Q);


--V1_SD[7] is I2C_AV_Config:u7|I2C_Controller:u0|SD[7] at LCFF_X32_Y14_N17
V1_SD[7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(J1L73),  ,  , V1L39, J1_mI2C_DATA[7],  ,  , VCC);


--V1_SD[0] is I2C_AV_Config:u7|I2C_Controller:u0|SD[0] at LCFF_X33_Y14_N25
V1_SD[0] = DFFEAS(V1L27, GLOBAL(J1L73),  ,  , V1L39,  ,  ,  ,  );


--V1L63 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1107 at LCCOMB_X32_Y14_N16
V1L63 = V1L43Q & (V1_SD[0] # V1L52Q) # !V1L43Q & (V1_SD[7] # !V1L52Q);


--V1_SD[11] is I2C_AV_Config:u7|I2C_Controller:u0|SD[11] at LCFF_X33_Y14_N5
V1_SD[11] = DFFEAS(V1L37, GLOBAL(J1L73),  ,  , V1L39,  ,  ,  ,  );


--V1_SD[10] is I2C_AV_Config:u7|I2C_Controller:u0|SD[10] at LCFF_X32_Y14_N1
V1_SD[10] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(J1L73),  ,  , V1L39, J1_mI2C_DATA[10],  ,  , VCC);


--V1L64 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1108 at LCCOMB_X32_Y14_N0
V1L64 = V1L43Q & (V1_SD[11]) # !V1L43Q & V1_SD[10];


--V1_SD[4] is I2C_AV_Config:u7|I2C_Controller:u0|SD[4] at LCFF_X32_Y14_N5
V1_SD[4] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(J1L73),  ,  , V1L39, J1_mI2C_DATA[4],  ,  , VCC);


--V1L65 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1109 at LCCOMB_X32_Y14_N4
V1L65 = V1L52Q & V1L64 # !V1L52Q & (V1_SD[4]);


--V1L66 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1110 at LCCOMB_X32_Y14_N10
V1L66 = V1L49Q & V1L65 & (V1L46Q) # !V1L49Q & (V1L63 # !V1L46Q);


--V1_SD[6] is I2C_AV_Config:u7|I2C_Controller:u0|SD[6] at LCFF_X32_Y14_N23
V1_SD[6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(J1L73),  ,  , V1L39, J1_mI2C_DATA[6],  ,  , VCC);


--V1L67 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1111 at LCCOMB_X32_Y14_N22
V1L67 = V1L52Q & (V1_SD[6]) # !V1L52Q & !V1L25Q & !V1L43Q;


--V1L68 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1112 at LCCOMB_X32_Y14_N2
V1L68 = V1L66 & (V1L67 # V1L46Q) # !V1L66 & (V1L62 & !V1L46Q);


--V1_SD[12] is I2C_AV_Config:u7|I2C_Controller:u0|SD[12] at LCFF_X32_Y14_N27
V1_SD[12] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(J1L73),  ,  , V1L39, J1_mI2C_DATA[12],  ,  , VCC);


--V1L69 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1113 at LCCOMB_X32_Y14_N28
V1L69 = V1L43Q & (V1L49Q & !V1L46Q # !V1L49Q & (V1L46Q # !V1L52Q)) # !V1L43Q & (V1L46Q & (V1L49Q # !V1L52Q) # !V1L46Q & (V1L52Q));


--V1L70 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1114 at LCCOMB_X32_Y14_N8
V1L70 = V1L49Q & (V1L43Q $ (!V1L46Q & !V1L52Q)) # !V1L49Q & V1L52Q & (V1L43Q $ V1L46Q);


--V1L71 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1115 at LCCOMB_X32_Y14_N26
V1L71 = V1L70 & (!V1L69 # !V1L25Q) # !V1L70 & (V1_SD[12] & !V1L69);


--V1L72 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1116 at LCCOMB_X32_Y14_N20
V1L72 = V1L58Q & (V1L55Q & (V1L71) # !V1L55Q & V1L68) # !V1L58Q & (!V1L55Q);


--V1L73 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1117 at LCCOMB_X32_Y14_N24
V1L73 = V1L58Q & !V1L72 # !V1L58Q & V1L25Q & (V1L72 # !V1L60);


--V1L10 is I2C_AV_Config:u7|I2C_Controller:u0|ACK3~215 at LCCOMB_X31_Y12_N14
V1L10 = V1L58Q & V1L43Q & (V1L40 # V1L59);


--V1L74 is I2C_AV_Config:u7|I2C_Controller:u0|Select~1118 at LCCOMB_X32_Y14_N30
V1L74 = V1L43Q & !V1L49Q & (A1L287) # !V1L43Q & (V1_ACK1);


--V1L2 is I2C_AV_Config:u7|I2C_Controller:u0|ACK1~170 at LCCOMB_X32_Y14_N12
V1L2 = V1L58Q & V1L55Q & (V1L49Q $ !V1L52Q);


--V1L3 is I2C_AV_Config:u7|I2C_Controller:u0|ACK1~171 at LCCOMB_X32_Y14_N14
V1L3 = V1L2 & (V1L46Q & V1L74 # !V1L46Q & (V1_ACK1)) # !V1L2 & (V1_ACK1);


--V1L6 is I2C_AV_Config:u7|I2C_Controller:u0|ACK2~251 at LCCOMB_X34_Y13_N16
V1L6 = V1L49Q & (!V1L55Q # !V1L43Q) # !V1L49Q & (V1L43Q # V1L55Q) # !V1L58Q;


--J1L21 is I2C_AV_Config:u7|Select~137 at LCCOMB_X35_Y14_N10
J1L21 = !J1_mSetup_ST.10 & (J1L90 # V1_END # !J1_mSetup_ST.01);


--F1L95 is VGA_Controller:u4|add~1144 at LCCOMB_X26_Y11_N14
F1L95 = F1_oCoord_Y[2] & (F1_oCoord_Y[0] $ VCC) # !F1_oCoord_Y[2] & F1_oCoord_Y[0] & VCC;

--F1L96 is VGA_Controller:u4|add~1145 at LCCOMB_X26_Y11_N14
F1L96 = CARRY(F1_oCoord_Y[2] & F1_oCoord_Y[0]);


--F1L97 is VGA_Controller:u4|add~1146 at LCCOMB_X26_Y11_N16
F1L97 = F1_oCoord_Y[1] & (F1_oCoord_Y[3] & F1L96 & VCC # !F1_oCoord_Y[3] & !F1L96) # !F1_oCoord_Y[1] & (F1_oCoord_Y[3] & !F1L96 # !F1_oCoord_Y[3] & (F1L96 # GND));

--F1L98 is VGA_Controller:u4|add~1147 at LCCOMB_X26_Y11_N16
F1L98 = CARRY(F1_oCoord_Y[1] & !F1_oCoord_Y[3] & !F1L96 # !F1_oCoord_Y[1] & (!F1L96 # !F1_oCoord_Y[3]));


--F1L99 is VGA_Controller:u4|add~1148 at LCCOMB_X26_Y11_N18
F1L99 = (F1_oCoord_Y[2] $ F1_oCoord_Y[4] $ !F1L98) # GND;

--F1L100 is VGA_Controller:u4|add~1149 at LCCOMB_X26_Y11_N18
F1L100 = CARRY(F1_oCoord_Y[2] & (F1_oCoord_Y[4] # !F1L98) # !F1_oCoord_Y[2] & F1_oCoord_Y[4] & !F1L98);


--F1L101 is VGA_Controller:u4|add~1150 at LCCOMB_X26_Y11_N20
F1L101 = F1_oCoord_Y[3] & (F1_oCoord_Y[5] & F1L100 & VCC # !F1_oCoord_Y[5] & !F1L100) # !F1_oCoord_Y[3] & (F1_oCoord_Y[5] & !F1L100 # !F1_oCoord_Y[5] & (F1L100 # GND));

--F1L102 is VGA_Controller:u4|add~1151 at LCCOMB_X26_Y11_N20
F1L102 = CARRY(F1_oCoord_Y[3] & !F1_oCoord_Y[5] & !F1L100 # !F1_oCoord_Y[3] & (!F1L100 # !F1_oCoord_Y[5]));


--F1L103 is VGA_Controller:u4|add~1152 at LCCOMB_X26_Y11_N22
F1L103 = (F1_oCoord_Y[6] $ F1_oCoord_Y[4] $ !F1L102) # GND;

--F1L104 is VGA_Controller:u4|add~1153 at LCCOMB_X26_Y11_N22
F1L104 = CARRY(F1_oCoord_Y[6] & (F1_oCoord_Y[4] # !F1L102) # !F1_oCoord_Y[6] & F1_oCoord_Y[4] & !F1L102);


--F1L105 is VGA_Controller:u4|add~1154 at LCCOMB_X26_Y11_N24
F1L105 = F1_oCoord_Y[7] & (F1_oCoord_Y[5] & F1L104 & VCC # !F1_oCoord_Y[5] & !F1L104) # !F1_oCoord_Y[7] & (F1_oCoord_Y[5] & !F1L104 # !F1_oCoord_Y[5] & (F1L104 # GND));

--F1L106 is VGA_Controller:u4|add~1155 at LCCOMB_X26_Y11_N24
F1L106 = CARRY(F1_oCoord_Y[7] & !F1_oCoord_Y[5] & !F1L104 # !F1_oCoord_Y[7] & (!F1L104 # !F1_oCoord_Y[5]));


--F1L107 is VGA_Controller:u4|add~1156 at LCCOMB_X26_Y11_N26
F1L107 = (F1_oCoord_Y[6] $ F1_oCoord_Y[8] $ !F1L106) # GND;

--F1L108 is VGA_Controller:u4|add~1157 at LCCOMB_X26_Y11_N26
F1L108 = CARRY(F1_oCoord_Y[6] & (F1_oCoord_Y[8] # !F1L106) # !F1_oCoord_Y[6] & F1_oCoord_Y[8] & !F1L106);


--F1L109 is VGA_Controller:u4|add~1158 at LCCOMB_X26_Y11_N28
F1L109 = F1_oCoord_Y[7] & (F1_oCoord_Y[9] & F1L108 & VCC # !F1_oCoord_Y[9] & !F1L108) # !F1_oCoord_Y[7] & (F1_oCoord_Y[9] & !F1L108 # !F1_oCoord_Y[9] & (F1L108 # GND));

--F1L110 is VGA_Controller:u4|add~1159 at LCCOMB_X26_Y11_N28
F1L110 = CARRY(F1_oCoord_Y[7] & !F1_oCoord_Y[9] & !F1L108 # !F1_oCoord_Y[7] & (!F1L108 # !F1_oCoord_Y[9]));


--F1L111 is VGA_Controller:u4|add~1160 at LCCOMB_X26_Y11_N30
F1L111 = F1_oCoord_Y[8] $ !F1L110;


--F1L113 is VGA_Controller:u4|add~1162 at LCCOMB_X27_Y11_N8
F1L113 = F1_oCoord_Y[0] & (F1_oCoord_X[7] $ VCC) # !F1_oCoord_Y[0] & F1_oCoord_X[7] & VCC;

--F1L114 is VGA_Controller:u4|add~1163 at LCCOMB_X27_Y11_N8
F1L114 = CARRY(F1_oCoord_Y[0] & F1_oCoord_X[7]);


--F1L115 is VGA_Controller:u4|add~1164 at LCCOMB_X27_Y11_N10
F1L115 = F1_oCoord_X[8] & (F1_oCoord_Y[1] & F1L114 & VCC # !F1_oCoord_Y[1] & !F1L114) # !F1_oCoord_X[8] & (F1_oCoord_Y[1] & !F1L114 # !F1_oCoord_Y[1] & (F1L114 # GND));

--F1L116 is VGA_Controller:u4|add~1165 at LCCOMB_X27_Y11_N10
F1L116 = CARRY(F1_oCoord_X[8] & !F1_oCoord_Y[1] & !F1L114 # !F1_oCoord_X[8] & (!F1L114 # !F1_oCoord_Y[1]));


--F1L117 is VGA_Controller:u4|add~1166 at LCCOMB_X27_Y11_N12
F1L117 = (F1L95 $ F1_oCoord_X[9] $ !F1L116) # GND;

--F1L118 is VGA_Controller:u4|add~1167 at LCCOMB_X27_Y11_N12
F1L118 = CARRY(F1L95 & (F1_oCoord_X[9] # !F1L116) # !F1L95 & F1_oCoord_X[9] & !F1L116);


--F1L119 is VGA_Controller:u4|add~1168 at LCCOMB_X27_Y11_N14
F1L119 = F1L97 & !F1L118 # !F1L97 & (F1L118 # GND);

--F1L120 is VGA_Controller:u4|add~1169 at LCCOMB_X27_Y11_N14
F1L120 = CARRY(!F1L118 # !F1L97);


--F1L121 is VGA_Controller:u4|add~1170 at LCCOMB_X27_Y11_N16
F1L121 = F1L99 & (F1L120 $ GND) # !F1L99 & !F1L120 & VCC;

--F1L122 is VGA_Controller:u4|add~1171 at LCCOMB_X27_Y11_N16
F1L122 = CARRY(F1L99 & !F1L120);


--F1L123 is VGA_Controller:u4|add~1172 at LCCOMB_X27_Y11_N18
F1L123 = F1L101 & !F1L122 # !F1L101 & (F1L122 # GND);

--F1L124 is VGA_Controller:u4|add~1173 at LCCOMB_X27_Y11_N18
F1L124 = CARRY(!F1L122 # !F1L101);


--F1L125 is VGA_Controller:u4|add~1174 at LCCOMB_X27_Y11_N20
F1L125 = F1L103 & (F1L124 $ GND) # !F1L103 & !F1L124 & VCC;

--F1L126 is VGA_Controller:u4|add~1175 at LCCOMB_X27_Y11_N20
F1L126 = CARRY(F1L103 & !F1L124);


--F1L127 is VGA_Controller:u4|add~1176 at LCCOMB_X27_Y11_N22
F1L127 = F1L105 & !F1L126 # !F1L105 & (F1L126 # GND);

--F1L128 is VGA_Controller:u4|add~1177 at LCCOMB_X27_Y11_N22
F1L128 = CARRY(!F1L126 # !F1L105);


--F1L129 is VGA_Controller:u4|add~1178 at LCCOMB_X27_Y11_N24
F1L129 = F1L107 & (F1L128 $ GND) # !F1L107 & !F1L128 & VCC;

--F1L130 is VGA_Controller:u4|add~1179 at LCCOMB_X27_Y11_N24
F1L130 = CARRY(F1L107 & !F1L128);


--F1L131 is VGA_Controller:u4|add~1180 at LCCOMB_X27_Y11_N26
F1L131 = F1L109 & !F1L130 # !F1L109 & (F1L130 # GND);

--F1L132 is VGA_Controller:u4|add~1181 at LCCOMB_X27_Y11_N26
F1L132 = CARRY(!F1L130 # !F1L109);


--F1L133 is VGA_Controller:u4|add~1182 at LCCOMB_X27_Y11_N28
F1L133 = F1L111 $ !F1L132;


--F1_oCoord_X[1] is VGA_Controller:u4|oCoord_X[1] at LCFF_X29_Y10_N27
F1_oCoord_X[1] = DFFEAS(F1L196, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1_oCoord_X[0] is VGA_Controller:u4|oCoord_X[0] at LCFF_X29_Y10_N21
F1_oCoord_X[0] = DFFEAS(F1L194, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--F1L139 is VGA_Controller:u4|oAddress[0]~163 at LCCOMB_X29_Y11_N14
F1L139 = F1_oCoord_X[0] $ VCC;

--F1L140 is VGA_Controller:u4|oAddress[0]~164 at LCCOMB_X29_Y11_N14
F1L140 = CARRY(F1_oCoord_X[0]);


--F1L142 is VGA_Controller:u4|oAddress[1]~165 at LCCOMB_X29_Y11_N16
F1L142 = F1_oCoord_X[1] & !F1L140 # !F1_oCoord_X[1] & (F1L140 # GND);

--F1L143 is VGA_Controller:u4|oAddress[1]~166 at LCCOMB_X29_Y11_N16
F1L143 = CARRY(!F1L140 # !F1_oCoord_X[1]);


--F1L145 is VGA_Controller:u4|oAddress[2]~167 at LCCOMB_X29_Y11_N18
F1L145 = F1_oCoord_X[2] & (GND # !F1L143) # !F1_oCoord_X[2] & (F1L143 $ GND);

--F1L146 is VGA_Controller:u4|oAddress[2]~168 at LCCOMB_X29_Y11_N18
F1L146 = CARRY(F1_oCoord_X[2] # !F1L143);


--F1L148 is VGA_Controller:u4|oAddress[3]~169 at LCCOMB_X29_Y11_N20
F1L148 = F1_oCoord_X[3] & F1L146 & VCC # !F1_oCoord_X[3] & !F1L146;

--F1L149 is VGA_Controller:u4|oAddress[3]~170 at LCCOMB_X29_Y11_N20
F1L149 = CARRY(!F1_oCoord_X[3] & !F1L146);


--F1L151 is VGA_Controller:u4|oAddress[4]~171 at LCCOMB_X29_Y11_N22
F1L151 = F1_oCoord_X[4] & (GND # !F1L149) # !F1_oCoord_X[4] & (F1L149 $ GND);

--F1L152 is VGA_Controller:u4|oAddress[4]~172 at LCCOMB_X29_Y11_N22
F1L152 = CARRY(F1_oCoord_X[4] # !F1L149);


--F1L154 is VGA_Controller:u4|oAddress[5]~173 at LCCOMB_X29_Y11_N24
F1L154 = F1_oCoord_X[5] & F1L152 & VCC # !F1_oCoord_X[5] & !F1L152;

--F1L155 is VGA_Controller:u4|oAddress[5]~174 at LCCOMB_X29_Y11_N24
F1L155 = CARRY(!F1_oCoord_X[5] & !F1L152);


--F1L157 is VGA_Controller:u4|oAddress[6]~175 at LCCOMB_X29_Y11_N26
F1L157 = F1_oCoord_X[6] & (GND # !F1L155) # !F1_oCoord_X[6] & (F1L155 $ GND);

--F1L158 is VGA_Controller:u4|oAddress[6]~176 at LCCOMB_X29_Y11_N26
F1L158 = CARRY(F1_oCoord_X[6] # !F1L155);


--F1L160 is VGA_Controller:u4|oAddress[7]~177 at LCCOMB_X29_Y11_N28
F1L160 = F1L113 & F1L158 & VCC # !F1L113 & !F1L158;

--F1L161 is VGA_Controller:u4|oAddress[7]~178 at LCCOMB_X29_Y11_N28
F1L161 = CARRY(!F1L113 & !F1L158);


--F1L163 is VGA_Controller:u4|oAddress[8]~179 at LCCOMB_X29_Y11_N30
F1L163 = F1L115 & (GND # !F1L161) # !F1L115 & (F1L161 $ GND);

--F1L164 is VGA_Controller:u4|oAddress[8]~180 at LCCOMB_X29_Y11_N30
F1L164 = CARRY(F1L115 # !F1L161);


--F1L166 is VGA_Controller:u4|oAddress[9]~181 at LCCOMB_X29_Y10_N0
F1L166 = F1L117 & F1L164 & VCC # !F1L117 & !F1L164;

--F1L167 is VGA_Controller:u4|oAddress[9]~182 at LCCOMB_X29_Y10_N0
F1L167 = CARRY(!F1L117 & !F1L164);


--F1L169 is VGA_Controller:u4|oAddress[10]~183 at LCCOMB_X29_Y10_N2
F1L169 = F1L119 & (GND # !F1L167) # !F1L119 & (F1L167 $ GND);

--F1L170 is VGA_Controller:u4|oAddress[10]~184 at LCCOMB_X29_Y10_N2
F1L170 = CARRY(F1L119 # !F1L167);


--F1L172 is VGA_Controller:u4|oAddress[11]~185 at LCCOMB_X29_Y10_N4
F1L172 = F1L121 & F1L170 & VCC # !F1L121 & !F1L170;

--F1L173 is VGA_Controller:u4|oAddress[11]~186 at LCCOMB_X29_Y10_N4
F1L173 = CARRY(!F1L121 & !F1L170);


--F1L175 is VGA_Controller:u4|oAddress[12]~187 at LCCOMB_X29_Y10_N6
F1L175 = F1L123 & (GND # !F1L173) # !F1L123 & (F1L173 $ GND);

--F1L176 is VGA_Controller:u4|oAddress[12]~188 at LCCOMB_X29_Y10_N6
F1L176 = CARRY(F1L123 # !F1L173);


--F1L178 is VGA_Controller:u4|oAddress[13]~189 at LCCOMB_X29_Y10_N8
F1L178 = F1L125 & F1L176 & VCC # !F1L125 & !F1L176;

--F1L179 is VGA_Controller:u4|oAddress[13]~190 at LCCOMB_X29_Y10_N8
F1L179 = CARRY(!F1L125 & !F1L176);


--F1L181 is VGA_Controller:u4|oAddress[14]~191 at LCCOMB_X29_Y10_N10
F1L181 = F1L127 & (GND # !F1L179) # !F1L127 & (F1L179 $ GND);

--F1L182 is VGA_Controller:u4|oAddress[14]~192 at LCCOMB_X29_Y10_N10
F1L182 = CARRY(F1L127 # !F1L179);


--F1L184 is VGA_Controller:u4|oAddress[15]~193 at LCCOMB_X29_Y10_N12
F1L184 = F1L129 & F1L182 & VCC # !F1L129 & !F1L182;

--F1L185 is VGA_Controller:u4|oAddress[15]~194 at LCCOMB_X29_Y10_N12
F1L185 = CARRY(!F1L129 & !F1L182);


--F1L187 is VGA_Controller:u4|oAddress[16]~195 at LCCOMB_X29_Y10_N14
F1L187 = F1L131 & (GND # !F1L185) # !F1L131 & (F1L185 $ GND);

--F1L188 is VGA_Controller:u4|oAddress[16]~196 at LCCOMB_X29_Y10_N14
F1L188 = CARRY(F1L131 # !F1L185);


--F1L190 is VGA_Controller:u4|oAddress[17]~197 at LCCOMB_X29_Y10_N16
F1L190 = F1L188 $ !F1L133;


--F1_oAddress[0] is VGA_Controller:u4|oAddress[0] at LCFF_X29_Y11_N15
F1_oAddress[0] = DFFEAS(F1L139, GLOBAL(M1L2), KEY[0],  , F1L136,  ,  ,  ,  );


--J1_mI2C_DATA[9] is I2C_AV_Config:u7|mI2C_DATA[9] at LCFF_X33_Y14_N21
J1_mI2C_DATA[9] = DFFEAS(J1L92, GLOBAL(J1L73),  ,  , J1L85,  ,  ,  ,  );


--J1_mI2C_DATA[2] is I2C_AV_Config:u7|mI2C_DATA[2] at LCFF_X33_Y14_N29
J1_mI2C_DATA[2] = DFFEAS(J1L1, GLOBAL(J1L73),  ,  , J1L85,  ,  ,  ,  );


--J1_mI2C_DATA[1] is I2C_AV_Config:u7|mI2C_DATA[1] at LCFF_X33_Y14_N15
J1_mI2C_DATA[1] = DFFEAS(J1L93, GLOBAL(J1L73),  ,  , J1L85,  ,  ,  ,  );


--J1_mI2C_DATA[7] is I2C_AV_Config:u7|mI2C_DATA[7] at LCFF_X33_Y14_N17
J1_mI2C_DATA[7] = DFFEAS(J1L2, GLOBAL(J1L73),  ,  , J1L85,  ,  ,  ,  );


--J1_mI2C_DATA[0] is I2C_AV_Config:u7|mI2C_DATA[0] at LCFF_X33_Y14_N23
J1_mI2C_DATA[0] = DFFEAS(J1L94, GLOBAL(J1L73),  ,  , J1L85,  ,  ,  ,  );


--J1_mI2C_DATA[11] is I2C_AV_Config:u7|mI2C_DATA[11] at LCFF_X33_Y14_N1
J1_mI2C_DATA[11] = DFFEAS(J1L95, GLOBAL(J1L73),  ,  , J1L85,  ,  ,  ,  );


--J1_mI2C_DATA[10] is I2C_AV_Config:u7|mI2C_DATA[10] at LCFF_X33_Y14_N13
J1_mI2C_DATA[10] = DFFEAS(J1L96, GLOBAL(J1L73),  ,  , J1L85,  ,  ,  ,  );


--J1_mI2C_DATA[4] is I2C_AV_Config:u7|mI2C_DATA[4] at LCFF_X33_Y14_N11
J1_mI2C_DATA[4] = DFFEAS(J1L97, GLOBAL(J1L73),  ,  , J1L85,  ,  ,  ,  );


--J1_mI2C_DATA[6] is I2C_AV_Config:u7|mI2C_DATA[6] at LCFF_X33_Y14_N27
J1_mI2C_DATA[6] = DFFEAS(J1L98, GLOBAL(J1L73),  ,  , J1L85,  ,  ,  ,  );


--J1_mI2C_DATA[12] is I2C_AV_Config:u7|mI2C_DATA[12] at LCFF_X33_Y14_N9
J1_mI2C_DATA[12] = DFFEAS(J1L3, GLOBAL(J1L73),  ,  , J1L85,  ,  ,  ,  );


--J1_LUT_INDEX[0] is I2C_AV_Config:u7|LUT_INDEX[0] at LCFF_X34_Y14_N31
J1_LUT_INDEX[0] = DFFEAS(J1L6, GLOBAL(J1L73), KEY[0],  ,  ,  ,  ,  ,  );


--J1_LUT_INDEX[1] is I2C_AV_Config:u7|LUT_INDEX[1] at LCFF_X34_Y14_N5
J1_LUT_INDEX[1] = DFFEAS(J1L8, GLOBAL(J1L73), KEY[0],  ,  ,  ,  ,  ,  );


--J1_LUT_INDEX[2] is I2C_AV_Config:u7|LUT_INDEX[2] at LCFF_X34_Y14_N1
J1_LUT_INDEX[2] = DFFEAS(J1L11, GLOBAL(J1L73), KEY[0],  ,  ,  ,  ,  ,  );


--J1_LUT_INDEX[3] is I2C_AV_Config:u7|LUT_INDEX[3] at LCFF_X34_Y14_N13
J1_LUT_INDEX[3] = DFFEAS(J1L13, GLOBAL(J1L73), KEY[0],  ,  ,  ,  ,  ,  );


--J1L92 is I2C_AV_Config:u7|reduce_or~73 at LCCOMB_X33_Y14_N20
J1L92 = !J1_LUT_INDEX[0] & (J1_LUT_INDEX[2] & (!J1_LUT_INDEX[3]) # !J1_LUT_INDEX[2] & (J1_LUT_INDEX[1] # J1_LUT_INDEX[3]));


--J1L85 is I2C_AV_Config:u7|mI2C_DATA[12]~871 at LCCOMB_X31_Y12_N8
J1L85 = KEY[0] & !J1_mSetup_ST.00;


--J1L1 is I2C_AV_Config:u7|Decoder~138 at LCCOMB_X33_Y14_N28
J1L1 = J1_LUT_INDEX[1] & J1_LUT_INDEX[2] & !J1_LUT_INDEX[3] & !J1_LUT_INDEX[0];


--J1L93 is I2C_AV_Config:u7|reduce_or~74 at LCCOMB_X33_Y14_N14
J1L93 = J1_LUT_INDEX[2] & (!J1_LUT_INDEX[3] & !J1_LUT_INDEX[0]) # !J1_LUT_INDEX[2] & (J1_LUT_INDEX[1] & !J1_LUT_INDEX[3] # !J1_LUT_INDEX[1] & (J1_LUT_INDEX[0]));


--J1L2 is I2C_AV_Config:u7|Decoder~139 at LCCOMB_X33_Y14_N16
J1L2 = !J1_LUT_INDEX[1] & J1_LUT_INDEX[2] & !J1_LUT_INDEX[3] & J1_LUT_INDEX[0];


--J1L94 is I2C_AV_Config:u7|reduce_or~75 at LCCOMB_X33_Y14_N22
J1L94 = J1_LUT_INDEX[1] & !J1_LUT_INDEX[2] & (J1_LUT_INDEX[3] $ J1_LUT_INDEX[0]) # !J1_LUT_INDEX[1] & !J1_LUT_INDEX[0] & (J1_LUT_INDEX[2] $ J1_LUT_INDEX[3]);


--J1L95 is I2C_AV_Config:u7|reduce_or~76 at LCCOMB_X33_Y14_N0
J1L95 = J1_LUT_INDEX[2] & !J1_LUT_INDEX[3] & (J1_LUT_INDEX[1] # J1_LUT_INDEX[0]) # !J1_LUT_INDEX[2] & !J1_LUT_INDEX[1] & J1_LUT_INDEX[3] & !J1_LUT_INDEX[0];


--J1L96 is I2C_AV_Config:u7|reduce_or~77 at LCCOMB_X33_Y14_N12
J1L96 = J1_LUT_INDEX[1] & (!J1_LUT_INDEX[3] & J1_LUT_INDEX[0]) # !J1_LUT_INDEX[1] & !J1_LUT_INDEX[0] & (J1_LUT_INDEX[2] $ J1_LUT_INDEX[3]);


--J1L97 is I2C_AV_Config:u7|reduce_or~78 at LCCOMB_X33_Y14_N10
J1L97 = !J1_LUT_INDEX[3] & (J1_LUT_INDEX[1] & !J1_LUT_INDEX[2] # !J1_LUT_INDEX[1] & (J1_LUT_INDEX[2] # J1_LUT_INDEX[0]));


--J1L98 is I2C_AV_Config:u7|reduce_or~79 at LCCOMB_X33_Y14_N26
J1L98 = !J1_LUT_INDEX[3] & (J1_LUT_INDEX[1] & !J1_LUT_INDEX[2] & J1_LUT_INDEX[0] # !J1_LUT_INDEX[1] & J1_LUT_INDEX[2]);


--J1L3 is I2C_AV_Config:u7|LUT_DATA~8 at LCCOMB_X33_Y14_N8
J1L3 = !J1_LUT_INDEX[2] & J1_LUT_INDEX[3] & (J1_LUT_INDEX[1] $ J1_LUT_INDEX[0]);


--J1L6 is I2C_AV_Config:u7|LUT_INDEX[0]~680 at LCCOMB_X34_Y14_N30
J1L6 = J1_LUT_INDEX[0] $ J1_mSetup_ST.10;


--J1L8 is I2C_AV_Config:u7|LUT_INDEX[1]~681 at LCCOMB_X34_Y14_N4
J1L8 = J1_LUT_INDEX[1] $ (J1_mSetup_ST.10 & J1_LUT_INDEX[0]);


--J1L11 is I2C_AV_Config:u7|LUT_INDEX[2]~682 at LCCOMB_X34_Y14_N0
J1L11 = J1_LUT_INDEX[2] $ (J1_mSetup_ST.10 & J1_LUT_INDEX[1] & J1_LUT_INDEX[0]);


--J1L9 is I2C_AV_Config:u7|LUT_INDEX[1]~683 at LCCOMB_X33_Y14_N2
J1L9 = J1_mSetup_ST.10 & J1_LUT_INDEX[0];


--J1L13 is I2C_AV_Config:u7|LUT_INDEX[3]~684 at LCCOMB_X34_Y14_N12
J1L13 = J1_LUT_INDEX[3] $ (J1L9 & J1_LUT_INDEX[1] & J1_LUT_INDEX[2]);


--F1L61 is VGA_Controller:u4|LessThan~1175 at LCCOMB_X29_Y10_N24
F1L61 = !F1_H_Cont[5] & !F1_H_Cont[6] & (F1L51 # !F1_H_Cont[4]);


--F1L62 is VGA_Controller:u4|LessThan~1176 at LCCOMB_X30_Y11_N0
F1L62 = !F1_H_Cont[9] & !F1_H_Cont[8] & (F1L61 # !F1_H_Cont[7]);


--H1L20 is VGA_OSD_RAM:u6|LessThan~457 at LCCOMB_X26_Y11_N6
H1L20 = !F1_oCoord_Y[1] & !F1_oCoord_Y[3] & !F1_oCoord_Y[2] # !G1L2;


--G1L13 is VGA_Pattern:u5|LessThan~2795 at LCCOMB_X25_Y10_N26
G1L13 = !F1_oCoord_Y[6] & (!F1_oCoord_Y[5] # !F1_oCoord_Y[4] # !G1L7);


--F1L63 is VGA_Controller:u4|LessThan~1177 at LCCOMB_X29_Y10_N28
F1L63 = !F1_H_Cont[6] & !F1_H_Cont[5] & (F1L17 # !F1_H_Cont[4]);


--S3_w_anode3056w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3056w[3] at LCCOMB_X26_Y14_N20
S3_w_anode3056w[3] = !H1L129 & !H1L133 & H1L131 & S3L23;


--S3_w_anode3066w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3066w[3] at LCCOMB_X26_Y14_N16
S3_w_anode3066w[3] = !H1L129 & !H1L133 & S3L93 & H1L131;


--S3_w_anode3045w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3045w[3] at LCCOMB_X22_Y14_N16
S3_w_anode3045w[3] = !H1L133 & H1L131 & S3L88 & !H1L129;


--S3_w_anode3159w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3159w[3] at LCCOMB_X26_Y14_N6
S3_w_anode3159w[3] = H1L129 & !H1L133 & S3L93 & H1L131;


--S3_w_anode3149w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3149w[3] at LCCOMB_X26_Y14_N28
S3_w_anode3149w[3] = H1L129 & !H1L133 & H1L131 & S3L23;


--S3_w_anode3138w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3138w[3] at LCCOMB_X22_Y14_N0
S3_w_anode3138w[3] = !H1L133 & H1L131 & S3L88 & H1L129;


--S3_w_anode3242w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3242w[3] at LCCOMB_X26_Y14_N4
S3_w_anode3242w[3] = !H1L129 & H1L133 & !H1L131 & S3L23;


--S3_w_anode3252w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3252w[3] at LCCOMB_X26_Y14_N12
S3_w_anode3252w[3] = !H1L129 & H1L133 & S3L93 & !H1L131;


--S3_w_anode3231w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3231w[3] at LCCOMB_X22_Y14_N26
S3_w_anode3231w[3] = H1L133 & !H1L131 & S3L88 & !H1L129;


--S3L6 is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2879w[3]~12 at LCCOMB_X26_Y14_N8
S3L6 = !H1L129 & !H1L133 & S3L93 & !H1L131;


--S3_w_anode2852w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2852w[3] at LCCOMB_X22_Y14_N4
S3_w_anode2852w[3] = !H1L133 & !H1L131 & S3L88 & !H1L129;


--S3_w_anode3335w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3335w[3] at LCCOMB_X26_Y14_N0
S3_w_anode3335w[3] = H1L129 & H1L133 & !H1L131 & S3L23;


--S3_w_anode3324w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3324w[3] at LCCOMB_X22_Y14_N8
S3_w_anode3324w[3] = H1L133 & !H1L131 & S3L88 & H1L129;


--S3_w_anode3345w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode3345w[3] at LCCOMB_X26_Y14_N26
S3_w_anode3345w[3] = H1L129 & H1L133 & S3L93 & !H1L131;


--S3_w_anode2973w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2973w[3] at LCCOMB_X26_Y14_N14
S3_w_anode2973w[3] = H1L129 & !H1L133 & S3L93 & !H1L131;


--S3_w_anode2952w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2952w[3] at LCCOMB_X22_Y14_N10
S3_w_anode2952w[3] = !H1L133 & !H1L131 & S3L88 & H1L129;


--S3_w_anode2963w[3] is VGA_OSD_RAM:u6|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_v4h1:auto_generated|altsyncram_99q1:altsyncram1|decode_qpa:decode_a|w_anode2963w[3] at LCCOMB_X26_Y14_N30
S3_w_anode2963w[3] = H1L129 & !H1L133 & !H1L131 & S3L23;


--V1L11 is I2C_AV_Config:u7|I2C_Controller:u0|ACK3~216 at LCCOMB_X34_Y14_N10
V1L11 = V1L10 & A1L287 & !V1L55Q # !V1L10 & (V1_ACK3);


--V1L39 is I2C_AV_Config:u7|I2C_Controller:u0|SD[12]~11 at LCCOMB_X31_Y12_N20
V1L39 = V1L58Q & V1L40 & !V1L43Q & KEY[0];


--G1L36 is VGA_Pattern:u5|oGreen~1193 at LCCOMB_X29_Y11_N4
G1L36 = F1_oCoord_X[7] & (F1_oCoord_X[5] & (!F1_oCoord_X[4] # !F1_oCoord_X[6]) # !F1_oCoord_X[5] & F1_oCoord_X[6]) # !F1_oCoord_X[7] & (!F1_oCoord_X[5] & !F1_oCoord_X[4] # !F1_oCoord_X[6]);


--G1L37 is VGA_Pattern:u5|oGreen~1194 at LCCOMB_X25_Y11_N22
G1L37 = F1_oCoord_X[5] & (F1_oCoord_X[6]) # !F1_oCoord_X[5] & (F1_oCoord_X[7] & !F1_oCoord_X[4] & !F1_oCoord_X[6] # !F1_oCoord_X[7] & (F1_oCoord_X[6]));


--G1L43 is VGA_Pattern:u5|oGreen~1207 at LCCOMB_X25_Y11_N12
G1L43 = F1_oCoord_X[9] # F1_oCoord_X[8] & G1L37 # !F1_oCoord_X[8] & (G1L36);


--G1L38 is VGA_Pattern:u5|oGreen~1200 at LCCOMB_X29_Y11_N6
G1L38 = F1_oCoord_X[7] & (!F1_oCoord_X[4] # !F1_oCoord_X[6] # !F1_oCoord_X[5]) # !F1_oCoord_X[7] & F1_oCoord_X[6] & (F1_oCoord_X[5] # F1_oCoord_X[4]);


--G1L39 is VGA_Pattern:u5|oGreen~1201 at LCCOMB_X29_Y11_N8
G1L39 = F1_oCoord_X[7] & (F1_oCoord_X[5] # F1_oCoord_X[6] # F1_oCoord_X[4]);


--G1L44 is VGA_Pattern:u5|oGreen~1208 at LCCOMB_X29_Y11_N2
G1L44 = F1_oCoord_X[9] # F1_oCoord_X[8] & G1L39 # !F1_oCoord_X[8] & (G1L38);


--V1L5 is I2C_AV_Config:u7|I2C_Controller:u0|ACK2~237 at LCCOMB_X34_Y13_N8
V1L5 = !V1L49Q & V1L58Q & !V1L43Q & !V1L55Q;


--V1L7 is I2C_AV_Config:u7|I2C_Controller:u0|ACK2~252 at LCCOMB_X34_Y13_N14
V1L7 = V1L6 & (V1_ACK2 # A1L287 & V1L5) # !V1L6 & A1L287 & V1L5;


--V1L8 is I2C_AV_Config:u7|I2C_Controller:u0|ACK2~253 at LCCOMB_X34_Y13_N0
V1L8 = V1L46Q & (V1L52Q & V1L7 # !V1L52Q & (V1_ACK2)) # !V1L46Q & (V1_ACK2);


--K1L127 is AUDIO_DAC:u8|oAUD_DATA~94 at LCCOMB_X29_Y20_N26
K1L127 = K1L134Q & (K1L89 & !K1L133Q) # !K1L134Q & (K1L114 # K1L133Q);


--K1L128 is AUDIO_DAC:u8|oAUD_DATA~95 at LCCOMB_X29_Y20_N24
K1L128 = !SW[9] & K1L127 & (K1L67 # !K1L133Q);


--K1L117 is AUDIO_DAC:u8|SEL_Cont[0]~53 at LCCOMB_X30_Y19_N28
K1L117 = !K1_SEL_Cont[0];


--H1L8 is VGA_OSD_RAM:u6|ADDR_dd[0]~6 at LCCOMB_X31_Y12_N0
H1L8 = !H1_ADDR_d[0];


--H1L10 is VGA_OSD_RAM:u6|ADDR_dd[1]~7 at LCCOMB_X31_Y12_N12
H1L10 = !H1_ADDR_d[1];


--H1L12 is VGA_OSD_RAM:u6|ADDR_dd[2]~8 at LCCOMB_X31_Y11_N2
H1L12 = !H1_ADDR_d[2];


--~GND is ~GND at LCCOMB_X36_Y2_N16
~GND = GND;


--CLOCK_24[1] is CLOCK_24[1] at PIN_A12
--operation mode is input

CLOCK_24[1] = INPUT();


--CLOCK_27[1] is CLOCK_27[1] at PIN_E12
--operation mode is input

CLOCK_27[1] = INPUT();


--EXT_CLOCK is EXT_CLOCK at PIN_M21
--operation mode is input

EXT_CLOCK = INPUT();


--KEY[1] is KEY[1] at PIN_R21
--operation mode is input

KEY[1] = INPUT();


--KEY[2] is KEY[2] at PIN_T22
--operation mode is input

KEY[2] = INPUT();


--KEY[3] is KEY[3] at PIN_T21
--operation mode is input

KEY[3] = INPUT();


--SW[1] is SW[1] at PIN_L21
--operation mode is input

SW[1] = INPUT();


--SW[2] is SW[2] at PIN_M22
--operation mode is input

SW[2] = INPUT();


--SW[3] is SW[3] at PIN_V12
--operation mode is input

SW[3] = INPUT();


--SW[4] is SW[4] at PIN_W12
--operation mode is input

SW[4] = INPUT();


--SW[5] is SW[5] at PIN_U12
--operation mode is input

SW[5] = INPUT();


--SW[6] is SW[6] at PIN_U11
--operation mode is input

SW[6] = INPUT();


--SW[7] is SW[7] at PIN_M2
--operation mode is input

SW[7] = INPUT();


--SW[8] is SW[8] at PIN_M1
--operation mode is input

SW[8] = INPUT();


--UART_RXD is UART_RXD at PIN_F14
--operation mode is input

UART_RXD = INPUT();


--TDI is TDI at PIN_E8
--operation mode is input

TDI = INPUT();


--TCK is TCK at PIN_C7
--operation mode is input

TCK = INPUT();


--TCS is TCS at PIN_D8
--operation mode is input

TCS = INPUT();


--PS2_DAT is PS2_DAT at PIN_J14
--operation mode is input

PS2_DAT = INPUT();


--PS2_CLK is PS2_CLK at PIN_H15
--operation mode is input

PS2_CLK = INPUT();


--AUD_ADCDAT is AUD_ADCDAT at PIN_B6
--operation mode is input

AUD_ADCDAT = INPUT();


--SW[9] is SW[9] at PIN_L2
--operation mode is input

SW[9] = INPUT();


--CLOCK_50 is CLOCK_50 at PIN_L1
--operation mode is input

CLOCK_50 = INPUT();


--KEY[0] is KEY[0] at PIN_R22
--operation mode is input

KEY[0] = INPUT();


--SW[0] is SW[0] at PIN_L22
--operation mode is input

SW[0] = INPUT();


--CLOCK_27[0] is CLOCK_27[0] at PIN_D12
--operation mode is input

CLOCK_27[0] = INPUT();


--CLOCK_24[0] is CLOCK_24[0] at PIN_B12
--operation mode is input

CLOCK_24[0] = INPUT();


--HEX0[0] is HEX0[0] at PIN_J2
--operation mode is output

HEX0[0] = OUTPUT(L1L1);


--HEX0[1] is HEX0[1] at PIN_J1
--operation mode is output

HEX0[1] = OUTPUT(L1L2);


--HEX0[2] is HEX0[2] at PIN_H2
--operation mode is output

HEX0[2] = OUTPUT(L1L3);


--HEX0[3] is HEX0[3] at PIN_H1
--operation mode is output

HEX0[3] = OUTPUT(L1L4);


--HEX0[4] is HEX0[4] at PIN_F2
--operation mode is output

HEX0[4] = OUTPUT(L1L5);


--HEX0[5] is HEX0[5] at PIN_F1
--operation mode is output

HEX0[5] = OUTPUT(L1L6);


--HEX0[6] is HEX0[6] at PIN_E2
--operation mode is output

HEX0[6] = OUTPUT(!L1L7);


--HEX1[0] is HEX1[0] at PIN_E1
--operation mode is output

HEX1[0] = OUTPUT(L1L1);


--HEX1[1] is HEX1[1] at PIN_H6
--operation mode is output

HEX1[1] = OUTPUT(L1L2);


--HEX1[2] is HEX1[2] at PIN_H5
--operation mode is output

HEX1[2] = OUTPUT(L1L3);


--HEX1[3] is HEX1[3] at PIN_H4
--operation mode is output

HEX1[3] = OUTPUT(L1L4);


--HEX1[4] is HEX1[4] at PIN_G3
--operation mode is output

HEX1[4] = OUTPUT(L1L5);


--HEX1[5] is HEX1[5] at PIN_D2
--operation mode is output

HEX1[5] = OUTPUT(L1L6);


--HEX1[6] is HEX1[6] at PIN_D1
--operation mode is output

HEX1[6] = OUTPUT(!L1L7);


--HEX2[0] is HEX2[0] at PIN_G5
--operation mode is output

HEX2[0] = OUTPUT(L1L1);


--HEX2[1] is HEX2[1] at PIN_G6
--operation mode is output

HEX2[1] = OUTPUT(L1L2);


--HEX2[2] is HEX2[2] at PIN_C2
--operation mode is output

HEX2[2] = OUTPUT(L1L3);


--HEX2[3] is HEX2[3] at PIN_C1
--operation mode is output

HEX2[3] = OUTPUT(L1L4);


--HEX2[4] is HEX2[4] at PIN_E3
--operation mode is output

HEX2[4] = OUTPUT(L1L5);


--HEX2[5] is HEX2[5] at PIN_E4
--operation mode is output

HEX2[5] = OUTPUT(L1L6);


--HEX2[6] is HEX2[6] at PIN_D3
--operation mode is output

HEX2[6] = OUTPUT(!L1L7);


--HEX3[0] is HEX3[0] at PIN_F4
--operation mode is output

HEX3[0] = OUTPUT(L1L1);


--HEX3[1] is HEX3[1] at PIN_D5
--operation mode is output

HEX3[1] = OUTPUT(L1L2);


--HEX3[2] is HEX3[2] at PIN_D6
--operation mode is output

HEX3[2] = OUTPUT(L1L3);


--HEX3[3] is HEX3[3] at PIN_J4
--operation mode is output

HEX3[3] = OUTPUT(L1L4);


--HEX3[4] is HEX3[4] at PIN_L8
--operation mode is output

HEX3[4] = OUTPUT(L1L5);


--HEX3[5] is HEX3[5] at PIN_F3
--operation mode is output

HEX3[5] = OUTPUT(L1L6);


--HEX3[6] is HEX3[6] at PIN_D4
--operation mode is output

HEX3[6] = OUTPUT(!L1L7);


--LEDG[0] is LEDG[0] at PIN_U22
--operation mode is output

LEDG[0] = OUTPUT(!D1_mLED[0]);


--LEDG[1] is LEDG[1] at PIN_U21
--operation mode is output

LEDG[1] = OUTPUT(!D1_mLED[1]);


--LEDG[2] is LEDG[2] at PIN_V22
--operation mode is output

LEDG[2] = OUTPUT(!D1_mLED[2]);


--LEDG[3] is LEDG[3] at PIN_V21
--operation mode is output

LEDG[3] = OUTPUT(D1_mLED[3]);


--LEDG[4] is LEDG[4] at PIN_W22
--operation mode is output

LEDG[4] = OUTPUT(D1_mLED[4]);


--LEDG[5] is LEDG[5] at PIN_W21
--operation mode is output

LEDG[5] = OUTPUT(D1_mLED[5]);


--LEDG[6] is LEDG[6] at PIN_Y22
--operation mode is output

LEDG[6] = OUTPUT(D1_mLED[6]);


--LEDG[7] is LEDG[7] at PIN_Y21
--operation mode is output

LEDG[7] = OUTPUT(D1_mLED[7]);


--LEDR[0] is LEDR[0] at PIN_R20
--operation mode is output

LEDR[0] = OUTPUT(!C1_mLED[0]);


--LEDR[1] is LEDR[1] at PIN_R19
--operation mode is output

LEDR[1] = OUTPUT(!C1_mLED[1]);


--LEDR[2] is LEDR[2] at PIN_U19
--operation mode is output

LEDR[2] = OUTPUT(!C1_mLED[2]);


--LEDR[3] is LEDR[3] at PIN_Y19
--operation mode is output

LEDR[3] = OUTPUT(C1_mLED[3]);


--LEDR[4] is LEDR[4] at PIN_T18
--operation mode is output

LEDR[4] = OUTPUT(C1_mLED[4]);


--LEDR[5] is LEDR[5] at PIN_V19
--operation mode is output

LEDR[5] = OUTPUT(C1_mLED[5]);


--LEDR[6] is LEDR[6] at PIN_Y18
--operation mode is output

LEDR[6] = OUTPUT(C1_mLED[6]);


--LEDR[7] is LEDR[7] at PIN_U18
--operation mode is output

LEDR[7] = OUTPUT(C1_mLED[7]);


--LEDR[8] is LEDR[8] at PIN_R18
--operation mode is output

LEDR[8] = OUTPUT(C1_mLED[8]);


--LEDR[9] is LEDR[9] at PIN_R17
--operation mode is output

LEDR[9] = OUTPUT(C1_mLED[9]);


--UART_TXD is UART_TXD at PIN_G12
--operation mode is output

UART_TXD = OUTPUT(GND);


--DRAM_ADDR[0] is DRAM_ADDR[0] at PIN_W4
--operation mode is output

DRAM_ADDR[0] = OUTPUT(GND);


--DRAM_ADDR[1] is DRAM_ADDR[1] at PIN_W5
--operation mode is output

DRAM_ADDR[1] = OUTPUT(GND);


--DRAM_ADDR[2] is DRAM_ADDR[2] at PIN_Y3
--operation mode is output

DRAM_ADDR[2] = OUTPUT(GND);


--DRAM_ADDR[3] is DRAM_ADDR[3] at PIN_Y4
--operation mode is output

DRAM_ADDR[3] = OUTPUT(GND);


--DRAM_ADDR[4] is DRAM_ADDR[4] at PIN_R6
--operation mode is output

DRAM_ADDR[4] = OUTPUT(GND);


--DRAM_ADDR[5] is DRAM_ADDR[5] at PIN_R5
--operation mode is output

DRAM_ADDR[5] = OUTPUT(GND);


--DRAM_ADDR[6] is DRAM_ADDR[6] at PIN_P6
--operation mode is output

DRAM_ADDR[6] = OUTPUT(GND);


--DRAM_ADDR[7] is DRAM_ADDR[7] at PIN_P5
--operation mode is output

DRAM_ADDR[7] = OUTPUT(GND);


--DRAM_ADDR[8] is DRAM_ADDR[8] at PIN_P3
--operation mode is output

DRAM_ADDR[8] = OUTPUT(GND);


--DRAM_ADDR[9] is DRAM_ADDR[9] at PIN_N4
--operation mode is output

DRAM_ADDR[9] = OUTPUT(GND);


--DRAM_ADDR[10] is DRAM_ADDR[10] at PIN_W3
--operation mode is output

DRAM_ADDR[10] = OUTPUT(GND);


--DRAM_ADDR[11] is DRAM_ADDR[11] at PIN_N6
--operation mode is output

DRAM_ADDR[11] = OUTPUT(GND);


--DRAM_LDQM is DRAM_LDQM at PIN_R7
--operation mode is output

DRAM_LDQM = OUTPUT(GND);


--DRAM_UDQM is DRAM_UDQM at PIN_M5
--operation mode is output

DRAM_UDQM = OUTPUT(GND);


--DRAM_WE_N is DRAM_WE_N at PIN_R8
--operation mode is output

DRAM_WE_N = OUTPUT(GND);


--DRAM_CAS_N is DRAM_CAS_N at PIN_T3
--operation mode is output

DRAM_CAS_N = OUTPUT(GND);


--DRAM_RAS_N is DRAM_RAS_N at PIN_T5
--operation mode is output

DRAM_RAS_N = OUTPUT(GND);


--DRAM_CS_N is DRAM_CS_N at PIN_T6
--operation mode is output

DRAM_CS_N = OUTPUT(GND);


--DRAM_BA_0 is DRAM_BA_0 at PIN_U3
--operation mode is output

DRAM_BA_0 = OUTPUT(GND);


--DRAM_BA_1 is DRAM_BA_1 at PIN_V4
--operation mode is output

DRAM_BA_1 = OUTPUT(GND);


--DRAM_CLK is DRAM_CLK at PIN_U4
--operation mode is output

DRAM_CLK = OUTPUT(GND);


--DRAM_CKE is DRAM_CKE at PIN_N3
--operation mode is output

DRAM_CKE = OUTPUT(GND);


--FL_ADDR[0] is FL_ADDR[0] at PIN_AB20
--operation mode is output

FL_ADDR[0] = OUTPUT(GND);


--FL_ADDR[1] is FL_ADDR[1] at PIN_AA14
--operation mode is output

FL_ADDR[1] = OUTPUT(GND);


--FL_ADDR[2] is FL_ADDR[2] at PIN_Y16
--operation mode is output

FL_ADDR[2] = OUTPUT(GND);


--FL_ADDR[3] is FL_ADDR[3] at PIN_R15
--operation mode is output

FL_ADDR[3] = OUTPUT(GND);


--FL_ADDR[4] is FL_ADDR[4] at PIN_T15
--operation mode is output

FL_ADDR[4] = OUTPUT(GND);


--FL_ADDR[5] is FL_ADDR[5] at PIN_U15
--operation mode is output

FL_ADDR[5] = OUTPUT(GND);


--FL_ADDR[6] is FL_ADDR[6] at PIN_V15
--operation mode is output

FL_ADDR[6] = OUTPUT(GND);


--FL_ADDR[7] is FL_ADDR[7] at PIN_W15
--operation mode is output

FL_ADDR[7] = OUTPUT(GND);


--FL_ADDR[8] is FL_ADDR[8] at PIN_R14
--operation mode is output

FL_ADDR[8] = OUTPUT(GND);


--FL_ADDR[9] is FL_ADDR[9] at PIN_Y13
--operation mode is output

FL_ADDR[9] = OUTPUT(GND);


--FL_ADDR[10] is FL_ADDR[10] at PIN_R12
--operation mode is output

FL_ADDR[10] = OUTPUT(GND);


--FL_ADDR[11] is FL_ADDR[11] at PIN_T12
--operation mode is output

FL_ADDR[11] = OUTPUT(GND);


--FL_ADDR[12] is FL_ADDR[12] at PIN_AB14
--operation mode is output

FL_ADDR[12] = OUTPUT(GND);


--FL_ADDR[13] is FL_ADDR[13] at PIN_AA13
--operation mode is output

FL_ADDR[13] = OUTPUT(GND);


--FL_ADDR[14] is FL_ADDR[14] at PIN_AB13
--operation mode is output

FL_ADDR[14] = OUTPUT(GND);


--FL_ADDR[15] is FL_ADDR[15] at PIN_AA12
--operation mode is output

FL_ADDR[15] = OUTPUT(GND);


--FL_ADDR[16] is FL_ADDR[16] at PIN_AB12
--operation mode is output

FL_ADDR[16] = OUTPUT(GND);


--FL_ADDR[17] is FL_ADDR[17] at PIN_AA20
--operation mode is output

FL_ADDR[17] = OUTPUT(GND);


--FL_ADDR[18] is FL_ADDR[18] at PIN_U14
--operation mode is output

FL_ADDR[18] = OUTPUT(GND);


--FL_ADDR[19] is FL_ADDR[19] at PIN_V14
--operation mode is output

FL_ADDR[19] = OUTPUT(GND);


--FL_ADDR[20] is FL_ADDR[20] at PIN_U13
--operation mode is output

FL_ADDR[20] = OUTPUT(GND);


--FL_ADDR[21] is FL_ADDR[21] at PIN_R13
--operation mode is output

FL_ADDR[21] = OUTPUT(GND);


--FL_WE_N is FL_WE_N at PIN_Y14
--operation mode is output

FL_WE_N = OUTPUT(GND);


--FL_RST_N is FL_RST_N at PIN_W14
--operation mode is output

FL_RST_N = OUTPUT(GND);


--FL_OE_N is FL_OE_N at PIN_AA15
--operation mode is output

FL_OE_N = OUTPUT(GND);


--FL_CE_N is FL_CE_N at PIN_H16
--operation mode is output

FL_CE_N = OUTPUT(GND);


--SRAM_ADDR[0] is SRAM_ADDR[0] at PIN_AA3
--operation mode is output

SRAM_ADDR[0] = OUTPUT(GND);


--SRAM_ADDR[1] is SRAM_ADDR[1] at PIN_AB3
--operation mode is output

SRAM_ADDR[1] = OUTPUT(GND);


--SRAM_ADDR[2] is SRAM_ADDR[2] at PIN_AA4
--operation mode is output

SRAM_ADDR[2] = OUTPUT(GND);


--SRAM_ADDR[3] is SRAM_ADDR[3] at PIN_AB4
--operation mode is output

SRAM_ADDR[3] = OUTPUT(GND);


--SRAM_ADDR[4] is SRAM_ADDR[4] at PIN_AA5
--operation mode is output

SRAM_ADDR[4] = OUTPUT(GND);


--SRAM_ADDR[5] is SRAM_ADDR[5] at PIN_AB10
--operation mode is output

SRAM_ADDR[5] = OUTPUT(GND);


--SRAM_ADDR[6] is SRAM_ADDR[6] at PIN_AA11
--operation mode is output

SRAM_ADDR[6] = OUTPUT(GND);


--SRAM_ADDR[7] is SRAM_ADDR[7] at PIN_AB11
--operation mode is output

SRAM_ADDR[7] = OUTPUT(GND);


--SRAM_ADDR[8] is SRAM_ADDR[8] at PIN_V11
--operation mode is output

SRAM_ADDR[8] = OUTPUT(GND);


--SRAM_ADDR[9] is SRAM_ADDR[9] at PIN_W11
--operation mode is output

SRAM_ADDR[9] = OUTPUT(GND);


--SRAM_ADDR[10] is SRAM_ADDR[10] at PIN_R11
--operation mode is output

SRAM_ADDR[10] = OUTPUT(GND);


--SRAM_ADDR[11] is SRAM_ADDR[11] at PIN_T11
--operation mode is output

SRAM_ADDR[11] = OUTPUT(GND);


--SRAM_ADDR[12] is SRAM_ADDR[12] at PIN_Y10
--operation mode is output

SRAM_ADDR[12] = OUTPUT(GND);


--SRAM_ADDR[13] is SRAM_ADDR[13] at PIN_U10
--operation mode is output

SRAM_ADDR[13] = OUTPUT(GND);


--SRAM_ADDR[14] is SRAM_ADDR[14] at PIN_R10
--operation mode is output

SRAM_ADDR[14] = OUTPUT(GND);


--SRAM_ADDR[15] is SRAM_ADDR[15] at PIN_T7
--operation mode is output

SRAM_ADDR[15] = OUTPUT(GND);


--SRAM_ADDR[16] is SRAM_ADDR[16] at PIN_Y6
--operation mode is output

SRAM_ADDR[16] = OUTPUT(GND);


--SRAM_ADDR[17] is SRAM_ADDR[17] at PIN_Y5
--operation mode is output

SRAM_ADDR[17] = OUTPUT(GND);


--SRAM_UB_N is SRAM_UB_N at PIN_W7
--operation mode is output

SRAM_UB_N = OUTPUT(GND);


--SRAM_LB_N is SRAM_LB_N at PIN_Y7
--operation mode is output

SRAM_LB_N = OUTPUT(GND);


--SRAM_WE_N is SRAM_WE_N at PIN_AA10
--operation mode is output

SRAM_WE_N = OUTPUT(GND);


--SRAM_CE_N is SRAM_CE_N at PIN_AB5
--operation mode is output

SRAM_CE_N = OUTPUT(GND);


--SRAM_OE_N is SRAM_OE_N at PIN_T8
--operation mode is output

SRAM_OE_N = OUTPUT(GND);


--SD_CLK is SD_CLK at PIN_H3
--operation mode is output

SD_CLK = OUTPUT(GND);


--TDO is TDO at PIN_D7
--operation mode is output

TDO = OUTPUT(GND);


--I2C_SCLK is I2C_SCLK at PIN_A3
--operation mode is output

I2C_SCLK = OUTPUT(V1L17);


--VGA_HS is VGA_HS at PIN_A11
--operation mode is output

VGA_HS = OUTPUT(F1_oVGA_H_SYNC);


--VGA_VS is VGA_VS at PIN_B11
--operation mode is output

VGA_VS = OUTPUT(F1_oVGA_V_SYNC);


--VGA_R[0] is VGA_R[0] at PIN_D9
--operation mode is output

VGA_R[0] = OUTPUT(F1L261);


--VGA_R[1] is VGA_R[1] at PIN_C9
--operation mode is output

VGA_R[1] = OUTPUT(F1L261);


--VGA_R[2] is VGA_R[2] at PIN_A7
--operation mode is output

VGA_R[2] = OUTPUT(F1L262);


--VGA_R[3] is VGA_R[3] at PIN_B7
--operation mode is output

VGA_R[3] = OUTPUT(F1L263);


--VGA_G[0] is VGA_G[0] at PIN_B8
--operation mode is output

VGA_G[0] = OUTPUT(F1L256);


--VGA_G[1] is VGA_G[1] at PIN_C10
--operation mode is output

VGA_G[1] = OUTPUT(F1L257);


--VGA_G[2] is VGA_G[2] at PIN_B9
--operation mode is output

VGA_G[2] = OUTPUT(F1L258);


--VGA_G[3] is VGA_G[3] at PIN_A8
--operation mode is output

VGA_G[3] = OUTPUT(F1L259);


--VGA_B[0] is VGA_B[0] at PIN_A9
--operation mode is output

VGA_B[0] = OUTPUT(F1L252);


--VGA_B[1] is VGA_B[1] at PIN_D11
--operation mode is output

VGA_B[1] = OUTPUT(F1L253);


--VGA_B[2] is VGA_B[2] at PIN_A10
--operation mode is output

VGA_B[2] = OUTPUT(F1L254);


--VGA_B[3] is VGA_B[3] at PIN_B10
--operation mode is output

VGA_B[3] = OUTPUT(F1L255);


--AUD_ADCLRCK is AUD_ADCLRCK at PIN_A6
--operation mode is output

AUD_ADCLRCK = OUTPUT(K1_LRCK_1X);


--AUD_DACLRCK is AUD_DACLRCK at PIN_A5
--operation mode is output

AUD_DACLRCK = OUTPUT(K1_LRCK_1X);


--AUD_DACDAT is AUD_DACDAT at PIN_B5
--operation mode is output

AUD_DACDAT = OUTPUT(K1L128);


--AUD_XCK is AUD_XCK at PIN_B4
--operation mode is output

AUD_XCK = OUTPUT(GLOBAL(M1L4));


--SD_DAT3 is SD_DAT3 at PIN_F11
--operation mode is bidir

SD_DAT3 = BIDIR(OPNDRN(VCC));


--SD_CMD is SD_CMD at PIN_E7
--operation mode is bidir

SD_CMD = BIDIR(OPNDRN(VCC));


--DRAM_DQ[0] is DRAM_DQ[0] at PIN_U1
--operation mode is bidir

DRAM_DQ[0] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[1] is DRAM_DQ[1] at PIN_U2
--operation mode is bidir

DRAM_DQ[1] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[2] is DRAM_DQ[2] at PIN_V1
--operation mode is bidir

DRAM_DQ[2] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[3] is DRAM_DQ[3] at PIN_V2
--operation mode is bidir

DRAM_DQ[3] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[4] is DRAM_DQ[4] at PIN_W1
--operation mode is bidir

DRAM_DQ[4] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[5] is DRAM_DQ[5] at PIN_W2
--operation mode is bidir

DRAM_DQ[5] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[6] is DRAM_DQ[6] at PIN_Y1
--operation mode is bidir

DRAM_DQ[6] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[7] is DRAM_DQ[7] at PIN_Y2
--operation mode is bidir

DRAM_DQ[7] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[8] is DRAM_DQ[8] at PIN_N1
--operation mode is bidir

DRAM_DQ[8] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[9] is DRAM_DQ[9] at PIN_N2
--operation mode is bidir

DRAM_DQ[9] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[10] is DRAM_DQ[10] at PIN_P1
--operation mode is bidir

DRAM_DQ[10] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[11] is DRAM_DQ[11] at PIN_P2
--operation mode is bidir

DRAM_DQ[11] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[12] is DRAM_DQ[12] at PIN_R1
--operation mode is bidir

DRAM_DQ[12] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[13] is DRAM_DQ[13] at PIN_R2
--operation mode is bidir

DRAM_DQ[13] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[14] is DRAM_DQ[14] at PIN_T1
--operation mode is bidir

DRAM_DQ[14] = BIDIR(OPNDRN(VCC));


--DRAM_DQ[15] is DRAM_DQ[15] at PIN_T2
--operation mode is bidir

DRAM_DQ[15] = BIDIR(OPNDRN(VCC));


--FL_DQ[0] is FL_DQ[0] at PIN_AB16
--operation mode is bidir

FL_DQ[0] = BIDIR(OPNDRN(VCC));


--FL_DQ[1] is FL_DQ[1] at PIN_AA16
--operation mode is bidir

FL_DQ[1] = BIDIR(OPNDRN(VCC));


--FL_DQ[2] is FL_DQ[2] at PIN_AB17
--operation mode is bidir

FL_DQ[2] = BIDIR(OPNDRN(VCC));


--FL_DQ[3] is FL_DQ[3] at PIN_AA17
--operation mode is bidir

FL_DQ[3] = BIDIR(OPNDRN(VCC));


--FL_DQ[4] is FL_DQ[4] at PIN_AB18
--operation mode is bidir

FL_DQ[4] = BIDIR(OPNDRN(VCC));


--FL_DQ[5] is FL_DQ[5] at PIN_AA18
--operation mode is bidir

FL_DQ[5] = BIDIR(OPNDRN(VCC));


--FL_DQ[6] is FL_DQ[6] at PIN_AB19
--operation mode is bidir

FL_DQ[6] = BIDIR(OPNDRN(VCC));


--FL_DQ[7] is FL_DQ[7] at PIN_AA19
--operation mode is bidir

FL_DQ[7] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[0] is SRAM_DQ[0] at PIN_AA6
--operation mode is bidir

SRAM_DQ[0] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[1] is SRAM_DQ[1] at PIN_AB6
--operation mode is bidir

SRAM_DQ[1] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[2] is SRAM_DQ[2] at PIN_AA7
--operation mode is bidir

SRAM_DQ[2] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[3] is SRAM_DQ[3] at PIN_AB7
--operation mode is bidir

SRAM_DQ[3] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[4] is SRAM_DQ[4] at PIN_AA8
--operation mode is bidir

SRAM_DQ[4] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[5] is SRAM_DQ[5] at PIN_AB8
--operation mode is bidir

SRAM_DQ[5] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[6] is SRAM_DQ[6] at PIN_AA9
--operation mode is bidir

SRAM_DQ[6] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[7] is SRAM_DQ[7] at PIN_AB9
--operation mode is bidir

SRAM_DQ[7] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[8] is SRAM_DQ[8] at PIN_Y9
--operation mode is bidir

SRAM_DQ[8] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[9] is SRAM_DQ[9] at PIN_W9
--operation mode is bidir

SRAM_DQ[9] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[10] is SRAM_DQ[10] at PIN_V9
--operation mode is bidir

SRAM_DQ[10] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[11] is SRAM_DQ[11] at PIN_U9
--operation mode is bidir

SRAM_DQ[11] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[12] is SRAM_DQ[12] at PIN_R9
--operation mode is bidir

SRAM_DQ[12] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[13] is SRAM_DQ[13] at PIN_W8
--operation mode is bidir

SRAM_DQ[13] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[14] is SRAM_DQ[14] at PIN_V8
--operation mode is bidir

SRAM_DQ[14] = BIDIR(OPNDRN(VCC));


--SRAM_DQ[15] is SRAM_DQ[15] at PIN_U8
--operation mode is bidir

SRAM_DQ[15] = BIDIR(OPNDRN(VCC));


--SD_DAT is SD_DAT at PIN_G8
--operation mode is bidir

SD_DAT = BIDIR(OPNDRN(VCC));


--A1L287 is I2C_SDAT~1 at PIN_B3
--operation mode is bidir

A1L287 = I2C_SDAT;

--I2C_SDAT is I2C_SDAT at PIN_B3
--operation mode is bidir

I2C_SDAT = BIDIR(OPNDRN(!V1L25Q));


--AUD_BCLK is AUD_BCLK at PIN_A4
--operation mode is bidir

AUD_BCLK_tri_out = TRI(K1_oAUD_BCK, VCC);
AUD_BCLK = BIDIR(AUD_BCLK_tri_out);


--GPIO_0[0] is GPIO_0[0] at PIN_A13
--operation mode is bidir

GPIO_0[0] = BIDIR(OPNDRN(VCC));


--GPIO_0[1] is GPIO_0[1] at PIN_B13
--operation mode is bidir

GPIO_0[1] = BIDIR(OPNDRN(VCC));


--GPIO_0[2] is GPIO_0[2] at PIN_A14
--operation mode is bidir

GPIO_0[2] = BIDIR(OPNDRN(VCC));


--GPIO_0[3] is GPIO_0[3] at PIN_B14
--operation mode is bidir

GPIO_0[3] = BIDIR(OPNDRN(VCC));


--GPIO_0[4] is GPIO_0[4] at PIN_A15
--operation mode is bidir

GPIO_0[4] = BIDIR(OPNDRN(VCC));


--GPIO_0[5] is GPIO_0[5] at PIN_B15
--operation mode is bidir

GPIO_0[5] = BIDIR(OPNDRN(VCC));


--GPIO_0[6] is GPIO_0[6] at PIN_A16
--operation mode is bidir

GPIO_0[6] = BIDIR(OPNDRN(VCC));


--GPIO_0[7] is GPIO_0[7] at PIN_B16
--operation mode is bidir

GPIO_0[7] = BIDIR(OPNDRN(VCC));


--GPIO_0[8] is GPIO_0[8] at PIN_A17
--operation mode is bidir

GPIO_0[8] = BIDIR(OPNDRN(VCC));


--GPIO_0[9] is GPIO_0[9] at PIN_B17
--operation mode is bidir

GPIO_0[9] = BIDIR(OPNDRN(VCC));


--GPIO_0[10] is GPIO_0[10] at PIN_A18
--operation mode is bidir

GPIO_0[10] = BIDIR(OPNDRN(VCC));


--GPIO_0[11] is GPIO_0[11] at PIN_B18
--operation mode is bidir

GPIO_0[11] = BIDIR(OPNDRN(VCC));


--GPIO_0[12] is GPIO_0[12] at PIN_A19
--operation mode is bidir

GPIO_0[12] = BIDIR(OPNDRN(VCC));


--GPIO_0[13] is GPIO_0[13] at PIN_B19
--operation mode is bidir

GPIO_0[13] = BIDIR(OPNDRN(VCC));


--GPIO_0[14] is GPIO_0[14] at PIN_A20
--operation mode is bidir

GPIO_0[14] = BIDIR(OPNDRN(VCC));


--GPIO_0[15] is GPIO_0[15] at PIN_B20
--operation mode is bidir

GPIO_0[15] = BIDIR(OPNDRN(VCC));


--GPIO_0[16] is GPIO_0[16] at PIN_C21
--operation mode is bidir

GPIO_0[16] = BIDIR(OPNDRN(VCC));


--GPIO_0[17] is GPIO_0[17] at PIN_C22
--operation mode is bidir

GPIO_0[17] = BIDIR(OPNDRN(VCC));


--GPIO_0[18] is GPIO_0[18] at PIN_D21
--operation mode is bidir

GPIO_0[18] = BIDIR(OPNDRN(VCC));


--GPIO_0[19] is GPIO_0[19] at PIN_D22
--operation mode is bidir

GPIO_0[19] = BIDIR(OPNDRN(VCC));


--GPIO_0[20] is GPIO_0[20] at PIN_E21
--operation mode is bidir

GPIO_0[20] = BIDIR(OPNDRN(VCC));


--GPIO_0[21] is GPIO_0[21] at PIN_E22
--operation mode is bidir

GPIO_0[21] = BIDIR(OPNDRN(VCC));


--GPIO_0[22] is GPIO_0[22] at PIN_F21
--operation mode is bidir

GPIO_0[22] = BIDIR(OPNDRN(VCC));


--GPIO_0[23] is GPIO_0[23] at PIN_F22
--operation mode is bidir

GPIO_0[23] = BIDIR(OPNDRN(VCC));


--GPIO_0[24] is GPIO_0[24] at PIN_G21
--operation mode is bidir

GPIO_0[24] = BIDIR(OPNDRN(VCC));


--GPIO_0[25] is GPIO_0[25] at PIN_G22
--operation mode is bidir

GPIO_0[25] = BIDIR(OPNDRN(VCC));


--GPIO_0[26] is GPIO_0[26] at PIN_J21
--operation mode is bidir

GPIO_0[26] = BIDIR(OPNDRN(VCC));


--GPIO_0[27] is GPIO_0[27] at PIN_J22
--operation mode is bidir

GPIO_0[27] = BIDIR(OPNDRN(VCC));


--GPIO_0[28] is GPIO_0[28] at PIN_K21
--operation mode is bidir

GPIO_0[28] = BIDIR(OPNDRN(VCC));


--GPIO_0[29] is GPIO_0[29] at PIN_K22
--operation mode is bidir

GPIO_0[29] = BIDIR(OPNDRN(VCC));


--GPIO_0[30] is GPIO_0[30] at PIN_J19
--operation mode is bidir

GPIO_0[30] = BIDIR(OPNDRN(VCC));


--GPIO_0[31] is GPIO_0[31] at PIN_J20
--operation mode is bidir

GPIO_0[31] = BIDIR(OPNDRN(VCC));


--GPIO_0[32] is GPIO_0[32] at PIN_J18
--operation mode is bidir

GPIO_0[32] = BIDIR(OPNDRN(VCC));


--GPIO_0[33] is GPIO_0[33] at PIN_K20
--operation mode is bidir

GPIO_0[33] = BIDIR(OPNDRN(VCC));


--GPIO_0[34] is GPIO_0[34] at PIN_L19
--operation mode is bidir

GPIO_0[34] = BIDIR(OPNDRN(VCC));


--GPIO_0[35] is GPIO_0[35] at PIN_L18
--operation mode is bidir

GPIO_0[35] = BIDIR(OPNDRN(VCC));


--GPIO_1[0] is GPIO_1[0] at PIN_H12
--operation mode is bidir

GPIO_1[0] = BIDIR(OPNDRN(VCC));


--GPIO_1[1] is GPIO_1[1] at PIN_H13
--operation mode is bidir

GPIO_1[1] = BIDIR(OPNDRN(VCC));


--GPIO_1[2] is GPIO_1[2] at PIN_H14
--operation mode is bidir

GPIO_1[2] = BIDIR(OPNDRN(VCC));


--GPIO_1[3] is GPIO_1[3] at PIN_G15
--operation mode is bidir

GPIO_1[3] = BIDIR(OPNDRN(VCC));


--GPIO_1[4] is GPIO_1[4] at PIN_E14
--operation mode is bidir

GPIO_1[4] = BIDIR(OPNDRN(VCC));


--GPIO_1[5] is GPIO_1[5] at PIN_E15
--operation mode is bidir

GPIO_1[5] = BIDIR(OPNDRN(VCC));


--GPIO_1[6] is GPIO_1[6] at PIN_F15
--operation mode is bidir

GPIO_1[6] = BIDIR(OPNDRN(VCC));


--GPIO_1[7] is GPIO_1[7] at PIN_G16
--operation mode is bidir

GPIO_1[7] = BIDIR(OPNDRN(VCC));


--GPIO_1[8] is GPIO_1[8] at PIN_F12
--operation mode is bidir

GPIO_1[8] = BIDIR(OPNDRN(VCC));


--GPIO_1[9] is GPIO_1[9] at PIN_F13
--operation mode is bidir

GPIO_1[9] = BIDIR(OPNDRN(VCC));


--GPIO_1[10] is GPIO_1[10] at PIN_C14
--operation mode is bidir

GPIO_1[10] = BIDIR(OPNDRN(VCC));


--GPIO_1[11] is GPIO_1[11] at PIN_D14
--operation mode is bidir

GPIO_1[11] = BIDIR(OPNDRN(VCC));


--GPIO_1[12] is GPIO_1[12] at PIN_D15
--operation mode is bidir

GPIO_1[12] = BIDIR(OPNDRN(VCC));


--GPIO_1[13] is GPIO_1[13] at PIN_D16
--operation mode is bidir

GPIO_1[13] = BIDIR(OPNDRN(VCC));


--GPIO_1[14] is GPIO_1[14] at PIN_C17
--operation mode is bidir

GPIO_1[14] = BIDIR(OPNDRN(VCC));


--GPIO_1[15] is GPIO_1[15] at PIN_C18
--operation mode is bidir

GPIO_1[15] = BIDIR(OPNDRN(VCC));


--GPIO_1[16] is GPIO_1[16] at PIN_C19
--operation mode is bidir

GPIO_1[16] = BIDIR(OPNDRN(VCC));


--GPIO_1[17] is GPIO_1[17] at PIN_C20
--operation mode is bidir

GPIO_1[17] = BIDIR(OPNDRN(VCC));


--GPIO_1[18] is GPIO_1[18] at PIN_D19
--operation mode is bidir

GPIO_1[18] = BIDIR(OPNDRN(VCC));


--GPIO_1[19] is GPIO_1[19] at PIN_D20
--operation mode is bidir

GPIO_1[19] = BIDIR(OPNDRN(VCC));


--GPIO_1[20] is GPIO_1[20] at PIN_E20
--operation mode is bidir

GPIO_1[20] = BIDIR(OPNDRN(VCC));


--GPIO_1[21] is GPIO_1[21] at PIN_F20
--operation mode is bidir

GPIO_1[21] = BIDIR(OPNDRN(VCC));


--GPIO_1[22] is GPIO_1[22] at PIN_E19
--operation mode is bidir

GPIO_1[22] = BIDIR(OPNDRN(VCC));


--GPIO_1[23] is GPIO_1[23] at PIN_E18
--operation mode is bidir

GPIO_1[23] = BIDIR(OPNDRN(VCC));


--GPIO_1[24] is GPIO_1[24] at PIN_G20
--operation mode is bidir

GPIO_1[24] = BIDIR(OPNDRN(VCC));


--GPIO_1[25] is GPIO_1[25] at PIN_G18
--operation mode is bidir

GPIO_1[25] = BIDIR(OPNDRN(VCC));


--GPIO_1[26] is GPIO_1[26] at PIN_G17
--operation mode is bidir

GPIO_1[26] = BIDIR(OPNDRN(VCC));


--GPIO_1[27] is GPIO_1[27] at PIN_H17
--operation mode is bidir

GPIO_1[27] = BIDIR(OPNDRN(VCC));


--GPIO_1[28] is GPIO_1[28] at PIN_J15
--operation mode is bidir

GPIO_1[28] = BIDIR(OPNDRN(VCC));


--GPIO_1[29] is GPIO_1[29] at PIN_H18
--operation mode is bidir

GPIO_1[29] = BIDIR(OPNDRN(VCC));


--GPIO_1[30] is GPIO_1[30] at PIN_N22
--operation mode is bidir

GPIO_1[30] = BIDIR(OPNDRN(VCC));


--GPIO_1[31] is GPIO_1[31] at PIN_N21
--operation mode is bidir

GPIO_1[31] = BIDIR(OPNDRN(VCC));


--GPIO_1[32] is GPIO_1[32] at PIN_P15
--operation mode is bidir

GPIO_1[32] = BIDIR(OPNDRN(VCC));


--GPIO_1[33] is GPIO_1[33] at PIN_N15
--operation mode is bidir

GPIO_1[33] = BIDIR(OPNDRN(VCC));


--GPIO_1[34] is GPIO_1[34] at PIN_P17
--operation mode is bidir

GPIO_1[34] = BIDIR(OPNDRN(VCC));


--GPIO_1[35] is GPIO_1[35] at PIN_P18
--operation mode is bidir

GPIO_1[35] = BIDIR(OPNDRN(VCC));





--D1L65 is LEDG_Driver:u2|Cont[20]~clkctrl at CLKCTRL_G1
D1L65 = cycloneii_clkctrl(.INCLK[0] = D1_Cont[20]) WITH (clock_type = "Global Clock");


--C1L65 is LEDR_Driver:u1|Cont[20]~clkctrl at CLKCTRL_G0
C1L65 = cycloneii_clkctrl(.INCLK[0] = C1_Cont[20]) WITH (clock_type = "Global Clock");


--J1L73 is I2C_AV_Config:u7|mI2C_CTRL_CLK~clkctrl at CLKCTRL_G5
J1L73 = cycloneii_clkctrl(.INCLK[0] = J1_mI2C_CTRL_CLK) WITH (clock_type = "Global Clock");


--A1L16 is CLOCK_50~clkctrl at CLKCTRL_G2
A1L16 = cycloneii_clkctrl(.INCLK[0] = CLOCK_50) WITH (clock_type = "Global Clock");


--K1L126 is AUDIO_DAC:u8|oAUD_BCK~clkctrl at CLKCTRL_G6
K1L126 = cycloneii_clkctrl(.INCLK[0] = K1_oAUD_BCK) WITH (clock_type = "Global Clock");


--M1L2 is VGA_Audio_PLL:u3|altpll:altpll_component|_clk0~clkctrl at CLKCTRL_G9
M1L2 = cycloneii_clkctrl(.INCLK[0] = M1__clk0) WITH (clock_type = "Global Clock");


--A1L13 is CLOCK_27[0]~clkctrl at CLKCTRL_G11
A1L13 = cycloneii_clkctrl(.INCLK[0] = CLOCK_27[0]) WITH (clock_type = "Global Clock");


--M1L4 is VGA_Audio_PLL:u3|altpll:altpll_component|_clk1~clkctrl at CLKCTRL_G8
M1L4 = cycloneii_clkctrl(.INCLK[0] = M1__clk1) WITH (clock_type = "Global Clock");


--A1L9 is CLOCK_24[0]~clkctrl at CLKCTRL_G10
A1L9 = cycloneii_clkctrl(.INCLK[0] = CLOCK_24[0]) WITH (clock_type = "Global Clock");


--K1L38 is AUDIO_DAC:u8|LRCK_1X~clkctrl at CLKCTRL_G14
K1L38 = cycloneii_clkctrl(.INCLK[0] = K1_LRCK_1X) WITH (clock_type = "Global Clock");


--F1L194 is VGA_Controller:u4|oCoord_X[0]~feeder at LCCOMB_X29_Y10_N20
F1L194 = F1_H_Cont[0];


--F1L196 is VGA_Controller:u4|oCoord_X[1]~feeder at LCCOMB_X29_Y10_N26
F1L196 = F1_H_Cont[1];


--H1L3 is VGA_OSD_RAM:u6|ADDR_d[0]~feeder at LCCOMB_X31_Y12_N30
H1L3 = F1_oAddress[0];


--V1L30 is I2C_AV_Config:u7|I2C_Controller:u0|SD[2]~feeder at LCCOMB_X33_Y14_N6
V1L30 = J1_mI2C_DATA[2];


--V1L27 is I2C_AV_Config:u7|I2C_Controller:u0|SD[0]~feeder at LCCOMB_X33_Y14_N24
V1L27 = J1_mI2C_DATA[0];


--V1L37 is I2C_AV_Config:u7|I2C_Controller:u0|SD[11]~feeder at LCCOMB_X33_Y14_N4
V1L37 = J1_mI2C_DATA[11];


--H1L137 is VGA_OSD_RAM:u6|oBlue[9]~feeder at LCCOMB_X26_Y12_N16
H1L137 = VCC;