1. Introduction to NCF29A1

      NCF29A1 /NCF29A2 is a very compact single-chip solution, very suitable for automotive applications, the chip has vehicle IMMO and keyless entry/start functions. The chip integrates a security transponder, supports multi-channel EEPROM access, and provides up to 2048 bytes of EEPROM for data storage of application-defined access control. UHF transmitters do not require external components, except for reference crystals and loop antenna matching circuits. The operating frequency band of the device is 310-447MHz. It can support the 868 MHz and 915 MHz frequency bands according to requirements. The UHF transmitter is directly controlled by the RISC controller and supports carrier FSK, ASK, and OOK modulation with rising data rates. The device has 10 I/O ports, allowing up to 10 command button inputs, on-chip hardware computing units or any user-defined software based on algorithms, and can be used for data communication.

Second, Timer/Counter 0, 1, 2

      Among them, timer 0 and timer 2 are the same, but unlike timer 0/2, timer 1 is an 8/16-bit timer and a 12-bit divider. In the following description, timer 0 is T0 and timer 2 is replaced by T2. T0/T2 is a 16-bit timer.Divider with 12 bits. Clock source RCCLK, the clock of the 16 MHz RC main oscillator The 16 MHz main RC oscillator is the main clock source for high-speed CPU and peripheral operations.

1. Timer/Counter 0, 2

      T0/T2 is a 16-bit timer and 12-bit divider, which can be used as an interval, event counter, digital modulator, or clock divider. If the timer 0/2 reaches a value of 0, an interrupt will be generated, which can be set and cleared. The output of timer 0/2 can be used to provide a time-sharing clock output on the I/O port. The timer can restart the timing by loading the reload value from the register TxRLD to the register TxREG, and then automatically counts down. When the value of the timer register TxREG is 0, reload the timer register TxREG with the value of the reload register TxRLD, generate an interrupt request and trigger other peripheral functions.

2. Timer/Counter 1

      Unlike timer 0/2, timer 1 is an 8/16-bit timer and 12-bit divider, which can be used in general-purpose applications, as well as time interval and event counters, demodulators, or signal generators and modulators.



      Timer 1 has four operating modes：

      Mode 0 ：

          In mode 0 timer 1 is a synchronous 16-bit timer with a 12-bit divider, providing a 16-bit comparison and 16-bit capture register. The timer is continuously operated in automatic overload mode.

      Mode 1 ：

          Mode 1 has the same properties as mode 0, except that the mode timer will automatically stop when the first comparison match occurs. If the TIRSTCMP bit is set, the timer register will be cleared when the timer stops.

      Mode 2 ：

          In mode 2. Timer 1 operates as an 8-bit timer and a 12-bit divider, providing two 8-bit comparators and two 8-bit capture resistors. The purpose of mode 2 is to generate a flexible PWM signal.
          The 8-bit timer registers T1REGL and T1REGH run in parallel. It is recommended to clear the timer register before starting to ensure that the two timer registers contain the same value.

      Mode 3 ：

          For example, in mode 2 and mode 3, timer 1 is used as an 8-bit timer and a 12-bit divider, and two 8-bit comparators and two 8-bit capture registers are also provided.

3. Timer 1 register

      T1REG :

          Timer 1 supports read access to the timer register. The contents of the timer register are not buffered or synchronized. Therefore, it is recommended to read T1REG only when the timer stops (T1RUN =0). When the timer is running, reading T1REG will produce unstable and incorrect values, because the value of the timer is read.It is not necessarily certain.

 

      T1CON 0 :

          Timer 1 control register 0 maintains the control bit to adjust the timer mode and output line, in addition to providing configuration reset and operating condition bits.

 

      T1CON1 :

          Timer 1 Control register 1 stores the selected divider value T1PRESC[3:0] and the clock source used T1CLKSEL[1:0].

 

      T1CON2 :

          Timer 1 Control register 2 maintains the control bit to adjust the capture function.

 

      T1CMP :

          The comparison register T1CMP is used to set the timeout of timer 1.

 

      T1CAP :

          Timer 1 captures the register T1CAP and automatically loads the contents of the timer register. It can only be read if the content is stable. Writing to T1CAP is not supported.

 

3. Reference materials

       【A brief discussion on PEPS Technology】
              https://www.wpgdadatong.com/blog/detail?BID=B2618

       【NXP PEPS solution in Simple Terms (1)-System structure and Selection】
              https://www.wpgdadatong.com/blog/detail?BID=B1177

       【NXP: Micro single-chip passive keyless switch solution】
             https://www.nxp.com.cn/products/security-and-authentication/secure-car-access/tiny-single-chip-passive-keyless-entry-go-solution:NCF29A1MHN