[DP5 Configuration File]
; [For DP5/PC5, +HV for SiPin]
; Rules:	No whitespace before command - it must start at left column
; 		Command must end with semicolon
;		Anything after semicolon is ignored (i.e. comments)
BOOT=OFF;
;
RESC=YES;		Clear the existing configuration
;CLCK=AUTO;		FPGA clock: 20, 80, or AUTO
CLCK=20;		FPGA clock: 20, 80, or AUTO
TPEA=38.4US;		Peaking time in uS
TFLA=1.6US;		Flat top in uS
;TPFA=1600NS;		Fast channel Peaking Time:[####] (100 or 400 @ 80MHz, 400 or 1600 @ 20MHz)
CUSP=0%;		Cusp parameter [OFF|##] (-99 to 99%, 0% or OFF=normal trapezoid, +%=cusp-like, -%=Gaussian-like)
;RESL=3000US;		Reset lockout
PDMD=NORM;		Peak detect mode; NORM, MIN (for min+max)
THSL=3.03%;		Slow threshold
TLLD=0;		LLD
THFA=50;		Fast threshold (0-255)
;THFA=2;			Fast threshold (0-255)
MCAC=1024;		MCA channels: [256|512|1024|2048|4096|8192]
SOFF=OFF;		Spectrum offset: +/-####.### (in channels)
DACO=SHAPED;		DAC output selection: [#|OFF|FAST|SHAPED|INPUT|PEAK|SDD|SUM|PZBD|RTDP] (1-8)
;DACO=SUM;		DAC output selection: [#|OFF|FAST|SHAPED|INPUT|PEAK|SDD|SUM|PZBD|RTDP] (1-8)
;DACO=INPUT;		DAC output selection: [#|OFF|FAST|SHAPED|INPUT|PEAK|SDD|SUM|PZBD|RTDP] (1-8)
;DACF=100MV;		DAC offset; +/-### (millivolts)
DACF=101MV;		DAC offset
;PURE=ON;		Pileup reject enable: [ON|OFF]
;GAIN=99.5;		Total gain; ###.###
;GAIN=100;
GAIN=91.9;		Total gain
RTDE=ON;		RTD enable
RTDS=600%;		RTD sensitivity threshold; ###%
RTDT=3.13%;		RTD threshold
RTDD=110;
RTDW=50;
BLRM=1;			BLR mode
BLRD=2;			BLR down correction
BLRU=1;			BLR up correction
GATE=OFF;		Gate control: [OFF|HIGH|LOW] ("HIGH" -> events rejected while gate is high)
;AUO1=ICR;		AUX_OUT1 selection: [#|ICR|PILEUP|MCSTB|ONESH|DETRES|MCAEN|PEAKH|SCA8]
AUO1=ICR;		AUX_OUT1 selection: [#|ICR|PILEUP|MCSTB|ONESH|DETRES|MCAEN|PEAKH|SCA8]
;PRET=60;		Preset Time (in seconds, 100mS precision): [#######.#|OFF] (0 same as OFF)
;PRER=10.123;		Preset Real Time (in seconds, 1mS precision): [#######.###|OFF] (0 same as OFF)
;PREC=10000;		Preset Counts: [##########|OFF] (up to 10 digits)
;PRCL=536;
;PRCH=538;
;AINP=NEG;		Analog input polarity: [POS|NEG] (SDD=+, SiPIN=-)
AINP=NEG;		Analog input polarity: [POS|NEG] (SDD=+, SiPIN=-)
;
HVSE=101.1V;		PC5 HV setting (if PC5 present): [{+|-}####|OFF] (HV is only turned on if PC5 is proper HV polarity. SDD requires negative HV, SiPIN requires positive HV)
TECS=230.0K;		PC5 TEC cooler setting: [###|OFF] (degrees K)
PAPS=8.5V;		PC5 Preamp power supply: [8.5|5|OFF|ON] ('8.5' or '5' turn on the PC5 preamp supplies if they're the proper voltage. 'ON' doesn't check.)
;
INOF=DEF;		Input offset: [{+|-}[####]|AUTO|DEF] ('DEF' uses standard default settings
;INOF=1000MV;		Input offset: [{+|-}[####]|AUTO|DEF] ('DEF' uses standard default settings; 'AUTO' searches for an appropriate setting; '####' is in mV.)
SCOE=FALLING;		Scope trigger edge: [RI{SING}|FA{LLING}]
;SCOT=-25%;		Scope trigger position: [87|50|12|-25] in %
SCOT=12%;		Scope trigger position: [87|50|12|-25] in %
SCOG=1;
;MCAS=NORM;		MCA source: [NORM|MCS|FAST|PUR|RTD]
;MCAS=FAST;		MCA source: [NORM|MCS|FAST|PUR|RTD]
;MCSL=536;
;MCSH=538;
;MCST=.05S;		MCS timebase: [###.###] (in seconds, multiples of 10mS)
AUO2=6;			AUX_OUT2 selection: [#] (1-8) (6=RTD_REJ)
;TPMO=-SNG;		Test pulser mode (output DAC): [OFF|+SNG|+DBL|-SNG|-DBL] (single or double pulses, + or -)
GPED=RI;		General purpose (GP) counter edge: [RI{SING}|FA{LLING}]
GPIN=DETRES;		GP counter input: [#|AUX1|AUX2|PILEUP|RTDREJ|SCA8|TBD|DETRES|OFF]
GPME=ON;		GP counter MCA EN: [ON|OF{F}] ('ON' means GP counter is disabled when MCA is disabled)
GPGA=ON;		GP counter Gate EN: [ON|OF{F}] ('ON' means GP counter is conditioned by GATE)
GPMC=ON;		GP clear control: [ON|OF{F}] ('ON' means GP counter is cleared when MCA is cleared; otherwise, command clears it)
MCAE=ON;		Initial state of MCA enable: [ON|OF{F}]
PURE=ON;
MCAS=NORM;
MCST=.01S;
PREC=PRESET;
RESL=1638US;
VOLU=OFF;
;SCAW=1000;
;SCAI=8;
;SCAL=535;
;SCAH=537;
;SCAO=HI;