RSRC LVINLBVWp H pp  <@" ^BH$⧝  U6lFC<\_ُ B~0ُ B~?m<&BOrP4yasa.$ LVINStatusToString.vi#@0 Status String @ FPGA@ Firmware@ SerialNumber@ DppDeviceID@ 80MHzMode@ DppConfigured@ DppOptions@FastThresholdLocked@InputOffsetLocked@ BoardTemp@ HVMonitor@ TECMonitor@ FastCount@ SlowCount@ AccumulationTime@ McaEnabled @MCSDone@PresetCountDone @Build@ FPGAAutoClock@ ReBootFlag@ RealTime@ LiveTime@ PresetRtDone@ PresetLtDone@ GpCounter@ PC5_PRESENT@ PC5_HV_POL@PC5_8_5V@ScopeDataReady@ GateDisabled@ PX5TECVoltageR@P   DPP Status! "\ cx d0` P c @flg@oRt@eof@Pudf@0 Status String @0dfd @0txd @0old @0extP  c @ FPGA@ Firmware@ SerialNumber@ DppDeviceID@ 80MHzMode@ DppConfigured@ DppOptions@FastThresholdLocked@InputOffsetLocked@ BoardTemp@ HVMonitor@ TECMonitor@ FastCount@ SlowCount@ AccumulationTime@ McaEnabled @MCSDone@PresetCountDone @Build@ FPGAAutoClock@ ReBootFlag@ RealTime@ LiveTime@ PresetRtDone@ PresetLtDone@ GpCounter@ PC5_PRESENT@ PC5_HV_POL@PC5_8_5V@ScopeDataReady@ GateDisabled@ PX5TECVoltageR@P  !"#$%&'()*+,-./0 DPP Status J@P 22344444422222244444422442444442dfdJ@P 22344444422222244444422442444442txdJ@P 22344444422222244444422442444442oldJ@P 22344444422222244444422442444442extP 15678 P222 P444 P333P44= @>0 @@PP?AB c,@@0 output string1& cL c`>P==UUUUUUUUUUUUUUUUVVV dW d dnr9:0;0;0;0;0;0:0;0;0:0:0;0;0;0;0;0;0:0:0:0:0:0:0;0;0;0;0;0;0<0:0:0C 38@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ DE@FF@@@@@@@@GHIJKLMNOPQRST&@X0Y0Z01[nfxտOa*H?p&A*ri4rZMLdppp0A7wWrVQ1 }}߻^E#r[q"Ci_Akڣ1'~_*D!|kLJ=H i@1d]DRE"ta[M&54mp5QmVil[&Mt.:u V6eC\͋^$w<{vEgUuU'Kh;6SKMm56mQBR^a5A5Tkp xJ2JhϪtUGK*3OʥP1JAzm'>?xa_<ó|'$ӌ>qs^9?gpV >,>3~$62y,&_jg9>2I䋴r9*(+qjf)s˪HJyZ؁,%vP,<mޞ)S 1%-P lUz&bt:{J"_ FCsa#; e3D~z\kA  'nރnW3*c'"tnbg.|.t,0=ة:Ϣ;NGІЙǕ~;_H;kM΄й;G:E9B'#;?ֹ g(z, 8t5~ELI,K|b;)eѺ@N£ Cs$s ZMN|JfIK&?=)DZ-r o2`֕K(Gc#Zy"8I:\JJ8W>{HySKJh?BYU~ˢ+Rc# 9)9}؈v^eXueq.܈ʇH3N5Rjl\^"*MѕIxۨ{eN+~RSVRc#l!\EJ1]6SAe1)_AR+B姒S~bzm3*4GWVKL/͔E~.Nv?ɴSePZ[4JiTLC]<ҿ=̗/Oo{q؉ZgO?`Ҽz{-31M+ TX z:cmK-m 5:*vNowe.$ f~rUfE4<I%$|&]7>Mw竸)7N:U\K ?'T|p7k" gBw~`RaL& +h-}]-.YxDž YgޥR-<%ggs3-~û+zh3/GClg?ҀH  8.2( P @ FPGA@ Firmware@ SerialNumber@ DppDeviceID@ 80MHzMode@ DppConfigured@ DppOptions@FastThresholdLocked@InputOffsetLocked@ BoardTemp@ HVMonitor@ TECMonitor@ FastCount@ SlowCount@ AccumulationTime@ McaEnabled @MCSDone@PresetCountDone @Build@ FPGAAutoClock@ ReBootFlag@ RealTime@ LiveTime@ PresetRtDone@ PresetLtDone@ GpCounter@ PC5_PRESENT@ PC5_HV_POL@PC5_8_5V@ScopeDataReady@ GateDisabled@ PX5TECVoltageR@P   !" DPP Status@0 Status String P#$ P% p&'LDRDHDDDRC,*' @ FPGA@ Firmware@ SerialNumber@ DppDeviceID@ 80MHzMode@ DppConfigured@ DppOptions@FastThresholdLocked@InputOffsetLocked@ BoardTemp@ HVMonitor@ TECMonitor@ FastCount@ SlowCount@ AccumulationTime@ McaEnabled @MCSDone@PresetCountDone @Build@ FPGAAutoClock@ ReBootFlag@ RealTime@ LiveTime@ PresetRtDone@ PresetLtDone@ GpCounter@ PC5_PRESENT@ PC5_HV_POL@PC5_8_5V@ScopeDataReady@ GateDisabled@ PX5TECVoltageR@P   DPP Status@0 Status String0 @0 output string !!  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