RSRC LVINLBVW P @!<@2>zzC w &,.KOcVُ B~@DPşҤSJSĨ_ݨv6杆,s0_,+40G>LVIN DppStatus.vi%@0 Status Packet@!Unit Configured@! MCA Enabled @ FPGA@ Firmware@ SerialNumber@ DppDeviceID@ 80MHzMode@ DppConfigured@ DppOptions@FastThresholdLocked@InputOffsetLocked@ BoardTemp@ HVMonitor@ TECMonitor@ FastCount@ SlowCount@ AccumulationTime@ McaEnabled @MCSDone@PresetCountDone @Build@ FPGAAutoClock@ ReBootFlag@ RealTime@ LiveTime@ PresetRtDone@ PresetLtDone@ GpCounter@ PC5_PRESENT@ PC5_HV_POL@PC5_8_5V@ScopeDataReady@ GateDisabled@ PX5TECVoltageR@P   !" DPP Status#" $Y` d3` P c@flg@oRt@eof@Pudf@! MCA Enabled@!txd@!extP c @ FPGA@ Firmware@ SerialNumber@ DppDeviceID@ 80MHzMode@ DppConfigured@ DppOptions@FastThresholdLocked@InputOffsetLocked@ BoardTemp@ HVMonitor@ TECMonitor@ FastCount@ SlowCount@ AccumulationTime@ McaEnabled @MCSDone@PresetCountDone @Build@ FPGAAutoClock@ ReBootFlag@ RealTime@ LiveTime@ PresetRtDone@ PresetLtDone@ GpCounter@ PC5_PRESENT@ PC5_HV_POL@PC5_8_5V@ScopeDataReady@ GateDisabled@ PX5TECVoltageR@P  !"#$%&'()*+,-. DPP Status J@P 00122222200000022222200220222220txdJ@P 00122222200000022222200220222220extP /34 c{@!Unit ConfiguredP 7 ck@0 Status Packet @0txd @0extP :;<`FP >?222@222222222222AAA dB@oRt@PDudf @0dfd @0oldPE:F;G<@!dfd@!oldPE7I J c P000 P222 c c c P111J@P  !"#$%&'()*+,-.dfdJ@P 00122222200000022222200220222220oldPE/S3T4PE I J cp 5689=C0HKLM N N N N N OM N N PM M N N N N N N QM M M M M M N N N N N N PR M M UOVL1  ( 1(  1(  1(  0 0 0 0 0   1(2 L0 2 W0     1(  >(P0   ?(Q0 ? P @(L 2 L   ?(Q0  X xc` XX[4n%B€ @@LgFՁ0Td"UdNp|!6lf1jb],@ww:kD2ka #;6@]]WKH0. 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MCA Enabled @ FPGA@ Firmware@ SerialNumber@ DppDeviceID@ 80MHzMode@ DppConfigured@ DppOptions@FastThresholdLocked@InputOffsetLocked@ BoardTemp@ HVMonitor@ TECMonitor@ FastCount@ SlowCount@ AccumulationTime@ McaEnabled @MCSDone@PresetCountDone @Build@ FPGAAutoClock@ ReBootFlag@ RealTime@ LiveTime@ PresetRtDone@ PresetLtDone@ GpCounter@ PC5_PRESENT@ PC5_HV_POL@PC5_8_5V@ScopeDataReady@ GateDisabled@ PX5TECVoltageR@P   !" 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