; Orange programmer module v2.2
; (c) 2003 CnCLab
; Xicor CPU Supervisor with 4K SPI EEPROM
; CHIP=X5043,512x8,X5045.HPL 
; CHIP=X5045,512x8,X5045.HPL 

;Status Register:    7   6   5   4    3   2   1    0
;                    0   0  WD1 WD0  BL1 BL0 WEN  WIP

; 43/45 - different RESET polarity

; tested X5045

SOCKET=4 ;"SPI"

PINO=SCK,0
PINO=SI,1
PINO=CS,2
PINO=WP,3
PINO=RESET,4
PINI=SO,1

CDELAY=2 ; one set delay 

R9=STATUS,B6

[READ]
RESET=1
WP=0
CS=1
SCK=0

CS=0
SI=0,LOOP=(3,0){SCK=1,SCK=0}            ;bits 7-4 = 0
SI=ADR[8],SCK=1,SCK=0                   ;Hi ADR bits - use only for 25040 
R0=011B     				;Read Instr.
LOOP=(2,0){SI=R0[I],SCK=1,SCK=0}

LOOP=(7,0){SI=ADR[I],SCK=1,SCK=0}

SI=1
LOOP=(7,0){SCK=1,DATA[I]=SO,SCK=0}
CS=1
P=10

[WRITEINIT]
RESET=1
WP=1              			; Must held Hi!
CS=1
SCK=0
CS=0
R0=00000110b   			; WREN - Write enable
LOOP=(7,0){SI=R0[I],SCK=1,SCK=0}
CS=1
P=20

CS=0
R0=00000001b   			;WRSR Instr.
LOOP=(7,0){SI=R0[I],SCK=1,SCK=0}
R0=00000000b      			;Status Register Clear BP bits
LOOP=(7,0){SI=R0[I],SCK=1,SCK=0}
CS=1
P=5000

[WRITE]
RESET=1
WP=1
SCK=0

CS=0
R0=00000110b   ; Write enable
LOOP=(7,0){SI=R0[I],SCK=1,SCK=0}
CS=1
P=20

CS=0
SI=0,LOOP=(3,0){SCK=1,SCK=0}            ;bits 7-4 = 0
SI=ADR[8],SCK=1,SCK=0                   ;Hi ADR bit - use only for 25040
R0=010B     				;Write Instr.
LOOP=(2,0){SI=R0[I],SCK=1,SCK=0}

LOOP=(7,0){SI=ADR[I],SCK=1,SCK=0}

LOOP=(7,0){SI=DATA[I],SCK=1,SCK=0}
CS=1
P=5000

[ReadStatus]
RESET=1
WP=1
SCK=0
CS=1
CS=0
R0=00000101b                      	; RDSR
LOOP=(7,0){SI=R0[I],SCK=1,SCK=0}
SI=1
LOOP=(7,0){SCK=1,R9[I]=SO,SCK=0}
CS=1
P=10

GET=("Status Register",R9)

[WriteStatus]
GET=("Status Register",R9)
RA?0{EXIT}
RESET=1
WP=1              			; Must held Hi!
CS=1
SCK=0
CS=0
R0=00000110b   			; WREN - Write enable
LOOP=(7,0){SI=R0[I],SCK=1,SCK=0}
CS=1
P=20

CS=0
R0=00000001b   			;WRSR Instr.
LOOP=(7,0){SI=R0[I],SCK=1,SCK=0}
LOOP=(7,0){SI=R9[I],SCK=1,SCK=0}
CS=1
P=20000