; Orange programmer module v2.4
; (c) 2008 CnCLab
; CHIP=x25650(8Kx8), x25128(16Kx8) SPI 
; ST95640


;Status Register:    7   6   5   4   3   2   1   0
;                  WPEN  X   X   X  BL1 BL0 WEL WIP
;					    r/o r/o

SOCKET=4 ;"SPI"

PINO=SCK,0
PINO=SI,1
PINO=CS,2
PINO=WP,3
PINO=HOLD,4
PINI=SO,1

CDELAY=1 ; one set delay 

R9=STATUS,C8,7,6,4,5,3,2,1,0

[!#SETUP]
$WDELAY=10000


[INIT]
HOLD=1
WP=0
CS=1
SCK=0


[_SEND]
LOOP=(7,0){SI=R0[I],SCK=P}


[_WAITWR]	;Wait for end write memory...
SCK=0
LOOP=(0,1000){
CS=0
_SEND(00000101b)                ;RDSR
SI=1
R9=0
LOOP=(7,0){SCK=1,R9[I]=SO,SCK=0}
CS=1
R9[0]?0{BREAK}   ;WIP bit
P=10
}


[READ]
CS=1
SCK=0

CS=0
_SEND(00000011b)     ;Read
LOOP=(15,0){SI=ADR[I],SCK=P}
SI=1
LOOP=(7,0){SCK=1,DATA[I]=SO,SCK=0}
CS=1
P=2

[READBLOCK]
CS=1
SCK=0

CS=0
_SEND(00000011b)	;cmd
LOOP=(15,0){SI=ADR[I],SCK=P}

SI=1
LOOP=($BLOCKSIZE){
LOOP=(7,0){SCK=1,DATA[I]=SO,SCK=0}
ADR=+1
}

CS=1
P=2



[WRITEINIT]
HOLD=1
WP=1
CS=1
SCK=0
CS=0
_SEND(00000110b)   ; Write enable
SI=1,CS=1
P=20
CS=0,SI=0
_SEND(00000001b)   ;WRSR 
_SEND(00000000b)      ;Status Register
SI=1,CS=1
P=12000

[WRITE]
WP=1
SCK=0

CS=0,SI=0
_SEND(00000110b)   ; Write enable
SI=1,CS=1
P=20
CS=0,SI=0
_SEND(00000010b)   ; Write
LOOP=(15,0){SI=ADR[I],SCK=P}
LOOP=(7,0){SI=DATA[I],SCK=P}
SI=1,CS=1
P=$WDELAY



[WRITEBLOCK]                                 ; Запись блока 
WP=1
SCK=0
CS=0,SI=0
_SEND(00000110b)   ; Write enable
SI=1,CS=1
P=10
CS=0,SI=0
_SEND(00000010b)   ; Write
LOOP=(15,0){SI=ADR[I],SCK=P}
LOOP=($BLOCKSIZE){
LOOP=(7,0){SI=DATA[I],SCK=P}
ADR=+1}
SI=1,CS=1
_WAITWR


[ReadStatus]
SCK=0
CS=1
CS=0
_SEND(00000101b)
SI=1
LOOP=(7,0){SCK=1,R9[I]=SO,SCK=0}
CS=1
P=10
GET=("Status Register",R9)


[WriteStatus]
GET=("Status Register",R9)
HOLD=1
WP=1
SCK=0

CS=0
_SEND(00000110b)   ; Write enable
CS=1
P=100

CS=0
_SEND(00000001b)                      	; WRSR
_SEND(R9)
CS=1
P=$WDELAY
P=$WDELAY