; Orange programmer module v3.4
; (c) 2000-2005 CnCLab
; National Semiconductor 
; CHIP=NMC93c56,128x16
; CHIP=NMC93c66,256x16
; Microwire bus with dummy bit and force erase 

; primary tested

SOCKET=2

PINO=CLK,0
PINO=DI,1
PINO=CS,2
PINI=DO,1
PINO=ORG,3

CDELAY=5 ; one set delay
TESTMASK=11110000

[!#SETUP]
$WDELAY=25000



[INIT]
ORG=1
CS=0
CLK=0
DI=0

[READ]
CS=1
R0=0110B
LOOP=(3,0){DI=R0[I],CLK=1,CLK=0} ; READ instr
LOOP=(7,0){DI=ADR[I],CLK=1,CLK=0}   ; out adr
DI=1
LOOP=(15,0){CLK=1,CLK=0,DATA[I]=DO} ; read data word
CS=0

[WRITE]
CS=1
R0=010011000000B
LOOP=(11,0){DI=R0[I],CLK=1,CLK=0} ; EWEN instr

CS=0,
DI=0,CLK=0,CS=1
R0=0111B
LOOP=(3,0){DI=R0[I],CLK=1,CLK=0} ; ERASE instr
LOOP=(7,0){DI=ADR[I],CLK=1,CLK=0}   ; out adr
CS=0
P=$WDELAY


DI=0,CLK=0,CS=1
R0=0101B
LOOP=(3,0){DI=R0[I],CLK=1,CLK=0} ; WRITE instr
LOOP=(7,0){DI=ADR[I],CLK=1,CLK=0}   ; out adr
LOOP=(15,0){CLK=0,DI=DATA[I],CLK=1} ; write data word
CS=0
CLK=0
P=$WDELAY 

[WRITEEND]
CLK=0,DI=0,CS=1
R0=010000000000B
LOOP=(11,0){DI=R0[I],CLK=1,CLK=0} ; EWDS instr
CS=0