; Orange programmer module v3.5
; (c) 1999-2008 CnCLab
; CHIP=AT17C65 (8K), AT17C128 (16K), AT17C256 (32K), AT17C512 (64K)
; CHIP=AT17LV65 (8K), AT17LV128 (16K), AT17LV256 (32K), AT17LV512 (64K)
; FPGA configuration EEPROM
; Test Version only for Orange-4/SE/5

; After the RESET/OE polarity has been modified
; the AT17C65/128/256 MUST be powered down
; and back up again before attempting to verify.



SOCKET=2 ;MW-AT17

PING=SCL,  0 ;2
PINO=RESOE,1 ;3
PING=SDA,  2 ;1
PINO=CEO,  3 ;6 used as Device selection input A2
PINO=SEREN,4 ;7
PINO=CE,   5 ;4



CDELAY=2 ; one cycle time

R9=ResetPol,L,Lo,Hi

[_START]
SDA=1,SCL=1,SDA=0,SCL=0               ; Start  10

[_STOP]
SCL=0,SDA=0,SCL=1,SDA=1                     ; Stop   01


[INIT]
RESOE=0
CE=0
SEREN=0
CEO=0
P=10


[_SEND]
LOOP=(7,0) {SDA=R0[I],SCL=1,SCL=0} ; out 8 bits 7...0


[READ]
_START
P=10

_SEND(0xA6)
SDA=1,SCL=1,SDA?0              ; ack check
SCL=0

LOOP=(15,8) {SDA=ADR[I],SCL=1,SCL=0}  ; out 8 bits adr Hi
SDA=1,SCL=1,SDA?0              ; ack check
SCL=0

LOOP=(7,0)  {SDA=ADR[I],SCL=1,SCL=0} ; out 8 bits adr Lo
SDA=1,SCL=1,SDA?0              ; ack check
SCL=0

;_STOP
_START

_SEND(0xA7)
SDA=1,SCL=1,SDA?0              ; ack check
SCL=0


SDA=1
LOOP=(0,7){SCL=1,DATA[I]=SDA,SCL=0} ;read byte
SDA=1,SCL=1,SCL=0                 ; programmer not ack

SCL=0,SDA=0,SCL=1,SDA=1 ;stop



[READBLOCK]
_START

_SEND(0xA6)
SDA=1,SCL=1,SDA?0              ; ack check
SCL=0

LOOP=(15,8) {SDA=ADR[I],SCL=1,SCL=0}  ; out 8 bits adr Hi
SDA=1,SCL=1,SDA?0              ; ack check
SCL=0

LOOP=(7,0)  {SDA=ADR[I],SCL=1,SCL=0} ; out 8 bits adr Lo
SDA=1,SCL=1,SDA?0              ; ack check
SCL=0

_START

_SEND(0xA7)
SDA=1,SCL=1,SDA?0              ; ack check
SCL=0


R8=2;
LOOP=(R8,RB){
SDA=1
LOOP=(0,7){SCL=1,DATA[I]=SDA,SCL=0} ;read byte
SDA=0, SCL=1, SCL=0               ; programmer ack
ADR=+1
}

;read last byte:
SDA=1
LOOP=(0,7){SCL=1,DATA[I]=SDA,SCL=0} ;read byte
SDA=1,SCL=1,SCL=0 ;no ack
SCL=0,SDA=0,SCL=1,SDA=1 ;stop
;P=10


[WRITEBLOCK]
_START

_SEND(0xA6)
SDA=1,SCL=1,SDA?0              ; ack check
SCL=0 ;,SDA=0

LOOP=(15,8) {SDA=ADR[I],SCL=1,SCL=0}  ; out 8 bits adr Hi
SDA=1,SCL=1,SDA?0              ; ack check
SCL=0 ;,SDA=0

LOOP=(7,0)  {SDA=ADR[I],SCL=1,SCL=0} ; out 8 bits adr Lo
SDA=1,SCL=1,SDA?0              ; ack check
SCL=0 ;,SDA=0


LOOP=($BLOCKSIZE){
LOOP=(0,7) {SDA=DATA[I],SCL=1,SCL=0}   ; DATA
SDA=1,SCL=1,SDA?0,SCL=0              ; ack check
ADR=+1 ;increment adr
}

;WRITEBLOCKEND
P=12000                        ; delay if Vcc=5V
SCL=0,SDA=0,SCL=1,SDA=1 ;stop
P=12000                        ; delay if Vcc=5V


[ReadResetPolarity]
R9=0
SEREN=1
SDA=1
SCL=0
RESOE=0
P=200
CEO=Z

;R9[0]=SDA ; if SDA == HighZ  Reset - Low
;SDA=0
;P=200
;R9[4]=SDA

;RESOE=1
;SDA=1
;P=20
;R9[8]=SDA ; if SDA == HighZ  Reset - Hi
;SDA=0
;P=2
;R9[12]=SDA

;RESOE=1
;P=10
;RESOE=0
;SEREN=1
;SCL=0
;CE=0
;SDA=1
;P=20
;RESOE=1
;P=30

;
LOOP=(0,4096){
R9?0{
SCL=1
SDA?0{R9=1,BREAK}
SCL=0}
} ;test read


GET=("Reset Polarity",R9)


[WriteResetPolarity]
GET=("Write Reset Polarity",R9)
CE=1
SEREN=0
R1=R9,R1=^1
RESOE=R1[0] ; out reset polaryty
P=2

_START

_SEND(0xA6)
SDA=1,SCL=1,SDA?0        ; ack check
SCL=0;,SDA=0

_SEND(0x3F)            ; adr = 3FFF
SDA=1,SCL=1,SDA?0        ; ack check
SCL=0

_SEND(0xFF)		 ; out 8 bits adr Lo
SDA=1,SCL=1,SDA?0        ; ack check
SCL=0


R0=0xFF
LOOP=(0,7)   {SDA=R0[I],SCL=1,SCL=0}   ; DATA = FF
SDA=1,SCL=1,SDA?0,SCL=0              ; ack check


P=10000                        ; delay if Vcc=5V
SCL=0,SDA=0,SCL=1,SDA=1 ;stop
P=10000                        ; delay if Vcc=5V