; Orange programmer module v2.8
; (c) 1999-2011 CnCLab
; CHIP=93CS46,64x16,93CS46.HPL

; TESTED: ST 93S46,93CS46B. NSC 93CS46

; При чтении Protect регистра
; результат сдвигается (ProtectFlag)!

SOCKET=2 ;"MW"

PINO=CLK,0
PINO=DI,1
PINO=CS,2
PINO=PE,3
PINO=PRE,4
PINI=DO,1

CDELAY=3 ; one set delay

R9=Protect,H
;R9=Protect,B16
R10=Protected,C1

[_SEND]
LOOP=(8,0){DI=R0[I],CLK=P}    ; out 3+6 bits

[_WAITWR]
LOOP=(0,5000){
DO?1{BREAK}
P=10
}


[!#SETUP]
$WDELAY=20000


[INIT]
PRE=0
PE=0
CS=0
CLK=0

[READ]
CS=0
CLK=0
CS=1
DI=1,CLK=P    ; start bit
DI=1,CLK=P    ; \ read instruction
DI=0,CLK=P    ; /
LOOP=(5,0){DI=ADR[I],CLK=P}    ; out adr
DI=1,P=1
DO?1{PRINT=A("Chip not respond at %04lX, continue?",ADR),RA?0{EXIT}}
LOOP=(15,0){CLK=P,DATA[I]=DO}  ; read data word
CS=0


[WRITEINIT]
PE=1
PRE=0
CS=0
CLK=0
CS=1
_SEND(100110000b)   ; out EWEN
CS=0
P=30000

[WRITE]
CS=0
CLK=0
CS=1
_SEND(100110000b)   ; out EWEN
CS=0

CS=1
DI=1,CLK=P    ; start bit
DI=0,CLK=P    ; \ write instruction
DI=1,CLK=P    ; /
LOOP=(5,0){DI=ADR[I],CLK=P}    ; out adr
LOOP=(15,0){DI=DATA[I],CLK=P}  ; write data word
CS=0,DI=1,CS=1      ; check status
P=$WDELAY
_WAITWR
CS=0

[WRITEEND]
PE=0

[_RDPROT]
PE=0
PRE=1   ;!!!
CLK=0,CS=1
DI=1,CLK=P    ; start bit
DI=1,CLK=P    ; \ PrRead instruction
DI=0,CLK=0,CLK=0    ; /
LOOP=(5,0) {DI=0,CLK=P}    ; don't care bits (adr emulate)
DI=1
CLK=P
R8=0
LOOP=(5,0){CLK=P,R8[I]=DO}  ; read protect reg
CS=0


[ReadProtect]
PE=0
PRE=1   ;!!!
CS=0,CLK=0,CS=1
DI=1,CLK=P    ; start bit
DI=1,CLK=P    ; \ PrRead instruction
DI=0,CLK=0,CLK=0    ; /
LOOP=(5,0) {DI=0,CLK=P}    ; don't care bits (adr emulate)
DI=1

R9=0
LOOP=(6,0){CLK=P,R9[I]=DO}  ; read protect reg
CLK=P   ;dummy???
CLK=P   ;dummy???
R10=0,CLK=P,R10[0]=DO

;LOOP=(15,0){CLK=P,R9[I]=DO}  ; read protect reg
;prot=1: 0000 0100 1
;prot=2: 0000 1000 1
;prot=4: 0001 0000 1
;prot=0: 0000 0000 0 (flag =0)

CS=0
PRE=0   ;!!!


;R10=R9,R10=&1 ; prot flag
;R9=>>1
;R9=&3Fh
;R1=0
;CLK=P,R1[0]=DO
R10=^1 ;invert flag
GET=("Protect",R9,R10)


[WriteProtect]
GET=("Protect",R9)
RA?0{EXIT}
CS=0
CLK=0


CS=0
CLK=0

PRE=0,PE=1

CS=1
_SEND(100110000b)    ; out EWEN
CS=0

PRE=1,PE=1

CS=1
_SEND(100110000b)    ; out PREN
CS=0

CS=1
_SEND(111111111b)    ; out PRCLEAR
CS=0

CS=0,DI=1,CS=1      ; check status
P=50000
;DO?1
CS=0


PRE=0,PE=1
CS=1
_SEND(100110000b)   ; out EWEN
CS=0

PRE=1,PE=1
CS=1
_SEND(100110000b)    ; out PREN
CS=0

CS=1
DI=1,CLK=P    ; start bit
DI=0,CLK=P    ; \ write instruction
DI=1,CLK=P    ; /
LOOP=(5,0){DI=R9[I],CLK=P}    ; out reg data  ??? or LOOP (5,0)
CS=0,DI=1,CS=1      ; check status
P=50000
;DO?1
CS=0

_RDPROT
R8?!R9{PRINT=E("Write failed")}


PRE=0

[ClearProtect]
CS=0
CLK=0

PRE=0,PE=1

CS=1
_SEND(100110000b)    ; out EWEN
CS=0

PRE=1,PE=1

CS=1
_SEND(100110000b)    ; out PREN
CS=0

CS=1
_SEND(111111111b)   ; out PRCLEAR
CS=0

CS=0,DI=1,CS=1      ; check status
P=50000
;DO?1
CS=0

_RDPROT
R8?!0x3F{PRINT=E("Clear failed")}